1 /* The main mips backend driver file. */
8 #include "pseudo_irg.h"
23 #include "../bearch.h" /* the general register allocator interface */
24 #include "../benode_t.h"
25 #include "../belower.h"
26 #include "../besched_t.h"
30 #include "bearch_mips_t.h"
32 #include "mips_new_nodes.h" /* mips nodes interface */
33 #include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "mips_gen_decls.h" /* interface declaration emitter */
35 #include "mips_transform.h"
36 #include "mips_emitter.h"
37 #include "mips_map_regs.h"
38 #include "mips_util.h"
39 #include "mips_scheduler.h"
41 #define DEBUG_MODULE "firm.be.mips.isa"
43 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
44 static set *cur_reg_set = NULL;
46 /**************************************************
49 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
50 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
51 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
52 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
55 **************************************************/
57 static ir_node *my_skip_proj(const ir_node *n) {
64 * Return register requirements for a mips node.
65 * If the node returns a tuple (mode_T) then the proj's
66 * will be asked for this information.
68 static const arch_register_req_t *mips_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
69 const mips_register_req_t *irn_req;
70 long node_pos = pos == -1 ? 0 : pos;
71 ir_mode *mode = get_irn_mode(irn);
72 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
74 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
75 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
79 if (mode == mode_T && pos < 0) {
80 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
84 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
87 /* in case of a proj, we need to get the correct OUT slot */
88 /* of the node corresponding to the proj number */
90 node_pos = mips_translate_proj_pos(irn);
96 irn = my_skip_proj(irn);
98 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
101 /* get requirements for our own nodes */
102 if (is_mips_irn(irn)) {
104 irn_req = get_mips_in_req(irn, pos);
107 irn_req = get_mips_out_req(irn, node_pos);
110 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
112 memcpy(req, &(irn_req->req), sizeof(*req));
114 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
115 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
116 req->other_same = get_irn_n(irn, irn_req->same_pos);
119 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
120 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
121 req->other_different = get_irn_n(irn, irn_req->different_pos);
124 /* get requirements for FIRM nodes */
126 /* treat Phi like Const with default requirements */
128 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
130 if (mode_is_float(mode)) {
131 //memcpy(req, &(mips_default_req_mips_floating_point.req), sizeof(*req));
132 assert(0 && "floating point not supported (yet)");
134 else if (mode_is_int(mode) || mode_is_reference(mode)) {
135 memcpy(req, &(mips_default_req_mips_gp.req), sizeof(*req));
137 else if (mode == mode_T || mode == mode_M) {
138 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
142 assert(0 && "unsupported Phi-Mode");
146 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
154 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
159 if (get_irn_mode(irn) == mode_X) {
163 pos = mips_translate_proj_pos(irn);
164 irn = my_skip_proj(irn);
167 if (is_mips_irn(irn)) {
168 const arch_register_t **slots;
170 slots = get_mips_slots(irn);
174 /* here we set the registers for the Phi nodes */
175 mips_set_firm_reg(irn, reg, cur_reg_set);
179 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
181 const arch_register_t *reg = NULL;
185 if (get_irn_mode(irn) == mode_X) {
189 pos = mips_translate_proj_pos(irn);
190 irn = my_skip_proj(irn);
193 if (is_mips_irn(irn)) {
194 const arch_register_t **slots;
195 slots = get_mips_slots(irn);
199 reg = mips_get_firm_reg(irn, cur_reg_set);
205 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
206 irn = my_skip_proj(irn);
209 return arch_irn_class_branch;
210 } else if (is_mips_irn(irn)) {
211 return arch_irn_class_normal;
217 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
218 irn = my_skip_proj(irn);
220 if (is_mips_irn(irn)) {
221 return get_mips_flags(irn);
223 else if (is_Unknown(irn)) {
224 return arch_irn_flags_ignore;
230 static entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
231 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
232 mips_attr_t *attr = get_mips_attr(irn);
234 return attr->stack_entity;
241 * This function is called by the generic backend to correct offsets for
242 * nodes accessing the stack.
244 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
245 mips_attr_t *attr = get_mips_attr(irn);
246 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
248 attr->stack_entity_offset = offset;
251 /* fill register allocator interface */
253 static const arch_irn_ops_if_t mips_irn_ops_if = {
254 mips_get_irn_reg_req,
259 mips_get_frame_entity,
260 mips_set_frame_offset,
264 mips_irn_ops_t mips_irn_ops = {
271 /**************************************************
274 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
275 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
276 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
277 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
280 **************************************************/
290 * Ext-Block walker: create a block schedule
292 static void create_block_list(ir_extblk *blk, void *env) {
296 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
297 ir_node *block = get_extbb_block(blk, i);
299 set_irn_link(block, NULL);
301 set_irn_link(list->end, block);
310 /* return the scheduled block at position pos */
311 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
312 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
313 return cg->bl_list[pos];
317 /* return the number of scheduled blocks */
318 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
319 return ARR_LEN(cg->bl_list);
322 /* set a block schedule number */
323 void mips_set_block_sched_nr(ir_node *block, int nr) {
324 set_irn_link(block, INT_TO_PTR(nr));
327 /* get a block schedule number */
328 int mips_get_block_sched_nr(ir_node *block) {
329 return PTR_TO_INT(get_irn_link(block));
333 * Creates a block schedule for the given graph.
335 static void mips_create_block_sched(mips_code_gen_t *cg) {
337 ir_node **bl_list, *block;
341 DEL_ARR_F(cg->bl_list);
342 free_survive_dce(cg->bl_list_sdce);
345 /* calculate the block schedule here */
346 compute_extbb(cg->irg);
351 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
354 bl_list = NEW_ARR_F(ir_node *, list.cnt);
355 cg->bl_list_sdce = new_survive_dce();
356 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
358 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
362 cg->bl_list = bl_list;
365 typedef struct _wenv_t {
370 * Walker: link all CopyB nodes
372 static void collect_copyb_nodes(ir_node *node, void *env) {
375 if (get_irn_op(node) == op_CopyB) {
376 set_irn_link(node, wenv->list);
381 static void replace_copyb_nodes(mips_code_gen_t *cg) {
383 ir_node *copy, *next;
384 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
385 const ir_edge_t *edge;
387 /* build code for all copyB */
389 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
391 for (copy = env.list; copy; copy = next) {
392 next = get_irn_link(copy);
394 old_bl = get_nodes_block(copy);
396 jmp = get_Block_cfgpred(old_bl, 0);
397 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
399 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
400 set_nodes_block(jmp, new_bl);
402 mem = gen_code_for_CopyB(new_bl, copy);
404 /* fix copyB's out edges */
405 foreach_out_edge(copy, edge) {
406 ir_node *succ = get_edge_src_irn(edge);
408 assert(is_Proj(succ));
409 switch (get_Proj_proj(succ)) {
410 case pn_CopyB_M_regular:
411 case pn_CopyB_M_except:
415 exchange(succ, get_irg_bad(cg->irg));
422 * Transforms the standard firm graph into
425 static void mips_prepare_graph(void *self) {
426 mips_code_gen_t *cg = self;
429 // replace all copyb nodes in the block with a loop
430 // and mips store/load nodes
431 replace_copyb_nodes(cg);
433 // Calculate block schedule
434 mips_create_block_sched(cg);
436 /* enter the block number into every blocks link field */
437 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
438 ir_node *bl = mips_get_sched_block(cg, bl_nr);
439 mips_set_block_sched_nr(bl, bl_nr);
442 // walk the graph and transform firm nodes into mips nodes where possible
443 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
445 dump_ir_block_graph_sched(cg->irg, "-transformed");
449 * Called immediately before emit phase.
451 static void mips_finish_irg(ir_graph *irg, mips_code_gen_t *cg) {
452 /* TODO: - fix offsets for nodes accessing stack
459 * These are some hooks which must be filled but are probably not needed.
461 static void mips_before_sched(void *self) {
462 /* Some stuff you need to do after scheduling but before register allocation */
465 static void mips_before_ra(void *self) {
466 /* Some stuff you need to do immediately after register allocation */
469 static void mips_after_ra(void* self) {
470 mips_code_gen_t *cg = self;
471 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
475 * Emits the code, closes the output file and frees
476 * the code generator interface.
478 static void mips_emit_and_done(void *self) {
479 mips_code_gen_t *cg = self;
480 ir_graph *irg = cg->irg;
481 FILE *out = cg->isa->out;
483 mips_register_emitters();
485 if (cg->emit_decls) {
490 mips_finish_irg(irg, cg);
491 dump_ir_block_graph_sched(irg, "-mips-finished");
492 mips_gen_routine(out, irg, cg);
496 /* de-allocate code generator */
497 del_set(cg->reg_set);
499 DEL_ARR_F(cg->bl_list);
500 free_survive_dce(cg->bl_list_sdce);
505 static void *mips_cg_init(const be_irg_t *birg);
507 static const arch_code_generator_if_t mips_code_gen_if = {
509 NULL, /* before abi introduce */
511 mips_before_sched, /* before scheduling hook */
512 mips_before_ra, /* before register allocation hook */
518 * Initializes the code generator.
520 static void *mips_cg_init(const be_irg_t *birg) {
521 mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa;
522 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
524 cg->impl = &mips_code_gen_if;
526 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
527 cg->arch_env = birg->main_env->arch_env;
531 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
535 if (isa->num_codegens > 1)
540 cur_reg_set = cg->reg_set;
542 mips_irn_ops.cg = cg;
544 return (arch_code_generator_t *)cg;
548 /*****************************************************************
549 * ____ _ _ _____ _____
550 * | _ \ | | | | |_ _|/ ____| /\
551 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
552 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
553 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
554 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
556 *****************************************************************/
558 static mips_isa_t mips_isa_template = {
560 &mips_gp_regs[REG_SP],
561 &mips_gp_regs[REG_FP],
562 -1, // stack direction
563 0, // num codegens?!? TODO what is this?
568 * Initializes the backend ISA and opens the output file.
570 static void *mips_init(FILE *file_handle) {
571 static int inited = 0;
577 isa = xcalloc(1, sizeof(*isa));
578 memcpy(isa, &mips_isa_template, sizeof(*isa));
580 isa->out = file_handle;
582 mips_register_init(isa);
583 mips_create_opcodes();
584 mips_init_opcode_transforms();
592 * Closes the output file and frees the ISA structure.
594 static void mips_done(void *self) {
598 static int mips_get_n_reg_class(const void *self) {
602 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
603 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
604 return &mips_reg_classes[i];
610 * Get the register class which shall be used to store a value of a given mode.
611 * @param self The this pointer.
612 * @param mode The mode in question.
613 * @return A register class which can hold values of the given mode.
615 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
616 ASSERT_NO_FLOAT(mode);
617 return &mips_reg_classes[CLASS_mips_gp];
621 be_abi_call_flags_bits_t flags;
622 const mips_isa_t *isa;
623 const arch_env_t *arch_env;
625 // do special handling to support debuggers
629 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
631 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
632 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
633 env->flags = fl.bits;
635 env->arch_env = arch_env;
636 env->isa = (const mips_isa_t*) arch_env->isa;
641 static void mips_abi_dont_save_regs(void *self, pset *s)
643 mips_abi_env_t *env = self;
644 if(env->flags.try_omit_fp)
645 pset_insert_ptr(s, env->isa->fp);
648 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
650 mips_abi_env_t *env = self;
651 ir_graph *irg = env->irg;
652 dbg_info *dbg = NULL; // TODO where can I get this from?
653 ir_node *block = get_irg_start_block(env->irg);
655 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
656 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
657 int initialstackframesize;
661 * The calling conventions wants a stack frame of at least 24bytes size with
662 * a0-a3 saved in offset 0-12
663 * fp saved in offset 16
664 * ra saved in offset 20
667 ir_node *sync, *reg, *store;
668 initialstackframesize = 24;
670 // - setup first part of stackframe
671 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
672 attr = get_mips_attr(sp);
673 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
674 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
675 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
677 /* TODO: where to get an edge with a0-a3
679 for(i = 0; i < 4; ++i) {
680 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
681 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
682 attr = get_mips_attr(store);
683 attr->load_store_mode = mode_Iu;
684 attr->tv = new_tarval_from_long(i * 4, mode_Is);
686 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
690 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
691 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
692 attr = get_mips_attr(store);
693 attr->modes.load_store_mode = mode_Iu;
694 attr->tv = new_tarval_from_long(16, mode_Is);
696 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
698 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
699 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
700 attr = get_mips_attr(store);
701 attr->modes.load_store_mode = mode_Iu;
702 attr->tv = new_tarval_from_long(20, mode_Is);
704 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
706 // TODO ideally we would route these mem edges directly towards the epilogue
707 sync = new_r_Sync(irg, block, 2, mm+4);
710 ir_node *reg, *store;
711 initialstackframesize = 4;
713 // save old framepointer
714 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
715 attr = get_mips_attr(sp);
716 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
717 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
718 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
720 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
721 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
722 attr = get_mips_attr(store);
723 attr->modes.load_store_mode = mode_Iu;
724 attr->tv = new_tarval_from_long(0, mode_Is);
726 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
729 // setup framepointer
730 fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
731 attr = get_mips_attr(fp);
732 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
733 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
734 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
736 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
737 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
739 return &mips_gp_regs[REG_SP];
742 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
744 mips_abi_env_t *env = self;
745 ir_graph *irg = env->irg;
746 dbg_info *dbg = NULL; // TODO where can I get this from?
748 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
749 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
751 int initial_frame_size = env->debug ? 24 : 4;
752 int fp_save_offset = env->debug ? 16 : 0;
755 //sp = be_new_IncSP(&mips_gp_regs[REG_SP], irg, block, sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
758 sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu);
759 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
760 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
763 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
764 attr = get_mips_attr(load);
765 attr->modes.load_store_mode = mode_Iu;
766 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
767 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
769 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
770 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
771 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
773 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
774 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
778 * Produces the type which sits between the stack args and the locals on the stack.
779 * it will contain the return address and space to store the old frame pointer.
780 * @return The Firm type modelling the ABI between type.
782 static ir_type *mips_abi_get_between_type(void *self) {
783 mips_abi_env_t *env = self;
785 static ir_type *debug_between_type = NULL;
786 static ir_type *opt_between_type = NULL;
787 static entity *old_fp_ent = NULL;
789 if(env->debug && debug_between_type == NULL) {
790 entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
791 entity *ret_addr_ent;
792 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
793 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
794 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
796 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
797 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
798 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
799 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
800 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
801 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
802 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
804 set_entity_offset_bytes(a0_ent, 0);
805 set_entity_offset_bytes(a1_ent, 4);
806 set_entity_offset_bytes(a2_ent, 8);
807 set_entity_offset_bytes(a3_ent, 12);
808 set_entity_offset_bytes(old_fp_ent, 16);
809 set_entity_offset_bytes(ret_addr_ent, 20);
811 set_type_size_bytes(debug_between_type, 24);
812 } else if(!env->debug && opt_between_type == NULL) {
813 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
816 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
817 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
818 set_entity_offset_bytes(old_fp_ent, 0);
819 set_type_size_bytes(opt_between_type, 4);
822 return env->debug ? debug_between_type : opt_between_type;
825 static const be_abi_callbacks_t mips_abi_callbacks = {
828 mips_abi_get_between_type,
829 mips_abi_dont_save_regs,
835 * Get the ABI restrictions for procedure calls.
836 * @param self The this pointer.
837 * @param method_type The type of the method (procedure) in question.
838 * @param abi The abi object to be modified
840 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
843 int n = get_method_n_params(method_type);
847 const arch_register_t *reg;
848 be_abi_call_flags_t call_flags;
850 memset(&call_flags, 0, sizeof(call_flags));
851 call_flags.bits.left_to_right = 0;
852 call_flags.bits.store_args_sequential = 0;
853 call_flags.bits.try_omit_fp = 1;
854 call_flags.bits.fp_free = 0;
855 call_flags.bits.call_has_imm = 1;
857 /* set stack parameter passing style */
858 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
860 /* collect the mode for each type */
861 modes = alloca(n * sizeof(modes[0]));
862 for (i = 0; i < n; i++) {
863 tp = get_method_param_type(method_type, i);
864 modes[i] = get_type_mode(tp);
867 // assigns parameters to registers or stack
868 for (i = 0; i < n; i++) {
869 // first 4 params in $a0-$a3, the others on the stack
871 reg = &mips_gp_regs[REG_A0 + i];
872 be_abi_call_param_reg(abi, i, reg);
874 /* default: all parameters on stack */
875 be_abi_call_param_stack(abi, i, 4, 0, 0);
879 /* set return register */
880 /* default: return value is in R0 (and maybe R1) */
881 result_count = get_method_n_ress(method_type);
882 assert(result_count <= 2 && "More than 2 result values not supported");
883 for(i = 0; i < result_count; ++i) {
884 const arch_register_t* reg;
885 tp = get_method_res_type(method_type, i);
886 mode = get_type_mode(tp);
887 ASSERT_NO_FLOAT(mode);
889 reg = &mips_gp_regs[REG_V0 + i];
890 be_abi_call_res_reg(abi, i, reg);
894 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
895 return &mips_irn_ops;
898 const arch_irn_handler_t mips_irn_handler = {
902 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
903 return &mips_irn_handler;
907 * Initializes the code generator interface.
909 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
910 return &mips_code_gen_if;
914 * Returns the necessary byte alignment for storing a register of given class.
916 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
917 ir_mode *mode = arch_register_class_mode(cls);
918 return get_mode_size_bytes(mode);
922 * Returns the libFirm configuration parameter for this backend.
924 static const backend_params *mips_get_libfirm_params(void) {
925 static arch_dep_params_t ad = {
927 0, /* Muls are fast enough on Mips */
928 31, /* shift would be ok */
931 32, /* Mulhs & Mulhu available for 32 bit */
933 static backend_params p = {
934 NULL, /* no additional opcodes */
935 NULL, /* will be set later */
936 1, /* need dword lowering */
937 NULL, /* but yet no creator function */
938 NULL, /* context for create_intrinsic_fkt */
946 static void mips_register_options(lc_opt_entry_t *ent)
949 #endif /* WITH_LIBCORE */
951 const arch_isa_if_t mips_isa_if = {
954 mips_get_n_reg_class,
956 mips_get_reg_class_for_mode,
958 mips_get_irn_handler,
959 mips_get_code_generator_if,
960 mips_get_list_sched_selector,
961 mips_get_reg_class_alignment,
962 mips_get_libfirm_params,
964 mips_register_options