1 /* The main mips backend driver file. */
8 #include "pseudo_irg.h"
23 #include "../bearch.h" /* the general register allocator interface */
24 #include "../benode_t.h"
25 #include "../belower.h"
26 #include "../besched_t.h"
29 #include "../bemachine.h"
31 #include "bearch_mips_t.h"
33 #include "mips_new_nodes.h" /* mips nodes interface */
34 #include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "mips_gen_decls.h" /* interface declaration emitter */
36 #include "mips_transform.h"
37 #include "mips_emitter.h"
38 #include "mips_map_regs.h"
39 #include "mips_util.h"
40 #include "mips_scheduler.h"
42 #define DEBUG_MODULE "firm.be.mips.isa"
44 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
45 static set *cur_reg_set = NULL;
47 /**************************************************
50 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
51 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
52 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
53 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
56 **************************************************/
58 static ir_node *my_skip_proj(const ir_node *n) {
65 * Return register requirements for a mips node.
66 * If the node returns a tuple (mode_T) then the proj's
67 * will be asked for this information.
69 static const arch_register_req_t *mips_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
70 const mips_register_req_t *irn_req;
71 long node_pos = pos == -1 ? 0 : pos;
72 ir_mode *mode = get_irn_mode(irn);
73 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
75 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
76 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
80 if (mode == mode_T && pos < 0) {
81 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
85 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
88 /* in case of a proj, we need to get the correct OUT slot */
89 /* of the node corresponding to the proj number */
91 node_pos = mips_translate_proj_pos(irn);
97 irn = my_skip_proj(irn);
99 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
102 /* get requirements for our own nodes */
103 if (is_mips_irn(irn)) {
105 irn_req = get_mips_in_req(irn, pos);
108 irn_req = get_mips_out_req(irn, node_pos);
111 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
113 memcpy(req, &(irn_req->req), sizeof(*req));
115 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
116 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
117 req->other_same = get_irn_n(irn, irn_req->same_pos);
120 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
121 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
122 req->other_different = get_irn_n(irn, irn_req->different_pos);
125 /* get requirements for FIRM nodes */
127 /* treat Phi like Const with default requirements */
129 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
131 if (mode_is_float(mode)) {
132 //memcpy(req, &(mips_default_req_mips_floating_point.req), sizeof(*req));
133 assert(0 && "floating point not supported (yet)");
135 else if (mode_is_int(mode) || mode_is_reference(mode)) {
136 memcpy(req, &(mips_default_req_mips_gp.req), sizeof(*req));
138 else if (mode == mode_T || mode == mode_M) {
139 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
143 assert(0 && "unsupported Phi-Mode");
147 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
155 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
160 if (get_irn_mode(irn) == mode_X) {
164 pos = mips_translate_proj_pos(irn);
165 irn = my_skip_proj(irn);
168 if (is_mips_irn(irn)) {
169 const arch_register_t **slots;
171 slots = get_mips_slots(irn);
175 /* here we set the registers for the Phi nodes */
176 mips_set_firm_reg(irn, reg, cur_reg_set);
180 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
182 const arch_register_t *reg = NULL;
186 if (get_irn_mode(irn) == mode_X) {
190 pos = mips_translate_proj_pos(irn);
191 irn = my_skip_proj(irn);
194 if (is_mips_irn(irn)) {
195 const arch_register_t **slots;
196 slots = get_mips_slots(irn);
200 reg = mips_get_firm_reg(irn, cur_reg_set);
206 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
207 irn = my_skip_proj(irn);
210 return arch_irn_class_branch;
211 } else if (is_mips_irn(irn)) {
212 return arch_irn_class_normal;
218 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
219 irn = my_skip_proj(irn);
221 if (is_mips_irn(irn)) {
222 return get_mips_flags(irn);
224 else if (is_Unknown(irn)) {
225 return arch_irn_flags_ignore;
231 static entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
232 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
233 mips_attr_t *attr = get_mips_attr(irn);
235 return attr->stack_entity;
241 static void mips_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
242 mips_attr_t *attr = get_mips_attr(irn);
243 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
244 attr->stack_entity = ent;
248 * This function is called by the generic backend to correct offsets for
249 * nodes accessing the stack.
251 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
252 mips_attr_t *attr = get_mips_attr(irn);
253 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
255 attr->stack_entity_offset = offset;
258 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
262 /* fill register allocator interface */
264 static const arch_irn_ops_if_t mips_irn_ops_if = {
265 mips_get_irn_reg_req,
270 mips_get_frame_entity,
271 mips_set_frame_entity,
272 mips_set_frame_offset,
274 NULL, /* get_inverse */
275 NULL, /* get_op_estimated_cost */
276 NULL, /* possible_memory_operand */
277 NULL, /* perform_memory_operand */
280 mips_irn_ops_t mips_irn_ops = {
287 /**************************************************
290 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
291 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
292 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
293 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
296 **************************************************/
306 * Ext-Block walker: create a block schedule
308 static void create_block_list(ir_extblk *blk, void *env) {
312 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
313 ir_node *block = get_extbb_block(blk, i);
315 set_irn_link(block, NULL);
317 set_irn_link(list->end, block);
326 /* return the scheduled block at position pos */
327 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
328 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
329 return cg->bl_list[pos];
333 /* return the number of scheduled blocks */
334 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
335 return ARR_LEN(cg->bl_list);
338 /* set a block schedule number */
339 void mips_set_block_sched_nr(ir_node *block, int nr) {
340 set_irn_link(block, INT_TO_PTR(nr));
343 /* get a block schedule number */
344 int mips_get_block_sched_nr(ir_node *block) {
345 return PTR_TO_INT(get_irn_link(block));
349 * Creates a block schedule for the given graph.
351 static void mips_create_block_sched(mips_code_gen_t *cg) {
353 ir_node **bl_list, *block;
357 DEL_ARR_F(cg->bl_list);
358 free_survive_dce(cg->bl_list_sdce);
361 /* calculate the block schedule here */
362 compute_extbb(cg->irg);
367 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
370 bl_list = NEW_ARR_F(ir_node *, list.cnt);
371 cg->bl_list_sdce = new_survive_dce();
372 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
374 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
378 cg->bl_list = bl_list;
381 typedef struct _wenv_t {
386 * Walker: link all CopyB nodes
388 static void collect_copyb_nodes(ir_node *node, void *env) {
391 if (get_irn_op(node) == op_CopyB) {
392 set_irn_link(node, wenv->list);
397 static void replace_copyb_nodes(mips_code_gen_t *cg) {
399 ir_node *copy, *next;
400 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
401 const ir_edge_t *edge;
403 /* build code for all copyB */
405 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
407 for (copy = env.list; copy; copy = next) {
408 next = get_irn_link(copy);
410 old_bl = get_nodes_block(copy);
412 jmp = get_Block_cfgpred(old_bl, 0);
413 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
415 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
416 set_nodes_block(jmp, new_bl);
418 mem = gen_code_for_CopyB(new_bl, copy);
420 /* fix copyB's out edges */
421 foreach_out_edge(copy, edge) {
422 ir_node *succ = get_edge_src_irn(edge);
424 assert(is_Proj(succ));
425 switch (get_Proj_proj(succ)) {
426 case pn_CopyB_M_regular:
427 case pn_CopyB_M_except:
431 exchange(succ, get_irg_bad(cg->irg));
438 * Transforms the standard firm graph into
441 static void mips_prepare_graph(void *self) {
442 mips_code_gen_t *cg = self;
445 // replace all copyb nodes in the block with a loop
446 // and mips store/load nodes
447 replace_copyb_nodes(cg);
449 // Calculate block schedule
450 mips_create_block_sched(cg);
452 /* enter the block number into every blocks link field */
453 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
454 ir_node *bl = mips_get_sched_block(cg, bl_nr);
455 mips_set_block_sched_nr(bl, bl_nr);
458 // walk the graph and transform firm nodes into mips nodes where possible
459 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
461 dump_ir_block_graph_sched(cg->irg, "-transformed");
465 * Called immediately before emit phase.
467 static void mips_finish_irg(void *self) {
468 mips_code_gen_t *cg = self;
469 ir_graph *irg = cg->irg;
471 dump_ir_block_graph_sched(irg, "-mips-finished");
476 * These are some hooks which must be filled but are probably not needed.
478 static void mips_before_sched(void *self) {
479 /* Some stuff you need to do after scheduling but before register allocation */
482 static void mips_before_ra(void *self) {
483 /* Some stuff you need to do immediately after register allocation */
486 static void mips_after_ra(void* self) {
487 mips_code_gen_t *cg = self;
488 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
492 * Emits the code, closes the output file and frees
493 * the code generator interface.
495 static void mips_emit_and_done(void *self) {
496 mips_code_gen_t *cg = self;
497 ir_graph *irg = cg->irg;
498 FILE *out = cg->isa->out;
500 mips_register_emitters();
502 if (cg->emit_decls) {
507 mips_gen_routine(out, irg, cg);
511 /* de-allocate code generator */
512 del_set(cg->reg_set);
514 DEL_ARR_F(cg->bl_list);
515 free_survive_dce(cg->bl_list_sdce);
520 static void *mips_cg_init(const be_irg_t *birg);
522 static const arch_code_generator_if_t mips_code_gen_if = {
524 NULL, /* before abi introduce */
526 mips_before_sched, /* before scheduling hook */
527 mips_before_ra, /* before register allocation hook */
534 * Initializes the code generator.
536 static void *mips_cg_init(const be_irg_t *birg) {
537 mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa;
538 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
540 cg->impl = &mips_code_gen_if;
542 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
543 cg->arch_env = birg->main_env->arch_env;
547 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
551 if (isa->num_codegens > 1)
556 cur_reg_set = cg->reg_set;
558 mips_irn_ops.cg = cg;
560 return (arch_code_generator_t *)cg;
564 /*****************************************************************
565 * ____ _ _ _____ _____
566 * | _ \ | | | | |_ _|/ ____| /\
567 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
568 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
569 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
570 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
572 *****************************************************************/
574 static mips_isa_t mips_isa_template = {
576 &mips_gp_regs[REG_SP],
577 &mips_gp_regs[REG_FP],
578 -1, // stack direction
579 0, // num codegens?!? TODO what is this?
584 * Initializes the backend ISA and opens the output file.
586 static void *mips_init(FILE *file_handle) {
587 static int inited = 0;
593 isa = xcalloc(1, sizeof(*isa));
594 memcpy(isa, &mips_isa_template, sizeof(*isa));
596 isa->out = file_handle;
598 mips_register_init(isa);
599 mips_create_opcodes();
600 mips_init_opcode_transforms();
608 * Closes the output file and frees the ISA structure.
610 static void mips_done(void *self) {
614 static int mips_get_n_reg_class(const void *self) {
618 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
619 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
620 return &mips_reg_classes[i];
626 * Get the register class which shall be used to store a value of a given mode.
627 * @param self The this pointer.
628 * @param mode The mode in question.
629 * @return A register class which can hold values of the given mode.
631 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
632 ASSERT_NO_FLOAT(mode);
633 return &mips_reg_classes[CLASS_mips_gp];
637 be_abi_call_flags_bits_t flags;
638 const mips_isa_t *isa;
639 const arch_env_t *arch_env;
641 // do special handling to support debuggers
645 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
647 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
648 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
649 env->flags = fl.bits;
651 env->arch_env = arch_env;
652 env->isa = (const mips_isa_t*) arch_env->isa;
657 static void mips_abi_dont_save_regs(void *self, pset *s)
659 mips_abi_env_t *env = self;
660 if(env->flags.try_omit_fp)
661 pset_insert_ptr(s, env->isa->fp);
664 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
666 mips_abi_env_t *env = self;
667 ir_graph *irg = env->irg;
668 dbg_info *dbg = NULL; // TODO where can I get this from?
669 ir_node *block = get_irg_start_block(env->irg);
671 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
672 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
673 int initialstackframesize;
677 * The calling conventions wants a stack frame of at least 24bytes size with
678 * a0-a3 saved in offset 0-12
679 * fp saved in offset 16
680 * ra saved in offset 20
683 ir_node *sync, *reg, *store;
684 initialstackframesize = 24;
686 // - setup first part of stackframe
687 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
688 attr = get_mips_attr(sp);
689 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
690 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
691 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
693 /* TODO: where to get an edge with a0-a3
695 for(i = 0; i < 4; ++i) {
696 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
697 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
698 attr = get_mips_attr(store);
699 attr->load_store_mode = mode_Iu;
700 attr->tv = new_tarval_from_long(i * 4, mode_Is);
702 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
706 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
707 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
708 attr = get_mips_attr(store);
709 attr->modes.load_store_mode = mode_Iu;
710 attr->tv = new_tarval_from_long(16, mode_Is);
712 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
714 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
715 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
716 attr = get_mips_attr(store);
717 attr->modes.load_store_mode = mode_Iu;
718 attr->tv = new_tarval_from_long(20, mode_Is);
720 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
722 // TODO ideally we would route these mem edges directly towards the epilogue
723 sync = new_r_Sync(irg, block, 2, mm+4);
726 ir_node *reg, *store;
727 initialstackframesize = 4;
729 // save old framepointer
730 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
731 attr = get_mips_attr(sp);
732 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
733 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
734 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
736 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
737 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
738 attr = get_mips_attr(store);
739 attr->modes.load_store_mode = mode_Iu;
740 attr->tv = new_tarval_from_long(0, mode_Is);
742 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
745 // setup framepointer
746 fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
747 attr = get_mips_attr(fp);
748 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
749 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
750 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
752 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
753 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
755 return &mips_gp_regs[REG_SP];
758 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
760 mips_abi_env_t *env = self;
761 ir_graph *irg = env->irg;
762 dbg_info *dbg = NULL; // TODO where can I get this from?
764 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
765 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
767 int initial_frame_size = env->debug ? 24 : 4;
768 int fp_save_offset = env->debug ? 16 : 0;
771 sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu);
772 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
773 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
776 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
777 attr = get_mips_attr(load);
778 attr->modes.load_store_mode = mode_Iu;
779 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
780 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
782 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
783 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
784 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
786 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
787 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
791 * Produces the type which sits between the stack args and the locals on the stack.
792 * it will contain the return address and space to store the old frame pointer.
793 * @return The Firm type modelling the ABI between type.
795 static ir_type *mips_abi_get_between_type(void *self) {
796 mips_abi_env_t *env = self;
798 static ir_type *debug_between_type = NULL;
799 static ir_type *opt_between_type = NULL;
800 static entity *old_fp_ent = NULL;
802 if(env->debug && debug_between_type == NULL) {
803 entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
804 entity *ret_addr_ent;
805 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
806 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
807 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
809 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
810 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
811 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
812 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
813 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
814 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
815 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
817 set_entity_offset_bytes(a0_ent, 0);
818 set_entity_offset_bytes(a1_ent, 4);
819 set_entity_offset_bytes(a2_ent, 8);
820 set_entity_offset_bytes(a3_ent, 12);
821 set_entity_offset_bytes(old_fp_ent, 16);
822 set_entity_offset_bytes(ret_addr_ent, 20);
824 set_type_size_bytes(debug_between_type, 24);
825 } else if(!env->debug && opt_between_type == NULL) {
826 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
829 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
830 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
831 set_entity_offset_bytes(old_fp_ent, 0);
832 set_type_size_bytes(opt_between_type, 4);
835 return env->debug ? debug_between_type : opt_between_type;
838 static const be_abi_callbacks_t mips_abi_callbacks = {
841 mips_abi_get_between_type,
842 mips_abi_dont_save_regs,
848 * Get the ABI restrictions for procedure calls.
849 * @param self The this pointer.
850 * @param method_type The type of the method (procedure) in question.
851 * @param abi The abi object to be modified
853 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
856 int n = get_method_n_params(method_type);
860 const arch_register_t *reg;
861 be_abi_call_flags_t call_flags;
863 memset(&call_flags, 0, sizeof(call_flags));
864 call_flags.bits.left_to_right = 0;
865 call_flags.bits.store_args_sequential = 0;
866 call_flags.bits.try_omit_fp = 1;
867 call_flags.bits.fp_free = 0;
868 call_flags.bits.call_has_imm = 1;
870 /* set stack parameter passing style */
871 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
873 /* collect the mode for each type */
874 modes = alloca(n * sizeof(modes[0]));
875 for (i = 0; i < n; i++) {
876 tp = get_method_param_type(method_type, i);
877 modes[i] = get_type_mode(tp);
880 // assigns parameters to registers or stack
881 for (i = 0; i < n; i++) {
882 // first 4 params in $a0-$a3, the others on the stack
884 reg = &mips_gp_regs[REG_A0 + i];
885 be_abi_call_param_reg(abi, i, reg);
887 /* default: all parameters on stack */
888 be_abi_call_param_stack(abi, i, 4, 0, 0);
892 /* set return register */
893 /* default: return value is in R0 (and maybe R1) */
894 result_count = get_method_n_ress(method_type);
895 assert(result_count <= 2 && "More than 2 result values not supported");
896 for(i = 0; i < result_count; ++i) {
897 const arch_register_t* reg;
898 tp = get_method_res_type(method_type, i);
899 mode = get_type_mode(tp);
900 ASSERT_NO_FLOAT(mode);
902 reg = &mips_gp_regs[REG_V0 + i];
903 be_abi_call_res_reg(abi, i, reg);
907 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
908 return &mips_irn_ops;
911 const arch_irn_handler_t mips_irn_handler = {
915 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
916 return &mips_irn_handler;
920 * Initializes the code generator interface.
922 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
923 return &mips_code_gen_if;
927 * Returns the necessary byte alignment for storing a register of given class.
929 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
930 ir_mode *mode = arch_register_class_mode(cls);
931 return get_mode_size_bytes(mode);
934 static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
940 static const be_machine_t *mips_get_machine(const void *self) {
947 * Returns the libFirm configuration parameter for this backend.
949 static const backend_params *mips_get_libfirm_params(void) {
950 static arch_dep_params_t ad = {
952 0, /* Muls are fast enough on Mips */
953 31, /* shift would be ok */
956 32, /* Mulhs & Mulhu available for 32 bit */
958 static backend_params p = {
959 NULL, /* no additional opcodes */
960 NULL, /* will be set later */
961 1, /* need dword lowering */
962 NULL, /* but yet no creator function */
963 NULL, /* context for create_intrinsic_fkt */
971 static void mips_register_options(lc_opt_entry_t *ent)
974 #endif /* WITH_LIBCORE */
976 const arch_isa_if_t mips_isa_if = {
979 mips_get_n_reg_class,
981 mips_get_reg_class_for_mode,
983 mips_get_irn_handler,
984 mips_get_code_generator_if,
985 mips_get_list_sched_selector,
986 mips_get_ilp_sched_selector,
987 mips_get_reg_class_alignment,
988 mips_get_libfirm_params,
989 mips_get_allowed_execution_units,
992 mips_register_options