2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
28 #include "pseudo_irg.h"
45 #include "../bearch.h"
46 #include "../benode.h"
47 #include "../belower.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
85 static arch_irn_class_t mips_classify(const ir_node *irn)
91 int mips_is_Load(const ir_node *node)
93 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
94 is_mips_lb(node) || is_mips_lbu(node);
97 int mips_is_Store(const ir_node *node)
99 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
102 static ir_entity *mips_get_frame_entity(const ir_node *node)
104 const mips_load_store_attr_t *attr;
106 if(!is_mips_irn(node))
108 if(!mips_is_Load(node) && !mips_is_Store(node))
111 attr = get_mips_load_store_attr_const(node);
112 return attr->stack_entity;
115 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
117 mips_load_store_attr_t *attr;
119 if(!is_mips_irn(node)) {
120 panic("trying to set frame entity on non load/store node %+F", node);
122 if(!mips_is_Load(node) && !mips_is_Store(node)) {
123 panic("trying to set frame entity on non load/store node %+F", node);
126 attr = get_irn_generic_attr(node);
127 attr->stack_entity = entity;
131 * This function is called by the generic backend to correct offsets for
132 * nodes accessing the stack.
134 static void mips_set_frame_offset(ir_node *node, int offset)
136 mips_load_store_attr_t *attr;
138 if(!is_mips_irn(node)) {
139 panic("trying to set frame offset on non load/store node %+F", node);
141 if(!mips_is_Load(node) && !mips_is_Store(node)) {
142 panic("trying to set frame offset on non load/store node %+F", node);
145 attr = get_irn_generic_attr(node);
146 attr->offset += offset;
148 if(attr->offset < -32768 || attr->offset > 32767) {
149 panic("Out of stack space! (mips supports only 16bit offsets)");
153 static int mips_get_sp_bias(const ir_node *irn)
159 /* fill register allocator interface */
161 static const arch_irn_ops_t mips_irn_ops = {
164 mips_get_frame_entity,
165 mips_set_frame_entity,
166 mips_set_frame_offset,
168 NULL, /* get_inverse */
169 NULL, /* get_op_estimated_cost */
170 NULL, /* possible_memory_operand */
171 NULL, /* perform_memory_operand */
174 /**************************************************
177 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
178 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
179 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
180 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
183 **************************************************/
186 * Transforms the standard firm graph into
189 static void mips_prepare_graph(void *self) {
190 mips_code_gen_t *cg = self;
192 /* do local optimizations */
193 optimize_graph_df(cg->irg);
195 /* TODO: we often have dead code reachable through out-edges here. So for
196 * now we rebuild edges (as we need correct user count for code selection)
199 edges_deactivate(cg->irg);
200 edges_activate(cg->irg);
203 // walk the graph and transform firm nodes into mips nodes where possible
204 mips_transform_graph(cg);
205 dump_ir_block_graph_sched(cg->irg, "-transformed");
207 /* do local optimizations (mainly CSE) */
208 optimize_graph_df(cg->irg);
210 /* do code placement, to optimize the position of constants */
213 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
217 * Called immediately before emit phase.
219 static void mips_finish_irg(void *self) {
220 mips_code_gen_t *cg = self;
221 ir_graph *irg = cg->irg;
223 /* create block schedule, this also removes empty blocks which might
224 * produce critical edges */
225 cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
227 dump_ir_block_graph_sched(irg, "-mips-finished");
231 static void mips_before_ra(void *self)
236 static void mips_after_ra(void* self)
238 mips_code_gen_t *cg = self;
239 be_coalesce_spillslots(cg->birg);
240 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
244 * Emits the code, closes the output file and frees
245 * the code generator interface.
247 static void mips_emit_and_done(void *self)
249 mips_code_gen_t *cg = self;
250 ir_graph *irg = cg->irg;
253 mips_gen_routine(cg, irg);
257 /* de-allocate code generator */
258 del_set(cg->reg_set);
262 static void *mips_cg_init(be_irg_t *birg);
264 static const arch_code_generator_if_t mips_code_gen_if = {
266 NULL, /* get_pic_base */
267 NULL, /* before abi introduce */
270 mips_before_ra, /* before register allocation hook */
277 * Initializes the code generator.
279 static void *mips_cg_init(be_irg_t *birg)
281 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
282 mips_isa_t *isa = (mips_isa_t *) arch_env;
283 mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
285 cg->impl = &mips_code_gen_if;
286 cg->irg = be_get_birg_irg(birg);
287 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
291 cur_reg_set = cg->reg_set;
295 return (arch_code_generator_t *)cg;
299 /*****************************************************************
300 * ____ _ _ _____ _____
301 * | _ \ | | | | |_ _|/ ____| /\
302 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
303 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
304 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
305 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
307 *****************************************************************/
309 static mips_isa_t mips_isa_template = {
312 &mips_gp_regs[REG_SP],
313 &mips_gp_regs[REG_FP],
314 &mips_reg_classes[CLASS_mips_gp],
315 -1, /* stack direction */
316 2, /* power of two stack alignment for calls, 2^2 == 4 */
317 NULL, /* main environment */
319 5, /* reload costs */
325 * Initializes the backend ISA and opens the output file.
327 static arch_env_t *mips_init(FILE *file_handle) {
328 static int inited = 0;
335 isa = XMALLOC(mips_isa_t);
336 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
338 be_emit_init(file_handle);
340 mips_register_init();
341 mips_create_opcodes(&mips_irn_ops);
342 // mips_init_opcode_transforms();
344 return &isa->arch_env;
348 * Closes the output file and frees the ISA structure.
350 static void mips_done(void *self)
352 mips_isa_t *isa = self;
354 be_gas_emit_decls(isa->arch_env.main_env);
360 static unsigned mips_get_n_reg_class(void)
365 static const arch_register_class_t *mips_get_reg_class(unsigned i)
367 assert(i < N_CLASSES);
368 return &mips_reg_classes[i];
374 * Get the register class which shall be used to store a value of a given mode.
375 * @param self The this pointer.
376 * @param mode The mode in question.
377 * @return A register class which can hold values of the given mode.
379 const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode)
382 ASSERT_NO_FLOAT(mode);
383 return &mips_reg_classes[CLASS_mips_gp];
387 be_abi_call_flags_bits_t flags;
388 const arch_env_t *arch_env;
390 // do special handling to support debuggers
394 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
396 mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
397 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
398 env->flags = fl.bits;
400 env->arch_env = arch_env;
405 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
407 mips_abi_env_t *env = self;
408 ir_graph *irg = env->irg;
409 ir_node *block = get_irg_start_block(irg);
410 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
411 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
412 int initialstackframesize;
418 * The calling conventions wants a stack frame of at least 24bytes size with
419 * a0-a3 saved in offset 0-12
420 * fp saved in offset 16
421 * ra saved in offset 20
424 ir_node *sync, *reg, *store;
425 initialstackframesize = 24;
427 // - setup first part of stackframe
428 sp = new_bd_mips_addu(NULL, block, sp,
429 mips_create_Immediate(initialstackframesize));
430 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
431 panic("FIXME Use IncSP or set register requirement with ignore");
433 /* TODO: where to get an edge with a0-a3
435 for(i = 0; i < 4; ++i) {
436 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
437 ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T);
438 attr = get_mips_attr(store);
439 attr->load_store_mode = mode_Iu;
440 attr->tv = new_tarval_from_long(i * 4, mode_Is);
442 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
446 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
447 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16);
451 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
452 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20);
456 /* Note: ideally we would route these mem edges directly towards the
457 * epilogue, but this is currently not supported so we sync all mems
459 sync = new_r_Sync(block, 2, mm+4);
462 ir_node *reg, *store;
463 initialstackframesize = 4;
465 // save old framepointer
466 sp = new_bd_mips_addu(NULL, block, sp,
467 mips_create_Immediate(-initialstackframesize));
468 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
469 panic("FIXME Use IncSP or set register requirement with ignore");
471 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
472 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0);
477 // setup framepointer
478 fp = new_bd_mips_addu(NULL, block, sp,
479 mips_create_Immediate(-initialstackframesize));
480 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
481 panic("FIXME Use IncSP or set register requirement with ignore");
483 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
484 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
486 return &mips_gp_regs[REG_SP];
489 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
491 mips_abi_env_t *env = self;
493 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
494 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
496 int initial_frame_size = env->debug ? 24 : 4;
497 int fp_save_offset = env->debug ? 16 : 0;
500 sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
501 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
502 panic("FIXME Use be_Copy or set register requirement with ignore");
505 load = new_bd_mips_lw(NULL, block, sp, *mem, NULL,
506 fp_save_offset - initial_frame_size);
507 panic("FIXME register requirement with ignore");
509 fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res);
510 *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M);
511 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
513 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
514 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
518 * Produces the type which sits between the stack args and the locals on the stack.
519 * it will contain the return address and space to store the old frame pointer.
520 * @return The Firm type modelling the ABI between type.
522 static ir_type *mips_abi_get_between_type(void *self) {
523 mips_abi_env_t *env = self;
525 static ir_type *debug_between_type = NULL;
526 static ir_type *opt_between_type = NULL;
527 static ir_entity *old_fp_ent = NULL;
529 if(env->debug && debug_between_type == NULL) {
530 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
531 ir_entity *ret_addr_ent;
532 ir_type *ret_addr_type = new_type_primitive(mode_P);
533 ir_type *old_fp_type = new_type_primitive(mode_P);
534 ir_type *old_param_type = new_type_primitive(mode_Iu);
536 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
537 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
538 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
539 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
540 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
541 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
542 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
544 set_entity_offset(a0_ent, 0);
545 set_entity_offset(a1_ent, 4);
546 set_entity_offset(a2_ent, 8);
547 set_entity_offset(a3_ent, 12);
548 set_entity_offset(old_fp_ent, 16);
549 set_entity_offset(ret_addr_ent, 20);
551 set_type_size_bytes(debug_between_type, 24);
552 } else if(!env->debug && opt_between_type == NULL) {
553 ir_type *old_fp_type = new_type_primitive(mode_P);
554 ir_entity *old_fp_ent;
556 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
557 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
558 set_entity_offset(old_fp_ent, 0);
559 set_type_size_bytes(opt_between_type, 4);
562 return env->debug ? debug_between_type : opt_between_type;
565 static const be_abi_callbacks_t mips_abi_callbacks = {
568 mips_abi_get_between_type,
574 * Get the ABI restrictions for procedure calls.
575 * @param self The this pointer.
576 * @param method_type The type of the method (procedure) in question.
577 * @param abi The abi object to be modified
579 static void mips_get_call_abi(const void *self, ir_type *method_type,
584 int n = get_method_n_params(method_type);
588 const arch_register_t *reg;
589 be_abi_call_flags_t call_flags;
592 memset(&call_flags, 0, sizeof(call_flags));
593 call_flags.bits.left_to_right = 0;
594 call_flags.bits.store_args_sequential = 0;
595 call_flags.bits.try_omit_fp = 1;
596 call_flags.bits.fp_free = 0;
597 call_flags.bits.call_has_imm = 1;
599 /* set stack parameter passing style */
600 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
602 /* collect the mode for each type */
603 modes = ALLOCAN(ir_mode*, n);
604 for (i = 0; i < n; i++) {
605 tp = get_method_param_type(method_type, i);
606 modes[i] = get_type_mode(tp);
609 // assigns parameters to registers or stack
610 for (i = 0; i < n; i++) {
611 // first 4 params in $a0-$a3, the others on the stack
613 reg = &mips_gp_regs[REG_A0 + i];
614 be_abi_call_param_reg(abi, i, reg);
616 /* default: all parameters on stack */
617 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
621 /* set return register */
622 /* default: return value is in R0 (and maybe R1) */
623 result_count = get_method_n_ress(method_type);
624 assert(result_count <= 2 && "More than 2 result values not supported");
625 for(i = 0; i < result_count; ++i) {
626 const arch_register_t* reg;
627 tp = get_method_res_type(method_type, i);
628 mode = get_type_mode(tp);
629 ASSERT_NO_FLOAT(mode);
631 reg = &mips_gp_regs[REG_V0 + i];
632 be_abi_call_res_reg(abi, i, reg);
637 * Initializes the code generator interface.
639 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
642 return &mips_code_gen_if;
646 * Returns the necessary byte alignment for storing a register of given class.
648 static int mips_get_reg_class_alignment(const arch_register_class_t *cls)
650 ir_mode *mode = arch_register_class_mode(cls);
651 return get_mode_size_bytes(mode);
654 static const be_execution_unit_t ***mips_get_allowed_execution_units(
659 panic("Unimplemented mips_get_allowed_execution_units()");
662 static const be_machine_t *mips_get_machine(const void *self)
666 panic("Unimplemented mips_get_machine()");
670 * Return irp irgs in the desired order.
672 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
680 * Returns the libFirm configuration parameter for this backend.
682 static const backend_params *mips_get_libfirm_params(void) {
683 static backend_params p = {
684 1, /* need dword lowering */
685 0, /* don't support inline assembler yet */
686 NULL, /* will be set later */
687 NULL, /* but yet no creator function */
688 NULL, /* context for create_intrinsic_fkt */
689 NULL, /* no if conversion settings */
690 NULL, /* float arithmetic mode (TODO) */
691 0, /* no trampoline support: size 0 */
692 0, /* no trampoline support: align 0 */
693 NULL, /* no trampoline support: no trampoline builder */
694 4 /* alignment of stack parameter */
700 static asm_constraint_flags_t mips_parse_asm_constraint(const char **c)
703 return ASM_CONSTRAINT_FLAG_INVALID;
706 static int mips_is_valid_clobber(const char *clobber)
712 const arch_isa_if_t mips_isa_if = {
715 NULL, /* handle intrinsics */
716 mips_get_n_reg_class,
718 mips_get_reg_class_for_mode,
720 mips_get_code_generator_if,
721 mips_get_list_sched_selector,
722 mips_get_ilp_sched_selector,
723 mips_get_reg_class_alignment,
724 mips_get_libfirm_params,
725 mips_get_allowed_execution_units,
728 NULL, /* mark remat */
729 mips_parse_asm_constraint,
730 mips_is_valid_clobber
733 void be_init_arch_mips(void)
735 be_register_isa_if("mips", &mips_isa_if);
738 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);