1 /* The main mips backend driver file. */
7 #include "pseudo_irg.h"
22 #include "../bearch_t.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
28 #include "../bemachine.h"
29 #include "../bemodule.h"
31 #include "bearch_mips_t.h"
33 #include "mips_new_nodes.h" /* mips nodes interface */
34 #include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "mips_gen_decls.h" /* interface declaration emitter */
36 #include "mips_transform.h"
37 #include "mips_emitter.h"
38 #include "mips_map_regs.h"
39 #include "mips_util.h"
40 #include "mips_scheduler.h"
42 #define DEBUG_MODULE "firm.be.mips.isa"
44 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
45 static set *cur_reg_set = NULL;
47 /**************************************************
50 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
51 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
52 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
53 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
56 **************************************************/
59 * Return register requirements for a mips node.
60 * If the node returns a tuple (mode_T) then the proj's
61 * will be asked for this information.
64 arch_register_req_t *mips_get_irn_reg_req(const void *self,
65 const ir_node *node, int pos) {
66 long node_pos = pos == -1 ? 0 : pos;
67 ir_mode *mode = get_irn_mode(node);
69 if (is_Block(node) || mode == mode_X || mode == mode_M) {
70 return arch_no_register_req;
73 if (mode == mode_T && pos < 0) {
74 return arch_no_register_req;
78 /* in case of a proj, we need to get the correct OUT slot */
79 /* of the node corresponding to the proj number */
81 node_pos = mips_translate_proj_pos(node);
87 node = skip_Proj_const(node);
90 /* get requirements for our own nodes */
91 if (is_mips_irn(node)) {
92 const arch_register_req_t *req;
94 req = get_mips_in_req(node, pos);
96 req = get_mips_out_req(node, node_pos);
102 /* unknown should be translated by now */
103 assert(!is_Unknown(node));
105 return arch_no_register_req;
108 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
113 if (get_irn_mode(irn) == mode_X) {
117 pos = mips_translate_proj_pos(irn);
118 irn = skip_Proj(irn);
121 if (is_mips_irn(irn)) {
122 const arch_register_t **slots;
124 slots = get_mips_slots(irn);
128 /* here we set the registers for the Phi nodes */
129 mips_set_firm_reg(irn, reg, cur_reg_set);
133 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
135 const arch_register_t *reg = NULL;
139 if (get_irn_mode(irn) == mode_X) {
143 pos = mips_translate_proj_pos(irn);
144 irn = skip_Proj_const(irn);
147 if (is_mips_irn(irn)) {
148 const arch_register_t **slots;
149 slots = get_mips_slots(irn);
153 reg = mips_get_firm_reg(irn, cur_reg_set);
159 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
160 irn = skip_Proj_const(irn);
163 return arch_irn_class_branch;
164 } else if (is_mips_irn(irn)) {
165 return arch_irn_class_normal;
171 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
172 irn = skip_Proj_const(irn);
174 if (is_mips_irn(irn)) {
175 return get_mips_flags(irn);
177 else if (is_Unknown(irn)) {
178 return arch_irn_flags_ignore;
184 static ir_entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
185 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
186 mips_attr_t *attr = get_mips_attr(irn);
188 return attr->stack_entity;
194 static void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
195 mips_attr_t *attr = get_mips_attr(irn);
196 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
197 attr->stack_entity = ent;
201 * This function is called by the generic backend to correct offsets for
202 * nodes accessing the stack.
204 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
205 mips_attr_t *attr = get_mips_attr(irn);
206 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
208 attr->stack_entity_offset = offset;
211 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
215 /* fill register allocator interface */
217 static const arch_irn_ops_if_t mips_irn_ops_if = {
218 mips_get_irn_reg_req,
223 mips_get_frame_entity,
224 mips_set_frame_entity,
225 mips_set_frame_offset,
227 NULL, /* get_inverse */
228 NULL, /* get_op_estimated_cost */
229 NULL, /* possible_memory_operand */
230 NULL, /* perform_memory_operand */
233 mips_irn_ops_t mips_irn_ops = {
240 /**************************************************
243 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
244 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
245 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
246 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
249 **************************************************/
259 * Ext-Block walker: create a block schedule
261 static void create_block_list(ir_extblk *blk, void *env) {
265 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
266 ir_node *block = get_extbb_block(blk, i);
268 set_irn_link(block, NULL);
270 set_irn_link(list->end, block);
279 /* return the scheduled block at position pos */
280 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
281 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
282 return cg->bl_list[pos];
286 /* return the number of scheduled blocks */
287 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
288 return ARR_LEN(cg->bl_list);
291 /* set a block schedule number */
292 void mips_set_block_sched_nr(ir_node *block, int nr) {
293 set_irn_link(block, INT_TO_PTR(nr));
296 /* get a block schedule number */
297 int mips_get_block_sched_nr(ir_node *block) {
298 return PTR_TO_INT(get_irn_link(block));
302 * Creates a block schedule for the given graph.
304 static void mips_create_block_sched(mips_code_gen_t *cg) {
306 ir_node **bl_list, *block;
310 DEL_ARR_F(cg->bl_list);
311 free_survive_dce(cg->bl_list_sdce);
314 /* calculate the block schedule here */
315 compute_extbb(cg->irg);
320 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
323 bl_list = NEW_ARR_F(ir_node *, list.cnt);
324 cg->bl_list_sdce = new_survive_dce();
325 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
327 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
331 cg->bl_list = bl_list;
334 typedef struct _wenv_t {
339 * Walker: link all CopyB nodes
341 static void collect_copyb_nodes(ir_node *node, void *env) {
344 if (get_irn_op(node) == op_CopyB) {
345 set_irn_link(node, wenv->list);
350 static void replace_copyb_nodes(mips_code_gen_t *cg) {
352 ir_node *copy, *next;
353 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
354 const ir_edge_t *edge;
356 /* build code for all copyB */
358 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
360 for (copy = env.list; copy; copy = next) {
361 next = get_irn_link(copy);
363 old_bl = get_nodes_block(copy);
365 jmp = get_Block_cfgpred(old_bl, 0);
366 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
368 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
369 set_nodes_block(jmp, new_bl);
371 mem = gen_code_for_CopyB(new_bl, copy);
373 /* fix copyB's out edges */
374 foreach_out_edge(copy, edge) {
375 ir_node *succ = get_edge_src_irn(edge);
377 assert(is_Proj(succ));
378 switch (get_Proj_proj(succ)) {
379 case pn_CopyB_M_regular:
380 case pn_CopyB_M_except:
384 exchange(succ, get_irg_bad(cg->irg));
391 * Transforms the standard firm graph into
394 static void mips_prepare_graph(void *self) {
395 mips_code_gen_t *cg = self;
398 // replace all copyb nodes in the block with a loop
399 // and mips store/load nodes
400 replace_copyb_nodes(cg);
402 // Calculate block schedule
403 mips_create_block_sched(cg);
405 /* enter the block number into every blocks link field */
406 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
407 ir_node *bl = mips_get_sched_block(cg, bl_nr);
408 mips_set_block_sched_nr(bl, bl_nr);
411 // walk the graph and transform firm nodes into mips nodes where possible
412 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
414 dump_ir_block_graph_sched(cg->irg, "-transformed");
418 * Called immediately before emit phase.
420 static void mips_finish_irg(void *self) {
421 mips_code_gen_t *cg = self;
422 ir_graph *irg = cg->irg;
424 dump_ir_block_graph_sched(irg, "-mips-finished");
429 * These are some hooks which must be filled but are probably not needed.
431 static void mips_before_sched(void *self) {
432 /* Some stuff you need to do after scheduling but before register allocation */
435 static void mips_before_ra(void *self) {
436 /* Some stuff you need to do immediately after register allocation */
439 static void mips_after_ra(void* self) {
440 mips_code_gen_t *cg = self;
441 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
445 * Emits the code, closes the output file and frees
446 * the code generator interface.
448 static void mips_emit_and_done(void *self) {
449 mips_code_gen_t *cg = self;
450 ir_graph *irg = cg->irg;
451 FILE *out = cg->isa->out;
453 mips_register_emitters();
455 if (cg->emit_decls) {
460 mips_gen_routine(out, irg, cg);
464 /* de-allocate code generator */
465 del_set(cg->reg_set);
467 DEL_ARR_F(cg->bl_list);
468 free_survive_dce(cg->bl_list_sdce);
473 static void *mips_cg_init(be_irg_t *birg);
475 static const arch_code_generator_if_t mips_code_gen_if = {
477 NULL, /* before abi introduce */
480 mips_before_sched, /* before scheduling hook */
481 mips_before_ra, /* before register allocation hook */
488 * Initializes the code generator.
490 static void *mips_cg_init(be_irg_t *birg) {
491 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
492 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
493 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
495 cg->impl = &mips_code_gen_if;
496 cg->irg = be_get_birg_irg(birg);
497 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
498 cg->arch_env = arch_env;
502 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
506 if (isa->num_codegens > 1)
511 cur_reg_set = cg->reg_set;
513 mips_irn_ops.cg = cg;
515 return (arch_code_generator_t *)cg;
519 /*****************************************************************
520 * ____ _ _ _____ _____
521 * | _ \ | | | | |_ _|/ ____| /\
522 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
523 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
524 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
525 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
527 *****************************************************************/
529 static mips_isa_t mips_isa_template = {
531 &mips_gp_regs[REG_SP],
532 &mips_gp_regs[REG_FP],
533 -1, // stack direction
534 0, // num codegens?!? TODO what is this?
539 * Initializes the backend ISA and opens the output file.
541 static void *mips_init(FILE *file_handle) {
542 static int inited = 0;
548 isa = xcalloc(1, sizeof(*isa));
549 memcpy(isa, &mips_isa_template, sizeof(*isa));
551 isa->out = file_handle;
553 mips_register_init(isa);
554 mips_create_opcodes();
555 mips_init_opcode_transforms();
563 * Closes the output file and frees the ISA structure.
565 static void mips_done(void *self) {
569 static int mips_get_n_reg_class(const void *self) {
573 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
574 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
575 return &mips_reg_classes[i];
581 * Get the register class which shall be used to store a value of a given mode.
582 * @param self The this pointer.
583 * @param mode The mode in question.
584 * @return A register class which can hold values of the given mode.
586 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
587 ASSERT_NO_FLOAT(mode);
588 return &mips_reg_classes[CLASS_mips_gp];
592 be_abi_call_flags_bits_t flags;
593 const mips_isa_t *isa;
594 const arch_env_t *arch_env;
596 // do special handling to support debuggers
600 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
602 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
603 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
604 env->flags = fl.bits;
606 env->arch_env = arch_env;
607 env->isa = (const mips_isa_t*) arch_env->isa;
612 static void mips_abi_dont_save_regs(void *self, pset *s)
614 mips_abi_env_t *env = self;
615 if(env->flags.try_omit_fp)
616 pset_insert_ptr(s, env->isa->fp);
619 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
621 mips_abi_env_t *env = self;
622 ir_graph *irg = env->irg;
623 dbg_info *dbg = NULL; // TODO where can I get this from?
624 ir_node *block = get_irg_start_block(env->irg);
626 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
627 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
628 int initialstackframesize;
632 * The calling conventions wants a stack frame of at least 24bytes size with
633 * a0-a3 saved in offset 0-12
634 * fp saved in offset 16
635 * ra saved in offset 20
638 ir_node *sync, *reg, *store;
639 initialstackframesize = 24;
641 // - setup first part of stackframe
642 sp = new_rd_mips_addiu(dbg, irg, block, sp);
643 attr = get_mips_attr(sp);
644 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
645 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
646 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
648 /* TODO: where to get an edge with a0-a3
650 for(i = 0; i < 4; ++i) {
651 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
652 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
653 attr = get_mips_attr(store);
654 attr->load_store_mode = mode_Iu;
655 attr->tv = new_tarval_from_long(i * 4, mode_Is);
657 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
661 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
662 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
663 attr = get_mips_attr(store);
664 attr->modes.load_store_mode = mode_Iu;
665 attr->tv = new_tarval_from_long(16, mode_Is);
667 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
669 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
670 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
671 attr = get_mips_attr(store);
672 attr->modes.load_store_mode = mode_Iu;
673 attr->tv = new_tarval_from_long(20, mode_Is);
675 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
677 // TODO ideally we would route these mem edges directly towards the epilogue
678 sync = new_r_Sync(irg, block, 2, mm+4);
681 ir_node *reg, *store;
682 initialstackframesize = 4;
684 // save old framepointer
685 sp = new_rd_mips_addiu(dbg, irg, block, sp);
686 attr = get_mips_attr(sp);
687 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
688 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
689 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
691 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
692 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
693 attr = get_mips_attr(store);
694 attr->modes.load_store_mode = mode_Iu;
695 attr->tv = new_tarval_from_long(0, mode_Is);
697 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
700 // setup framepointer
701 fp = new_rd_mips_addiu(dbg, irg, block, sp);
702 attr = get_mips_attr(fp);
703 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
704 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
705 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
707 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
708 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
710 return &mips_gp_regs[REG_SP];
713 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
715 mips_abi_env_t *env = self;
716 ir_graph *irg = env->irg;
717 dbg_info *dbg = NULL; // TODO where can I get this from?
719 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
720 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
722 int initial_frame_size = env->debug ? 24 : 4;
723 int fp_save_offset = env->debug ? 16 : 0;
726 sp = new_rd_mips_move(dbg, irg, block, fp);
727 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
728 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
731 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
732 attr = get_mips_attr(load);
733 attr->modes.load_store_mode = mode_Iu;
734 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
735 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
737 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
738 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
739 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
741 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
742 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
746 * Produces the type which sits between the stack args and the locals on the stack.
747 * it will contain the return address and space to store the old frame pointer.
748 * @return The Firm type modelling the ABI between type.
750 static ir_type *mips_abi_get_between_type(void *self) {
751 mips_abi_env_t *env = self;
753 static ir_type *debug_between_type = NULL;
754 static ir_type *opt_between_type = NULL;
755 static ir_entity *old_fp_ent = NULL;
757 if(env->debug && debug_between_type == NULL) {
758 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
759 ir_entity *ret_addr_ent;
760 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
761 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
762 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
764 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
765 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
766 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
767 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
768 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
769 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
770 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
772 set_entity_offset(a0_ent, 0);
773 set_entity_offset(a1_ent, 4);
774 set_entity_offset(a2_ent, 8);
775 set_entity_offset(a3_ent, 12);
776 set_entity_offset(old_fp_ent, 16);
777 set_entity_offset(ret_addr_ent, 20);
779 set_type_size_bytes(debug_between_type, 24);
780 } else if(!env->debug && opt_between_type == NULL) {
781 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
782 ir_entity *old_fp_ent;
784 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
785 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
786 set_entity_offset(old_fp_ent, 0);
787 set_type_size_bytes(opt_between_type, 4);
790 return env->debug ? debug_between_type : opt_between_type;
793 static const be_abi_callbacks_t mips_abi_callbacks = {
796 mips_abi_get_between_type,
797 mips_abi_dont_save_regs,
803 * Get the ABI restrictions for procedure calls.
804 * @param self The this pointer.
805 * @param method_type The type of the method (procedure) in question.
806 * @param abi The abi object to be modified
808 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
811 int n = get_method_n_params(method_type);
815 const arch_register_t *reg;
816 be_abi_call_flags_t call_flags;
818 memset(&call_flags, 0, sizeof(call_flags));
819 call_flags.bits.left_to_right = 0;
820 call_flags.bits.store_args_sequential = 0;
821 call_flags.bits.try_omit_fp = 1;
822 call_flags.bits.fp_free = 0;
823 call_flags.bits.call_has_imm = 1;
825 /* set stack parameter passing style */
826 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
828 /* collect the mode for each type */
829 modes = alloca(n * sizeof(modes[0]));
830 for (i = 0; i < n; i++) {
831 tp = get_method_param_type(method_type, i);
832 modes[i] = get_type_mode(tp);
835 // assigns parameters to registers or stack
836 for (i = 0; i < n; i++) {
837 // first 4 params in $a0-$a3, the others on the stack
839 reg = &mips_gp_regs[REG_A0 + i];
840 be_abi_call_param_reg(abi, i, reg);
842 /* default: all parameters on stack */
843 be_abi_call_param_stack(abi, i, 4, 0, 0);
847 /* set return register */
848 /* default: return value is in R0 (and maybe R1) */
849 result_count = get_method_n_ress(method_type);
850 assert(result_count <= 2 && "More than 2 result values not supported");
851 for(i = 0; i < result_count; ++i) {
852 const arch_register_t* reg;
853 tp = get_method_res_type(method_type, i);
854 mode = get_type_mode(tp);
855 ASSERT_NO_FLOAT(mode);
857 reg = &mips_gp_regs[REG_V0 + i];
858 be_abi_call_res_reg(abi, i, reg);
862 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
863 return &mips_irn_ops;
866 const arch_irn_handler_t mips_irn_handler = {
870 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
871 return &mips_irn_handler;
875 * Initializes the code generator interface.
877 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
878 return &mips_code_gen_if;
882 * Returns the necessary byte alignment for storing a register of given class.
884 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
885 ir_mode *mode = arch_register_class_mode(cls);
886 return get_mode_size_bytes(mode);
889 static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
895 static const be_machine_t *mips_get_machine(const void *self) {
902 * Return irp irgs in the desired order.
904 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) {
909 * Returns the libFirm configuration parameter for this backend.
911 static const backend_params *mips_get_libfirm_params(void) {
912 static arch_dep_params_t ad = {
914 0, /* Muls are fast enough on Mips */
915 31, /* shift would be ok */
918 32, /* Mulhs & Mulhu available for 32 bit */
920 static backend_params p = {
921 NULL, /* no additional opcodes */
922 NULL, /* will be set later */
923 1, /* need dword lowering */
924 NULL, /* but yet no creator function */
925 NULL, /* context for create_intrinsic_fkt */
932 const arch_isa_if_t mips_isa_if = {
935 mips_get_n_reg_class,
937 mips_get_reg_class_for_mode,
939 mips_get_irn_handler,
940 mips_get_code_generator_if,
941 mips_get_list_sched_selector,
942 mips_get_ilp_sched_selector,
943 mips_get_reg_class_alignment,
944 mips_get_libfirm_params,
945 mips_get_allowed_execution_units,
950 void be_init_arch_mips(void)
952 be_register_isa_if("mips", &mips_isa_if);
955 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);