2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
28 #include "pseudo_irg.h"
45 #include "../bearch.h"
46 #include "../benode.h"
47 #include "../belower.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
85 static arch_irn_class_t mips_classify(const ir_node *irn)
91 int mips_is_Load(const ir_node *node)
93 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
94 is_mips_lb(node) || is_mips_lbu(node);
97 int mips_is_Store(const ir_node *node)
99 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
102 static ir_entity *mips_get_frame_entity(const ir_node *node)
104 const mips_load_store_attr_t *attr;
106 if (!is_mips_irn(node))
108 if (!mips_is_Load(node) && !mips_is_Store(node))
111 attr = get_mips_load_store_attr_const(node);
112 return attr->stack_entity;
115 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
117 mips_load_store_attr_t *attr;
119 if (!is_mips_irn(node)) {
120 panic("trying to set frame entity on non load/store node %+F", node);
122 if (!mips_is_Load(node) && !mips_is_Store(node)) {
123 panic("trying to set frame entity on non load/store node %+F", node);
126 attr = get_irn_generic_attr(node);
127 attr->stack_entity = entity;
131 * This function is called by the generic backend to correct offsets for
132 * nodes accessing the stack.
134 static void mips_set_frame_offset(ir_node *node, int offset)
136 mips_load_store_attr_t *attr;
138 if (!is_mips_irn(node)) {
139 panic("trying to set frame offset on non load/store node %+F", node);
141 if (!mips_is_Load(node) && !mips_is_Store(node)) {
142 panic("trying to set frame offset on non load/store node %+F", node);
145 attr = get_irn_generic_attr(node);
146 attr->offset += offset;
148 if (attr->offset < -32768 || attr->offset > 32767) {
149 panic("Out of stack space! (mips supports only 16bit offsets)");
153 static int mips_get_sp_bias(const ir_node *irn)
159 /* fill register allocator interface */
161 static const arch_irn_ops_t mips_irn_ops = {
164 mips_get_frame_entity,
165 mips_set_frame_entity,
166 mips_set_frame_offset,
168 NULL, /* get_inverse */
169 NULL, /* get_op_estimated_cost */
170 NULL, /* possible_memory_operand */
171 NULL, /* perform_memory_operand */
174 /**************************************************
177 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
178 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
179 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
180 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
183 **************************************************/
186 * Transforms the standard firm graph into
189 static void mips_prepare_graph(void *self)
191 mips_code_gen_t *cg = self;
193 /* do local optimizations */
194 optimize_graph_df(cg->irg);
196 /* TODO: we often have dead code reachable through out-edges here. So for
197 * now we rebuild edges (as we need correct user count for code selection)
200 edges_deactivate(cg->irg);
201 edges_activate(cg->irg);
204 // walk the graph and transform firm nodes into mips nodes where possible
205 mips_transform_graph(cg);
206 dump_ir_block_graph_sched(cg->irg, "-transformed");
208 /* do local optimizations (mainly CSE) */
209 optimize_graph_df(cg->irg);
211 /* do code placement, to optimize the position of constants */
214 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
218 * Called immediately before emit phase.
220 static void mips_finish_irg(void *self)
222 mips_code_gen_t *cg = self;
223 ir_graph *irg = cg->irg;
225 /* create block schedule, this also removes empty blocks which might
226 * produce critical edges */
227 cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
229 dump_ir_block_graph_sched(irg, "-mips-finished");
233 static void mips_before_ra(void *self)
238 static void mips_after_ra(void* self)
240 mips_code_gen_t *cg = self;
241 be_coalesce_spillslots(cg->birg);
242 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
246 * Emits the code, closes the output file and frees
247 * the code generator interface.
249 static void mips_emit_and_done(void *self)
251 mips_code_gen_t *cg = self;
252 ir_graph *irg = cg->irg;
255 mips_gen_routine(cg, irg);
259 /* de-allocate code generator */
260 del_set(cg->reg_set);
264 static void *mips_cg_init(be_irg_t *birg);
266 static const arch_code_generator_if_t mips_code_gen_if = {
268 NULL, /* get_pic_base */
269 NULL, /* before abi introduce */
272 mips_before_ra, /* before register allocation hook */
279 * Initializes the code generator.
281 static void *mips_cg_init(be_irg_t *birg)
283 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
284 mips_isa_t *isa = (mips_isa_t *) arch_env;
285 mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
287 cg->impl = &mips_code_gen_if;
288 cg->irg = be_get_birg_irg(birg);
289 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
293 cur_reg_set = cg->reg_set;
297 return (arch_code_generator_t *)cg;
301 /*****************************************************************
302 * ____ _ _ _____ _____
303 * | _ \ | | | | |_ _|/ ____| /\
304 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
305 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
306 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
307 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
309 *****************************************************************/
311 static mips_isa_t mips_isa_template = {
314 &mips_gp_regs[REG_SP],
315 &mips_gp_regs[REG_FP],
316 &mips_reg_classes[CLASS_mips_gp],
317 -1, /* stack direction */
318 2, /* power of two stack alignment for calls, 2^2 == 4 */
319 NULL, /* main environment */
321 5, /* reload costs */
327 * Initializes the backend ISA and opens the output file.
329 static arch_env_t *mips_init(FILE *file_handle)
331 static int inited = 0;
338 isa = XMALLOC(mips_isa_t);
339 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
341 be_emit_init(file_handle);
343 mips_register_init();
344 mips_create_opcodes(&mips_irn_ops);
345 // mips_init_opcode_transforms();
347 return &isa->arch_env;
351 * Closes the output file and frees the ISA structure.
353 static void mips_done(void *self)
355 mips_isa_t *isa = self;
357 be_gas_emit_decls(isa->arch_env.main_env);
363 static unsigned mips_get_n_reg_class(void)
368 static const arch_register_class_t *mips_get_reg_class(unsigned i)
370 assert(i < N_CLASSES);
371 return &mips_reg_classes[i];
377 * Get the register class which shall be used to store a value of a given mode.
378 * @param self The this pointer.
379 * @param mode The mode in question.
380 * @return A register class which can hold values of the given mode.
382 const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode)
385 ASSERT_NO_FLOAT(mode);
386 return &mips_reg_classes[CLASS_mips_gp];
390 be_abi_call_flags_bits_t flags;
391 const arch_env_t *arch_env;
393 // do special handling to support debuggers
397 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
399 mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
400 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
401 env->flags = fl.bits;
403 env->arch_env = arch_env;
408 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
410 mips_abi_env_t *env = self;
411 ir_graph *irg = env->irg;
412 ir_node *block = get_irg_start_block(irg);
413 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
414 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
415 int initialstackframesize;
421 * The calling conventions wants a stack frame of at least 24bytes size with
422 * a0-a3 saved in offset 0-12
423 * fp saved in offset 16
424 * ra saved in offset 20
427 ir_node *sync, *reg, *store;
428 initialstackframesize = 24;
430 // - setup first part of stackframe
431 sp = new_bd_mips_addu(NULL, block, sp,
432 mips_create_Immediate(initialstackframesize));
433 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
434 panic("FIXME Use IncSP or set register requirement with ignore");
436 /* TODO: where to get an edge with a0-a3
438 for (i = 0; i < 4; ++i) {
439 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
440 ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T);
441 attr = get_mips_attr(store);
442 attr->load_store_mode = mode_Iu;
443 attr->tv = new_tarval_from_long(i * 4, mode_Is);
445 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
449 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
450 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16);
454 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
455 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20);
459 /* Note: ideally we would route these mem edges directly towards the
460 * epilogue, but this is currently not supported so we sync all mems
462 sync = new_r_Sync(block, 2, mm+4);
465 ir_node *reg, *store;
466 initialstackframesize = 4;
468 // save old framepointer
469 sp = new_bd_mips_addu(NULL, block, sp,
470 mips_create_Immediate(-initialstackframesize));
471 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
472 panic("FIXME Use IncSP or set register requirement with ignore");
474 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
475 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0);
480 // setup framepointer
481 fp = new_bd_mips_addu(NULL, block, sp,
482 mips_create_Immediate(-initialstackframesize));
483 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
484 panic("FIXME Use IncSP or set register requirement with ignore");
486 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
487 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
489 return &mips_gp_regs[REG_SP];
492 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
494 mips_abi_env_t *env = self;
496 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
497 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
499 int initial_frame_size = env->debug ? 24 : 4;
500 int fp_save_offset = env->debug ? 16 : 0;
503 sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
504 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
505 panic("FIXME Use be_Copy or set register requirement with ignore");
508 load = new_bd_mips_lw(NULL, block, sp, *mem, NULL,
509 fp_save_offset - initial_frame_size);
510 panic("FIXME register requirement with ignore");
512 fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res);
513 *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M);
514 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
516 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
517 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
521 * Produces the type which sits between the stack args and the locals on the stack.
522 * it will contain the return address and space to store the old frame pointer.
523 * @return The Firm type modelling the ABI between type.
525 static ir_type *mips_abi_get_between_type(void *self)
527 mips_abi_env_t *env = self;
529 static ir_type *debug_between_type = NULL;
530 static ir_type *opt_between_type = NULL;
531 static ir_entity *old_fp_ent = NULL;
533 if (env->debug && debug_between_type == NULL) {
534 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
535 ir_entity *ret_addr_ent;
536 ir_type *ret_addr_type = new_type_primitive(mode_P);
537 ir_type *old_fp_type = new_type_primitive(mode_P);
538 ir_type *old_param_type = new_type_primitive(mode_Iu);
540 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
541 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
542 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
543 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
544 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
545 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
546 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
548 set_entity_offset(a0_ent, 0);
549 set_entity_offset(a1_ent, 4);
550 set_entity_offset(a2_ent, 8);
551 set_entity_offset(a3_ent, 12);
552 set_entity_offset(old_fp_ent, 16);
553 set_entity_offset(ret_addr_ent, 20);
555 set_type_size_bytes(debug_between_type, 24);
556 } else if (!env->debug && opt_between_type == NULL) {
557 ir_type *old_fp_type = new_type_primitive(mode_P);
558 ir_entity *old_fp_ent;
560 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
561 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
562 set_entity_offset(old_fp_ent, 0);
563 set_type_size_bytes(opt_between_type, 4);
566 return env->debug ? debug_between_type : opt_between_type;
569 static const be_abi_callbacks_t mips_abi_callbacks = {
572 mips_abi_get_between_type,
578 * Get the ABI restrictions for procedure calls.
579 * @param self The this pointer.
580 * @param method_type The type of the method (procedure) in question.
581 * @param abi The abi object to be modified
583 static void mips_get_call_abi(const void *self, ir_type *method_type,
588 int n = get_method_n_params(method_type);
592 const arch_register_t *reg;
593 be_abi_call_flags_t call_flags;
596 memset(&call_flags, 0, sizeof(call_flags));
597 call_flags.bits.left_to_right = 0;
598 call_flags.bits.store_args_sequential = 0;
599 call_flags.bits.try_omit_fp = 1;
600 call_flags.bits.fp_free = 0;
601 call_flags.bits.call_has_imm = 1;
603 /* set stack parameter passing style */
604 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
606 /* collect the mode for each type */
607 modes = ALLOCAN(ir_mode*, n);
608 for (i = 0; i < n; i++) {
609 tp = get_method_param_type(method_type, i);
610 modes[i] = get_type_mode(tp);
613 // assigns parameters to registers or stack
614 for (i = 0; i < n; i++) {
615 // first 4 params in $a0-$a3, the others on the stack
617 reg = &mips_gp_regs[REG_A0 + i];
618 be_abi_call_param_reg(abi, i, reg);
620 /* default: all parameters on stack */
621 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
625 /* set return register */
626 /* default: return value is in R0 (and maybe R1) */
627 result_count = get_method_n_ress(method_type);
628 assert(result_count <= 2 && "More than 2 result values not supported");
629 for (i = 0; i < result_count; ++i) {
630 const arch_register_t* reg;
631 tp = get_method_res_type(method_type, i);
632 mode = get_type_mode(tp);
633 ASSERT_NO_FLOAT(mode);
635 reg = &mips_gp_regs[REG_V0 + i];
636 be_abi_call_res_reg(abi, i, reg);
641 * Initializes the code generator interface.
643 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
646 return &mips_code_gen_if;
650 * Returns the necessary byte alignment for storing a register of given class.
652 static int mips_get_reg_class_alignment(const arch_register_class_t *cls)
654 ir_mode *mode = arch_register_class_mode(cls);
655 return get_mode_size_bytes(mode);
658 static const be_execution_unit_t ***mips_get_allowed_execution_units(
663 panic("Unimplemented mips_get_allowed_execution_units()");
666 static const be_machine_t *mips_get_machine(const void *self)
670 panic("Unimplemented mips_get_machine()");
674 * Return irp irgs in the desired order.
676 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
684 * Returns the libFirm configuration parameter for this backend.
686 static const backend_params *mips_get_libfirm_params(void)
688 static backend_params p = {
689 1, /* need dword lowering */
690 0, /* don't support inline assembler yet */
691 NULL, /* will be set later */
692 NULL, /* but yet no creator function */
693 NULL, /* context for create_intrinsic_fkt */
694 NULL, /* no if conversion settings */
695 NULL, /* float arithmetic mode (TODO) */
696 0, /* no trampoline support: size 0 */
697 0, /* no trampoline support: align 0 */
698 NULL, /* no trampoline support: no trampoline builder */
699 4 /* alignment of stack parameter */
705 static asm_constraint_flags_t mips_parse_asm_constraint(const char **c)
708 return ASM_CONSTRAINT_FLAG_INVALID;
711 static int mips_is_valid_clobber(const char *clobber)
717 const arch_isa_if_t mips_isa_if = {
720 NULL, /* handle intrinsics */
721 mips_get_n_reg_class,
723 mips_get_reg_class_for_mode,
725 mips_get_code_generator_if,
726 mips_get_list_sched_selector,
727 mips_get_ilp_sched_selector,
728 mips_get_reg_class_alignment,
729 mips_get_libfirm_params,
730 mips_get_allowed_execution_units,
733 NULL, /* mark remat */
734 mips_parse_asm_constraint,
735 mips_is_valid_clobber
738 void be_init_arch_mips(void)
740 be_register_isa_if("mips", &mips_isa_if);
743 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);