2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
30 #include "pseudo_irg.h"
46 #include "../bearch_t.h"
47 #include "../benode_t.h"
48 #include "../belower.h"
49 #include "../besched_t.h"
52 #include "../bemachine.h"
53 #include "../bemodule.h"
54 #include "../bespillslots.h"
55 #include "../beemitter.h"
56 #include "../begnuas.h"
58 #include "bearch_mips_t.h"
60 #include "mips_new_nodes.h"
61 #include "gen_mips_regalloc_if.h"
62 #include "mips_transform.h"
63 #include "mips_emitter.h"
64 #include "mips_map_regs.h"
65 #include "mips_util.h"
66 #include "mips_scheduler.h"
68 #define DEBUG_MODULE "firm.be.mips.isa"
70 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
71 static set *cur_reg_set = NULL;
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
85 * Return register requirements for a mips node.
86 * If the node returns a tuple (mode_T) then the proj's
87 * will be asked for this information.
90 arch_register_req_t *mips_get_irn_reg_req(const void *self,
91 const ir_node *node, int pos) {
92 long node_pos = pos == -1 ? 0 : pos;
93 ir_mode *mode = get_irn_mode(node);
95 if (is_Block(node) || mode == mode_X || mode == mode_M) {
96 return arch_no_register_req;
99 if (mode == mode_T && pos < 0) {
100 return arch_no_register_req;
104 /* in case of a proj, we need to get the correct OUT slot */
105 /* of the node corresponding to the proj number */
107 node_pos = mips_translate_proj_pos(node);
113 node = skip_Proj_const(node);
116 /* get requirements for our own nodes */
117 if (is_mips_irn(node)) {
118 const arch_register_req_t *req;
120 req = get_mips_in_req(node, pos);
122 req = get_mips_out_req(node, node_pos);
128 /* unknown should be translated by now */
129 assert(!is_Unknown(node));
131 return arch_no_register_req;
134 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
139 if (get_irn_mode(irn) == mode_X) {
143 pos = mips_translate_proj_pos(irn);
144 irn = skip_Proj(irn);
147 if (is_mips_irn(irn)) {
148 const arch_register_t **slots;
150 slots = get_mips_slots(irn);
154 /* here we set the registers for the Phi nodes */
155 mips_set_firm_reg(irn, reg, cur_reg_set);
159 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
161 const arch_register_t *reg = NULL;
165 if (get_irn_mode(irn) == mode_X) {
169 pos = mips_translate_proj_pos(irn);
170 irn = skip_Proj_const(irn);
173 if (is_mips_irn(irn)) {
174 const arch_register_t **slots;
175 slots = get_mips_slots(irn);
179 reg = mips_get_firm_reg(irn, cur_reg_set);
185 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
186 irn = skip_Proj_const(irn);
189 return arch_irn_class_branch;
190 } else if (is_mips_irn(irn)) {
191 return arch_irn_class_normal;
197 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
198 irn = skip_Proj_const(irn);
200 if (is_mips_irn(irn)) {
201 return get_mips_flags(irn);
203 else if (is_Unknown(irn)) {
204 return arch_irn_flags_ignore;
211 ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) {
214 if(!is_mips_irn(node))
217 attr = get_mips_attr(node);
218 return attr->stack_entity;
222 void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
223 mips_attr_t *attr = get_mips_attr(irn);
224 attr->stack_entity = ent;
228 * This function is called by the generic backend to correct offsets for
229 * nodes accessing the stack.
231 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset)
235 mips_attr_t *attr = get_mips_attr(irn);
236 attr->stack_entity_offset = offset;
240 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
244 /* fill register allocator interface */
246 static const arch_irn_ops_if_t mips_irn_ops_if = {
247 mips_get_irn_reg_req,
252 mips_get_frame_entity,
253 mips_set_frame_entity,
254 mips_set_frame_offset,
256 NULL, /* get_inverse */
257 NULL, /* get_op_estimated_cost */
258 NULL, /* possible_memory_operand */
259 NULL, /* perform_memory_operand */
262 mips_irn_ops_t mips_irn_ops = {
269 /**************************************************
272 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
273 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
274 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
275 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
278 **************************************************/
288 * Ext-Block walker: create a block schedule
290 static void create_block_list(ir_extblk *blk, void *env) {
294 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
295 ir_node *block = get_extbb_block(blk, i);
297 set_irn_link(block, NULL);
299 set_irn_link(list->end, block);
308 /* return the scheduled block at position pos */
309 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
310 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
311 return cg->bl_list[pos];
315 /* return the number of scheduled blocks */
316 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
317 return ARR_LEN(cg->bl_list);
320 /* set a block schedule number */
321 void mips_set_block_sched_nr(ir_node *block, int nr) {
322 set_irn_link(block, INT_TO_PTR(nr));
325 /* get a block schedule number */
326 int mips_get_block_sched_nr(ir_node *block) {
327 return PTR_TO_INT(get_irn_link(block));
331 * Creates a block schedule for the given graph.
333 static void mips_create_block_sched(mips_code_gen_t *cg) {
335 ir_node **bl_list, *block;
339 DEL_ARR_F(cg->bl_list);
340 free_survive_dce(cg->bl_list_sdce);
343 /* calculate the block schedule here */
344 compute_extbb(cg->irg);
349 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
352 bl_list = NEW_ARR_F(ir_node *, list.cnt);
353 cg->bl_list_sdce = new_survive_dce();
354 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
356 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
360 cg->bl_list = bl_list;
364 typedef struct _wenv_t {
369 * Walker: link all CopyB nodes
371 static void collect_copyb_nodes(ir_node *node, void *env) {
374 if (get_irn_op(node) == op_CopyB) {
375 set_irn_link(node, wenv->list);
381 static void replace_copyb_nodes(mips_code_gen_t *cg) {
384 ir_node *copy, *next;
385 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
386 const ir_edge_t *edge;
388 /* build code for all copyB */
390 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
392 for (copy = env.list; copy; copy = next) {
393 next = get_irn_link(copy);
395 old_bl = get_nodes_block(copy);
397 jmp = get_Block_cfgpred(old_bl, 0);
398 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
400 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
401 set_nodes_block(jmp, new_bl);
403 mem = gen_code_for_CopyB(new_bl, copy);
405 /* fix copyB's out edges */
406 foreach_out_edge(copy, edge) {
407 ir_node *succ = get_edge_src_irn(edge);
409 assert(is_Proj(succ));
410 switch (get_Proj_proj(succ)) {
411 case pn_CopyB_M_regular:
412 case pn_CopyB_M_except:
416 exchange(succ, get_irg_bad(cg->irg));
425 * Transforms the standard firm graph into
428 static void mips_prepare_graph(void *self) {
429 mips_code_gen_t *cg = self;
432 // replace all copyb nodes in the block with a loop
433 // and mips store/load nodes
434 replace_copyb_nodes(cg);
436 // Calculate block schedule
437 mips_create_block_sched(cg);
439 /* enter the block number into every blocks link field */
440 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
441 ir_node *bl = mips_get_sched_block(cg, bl_nr);
442 mips_set_block_sched_nr(bl, bl_nr);
445 // walk the graph and transform firm nodes into mips nodes where possible
446 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
448 dump_ir_block_graph_sched(cg->irg, "-transformed");
452 * Called immediately before emit phase.
454 static void mips_finish_irg(void *self) {
455 mips_code_gen_t *cg = self;
456 ir_graph *irg = cg->irg;
458 dump_ir_block_graph_sched(irg, "-mips-finished");
463 * These are some hooks which must be filled but are probably not needed.
465 static void mips_before_sched(void *self) {
466 /* Some stuff you need to do after scheduling but before register allocation */
469 static void mips_before_ra(void *self) {
470 /* Some stuff you need to do immediately after register allocation */
473 static void mips_after_ra(void* self) {
474 mips_code_gen_t *cg = self;
475 be_coalesce_spillslots(cg->birg);
476 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
480 * Emits the code, closes the output file and frees
481 * the code generator interface.
483 static void mips_emit_and_done(void *self) {
484 mips_code_gen_t *cg = self;
485 ir_graph *irg = cg->irg;
487 mips_gen_routine(cg, irg);
491 /* de-allocate code generator */
492 del_set(cg->reg_set);
494 DEL_ARR_F(cg->bl_list);
495 free_survive_dce(cg->bl_list_sdce);
500 static void *mips_cg_init(be_irg_t *birg);
502 static const arch_code_generator_if_t mips_code_gen_if = {
504 NULL, /* before abi introduce */
507 mips_before_sched, /* before scheduling hook */
508 mips_before_ra, /* before register allocation hook */
515 * Initializes the code generator.
517 static void *mips_cg_init(be_irg_t *birg) {
518 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
519 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
520 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
522 cg->impl = &mips_code_gen_if;
523 cg->irg = be_get_birg_irg(birg);
524 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
525 cg->arch_env = arch_env;
530 cur_reg_set = cg->reg_set;
532 mips_irn_ops.cg = cg;
534 return (arch_code_generator_t *)cg;
538 /*****************************************************************
539 * ____ _ _ _____ _____
540 * | _ \ | | | | |_ _|/ ____| /\
541 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
542 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
543 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
544 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
546 *****************************************************************/
548 static mips_isa_t mips_isa_template = {
551 &mips_gp_regs[REG_SP],
552 &mips_gp_regs[REG_FP],
553 -1, /* stack direction */
554 NULL, /* main environment */
556 5, /* reload costs */
558 { NULL, }, /* emitter environment */
562 * Initializes the backend ISA and opens the output file.
564 static void *mips_init(FILE *file_handle) {
565 static int inited = 0;
572 isa = xcalloc(1, sizeof(isa[0]));
573 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
575 be_emit_init_env(&isa->emit, file_handle);
577 mips_register_init(isa);
578 mips_create_opcodes();
579 // mips_init_opcode_transforms();
581 /* we mark referenced global entities, so we can only emit those which
582 * are actually referenced. (Note: you mustn't use the type visited flag
583 * elsewhere in the backend)
585 inc_master_type_visited();
591 * Closes the output file and frees the ISA structure.
593 static void mips_done(void *self) {
594 mips_isa_t *isa = self;
596 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
598 be_emit_destroy_env(&isa->emit);
602 static int mips_get_n_reg_class(const void *self) {
606 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
607 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
608 return &mips_reg_classes[i];
614 * Get the register class which shall be used to store a value of a given mode.
615 * @param self The this pointer.
616 * @param mode The mode in question.
617 * @return A register class which can hold values of the given mode.
619 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
620 ASSERT_NO_FLOAT(mode);
621 return &mips_reg_classes[CLASS_mips_gp];
625 be_abi_call_flags_bits_t flags;
626 const arch_isa_t *isa;
627 const arch_env_t *arch_env;
629 // do special handling to support debuggers
633 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
635 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
636 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
637 env->flags = fl.bits;
639 env->arch_env = arch_env;
640 env->isa = arch_env->isa;
645 static void mips_abi_dont_save_regs(void *self, pset *s)
647 mips_abi_env_t *env = self;
649 if(env->flags.try_omit_fp)
650 pset_insert_ptr(s, env->isa->bp);
653 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
655 mips_abi_env_t *env = self;
656 ir_graph *irg = env->irg;
657 dbg_info *dbg = NULL; // TODO where can I get this from?
658 ir_node *block = get_irg_start_block(env->irg);
660 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
661 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
662 int initialstackframesize;
666 * The calling conventions wants a stack frame of at least 24bytes size with
667 * a0-a3 saved in offset 0-12
668 * fp saved in offset 16
669 * ra saved in offset 20
672 ir_node *sync, *reg, *store;
673 initialstackframesize = 24;
675 // - setup first part of stackframe
676 sp = new_rd_mips_addiu(dbg, irg, block, sp);
677 attr = get_mips_attr(sp);
678 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
679 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
680 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
682 /* TODO: where to get an edge with a0-a3
684 for(i = 0; i < 4; ++i) {
685 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
686 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
687 attr = get_mips_attr(store);
688 attr->load_store_mode = mode_Iu;
689 attr->tv = new_tarval_from_long(i * 4, mode_Is);
691 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
695 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
696 store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
697 attr = get_mips_attr(store);
698 attr->tv = new_tarval_from_long(16, mode_Hs);
702 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
703 store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
704 attr = get_mips_attr(store);
705 attr->tv = new_tarval_from_long(20, mode_Hs);
709 // TODO ideally we would route these mem edges directly towards the epilogue
710 sync = new_r_Sync(irg, block, 2, mm+4);
713 ir_node *reg, *store;
714 initialstackframesize = 4;
716 // save old framepointer
717 sp = new_rd_mips_addiu(dbg, irg, block, sp);
718 attr = get_mips_attr(sp);
719 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
720 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
721 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
723 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
724 store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
725 attr = get_mips_attr(store);
726 attr->tv = new_tarval_from_long(0, mode_Hs);
731 // setup framepointer
732 fp = new_rd_mips_addiu(dbg, irg, block, sp);
733 attr = get_mips_attr(fp);
734 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
735 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
736 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
738 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
739 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
741 return &mips_gp_regs[REG_SP];
744 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
746 mips_abi_env_t *env = self;
747 ir_graph *irg = env->irg;
748 dbg_info *dbg = NULL; // TODO where can I get this from?
750 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
751 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
753 int initial_frame_size = env->debug ? 24 : 4;
754 int fp_save_offset = env->debug ? 16 : 0;
757 sp = new_rd_mips_move(dbg, irg, block, fp);
758 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
759 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
762 load = new_rd_mips_lw(dbg, irg, block, *mem, sp);
763 attr = get_mips_attr(load);
764 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
765 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Hs);
767 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
768 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
769 arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]);
771 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
772 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
776 * Produces the type which sits between the stack args and the locals on the stack.
777 * it will contain the return address and space to store the old frame pointer.
778 * @return The Firm type modelling the ABI between type.
780 static ir_type *mips_abi_get_between_type(void *self) {
781 mips_abi_env_t *env = self;
783 static ir_type *debug_between_type = NULL;
784 static ir_type *opt_between_type = NULL;
785 static ir_entity *old_fp_ent = NULL;
787 if(env->debug && debug_between_type == NULL) {
788 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
789 ir_entity *ret_addr_ent;
790 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
791 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
792 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
794 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
795 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
796 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
797 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
798 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
799 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
800 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
802 set_entity_offset(a0_ent, 0);
803 set_entity_offset(a1_ent, 4);
804 set_entity_offset(a2_ent, 8);
805 set_entity_offset(a3_ent, 12);
806 set_entity_offset(old_fp_ent, 16);
807 set_entity_offset(ret_addr_ent, 20);
809 set_type_size_bytes(debug_between_type, 24);
810 } else if(!env->debug && opt_between_type == NULL) {
811 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
812 ir_entity *old_fp_ent;
814 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
815 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
816 set_entity_offset(old_fp_ent, 0);
817 set_type_size_bytes(opt_between_type, 4);
820 return env->debug ? debug_between_type : opt_between_type;
823 static const be_abi_callbacks_t mips_abi_callbacks = {
826 mips_abi_get_between_type,
827 mips_abi_dont_save_regs,
833 * Get the ABI restrictions for procedure calls.
834 * @param self The this pointer.
835 * @param method_type The type of the method (procedure) in question.
836 * @param abi The abi object to be modified
838 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
841 int n = get_method_n_params(method_type);
845 const arch_register_t *reg;
846 be_abi_call_flags_t call_flags;
848 memset(&call_flags, 0, sizeof(call_flags));
849 call_flags.bits.left_to_right = 0;
850 call_flags.bits.store_args_sequential = 0;
851 call_flags.bits.try_omit_fp = 1;
852 call_flags.bits.fp_free = 0;
853 call_flags.bits.call_has_imm = 1;
855 /* set stack parameter passing style */
856 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
858 /* collect the mode for each type */
859 modes = alloca(n * sizeof(modes[0]));
860 for (i = 0; i < n; i++) {
861 tp = get_method_param_type(method_type, i);
862 modes[i] = get_type_mode(tp);
865 // assigns parameters to registers or stack
866 for (i = 0; i < n; i++) {
867 // first 4 params in $a0-$a3, the others on the stack
869 reg = &mips_gp_regs[REG_A0 + i];
870 be_abi_call_param_reg(abi, i, reg);
872 /* default: all parameters on stack */
873 be_abi_call_param_stack(abi, i, 4, 0, 0);
877 /* set return register */
878 /* default: return value is in R0 (and maybe R1) */
879 result_count = get_method_n_ress(method_type);
880 assert(result_count <= 2 && "More than 2 result values not supported");
881 for(i = 0; i < result_count; ++i) {
882 const arch_register_t* reg;
883 tp = get_method_res_type(method_type, i);
884 mode = get_type_mode(tp);
885 ASSERT_NO_FLOAT(mode);
887 reg = &mips_gp_regs[REG_V0 + i];
888 be_abi_call_res_reg(abi, i, reg);
892 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
893 return &mips_irn_ops;
896 const arch_irn_handler_t mips_irn_handler = {
900 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
901 return &mips_irn_handler;
905 * Initializes the code generator interface.
907 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
908 return &mips_code_gen_if;
912 * Returns the necessary byte alignment for storing a register of given class.
914 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
915 ir_mode *mode = arch_register_class_mode(cls);
916 return get_mode_size_bytes(mode);
919 static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
925 static const be_machine_t *mips_get_machine(const void *self) {
932 * Return irp irgs in the desired order.
934 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) {
939 * Returns the libFirm configuration parameter for this backend.
941 static const backend_params *mips_get_libfirm_params(void) {
942 static arch_dep_params_t ad = {
944 0, /* Muls are fast enough on Mips */
945 31, /* shift would be ok */
948 32, /* Mulhs & Mulhu available for 32 bit */
950 static backend_params p = {
951 NULL, /* no additional opcodes */
952 NULL, /* will be set later */
953 1, /* need dword lowering */
954 NULL, /* but yet no creator function */
955 NULL, /* context for create_intrinsic_fkt */
962 const arch_isa_if_t mips_isa_if = {
965 mips_get_n_reg_class,
967 mips_get_reg_class_for_mode,
969 mips_get_irn_handler,
970 mips_get_code_generator_if,
971 mips_get_list_sched_selector,
972 mips_get_ilp_sched_selector,
973 mips_get_reg_class_alignment,
974 mips_get_libfirm_params,
975 mips_get_allowed_execution_units,
980 void be_init_arch_mips(void)
982 be_register_isa_if("mips", &mips_isa_if);
985 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);