2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
30 #include "pseudo_irg.h"
45 #include "../bearch_t.h"
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
51 #include "../bemachine.h"
52 #include "../bemodule.h"
53 #include "../beemitter.h"
54 #include "../begnuas.h"
55 #include "../begnuas.h"
57 #include "bearch_mips_t.h"
59 #include "mips_new_nodes.h"
60 #include "gen_mips_regalloc_if.h"
61 #include "mips_transform.h"
62 #include "mips_emitter.h"
63 #include "mips_map_regs.h"
64 #include "mips_util.h"
65 #include "mips_scheduler.h"
67 #define DEBUG_MODULE "firm.be.mips.isa"
69 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
70 static set *cur_reg_set = NULL;
72 /**************************************************
75 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
76 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
77 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
78 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
81 **************************************************/
84 * Return register requirements for a mips node.
85 * If the node returns a tuple (mode_T) then the proj's
86 * will be asked for this information.
89 arch_register_req_t *mips_get_irn_reg_req(const void *self,
90 const ir_node *node, int pos) {
91 long node_pos = pos == -1 ? 0 : pos;
92 ir_mode *mode = get_irn_mode(node);
94 if (is_Block(node) || mode == mode_X || mode == mode_M) {
95 return arch_no_register_req;
98 if (mode == mode_T && pos < 0) {
99 return arch_no_register_req;
103 /* in case of a proj, we need to get the correct OUT slot */
104 /* of the node corresponding to the proj number */
106 node_pos = mips_translate_proj_pos(node);
112 node = skip_Proj_const(node);
115 /* get requirements for our own nodes */
116 if (is_mips_irn(node)) {
117 const arch_register_req_t *req;
119 req = get_mips_in_req(node, pos);
121 req = get_mips_out_req(node, node_pos);
127 /* unknown should be translated by now */
128 assert(!is_Unknown(node));
130 return arch_no_register_req;
133 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
138 if (get_irn_mode(irn) == mode_X) {
142 pos = mips_translate_proj_pos(irn);
143 irn = skip_Proj(irn);
146 if (is_mips_irn(irn)) {
147 const arch_register_t **slots;
149 slots = get_mips_slots(irn);
153 /* here we set the registers for the Phi nodes */
154 mips_set_firm_reg(irn, reg, cur_reg_set);
158 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
160 const arch_register_t *reg = NULL;
164 if (get_irn_mode(irn) == mode_X) {
168 pos = mips_translate_proj_pos(irn);
169 irn = skip_Proj_const(irn);
172 if (is_mips_irn(irn)) {
173 const arch_register_t **slots;
174 slots = get_mips_slots(irn);
178 reg = mips_get_firm_reg(irn, cur_reg_set);
184 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
185 irn = skip_Proj_const(irn);
188 return arch_irn_class_branch;
189 } else if (is_mips_irn(irn)) {
190 return arch_irn_class_normal;
196 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
197 irn = skip_Proj_const(irn);
199 if (is_mips_irn(irn)) {
200 return get_mips_flags(irn);
202 else if (is_Unknown(irn)) {
203 return arch_irn_flags_ignore;
209 static ir_entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
210 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
211 mips_attr_t *attr = get_mips_attr(irn);
213 return attr->stack_entity;
219 static void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
220 mips_attr_t *attr = get_mips_attr(irn);
221 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
222 attr->stack_entity = ent;
226 * This function is called by the generic backend to correct offsets for
227 * nodes accessing the stack.
229 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
230 mips_attr_t *attr = get_mips_attr(irn);
231 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
233 attr->stack_entity_offset = offset;
236 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
240 /* fill register allocator interface */
242 static const arch_irn_ops_if_t mips_irn_ops_if = {
243 mips_get_irn_reg_req,
248 mips_get_frame_entity,
249 mips_set_frame_entity,
250 mips_set_frame_offset,
252 NULL, /* get_inverse */
253 NULL, /* get_op_estimated_cost */
254 NULL, /* possible_memory_operand */
255 NULL, /* perform_memory_operand */
258 mips_irn_ops_t mips_irn_ops = {
265 /**************************************************
268 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
269 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
270 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
271 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
274 **************************************************/
284 * Ext-Block walker: create a block schedule
286 static void create_block_list(ir_extblk *blk, void *env) {
290 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
291 ir_node *block = get_extbb_block(blk, i);
293 set_irn_link(block, NULL);
295 set_irn_link(list->end, block);
304 /* return the scheduled block at position pos */
305 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
306 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
307 return cg->bl_list[pos];
311 /* return the number of scheduled blocks */
312 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
313 return ARR_LEN(cg->bl_list);
316 /* set a block schedule number */
317 void mips_set_block_sched_nr(ir_node *block, int nr) {
318 set_irn_link(block, INT_TO_PTR(nr));
321 /* get a block schedule number */
322 int mips_get_block_sched_nr(ir_node *block) {
323 return PTR_TO_INT(get_irn_link(block));
327 * Creates a block schedule for the given graph.
329 static void mips_create_block_sched(mips_code_gen_t *cg) {
331 ir_node **bl_list, *block;
335 DEL_ARR_F(cg->bl_list);
336 free_survive_dce(cg->bl_list_sdce);
339 /* calculate the block schedule here */
340 compute_extbb(cg->irg);
345 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
348 bl_list = NEW_ARR_F(ir_node *, list.cnt);
349 cg->bl_list_sdce = new_survive_dce();
350 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
352 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
356 cg->bl_list = bl_list;
359 typedef struct _wenv_t {
364 * Walker: link all CopyB nodes
366 static void collect_copyb_nodes(ir_node *node, void *env) {
369 if (get_irn_op(node) == op_CopyB) {
370 set_irn_link(node, wenv->list);
375 static void replace_copyb_nodes(mips_code_gen_t *cg) {
377 ir_node *copy, *next;
378 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
379 const ir_edge_t *edge;
381 /* build code for all copyB */
383 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
385 for (copy = env.list; copy; copy = next) {
386 next = get_irn_link(copy);
388 old_bl = get_nodes_block(copy);
390 jmp = get_Block_cfgpred(old_bl, 0);
391 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
393 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
394 set_nodes_block(jmp, new_bl);
396 mem = gen_code_for_CopyB(new_bl, copy);
398 /* fix copyB's out edges */
399 foreach_out_edge(copy, edge) {
400 ir_node *succ = get_edge_src_irn(edge);
402 assert(is_Proj(succ));
403 switch (get_Proj_proj(succ)) {
404 case pn_CopyB_M_regular:
405 case pn_CopyB_M_except:
409 exchange(succ, get_irg_bad(cg->irg));
416 * Transforms the standard firm graph into
419 static void mips_prepare_graph(void *self) {
420 mips_code_gen_t *cg = self;
423 // replace all copyb nodes in the block with a loop
424 // and mips store/load nodes
425 replace_copyb_nodes(cg);
427 // Calculate block schedule
428 mips_create_block_sched(cg);
430 /* enter the block number into every blocks link field */
431 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
432 ir_node *bl = mips_get_sched_block(cg, bl_nr);
433 mips_set_block_sched_nr(bl, bl_nr);
436 // walk the graph and transform firm nodes into mips nodes where possible
437 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
439 dump_ir_block_graph_sched(cg->irg, "-transformed");
443 * Called immediately before emit phase.
445 static void mips_finish_irg(void *self) {
446 mips_code_gen_t *cg = self;
447 ir_graph *irg = cg->irg;
449 dump_ir_block_graph_sched(irg, "-mips-finished");
454 * These are some hooks which must be filled but are probably not needed.
456 static void mips_before_sched(void *self) {
457 /* Some stuff you need to do after scheduling but before register allocation */
460 static void mips_before_ra(void *self) {
461 /* Some stuff you need to do immediately after register allocation */
464 static void mips_after_ra(void* self) {
465 mips_code_gen_t *cg = self;
466 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
470 * Emits the code, closes the output file and frees
471 * the code generator interface.
473 static void mips_emit_and_done(void *self) {
474 mips_code_gen_t *cg = self;
475 ir_graph *irg = cg->irg;
477 mips_gen_routine(cg, irg);
481 /* de-allocate code generator */
482 del_set(cg->reg_set);
484 DEL_ARR_F(cg->bl_list);
485 free_survive_dce(cg->bl_list_sdce);
490 static void *mips_cg_init(be_irg_t *birg);
492 static const arch_code_generator_if_t mips_code_gen_if = {
494 NULL, /* before abi introduce */
497 mips_before_sched, /* before scheduling hook */
498 mips_before_ra, /* before register allocation hook */
505 * Initializes the code generator.
507 static void *mips_cg_init(be_irg_t *birg) {
508 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
509 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
510 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
512 cg->impl = &mips_code_gen_if;
513 cg->irg = be_get_birg_irg(birg);
514 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
515 cg->arch_env = arch_env;
519 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
521 cur_reg_set = cg->reg_set;
523 mips_irn_ops.cg = cg;
525 return (arch_code_generator_t *)cg;
529 /*****************************************************************
530 * ____ _ _ _____ _____
531 * | _ \ | | | | |_ _|/ ____| /\
532 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
533 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
534 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
535 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
537 *****************************************************************/
539 static mips_isa_t mips_isa_template = {
542 &mips_gp_regs[REG_SP],
543 &mips_gp_regs[REG_FP],
544 -1, /* stack direction */
545 NULL, /* main environment */
547 { NULL, }, /* emitter environment */
551 * Initializes the backend ISA and opens the output file.
553 static void *mips_init(FILE *file_handle) {
554 static int inited = 0;
561 isa = xcalloc(1, sizeof(isa[0]));
562 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
564 be_emit_init_env(&isa->emit, file_handle);
566 mips_register_init(isa);
567 mips_create_opcodes();
568 mips_init_opcode_transforms();
570 /* we mark referenced global entities, so we can only emit those which
571 * are actually referenced. (Note: you mustn't use the type visited flag
572 * elsewhere in the backend)
574 inc_master_type_visited();
580 * Closes the output file and frees the ISA structure.
582 static void mips_done(void *self) {
583 mips_isa_t *isa = self;
585 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
587 be_emit_destroy_env(&isa->emit);
591 static int mips_get_n_reg_class(const void *self) {
595 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
596 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
597 return &mips_reg_classes[i];
603 * Get the register class which shall be used to store a value of a given mode.
604 * @param self The this pointer.
605 * @param mode The mode in question.
606 * @return A register class which can hold values of the given mode.
608 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
609 ASSERT_NO_FLOAT(mode);
610 return &mips_reg_classes[CLASS_mips_gp];
614 be_abi_call_flags_bits_t flags;
615 const arch_isa_t *isa;
616 const arch_env_t *arch_env;
618 // do special handling to support debuggers
622 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
624 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
625 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
626 env->flags = fl.bits;
628 env->arch_env = arch_env;
629 env->isa = arch_env->isa;
634 static void mips_abi_dont_save_regs(void *self, pset *s)
636 mips_abi_env_t *env = self;
638 if(env->flags.try_omit_fp)
639 pset_insert_ptr(s, env->isa->bp);
642 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
644 mips_abi_env_t *env = self;
645 ir_graph *irg = env->irg;
646 dbg_info *dbg = NULL; // TODO where can I get this from?
647 ir_node *block = get_irg_start_block(env->irg);
649 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
650 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
651 int initialstackframesize;
655 * The calling conventions wants a stack frame of at least 24bytes size with
656 * a0-a3 saved in offset 0-12
657 * fp saved in offset 16
658 * ra saved in offset 20
661 ir_node *sync, *reg, *store;
662 initialstackframesize = 24;
664 // - setup first part of stackframe
665 sp = new_rd_mips_addiu(dbg, irg, block, sp);
666 attr = get_mips_attr(sp);
667 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
668 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
669 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
671 /* TODO: where to get an edge with a0-a3
673 for(i = 0; i < 4; ++i) {
674 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
675 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
676 attr = get_mips_attr(store);
677 attr->load_store_mode = mode_Iu;
678 attr->tv = new_tarval_from_long(i * 4, mode_Is);
680 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
684 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
685 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
686 attr = get_mips_attr(store);
687 attr->modes.load_store_mode = mode_Iu;
688 attr->tv = new_tarval_from_long(16, mode_Is);
690 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
692 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
693 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
694 attr = get_mips_attr(store);
695 attr->modes.load_store_mode = mode_Iu;
696 attr->tv = new_tarval_from_long(20, mode_Is);
698 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
700 // TODO ideally we would route these mem edges directly towards the epilogue
701 sync = new_r_Sync(irg, block, 2, mm+4);
704 ir_node *reg, *store;
705 initialstackframesize = 4;
707 // save old framepointer
708 sp = new_rd_mips_addiu(dbg, irg, block, sp);
709 attr = get_mips_attr(sp);
710 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
711 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
712 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
714 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
715 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
716 attr = get_mips_attr(store);
717 attr->modes.load_store_mode = mode_Iu;
718 attr->tv = new_tarval_from_long(0, mode_Is);
720 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
723 // setup framepointer
724 fp = new_rd_mips_addiu(dbg, irg, block, sp);
725 attr = get_mips_attr(fp);
726 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
727 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
728 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
730 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
731 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
733 return &mips_gp_regs[REG_SP];
736 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
738 mips_abi_env_t *env = self;
739 ir_graph *irg = env->irg;
740 dbg_info *dbg = NULL; // TODO where can I get this from?
742 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
743 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
745 int initial_frame_size = env->debug ? 24 : 4;
746 int fp_save_offset = env->debug ? 16 : 0;
749 sp = new_rd_mips_move(dbg, irg, block, fp);
750 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
751 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
754 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
755 attr = get_mips_attr(load);
756 attr->modes.load_store_mode = mode_Iu;
757 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
758 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
760 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
761 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
762 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
764 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
765 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
769 * Produces the type which sits between the stack args and the locals on the stack.
770 * it will contain the return address and space to store the old frame pointer.
771 * @return The Firm type modelling the ABI between type.
773 static ir_type *mips_abi_get_between_type(void *self) {
774 mips_abi_env_t *env = self;
776 static ir_type *debug_between_type = NULL;
777 static ir_type *opt_between_type = NULL;
778 static ir_entity *old_fp_ent = NULL;
780 if(env->debug && debug_between_type == NULL) {
781 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
782 ir_entity *ret_addr_ent;
783 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
784 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
785 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
787 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
788 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
789 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
790 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
791 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
792 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
793 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
795 set_entity_offset(a0_ent, 0);
796 set_entity_offset(a1_ent, 4);
797 set_entity_offset(a2_ent, 8);
798 set_entity_offset(a3_ent, 12);
799 set_entity_offset(old_fp_ent, 16);
800 set_entity_offset(ret_addr_ent, 20);
802 set_type_size_bytes(debug_between_type, 24);
803 } else if(!env->debug && opt_between_type == NULL) {
804 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
805 ir_entity *old_fp_ent;
807 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
808 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
809 set_entity_offset(old_fp_ent, 0);
810 set_type_size_bytes(opt_between_type, 4);
813 return env->debug ? debug_between_type : opt_between_type;
816 static const be_abi_callbacks_t mips_abi_callbacks = {
819 mips_abi_get_between_type,
820 mips_abi_dont_save_regs,
826 * Get the ABI restrictions for procedure calls.
827 * @param self The this pointer.
828 * @param method_type The type of the method (procedure) in question.
829 * @param abi The abi object to be modified
831 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
834 int n = get_method_n_params(method_type);
838 const arch_register_t *reg;
839 be_abi_call_flags_t call_flags;
841 memset(&call_flags, 0, sizeof(call_flags));
842 call_flags.bits.left_to_right = 0;
843 call_flags.bits.store_args_sequential = 0;
844 call_flags.bits.try_omit_fp = 1;
845 call_flags.bits.fp_free = 0;
846 call_flags.bits.call_has_imm = 1;
848 /* set stack parameter passing style */
849 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
851 /* collect the mode for each type */
852 modes = alloca(n * sizeof(modes[0]));
853 for (i = 0; i < n; i++) {
854 tp = get_method_param_type(method_type, i);
855 modes[i] = get_type_mode(tp);
858 // assigns parameters to registers or stack
859 for (i = 0; i < n; i++) {
860 // first 4 params in $a0-$a3, the others on the stack
862 reg = &mips_gp_regs[REG_A0 + i];
863 be_abi_call_param_reg(abi, i, reg);
865 /* default: all parameters on stack */
866 be_abi_call_param_stack(abi, i, 4, 0, 0);
870 /* set return register */
871 /* default: return value is in R0 (and maybe R1) */
872 result_count = get_method_n_ress(method_type);
873 assert(result_count <= 2 && "More than 2 result values not supported");
874 for(i = 0; i < result_count; ++i) {
875 const arch_register_t* reg;
876 tp = get_method_res_type(method_type, i);
877 mode = get_type_mode(tp);
878 ASSERT_NO_FLOAT(mode);
880 reg = &mips_gp_regs[REG_V0 + i];
881 be_abi_call_res_reg(abi, i, reg);
885 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
886 return &mips_irn_ops;
889 const arch_irn_handler_t mips_irn_handler = {
893 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
894 return &mips_irn_handler;
898 * Initializes the code generator interface.
900 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
901 return &mips_code_gen_if;
905 * Returns the necessary byte alignment for storing a register of given class.
907 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
908 ir_mode *mode = arch_register_class_mode(cls);
909 return get_mode_size_bytes(mode);
912 static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
918 static const be_machine_t *mips_get_machine(const void *self) {
925 * Return irp irgs in the desired order.
927 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) {
932 * Returns the libFirm configuration parameter for this backend.
934 static const backend_params *mips_get_libfirm_params(void) {
935 static arch_dep_params_t ad = {
937 0, /* Muls are fast enough on Mips */
938 31, /* shift would be ok */
941 32, /* Mulhs & Mulhu available for 32 bit */
943 static backend_params p = {
944 NULL, /* no additional opcodes */
945 NULL, /* will be set later */
946 1, /* need dword lowering */
947 NULL, /* but yet no creator function */
948 NULL, /* context for create_intrinsic_fkt */
955 const arch_isa_if_t mips_isa_if = {
958 mips_get_n_reg_class,
960 mips_get_reg_class_for_mode,
962 mips_get_irn_handler,
963 mips_get_code_generator_if,
964 mips_get_list_sched_selector,
965 mips_get_ilp_sched_selector,
966 mips_get_reg_class_alignment,
967 mips_get_libfirm_params,
968 mips_get_allowed_execution_units,
973 void be_init_arch_mips(void)
975 be_register_isa_if("mips", &mips_isa_if);
978 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);