13 #include "../firm2arch_nodes_attr.h"
14 #include "../bearch_firm.h"
15 #include "../arch/archop.h" /* we need this for Min and Max nodes */
16 #include "transform.h"
17 #include "new_nodes.h"
19 extern ir_op *get_op_Mulh(void);
21 /* determine if one operator is an Imm */
22 ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
24 return is_Imm(op1) ? op1 : (is_Imm(op2) ? op2 : NULL);
25 else return is_Imm(op2) ? op2 : NULL;
28 /* determine if one operator is not an Imm */
29 ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
30 return !is_Imm(op1) ? op1 : (!is_Imm(op2) ? op2 : NULL);
36 * Creates an ia32 Add with immediate.
39 * @param block the block the new node should belong to
40 * @param expr_op operator
41 * @param mode node mode
42 * @return the created ia23 Add_i node
44 ir_node *gen_imm_Add(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
46 tarval *tv = get_Immop_tarval(const_op);
48 tarval_classification_t class_tv, class_negtv;
50 /* const_op: tarval or SymConst? */
52 /* optimize tarvals */
53 class_tv = classify_tarval(tv);
54 class_negtv = classify_tarval(tarval_neg(tv));
56 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
57 new_op = new_rd_ia32_Inc(dbg, current_ir_graph, block, expr_op, mode);
59 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == Sub */
60 new_op = new_rd_ia32_Dec(dbg, current_ir_graph, block, expr_op, mode);
69 new_op = new_rd_ia32_Lea_i(dbg, current_ir_graph, block, expr_op, mode);
75 * Creates an ia32 Add.
77 * @param dbg firm node dbg
78 * @param block the block the new node should belong to
79 * @param op1 first operator
80 * @param op2 second operator
81 * @param mode node mode
82 * @return the created ia32 Add node
84 ir_node *gen_Add(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
85 /* try to optimize with LEA */
86 ir_node *shli_op = is_ia32_Shl_i(op1) ? op1 : (is_ia32_Shl_i(op2) ? op2 : NULL);
87 ir_node *expr_op = shli_op == op1 ? op2 : (shli_op == op2 ? op1 : NULL);
92 tarval *tv = get_Immop_tarval(shli_op);
95 switch (get_tarval_long(tv)) {
99 // If the other operand of the LEA is an LEA_i (that means LEA ofs(%regop1)),
100 // we can skip it and transform the whole sequence into LEA ofs(%regop1, %regop2, shl_val),
101 if (is_ia32_Lea_i(expr_op)) {
102 offs = get_Immop_tarval(expr_op);
103 expr_op = get_irn_n(expr_op, 0);
106 new_op = new_rd_ia32_Lea(dbg, current_ir_graph, block, expr_op, get_irn_n(shli_op, 0), mode);
107 set_Immop_attr_tv(new_op, tv);
110 set_ia32_Lea_offs(new_op, offs);
125 new_op = new_rd_ia32_Lea(dbg, current_ir_graph, block, op1, op2, mode);
126 set_Immop_attr_tv(new_op, get_tarval_one(mode_Iu));
127 set_ia32_Lea_offs(new_op, NULL);
136 * Creates an ia32 Mul with immediate.
138 * @param dbg firm dbg
139 * @param block the block the new node should belong to
140 * @param expr_op operator
141 * @param mode node mode
142 * @return the created ia23 Mul_i node
144 ir_node *gen_imm_Mul(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
145 return new_rd_ia32_Mul_i(dbg, current_ir_graph, block, expr_op, mode);
149 * Creates an ia32 Mul.
151 * @param dbg firm node dbg
152 * @param block the block the new node should belong to
153 * @param op1 first operator
154 * @param op2 second operator
155 * @param mode node mode
156 * @return the created ia32 Mul node
158 ir_node *gen_Mul(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
159 return new_rd_ia32_Mul(dbg, current_ir_graph, block, op1, op2, mode);
165 * Creates an ia32 Mulh with immediate.
166 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
167 * this result while Mul returns the lower 32 bit.
169 * @param dbg firm dbg
170 * @param block the block the new node should belong to
171 * @param expr_op operator
172 * @param mode node mode
173 * @return the created ia23 Mulh_i node
175 ir_node *gen_imm_Mulh(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
176 return new_rd_ia32_Mulh_i(dbg, current_ir_graph, block, expr_op, mode);
180 * Creates an ia32 Mulh.
181 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
182 * this result while Mul returns the lower 32 bit.
184 * @param dbg firm node dbg
185 * @param block the block the new node should belong to
186 * @param op1 first operator
187 * @param op2 second operator
188 * @param mode node mode
189 * @return the created ia32 Mulh node
191 ir_node *gen_Mulh(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
192 return new_rd_ia32_Mulh(dbg, current_ir_graph, block, op1, op2, mode);
198 * Creates an ia32 And with immediate.
200 * @param dbg firm dbg
201 * @param block the block the new node should belong to
202 * @param expr_op operator
203 * @param mode node mode
204 * @return the created ia23 And_i node
206 ir_node *gen_imm_And(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
207 return new_rd_ia32_And_i(dbg, current_ir_graph, block, expr_op, mode);
211 * Creates an ia32 And.
213 * @param dbg firm node dbg
214 * @param block the block the new node should belong to
215 * @param op1 first operator
216 * @param op2 second operator
217 * @param mode node mode
218 * @return the created ia32 And node
220 ir_node *gen_And(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
221 return new_rd_ia32_And(dbg, current_ir_graph, block, op1, op2, mode);
227 * Creates an ia32 Or with immediate.
229 * @param dbg firm dbg
230 * @param block the block the new node should belong to
231 * @param expr_op operator
232 * @param mode node mode
233 * @return the created ia23 Or_i node
235 ir_node *gen_imm_Or(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
236 return new_rd_ia32_Or_i(dbg, current_ir_graph, block, expr_op, mode);
240 * Creates an ia32 Or.
242 * @param dbg firm node dbg
243 * @param block the block the new node should belong to
244 * @param op1 first operator
245 * @param op2 second operator
246 * @param mode node mode
247 * @return the created ia32 Or node
249 ir_node *gen_Or(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
250 return new_rd_ia32_Or(dbg, current_ir_graph, block, op1, op2, mode);
256 * Creates an ia32 Eor with immediate.
258 * @param dbg firm dbg
259 * @param block the block the new node should belong to
260 * @param expr_op operator
261 * @param mode node mode
262 * @return the created ia23 Eor_i node
264 ir_node *gen_imm_Eor(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
265 return new_rd_ia32_Eor_i(dbg, current_ir_graph, block, expr_op, mode);
269 * Creates an ia32 Eor.
271 * @param dbg firm node dbg
272 * @param block the block the new node should belong to
273 * @param op1 first operator
274 * @param op2 second operator
275 * @param mode node mode
276 * @return the created ia32 Eor node
278 ir_node *gen_Eor(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
279 return new_rd_ia32_Eor(dbg, current_ir_graph, block, op1, op2, mode);
285 * Creates an ia32 Max.
287 * @param dbg firm dbg
288 * @param block the block the new node should belong to
289 * @param expr_op operator
290 * @param mode node mode
291 * @return the created ia23 Max node
293 ir_node *gen_Max(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
294 return new_rd_ia32_Max(dbg, current_ir_graph, block, op1, op2, mode);
300 * Creates an ia32 Min.
302 * @param dbg firm dbg
303 * @param block the block the new node should belong to
304 * @param expr_op operator
305 * @param mode node mode
306 * @return the created ia23 Min node
308 ir_node *gen_Min(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
309 return new_rd_ia32_Min(dbg, current_ir_graph, block, op1, op2, mode);
315 * Creates an ia32 Cmp with immediate.
317 * @param dbg firm dbg
318 * @param block the block the new node should belong to
319 * @param expr_op operator
320 * @param mode node mode
321 * @return the created ia23 Cmp_i node
323 ir_node *gen_imm_Cmp(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
324 return new_rd_ia32_Cmp_i(dbg, current_ir_graph, block, expr_op, mode);
328 * Creates an ia32 Cmp.
330 * @param dbg firm node dbg
331 * @param block the block the new node should belong to
332 * @param op1 first operator
333 * @param op2 second operator
334 * @param mode node mode
335 * @return the created ia32 Cmp node
337 ir_node *gen_Cmp(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
338 return new_rd_ia32_Cmp(dbg, current_ir_graph, block, op1, op2, mode);
344 * Creates an ia32 Sub with immediate.
346 * @param dbg firm dbg
347 * @param block the block the new node should belong to
348 * @param expr_op operator
349 * @param mode node mode
350 * @return the created ia23 Sub_i node
352 ir_node *gen_imm_Sub(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
354 tarval *tv = get_Immop_tarval(const_op);
356 tarval_classification_t class_tv, class_negtv;
358 /* const_op: tarval or SymConst? */
360 /* optimize tarvals */
361 class_tv = classify_tarval(tv);
362 class_negtv = classify_tarval(tarval_neg(tv));
364 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
365 new_op = new_rd_ia32_Dec(dbg, current_ir_graph, block, expr_op, mode);
367 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
368 new_op = new_rd_ia32_Inc(dbg, current_ir_graph, block, expr_op, mode);
377 new_op = new_rd_ia32_Sub_i(dbg, current_ir_graph, block, expr_op, mode);
383 * Creates an ia32 Sub.
385 * @param dbg firm node dbg
386 * @param block the block the new node should belong to
387 * @param op1 first operator
388 * @param op2 second operator
389 * @param mode node mode
390 * @return the created ia32 Sub node
392 ir_node *gen_Sub(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
395 /* transform "const - expr" into "-expr + const" */
396 if (is_Imm(op1) && !is_Imm(op2)) {
397 DBG((mod, LEVEL_1, "optimizing c-e into -e+c ... "));
399 sub = new_rd_ia32_Minus(dbg, current_ir_graph, block, op2, mode);
400 sub = gen_imm_Add(dbg, block, sub, op1, mode);
401 set_Immop_attr(sub, op1);
404 sub = new_rd_ia32_Sub(dbg, current_ir_graph, block, op1, op2, mode);
413 * Creates an ia32 Mod.
415 * @param dbg firm node dbg
416 * @param block the block the new node should belong to
417 * @param op1 first operator
418 * @param op2 second operator
419 * @param mode node mode
420 * @return the created ia32 Mod node
422 ir_node *gen_Mod(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
423 return new_rd_ia32_Mod(dbg, current_ir_graph, block, op1, op2, mode);
429 * Creates an ia32 Div.
431 * @param dbg firm node dbg
432 * @param block the block the new node should belong to
433 * @param op1 first operator
434 * @param op2 second operator
435 * @param mode node mode
436 * @return the created ia32 Div node
438 ir_node *gen_Div(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
439 return new_rd_ia32_Div(dbg, current_ir_graph, block, op1, op2, mode);
445 * Creates an ia32 DivMod.
447 * @param dbg firm node dbg
448 * @param block the block the new node should belong to
449 * @param op1 first operator
450 * @param op2 second operator
451 * @param mode node mode
452 * @return the created ia32 DivMod node
454 ir_node *gen_DivMod(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
455 return new_rd_ia32_DivMod(dbg, current_ir_graph, block, op1, op2, mode);
461 * Creates an ia32 Shl with immediate.
463 * @param dbg firm dbg
464 * @param block the block the new node should belong to
465 * @param expr_op operator
466 * @param mode node mode
467 * @return the created ia23 Shl_i node
469 ir_node *gen_imm_Shl(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
470 return new_rd_ia32_Shl_i(dbg, current_ir_graph, block, expr_op, mode);
474 * Creates an ia32 Shl.
476 * @param dbg firm node dbg
477 * @param block the block the new node should belong to
478 * @param op1 first operator
479 * @param op2 second operator
480 * @param mode node mode
481 * @return the created ia32 Shl node
483 ir_node *gen_Shl(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
484 return new_rd_ia32_Shl(dbg, current_ir_graph, block, op1, op2, mode);
490 * Creates an ia32 Shr with immediate.
492 * @param dbg firm dbg
493 * @param block the block the new node should belong to
494 * @param expr_op operator
495 * @param mode node mode
496 * @return the created ia23 Shr_i node
498 ir_node *gen_imm_Shr(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
499 return new_rd_ia32_Shr_i(dbg, current_ir_graph, block, expr_op, mode);
503 * Creates an ia32 Shr.
505 * @param dbg firm node dbg
506 * @param block the block the new node should belong to
507 * @param op1 first operator
508 * @param op2 second operator
509 * @param mode node mode
510 * @return the created ia32 Shr node
512 ir_node *gen_Shr(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
513 return new_rd_ia32_Shr(dbg, current_ir_graph, block, op1, op2, mode);
519 * Creates an ia32 Shrs with immediate.
521 * @param dbg firm dbg
522 * @param block the block the new node should belong to
523 * @param expr_op operator
524 * @param mode node mode
525 * @return the created ia23 Shrs_i node
527 ir_node *gen_imm_Shrs(dbg_info *dbg, ir_node *block, ir_node *expr_op, ir_node *const_op, ir_mode *mode) {
528 return new_rd_ia32_Shrs_i(dbg, current_ir_graph, block, expr_op, mode);
532 * Creates an ia32 Shrs.
534 * @param dbg firm node dbg
535 * @param block the block the new node should belong to
536 * @param op1 first operator
537 * @param op2 second operator
538 * @param mode node mode
539 * @return the created ia32 Shrs node
541 ir_node *gen_Shrs(firm_dbg_module_t *mod, dbg_info *dbg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) {
542 return new_rd_ia32_Shrs(dbg, current_ir_graph, block, op1, op2, mode);
548 * Transforms commutative operations (op_Add, op_Mul, op_And, op_Or, op_Eor, op_Cmp)
549 * and non-commutative operations with com == 0 (op_Sub, op_Mod, op_Div, op_DivMod, op_Shl, op_Shr, op_Shrs)
551 * @param mod the debug module
552 * @param block the block node belongs to
553 * @param node the node to transform
554 * @param op1 first operator
555 * @param op2 second operator
556 * @param mode node mode
557 * @param com flag if op is commutative
558 * @return the created assembler node
560 ir_node *gen_arith_Op(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_node *op1, ir_node *op2, ir_mode *mode, int com) {
561 dbg_info *dbg = get_irn_dbg_info(node);
562 ir_node *imm_op = NULL;
563 ir_node *expr_op = NULL;
564 ir_node *asm_node = NULL;
565 opcode opc = get_irn_opcode(node);
566 ir_op *op = get_irn_op(node);
568 #define GENOP(a) case iro_##a: asm_node = gen_##a(mod, dbg, block, op1, op2, mode); break
569 #define GENOPI(a) case iro_##a: asm_node = gen_imm_##a(dbg, block, expr_op, imm_op, mode); break
572 imm_op = get_immediate_op(op1, op2);
574 imm_op = get_immediate_op(NULL, op2);
576 expr_op = get_expr_op(op1, op2);
578 /* TODO: Op(Imm, Imm) support */
579 if (is_Imm(op1) && is_Imm(op2)) {
580 DBG((mod, LEVEL_2, "found unexpected %s(Imm, Imm), creating binop ... ", get_irn_opname(node)));
584 /* On x86 there is only a DivMod operation, which
585 takes a register or a memory as argument (eax = eax DIV reg, edx = eax MOD reg)
586 Immediate is not possible, so we always generate "DIV reg" ops */
587 if (opc == iro_Div || opc == iro_Mod || opc == iro_DivMod) {
588 DBG((mod, LEVEL_2, "DIV imm not available, creating binop ... "));
591 else if (op == get_op_Min() || op == get_op_Max()) {
592 DBG((mod, LEVEL_2, "MIN/MAX imm not available, creating binop ... "));
596 DBG((mod, LEVEL_1, "(op1: %s -- op2: %s) ... ", get_irn_opname(op1), get_irn_opname(op2)));
599 DBG((mod, LEVEL_1, "%s with imm ... ", get_irn_opname(node)));
614 if (op == get_op_Mulh()) {
615 asm_node = gen_imm_Mulh(dbg, block, expr_op, imm_op, mode);
618 assert("binop_i: THIS SHOULD NOT HAPPEN");
621 set_Immop_attr(asm_node, imm_op);
624 DBG((mod, LEVEL_1, "%s as binop ... ", get_irn_opname(node)));
642 if (op == get_op_Mulh()) {
643 asm_node = gen_Mulh(mod, dbg, block, op1, op2, mode);
645 else if (op == get_op_Max()) {
646 asm_node = gen_Max(mod, dbg, block, op1, op2, mode);
648 else if (op == get_op_Min()) {
649 asm_node = gen_Min(mod, dbg, block, op1, op2, mode);
652 assert("binop: THIS SHOULD NOT HAPPEN");
662 * Transforms a Minus node.
664 * @param mod the debug module
665 * @param block the block the new node should belong to
666 * @param node the ir Minus node
668 * @param mode node mode
669 * @return the created ia32 Minus node
671 ir_node *gen_Minus(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_node *op, ir_mode *mode) {
672 if (is_ia32_Minus(op)) {
673 DBG((mod, LEVEL_1, "optimizing --(e) to e ..."));
674 return get_irn_n(op, 0);
677 return new_rd_ia32_Minus(get_irn_dbg_info(node), current_ir_graph, block, op, mode);
683 * Transforms a Conv node.
685 * @param mod the debug module
686 * @param block the block the new node should belong to
687 * @param node the ir Conv node
689 * @param mode node mode
690 * @return the created ia32 Conv node
692 ir_node *gen_Conv(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_node *op, ir_mode *mode) {
693 return new_rd_ia32_Conv(get_irn_dbg_info(node), current_ir_graph, block, op, mode);
699 * Transforms a Not node.
701 * @param mod the debug module
702 * @param block the block the new node should belong to
703 * @param node the ir Not node
705 * @param mode node mode
706 * @return the created ia32 Not node
708 ir_node *gen_Not(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_node *op, ir_mode *mode) {
709 return new_rd_ia32_Not(get_irn_dbg_info(node), current_ir_graph, block, op, mode);
715 * Transforms an Abs node.
717 * @param mod the debug module
718 * @param block the block the new node should belong to
719 * @param node the ir Abs node
721 * @param mode node mode
722 * @return the created ia32 Abs node
724 ir_node *gen_Abs(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_node *op, ir_mode *mode) {
725 return new_rd_ia32_Abs(get_irn_dbg_info(node), current_ir_graph, block, op, mode);
733 * @param mod the debug module
734 * @param block the block the new node should belong to
735 * @param node the ir Load node
736 * @param mode node mode
737 * @return the created ia32 Load node
739 ir_node *gen_Load(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_mode *mode) {
740 return new_rd_ia32_Load(get_irn_dbg_info(node), current_ir_graph, block, get_Load_mem(node), get_Load_ptr(node), mode);
746 * Transforms a Store.
748 * @param mod the debug module
749 * @param block the block the new node should belong to
750 * @param node the ir Store node
751 * @param mode node mode
752 * @return the created ia32 Store node
754 ir_node *gen_Store(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_mode *mode) {
755 return new_rd_ia32_Store(get_irn_dbg_info(node), current_ir_graph, block, get_Store_mem(node), get_Store_ptr(node), get_Store_value(node), mode);
763 * @param mod the debug module
764 * @param block the block the new node should belong to
765 * @param node the ir Call node
766 * @param dummy mode doesn't matter
767 * @return the created ia32 Store node
769 ir_node *gen_Call(firm_dbg_module_t *mod, ir_node *block, ir_node *node, ir_mode *dummy) {
770 return new_rd_ia32_Call(get_irn_dbg_info(node), current_ir_graph, block, node);
776 * Transforms the given firm node (and maybe some other related nodes)
777 * into one or more assembler nodes.
779 * @param node the firm node
780 * @param env the debug module
782 void transform_node(ir_node *node, void *env) {
783 firm_dbg_module_t *mod = (firm_dbg_module_t *)env;
784 opcode code = get_irn_opcode(node);
785 ir_node *asm_node = NULL;
792 block = get_nodes_block(node);
793 mode = get_irn_mode(node);
795 #define BINOP_COM(a) case iro_##a: asm_node = gen_arith_Op(mod, block, node, get_irn_n(node, 0), get_irn_n(node, 1), mode, 1); break
796 #define BINOP_NCOM(a) case iro_##a: asm_node = gen_arith_Op(mod, block, node, get_irn_n(node, 0), get_irn_n(node, 1), mode, 0); break
797 #define UNOP(a) case iro_##a: asm_node = gen_##a(mod, block, node, get_irn_n(node, 0), mode); break
798 #define GEN(a) case iro_##a: asm_node = gen_##a(mod, block, node, mode); break
799 #define IGN(a) case iro_##a: break
800 #define BAD(a) case iro_##a: goto bad
802 DBG((mod, LEVEL_1, "transforming node %s (%ld) ... ", get_irn_opname(node), get_irn_node_nr(node)));
863 if (get_irn_op(node) == get_op_Mulh() ||
864 get_irn_op(node) == get_op_Max() ||
865 get_irn_op(node) == get_op_Min())
867 asm_node = gen_arith_Op(mod, block, node, get_irn_n(node, 0), get_irn_n(node, 1), mode, 1);
871 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
876 exchange(node, asm_node);
877 DBG((mod, LEVEL_1, "created node %u\n", get_irn_node_nr(asm_node)));
880 DBG((mod, LEVEL_1, "ignored\n"));