2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define N_FLOAT_REGS (N_ia32_fp_REGS-1) // exclude NOREG
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An entry on the simulated x87 stack.
66 typedef struct st_entry {
67 int reg_idx; /**< the virtual register index of this stack value */
68 ir_node *node; /**< the node that produced this value */
74 typedef struct x87_state {
75 st_entry st[N_FLOAT_REGS]; /**< the register stack */
76 int depth; /**< the current stack depth */
77 x87_simulator *sim; /**< The simulator. */
80 /** An empty state, used for blocks without fp instructions. */
81 static x87_state empty = { { {0, NULL}, }, 0, NULL };
84 * Return values of the instruction simulator functions.
87 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
88 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
89 in the schedule AFTER the current node. */
93 * The type of an instruction simulator function.
95 * @param state the x87 state
96 * @param n the node to be simulated
98 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
100 * NO_NODE_ADDED otherwise
102 typedef int (*sim_func)(x87_state *state, ir_node *n);
105 * A block state: Every block has a x87 state at the beginning and at the end.
107 typedef struct blk_state {
108 x87_state *begin; /**< state at the begin or NULL if not assigned */
109 x87_state *end; /**< state at the end or NULL if not assigned */
112 /** liveness bitset for fp registers. */
113 typedef unsigned char fp_liveness;
118 struct x87_simulator {
119 struct obstack obst; /**< An obstack for fast allocating. */
120 pmap *blk_states; /**< Map blocks to states. */
121 be_lv_t *lv; /**< intrablock liveness. */
122 fp_liveness *live; /**< Liveness information. */
123 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
124 waitq *worklist; /**< Worklist of blocks that must be processed. */
128 * Returns the current stack depth.
130 * @param state the x87 state
132 * @return the x87 stack depth
134 static int x87_get_depth(const x87_state *state)
139 static st_entry *x87_get_entry(x87_state *const state, int const pos)
141 assert(0 <= pos && pos < state->depth);
142 return &state->st[N_FLOAT_REGS - state->depth + pos];
146 * Return the virtual register index at st(pos).
148 * @param state the x87 state
149 * @param pos a stack position
151 * @return the fp register index that produced the value at st(pos)
153 static int x87_get_st_reg(const x87_state *state, int pos)
155 return x87_get_entry((x87_state*)state, pos)->reg_idx;
160 * Dump the stack for debugging.
162 * @param state the x87 state
164 static void x87_dump_stack(const x87_state *state)
166 for (int i = state->depth; i-- != 0;) {
167 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
168 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
170 DB((dbg, LEVEL_2, "<-- TOS\n"));
172 #endif /* DEBUG_libfirm */
175 * Set a virtual register to st(pos).
177 * @param state the x87 state
178 * @param reg_idx the fp register index that should be set
179 * @param node the IR node that produces the value of the fp register
180 * @param pos the stack position where the new value should be entered
182 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
184 st_entry *const entry = x87_get_entry(state, pos);
185 entry->reg_idx = reg_idx;
188 DB((dbg, LEVEL_2, "After SET_REG: "));
189 DEBUG_ONLY(x87_dump_stack(state);)
193 * Swap st(0) with st(pos).
195 * @param state the x87 state
196 * @param pos the stack position to change the tos with
198 static void x87_fxch(x87_state *state, int pos)
200 st_entry *const a = x87_get_entry(state, pos);
201 st_entry *const b = x87_get_entry(state, 0);
202 st_entry const t = *a;
206 DB((dbg, LEVEL_2, "After FXCH: "));
207 DEBUG_ONLY(x87_dump_stack(state);)
211 * Convert a virtual register to the stack index.
213 * @param state the x87 state
214 * @param reg_idx the register fp index
216 * @return the stack position where the register is stacked
217 * or -1 if the virtual register was not found
219 static int x87_on_stack(const x87_state *state, int reg_idx)
221 for (int i = 0; i < state->depth; ++i) {
222 if (x87_get_st_reg(state, i) == reg_idx)
229 * Push a virtual Register onto the stack, double pushes are NOT allowed.
231 * @param state the x87 state
232 * @param reg_idx the register fp index
233 * @param node the node that produces the value of the fp register
235 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
237 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
238 assert(state->depth < N_FLOAT_REGS && "stack overrun");
241 st_entry *const entry = x87_get_entry(state, 0);
242 entry->reg_idx = reg_idx;
245 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
249 * Pop a virtual Register from the stack.
251 * @param state the x87 state
253 static void x87_pop(x87_state *state)
255 assert(state->depth > 0 && "stack underrun");
259 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
263 * Empty the fpu stack
265 * @param state the x87 state
267 static void x87_emms(x87_state *state)
273 * Returns the block state of a block.
275 * @param sim the x87 simulator handle
276 * @param block the current block
278 * @return the block state
280 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
282 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
285 res = OALLOC(&sim->obst, blk_state);
289 pmap_insert(sim->blk_states, block, res);
298 * @param sim the x87 simulator handle
299 * @param src the x87 state that will be cloned
301 * @return a cloned copy of the src state
303 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
305 x87_state *const res = OALLOC(&sim->obst, x87_state);
311 * Returns the first Proj of a mode_T node having a given mode.
313 * @param n the mode_T node
314 * @param m the desired mode of the Proj
315 * @return The first Proj of mode @p m found.
317 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
319 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
321 foreach_out_edge(n, edge) {
322 ir_node *proj = get_edge_src_irn(edge);
323 if (get_irn_mode(proj) == m)
327 panic("Proj not found");
331 * Wrap the arch_* function here so we can check for errors.
333 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
335 const arch_register_t *res = arch_get_irn_register(irn);
337 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
341 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
344 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
346 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
350 static inline const arch_register_t *get_st_reg(int index)
352 return &ia32_registers[REG_ST0 + index];
356 * Create a fxch node before another node.
358 * @param state the x87 state
359 * @param n the node after the fxch
360 * @param pos exchange st(pos) with st(0)
362 static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
364 x87_fxch(state, pos);
366 ir_node *const block = get_nodes_block(n);
367 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
368 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
369 attr->reg = get_st_reg(pos);
373 sched_add_before(n, fxch);
374 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fxch), attr->reg->name));
377 /* -------------- x87 perm --------------- */
380 * Calculate the necessary permutations to reach dst_state.
382 * These permutations are done with fxch instructions and placed
383 * at the end of the block.
385 * Note that critical edges are removed here, so we need only
386 * a shuffle if the current block has only one successor.
388 * @param block the current block
389 * @param state the current x87 stack state, might be modified
390 * @param dst_state destination state
394 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
396 int i, n_cycles, k, ri;
397 unsigned cycles[4], all_mask;
398 char cycle_idx[4][8];
400 assert(state->depth == dst_state->depth);
402 /* Some mathematics here:
403 * If we have a cycle of length n that includes the tos,
404 * we need n-1 exchange operations.
405 * We can always add the tos and restore it, so we need
406 * n+1 exchange operations for a cycle not containing the tos.
407 * So, the maximum of needed operations is for a cycle of 7
408 * not including the tos == 8.
409 * This is the same number of ops we would need for using stores,
410 * so exchange is cheaper (we save the loads).
411 * On the other hand, we might need an additional exchange
412 * in the next block to bring one operand on top, so the
413 * number of ops in the first case is identical.
414 * Further, no more than 4 cycles can exists (4 x 2). */
415 all_mask = (1 << (state->depth)) - 1;
417 for (n_cycles = 0; all_mask; ++n_cycles) {
418 int src_idx, dst_idx;
420 /* find the first free slot */
421 for (i = 0; i < state->depth; ++i) {
422 if (all_mask & (1 << i)) {
423 all_mask &= ~(1 << i);
425 /* check if there are differences here */
426 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
432 /* no more cycles found */
437 cycles[n_cycles] = (1 << i);
438 cycle_idx[n_cycles][k++] = i;
439 for (src_idx = i; ; src_idx = dst_idx) {
440 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
442 if ((all_mask & (1 << dst_idx)) == 0)
445 cycle_idx[n_cycles][k++] = dst_idx;
446 cycles[n_cycles] |= (1 << dst_idx);
447 all_mask &= ~(1 << dst_idx);
449 cycle_idx[n_cycles][k] = -1;
453 /* no permutation needed */
457 /* Hmm: permutation needed */
458 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
459 DEBUG_ONLY(x87_dump_stack(state);)
460 DB((dbg, LEVEL_2, " to\n"));
461 DEBUG_ONLY(x87_dump_stack(dst_state);)
465 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
466 for (ri = 0; ri < n_cycles; ++ri) {
467 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
468 for (k = 0; cycle_idx[ri][k] != -1; ++k)
469 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
470 DB((dbg, LEVEL_2, "\n"));
475 * Find the place node must be insert.
476 * We have only one successor block, so the last instruction should
479 ir_node *const before = sched_last(block);
480 assert(is_cfop(before));
482 /* now do the permutations */
483 for (ri = 0; ri < n_cycles; ++ri) {
484 if ((cycles[ri] & 1) == 0) {
485 /* this cycle does not include the tos */
486 x87_create_fxch(state, before, cycle_idx[ri][0]);
488 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
489 x87_create_fxch(state, before, cycle_idx[ri][k]);
491 if ((cycles[ri] & 1) == 0) {
492 /* this cycle does not include the tos */
493 x87_create_fxch(state, before, cycle_idx[ri][0]);
500 * Create a fpush before node n.
502 * @param state the x87 state
503 * @param n the node after the fpush
504 * @param pos push st(pos) on stack
505 * @param val the value to push
507 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
509 x87_push(state, out_reg_idx, val);
511 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
512 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
513 attr->reg = get_st_reg(pos);
516 sched_add_before(n, fpush);
518 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpush), attr->reg->name));
522 * Create a fpop before node n.
523 * This overwrites st(pos) with st(0) and pops st(0).
525 * @param state the x87 state
526 * @param n the node after the fpop
527 * @param pos the index of the entry to remove the register stack
529 * @return the fpop node
531 static ir_node *x87_create_fpop(x87_state *const state, ir_node *const n, int const pos)
534 st_entry *const dst = x87_get_entry(state, pos);
535 st_entry *const src = x87_get_entry(state, 0);
539 ir_node *const block = get_nodes_block(n);
540 ir_node *const fpop = pos == 0 && ia32_cg_config.use_ffreep ?
541 new_bd_ia32_ffreep(NULL, block) :
542 new_bd_ia32_fpop( NULL, block);
543 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpop);
544 attr->reg = get_st_reg(pos);
547 sched_add_before(n, fpop);
548 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->reg->name));
552 /* --------------------------------- liveness ------------------------------------------ */
555 * The liveness transfer function.
556 * Updates a live set over a single step from a given node to its predecessor.
557 * Everything defined at the node is removed from the set, the uses of the node get inserted.
559 * @param irn The node at which liveness should be computed.
560 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
561 * the registers live after irn.
563 * @return The live bitset.
565 static fp_liveness fp_liveness_transfer(ir_node *irn, fp_liveness live)
568 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
570 if (get_irn_mode(irn) == mode_T) {
571 foreach_out_edge(irn, edge) {
572 ir_node *proj = get_edge_src_irn(edge);
574 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
575 const arch_register_t *reg = x87_get_irn_register(proj);
576 live &= ~(1 << reg->index);
579 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
580 const arch_register_t *reg = x87_get_irn_register(irn);
581 live &= ~(1 << reg->index);
584 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
585 ir_node *op = get_irn_n(irn, i);
587 if (mode_is_float(get_irn_mode(op)) &&
588 arch_irn_consider_in_reg_alloc(cls, op)) {
589 const arch_register_t *reg = x87_get_irn_register(op);
590 live |= 1 << reg->index;
597 * Put all live virtual registers at the end of a block into a bitset.
599 * @param sim the simulator handle
600 * @param bl the block
602 * @return The live bitset at the end of this block
604 static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
606 fp_liveness live = 0;
607 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
608 const be_lv_t *lv = sim->lv;
610 be_lv_foreach_cls(lv, block, be_lv_state_end, cls, node) {
611 const arch_register_t *reg = x87_get_irn_register(node);
612 live |= 1 << reg->index;
618 /** get the register mask from an arch_register */
619 #define REGMASK(reg) (1 << (reg->index))
622 * Return a bitset of argument registers which are live at the end of a node.
624 * @param sim the simulator handle
625 * @param pos the node
626 * @param kill kill mask for the output registers
628 * @return The live bitset.
630 static unsigned fp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
632 unsigned idx = get_irn_idx(pos);
634 assert(idx < sim->n_idx);
635 return sim->live[idx] & ~kill;
639 * Calculate the liveness for a whole block and cache it.
641 * @param sim the simulator handle
642 * @param block the block
644 static void update_liveness(x87_simulator *sim, ir_node *block)
646 fp_liveness live = fp_liveness_end_of_block(sim, block);
649 /* now iterate through the block backward and cache the results */
650 sched_foreach_reverse(block, irn) {
651 /* stop at the first Phi: this produces the live-in */
655 idx = get_irn_idx(irn);
656 sim->live[idx] = live;
658 live = fp_liveness_transfer(irn, live);
660 idx = get_irn_idx(block);
661 sim->live[idx] = live;
665 * Returns true if a register is live in a set.
667 * @param reg_idx the fp register index
668 * @param live a live bitset
670 #define is_fp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
674 * Dump liveness info.
676 * @param live the live bitset
678 static void fp_dump_live(fp_liveness live)
682 DB((dbg, LEVEL_2, "Live after: "));
683 for (i = 0; i < 8; ++i) {
684 if (live & (1 << i)) {
685 DB((dbg, LEVEL_2, "vf%d ", i));
688 DB((dbg, LEVEL_2, "\n"));
690 #endif /* DEBUG_libfirm */
692 /* --------------------------------- simulators ---------------------------------------- */
695 * Simulate a virtual binop.
697 * @param state the x87 state
698 * @param n the node that should be simulated (and patched)
700 * @return NO_NODE_ADDED
702 static int sim_binop(x87_state *const state, ir_node *const n)
704 x87_simulator *sim = state->sim;
705 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
706 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
707 const arch_register_t *op1_reg = x87_get_irn_register(op1);
708 const arch_register_t *op2_reg = x87_get_irn_register(op2);
709 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
710 int reg_index_1 = op1_reg->index;
711 int reg_index_2 = op2_reg->index;
712 fp_liveness live = fp_live_args_after(sim, n, REGMASK(out));
716 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, op1_reg->name, op2_reg->name, out->name));
717 DEBUG_ONLY(fp_dump_live(live);)
718 DB((dbg, LEVEL_1, "Stack before: "));
719 DEBUG_ONLY(x87_dump_stack(state);)
721 int op1_idx = x87_on_stack(state, reg_index_1);
722 assert(op1_idx >= 0);
723 op1_live_after = is_fp_live(reg_index_1, live);
728 int const out_reg_idx = out->index;
729 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
730 if (reg_index_2 != REG_FP_FP_NOREG) {
731 /* second operand is a fp register */
732 op2_idx = x87_on_stack(state, reg_index_2);
733 assert(op2_idx >= 0);
734 op2_live_after = is_fp_live(reg_index_2, live);
736 if (op2_live_after) {
737 /* Second operand is live. */
739 if (op1_live_after) {
740 /* Both operands are live: push the first one.
741 * This works even for op1 == op2. */
742 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
743 /* now do fxxx (tos=tos X op) */
748 /* Second live, first operand is dead: Overwrite first. */
749 if (op1_idx != 0 && op2_idx != 0) {
750 /* Bring one operand to tos. */
751 x87_create_fxch(state, n, op1_idx);
757 /* Second operand is dead. */
758 if (op1_live_after) {
759 /* First operand is live, second is dead: Overwrite second. */
760 if (op1_idx != 0 && op2_idx != 0) {
761 /* Bring one operand to tos. */
762 x87_create_fxch(state, n, op2_idx);
767 /* Both operands are dead. */
768 if (op1_idx == op2_idx) {
769 /* Operands are identical: no pop. */
771 x87_create_fxch(state, n, op1_idx);
776 if (op1_idx != 0 && op2_idx != 0) {
777 /* Bring one operand to tos. Heuristically swap the operand not at
778 * st(1) to tos. This way, if any operand was at st(1), the result
779 * will end up in the new st(0) after the implicit pop. If the next
780 * operation uses the result, then no fxch will be necessary. */
782 x87_create_fxch(state, n, op1_idx);
785 x87_create_fxch(state, n, op2_idx);
791 out_idx = op1_idx != 0 ? op1_idx : op2_idx;
795 /* second operand is an address mode */
796 if (op1_live_after) {
797 /* first operand is live: push it here */
798 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
800 /* first operand is dead: bring it to tos */
802 x87_create_fxch(state, n, op1_idx);
805 op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
806 op2_idx = attr->attr.data.ins_permuted ? 0 : -1;
809 assert(op1_idx == 0 || op2_idx == 0);
810 assert(out_idx == op1_idx || out_idx == op2_idx);
812 x87_set_st(state, out_reg_idx, n, out_idx);
816 /* patch the operation */
817 int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
818 attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
819 attr->attr.data.ins_permuted = op1_idx != 0;
820 attr->res_in_reg = out_idx != 0;
824 char const *const l = op1_idx >= 0 ? get_st_reg(op1_idx)->name : "[AM]";
825 char const *const r = op2_idx >= 0 ? get_st_reg(op2_idx)->name : "[AM]";
826 char const *const o = get_st_reg(out_idx)->name;
827 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), l, r, o));
830 return NO_NODE_ADDED;
834 * Simulate a virtual Unop.
836 * @param state the x87 state
837 * @param n the node that should be simulated (and patched)
839 * @return NO_NODE_ADDED
841 static int sim_unop(x87_state *state, ir_node *n)
843 arch_register_t const *const out = x87_get_irn_register(n);
844 unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
845 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
846 DEBUG_ONLY(fp_dump_live(live);)
848 ir_node *const op1 = get_irn_n(n, 0);
849 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
850 int const op1_reg_idx = op1_reg->index;
851 int const op1_idx = x87_on_stack(state, op1_reg_idx);
852 int const out_reg_idx = out->index;
853 if (is_fp_live(op1_reg_idx, live)) {
854 /* push the operand here */
855 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
857 /* operand is dead, bring it to tos */
859 x87_create_fxch(state, n, op1_idx);
863 x87_set_st(state, out_reg_idx, n, 0);
864 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
866 return NO_NODE_ADDED;
870 * Simulate a virtual Load instruction.
872 * @param state the x87 state
873 * @param n the node that should be simulated (and patched)
875 * @return NO_NODE_ADDED
877 static int sim_load(x87_state *state, ir_node *n)
879 assert((int)pn_ia32_fld_res == (int)pn_ia32_fild_res
880 && (int)pn_ia32_fld_res == (int)pn_ia32_fld1_res
881 && (int)pn_ia32_fld_res == (int)pn_ia32_fldz_res);
882 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_fld_res);
884 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
885 x87_push(state, out->index, n);
886 assert(out == x87_irn_get_register(n, pn_ia32_fld_res));
887 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
889 return NO_NODE_ADDED;
893 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
895 * @param store The store
896 * @param old_val The former value
897 * @param new_val The new value
899 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
901 foreach_out_edge_safe(old_val, edge) {
902 ir_node *user = get_edge_src_irn(edge);
903 /* if the user is scheduled after the store: rewire */
904 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
905 set_irn_n(user, get_edge_src_pos(edge), new_val);
911 * Simulate a virtual Store.
913 * @param state the x87 state
914 * @param n the node that should be simulated (and patched)
916 static int sim_store(x87_state *state, ir_node *n)
918 ir_node *const val = get_irn_n(n, n_ia32_fst_val);
919 arch_register_t const *const op2 = x87_get_irn_register(val);
920 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
923 int insn = NO_NODE_ADDED;
924 int const op2_reg_idx = op2->index;
925 int const op2_idx = x87_on_stack(state, op2_reg_idx);
926 unsigned const live = fp_live_args_after(state->sim, n, 0);
927 int const live_after_node = is_fp_live(op2_reg_idx, live);
928 assert(op2_idx >= 0);
929 if (live_after_node) {
930 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
931 * fist doesn't support 64bit mode, only fistp
933 * - stack not full: push value and fstp
934 * - stack full: fstp value and load again
935 * Note that we cannot test on mode_E, because floats might be 80bit ... */
936 ir_mode *const mode = get_ia32_ls_mode(n);
937 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
938 if (x87_get_depth(state) < N_FLOAT_REGS) {
939 /* ok, we have a free register: push + fstp */
940 x87_create_fpush(state, n, op2_idx, REG_FP_FP_NOREG, val);
943 /* stack full here: need fstp + load */
946 ir_node *const block = get_nodes_block(n);
947 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
948 ir_node *const vfld = new_bd_ia32_fld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
950 /* copy all attributes */
951 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
952 if (is_ia32_use_frame(n))
953 set_ia32_use_frame(vfld);
954 set_ia32_op_type(vfld, ia32_AddrModeS);
955 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
956 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
957 set_ia32_ls_mode(vfld, mode);
959 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_fld_res);
960 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_fld_M);
962 arch_set_irn_register(rproj, op2);
964 /* reroute all former users of the store memory to the load memory */
965 edges_reroute_except(mem, mproj, vfld);
967 sched_add_after(n, vfld);
969 /* rewire all users, scheduled after the store, to the loaded value */
970 collect_and_rewire_users(n, val, rproj);
975 /* we can only store the tos to memory */
977 x87_create_fxch(state, n, op2_idx);
980 /* we can only store the tos to memory */
982 x87_create_fxch(state, n, op2_idx);
990 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
992 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
997 static int sim_fprem(x87_state *const state, ir_node *const n)
1001 panic("TODO implement");
1002 return NO_NODE_ADDED;
1006 * Simulate a virtual fisttp.
1008 * @param state the x87 state
1009 * @param n the node that should be simulated (and patched)
1011 * @return NO_NODE_ADDED
1013 static int sim_fisttp(x87_state *state, ir_node *n)
1015 ir_node *val = get_irn_n(n, n_ia32_fst_val);
1016 const arch_register_t *op2 = x87_get_irn_register(val);
1018 int const op2_idx = x87_on_stack(state, op2->index);
1019 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
1020 assert(op2_idx >= 0);
1022 /* Note: although the value is still live here, it is destroyed because
1023 of the pop. The register allocator is aware of that and introduced a copy
1024 if the value must be alive. */
1026 /* we can only store the tos to memory */
1028 x87_create_fxch(state, n, op2_idx);
1032 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
1034 return NO_NODE_ADDED;
1038 * Simulate a virtual FtstFnstsw.
1040 * @param state the x87 state
1041 * @param n the node that should be simulated (and patched)
1043 * @return NO_NODE_ADDED
1045 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1047 x87_simulator *sim = state->sim;
1048 ir_node *op1_node = get_irn_n(n, n_ia32_FtstFnstsw_left);
1049 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1050 int reg_index_1 = reg1->index;
1051 int op1_idx = x87_on_stack(state, reg_index_1);
1052 unsigned live = fp_live_args_after(sim, n, 0);
1054 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, reg1->name));
1055 DEBUG_ONLY(fp_dump_live(live);)
1056 DB((dbg, LEVEL_1, "Stack before: "));
1057 DEBUG_ONLY(x87_dump_stack(state);)
1058 assert(op1_idx >= 0);
1061 /* bring the value to tos */
1062 x87_create_fxch(state, n, op1_idx);
1065 if (!is_fp_live(reg_index_1, live))
1066 x87_create_fpop(state, sched_next(n), 0);
1068 return NO_NODE_ADDED;
1074 * @param state the x87 state
1075 * @param n the node that should be simulated (and patched)
1077 * @return NO_NODE_ADDED
1079 static int sim_Fucom(x87_state *state, ir_node *n)
1081 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1082 x87_simulator *sim = state->sim;
1083 ir_node *op1_node = get_irn_n(n, n_ia32_FucomFnstsw_left);
1084 ir_node *op2_node = get_irn_n(n, n_ia32_FucomFnstsw_right);
1085 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1086 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1087 int reg_index_1 = op1->index;
1088 int reg_index_2 = op2->index;
1089 unsigned live = fp_live_args_after(sim, n, 0);
1091 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, op1->name, op2->name));
1092 DEBUG_ONLY(fp_dump_live(live);)
1093 DB((dbg, LEVEL_1, "Stack before: "));
1094 DEBUG_ONLY(x87_dump_stack(state);)
1096 int op1_idx = x87_on_stack(state, reg_index_1);
1097 assert(op1_idx >= 0);
1101 /* BEWARE: check for comp a,a cases, they might happen */
1102 if (reg_index_2 != REG_FP_FP_NOREG) {
1103 /* second operand is a fp register */
1104 op2_idx = x87_on_stack(state, reg_index_2);
1105 assert(op2_idx >= 0);
1107 if (is_fp_live(reg_index_2, live)) {
1108 /* second operand is live */
1110 if (is_fp_live(reg_index_1, live)) {
1111 /* both operands are live */
1112 if (op1_idx != 0 && op2_idx != 0) {
1113 /* bring the first one to tos */
1114 x87_create_fxch(state, n, op1_idx);
1115 if (op1_idx == op2_idx)
1118 /* res = tos X op */
1121 /* second live, first operand is dead here, bring it to tos.
1122 This means further, op1_idx != op2_idx. */
1123 assert(op1_idx != op2_idx);
1125 x87_create_fxch(state, n, op1_idx);
1130 /* res = tos X op, pop */
1134 /* second operand is dead */
1135 if (is_fp_live(reg_index_1, live)) {
1136 /* first operand is live: bring second to tos.
1137 This means further, op1_idx != op2_idx. */
1138 assert(op1_idx != op2_idx);
1140 x87_create_fxch(state, n, op2_idx);
1145 /* res = op X tos, pop */
1148 /* both operands are dead here, check first for identity. */
1149 if (op1_idx == op2_idx) {
1150 /* identically, one pop needed */
1152 x87_create_fxch(state, n, op1_idx);
1156 /* res = tos X op, pop */
1159 if (op1_idx != 0 && op2_idx != 0) {
1160 /* Both not at tos: Move one operand to tos. Move the one not at
1161 * pos 1, so we get a chance to use fucompp. */
1163 x87_create_fxch(state, n, op1_idx);
1166 x87_create_fxch(state, n, op2_idx);
1175 /* second operand is an address mode */
1177 x87_create_fxch(state, n, op1_idx);
1178 /* Pop first operand, if it is dead. */
1179 if (!is_fp_live(reg_index_1, live))
1182 op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
1183 op2_idx = attr->attr.data.ins_permuted ? 0 : -1;
1185 assert(op1_idx == 0 || op2_idx == 0);
1187 /* patch the operation */
1188 if (is_ia32_FucomFnstsw(n) && pops == 2
1189 && (op1_idx == 1 || op2_idx == 1)) {
1190 set_irn_op(n, op_ia32_FucomppFnstsw);
1197 int const idx = (op1_idx != 0 ? op1_idx : op2_idx) - 1 /* Due to prior pop. */;
1198 x87_create_fpop(state, sched_next(n), idx);
1202 int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
1203 attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
1204 attr->attr.data.ins_permuted = op1_idx != 0;
1205 attr->pop = pops != 0;
1208 char const *const l = op1_idx >= 0 ? get_st_reg(op1_idx)->name : "[AM]";
1209 char const *const r = op2_idx >= 0 ? get_st_reg(op2_idx)->name : "[AM]";
1210 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n), l, r));
1213 return NO_NODE_ADDED;
1219 * @param state the x87 state
1220 * @param n the node that should be simulated (and patched)
1222 * @return NO_NODE_ADDED
1224 static int sim_Keep(x87_state *state, ir_node *node)
1227 const arch_register_t *op_reg;
1233 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1235 arity = get_irn_arity(node);
1236 for (i = 0; i < arity; ++i) {
1237 op = get_irn_n(node, i);
1238 op_reg = arch_get_irn_register(op);
1239 if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_fp])
1242 reg_id = op_reg->index;
1243 live = fp_live_args_after(state->sim, node, 0);
1245 op_stack_idx = x87_on_stack(state, reg_id);
1246 if (op_stack_idx >= 0 && !is_fp_live(reg_id, live))
1247 x87_create_fpop(state, sched_next(node), 0);
1250 DB((dbg, LEVEL_1, "Stack after: "));
1251 DEBUG_ONLY(x87_dump_stack(state);)
1253 return NO_NODE_ADDED;
1257 * Keep the given node alive by adding a be_Keep.
1259 * @param node the node to kept alive
1261 static void keep_float_node_alive(ir_node *node)
1263 ir_node *block = get_nodes_block(node);
1264 ir_node *keep = be_new_Keep(block, 1, &node);
1265 sched_add_after(node, keep);
1269 * Create a copy of a node. Recreate the node if it's a constant.
1271 * @param state the x87 state
1272 * @param n the node to be copied
1274 * @return the copy of n
1276 static ir_node *create_Copy(x87_state *state, ir_node *n)
1278 dbg_info *n_dbg = get_irn_dbg_info(n);
1279 ir_mode *mode = get_irn_mode(n);
1280 ir_node *block = get_nodes_block(n);
1281 ir_node *pred = get_irn_n(n, 0);
1282 ir_node *(*cnstr)(dbg_info *, ir_node *) = NULL;
1284 const arch_register_t *out;
1285 const arch_register_t *op1;
1287 /* Do not copy constants, recreate them. */
1288 switch (get_ia32_irn_opcode(pred)) {
1290 cnstr = new_bd_ia32_fldz;
1293 cnstr = new_bd_ia32_fld1;
1295 case iro_ia32_fldpi:
1296 cnstr = new_bd_ia32_fldpi;
1298 case iro_ia32_fldl2e:
1299 cnstr = new_bd_ia32_fldl2e;
1301 case iro_ia32_fldl2t:
1302 cnstr = new_bd_ia32_fldl2t;
1304 case iro_ia32_fldlg2:
1305 cnstr = new_bd_ia32_fldlg2;
1307 case iro_ia32_fldln2:
1308 cnstr = new_bd_ia32_fldln2;
1314 out = x87_get_irn_register(n);
1315 op1 = x87_get_irn_register(pred);
1317 if (cnstr != NULL) {
1318 /* copy a constant */
1319 res = (*cnstr)(n_dbg, block);
1321 x87_push(state, out->index, res);
1323 int op1_idx = x87_on_stack(state, op1->index);
1325 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1327 x87_push(state, out->index, res);
1329 ia32_x87_attr_t *const attr = get_ia32_x87_attr(res);
1330 attr->reg = get_st_reg(op1_idx);
1332 arch_set_irn_register(res, out);
1338 * Simulate a be_Copy.
1340 * @param state the x87 state
1341 * @param n the node that should be simulated (and patched)
1343 * @return NO_NODE_ADDED
1345 static int sim_Copy(x87_state *state, ir_node *n)
1347 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1348 if (cls != &ia32_reg_classes[CLASS_ia32_fp])
1349 return NO_NODE_ADDED;
1351 ir_node *const pred = be_get_Copy_op(n);
1352 arch_register_t const *const op1 = x87_get_irn_register(pred);
1353 arch_register_t const *const out = x87_get_irn_register(n);
1354 unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
1356 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, op1->name, out->name));
1357 DEBUG_ONLY(fp_dump_live(live);)
1359 if (is_fp_live(op1->index, live)) {
1360 /* Operand is still live, a real copy. We need here an fpush that can
1361 hold a a register, so use the fpushCopy or recreate constants */
1362 ir_node *const node = create_Copy(state, n);
1364 /* We have to make sure the old value doesn't go dead (which can happen
1365 * when we recreate constants). As the simulator expected that value in
1366 * the pred blocks. This is unfortunate as removing it would save us 1
1367 * instruction, but we would have to rerun all the simulation to get
1370 ir_node *const next = sched_next(n);
1373 sched_add_before(next, node);
1375 if (get_irn_n_edges(pred) == 0) {
1376 keep_float_node_alive(pred);
1379 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1381 /* Just a virtual copy. */
1382 int const op1_idx = x87_on_stack(state, op1->index);
1383 x87_set_st(state, out->index, n, op1_idx);
1385 return NO_NODE_ADDED;
1389 * Returns the vf0 result Proj of a Call.
1391 * @para call the Call node
1393 static ir_node *get_call_result_proj(ir_node *call)
1395 /* search the result proj */
1396 foreach_out_edge(call, edge) {
1397 ir_node *proj = get_edge_src_irn(edge);
1398 long pn = get_Proj_proj(proj);
1400 if (pn == pn_ia32_Call_st0)
1404 panic("result Proj missing");
1407 static int sim_Asm(x87_state *const state, ir_node *const n)
1411 for (size_t i = get_irn_arity(n); i-- != 0;) {
1412 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1413 if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
1414 panic("cannot handle %+F with x87 constraints", n);
1417 be_foreach_out(n, i) {
1418 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1419 if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
1420 panic("cannot handle %+F with x87 constraints", n);
1423 return NO_NODE_ADDED;
1427 * Simulate a ia32_Call.
1429 * @param state the x87 state
1430 * @param n the node that should be simulated (and patched)
1432 * @return NO_NODE_ADDED
1434 static int sim_Call(x87_state *state, ir_node *n)
1436 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1438 /* at the begin of a call the x87 state should be empty */
1439 assert(state->depth == 0 && "stack not empty before call");
1441 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1442 if (get_method_n_ress(call_tp) != 0) {
1443 /* If the called function returns a float, it is returned in st(0).
1444 * This even happens if the return value is NOT used.
1445 * Moreover, only one return result is supported. */
1446 ir_type *const res_type = get_method_res_type(call_tp, 0);
1447 ir_mode *const mode = get_type_mode(res_type);
1448 if (mode && mode_is_float(mode)) {
1449 ir_node *const resproj = get_call_result_proj(n);
1450 arch_register_t const *const reg = x87_get_irn_register(resproj);
1451 x87_push(state, reg->index, resproj);
1454 DB((dbg, LEVEL_1, "Stack after: "));
1455 DEBUG_ONLY(x87_dump_stack(state);)
1457 return NO_NODE_ADDED;
1461 * Simulate a be_Return.
1463 * @param state the x87 state
1464 * @param n the node that should be simulated (and patched)
1466 * @return NO_NODE_ADDED
1468 static int sim_Return(x87_state *state, ir_node *n)
1470 #ifdef DEBUG_libfirm
1471 /* only floating point return values must reside on stack */
1472 int n_float_res = 0;
1473 int const n_res = be_Return_get_n_rets(n);
1474 for (int i = 0; i < n_res; ++i) {
1475 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1476 if (mode_is_float(get_irn_mode(res)))
1479 assert(x87_get_depth(state) == n_float_res);
1482 /* pop them virtually */
1484 return NO_NODE_ADDED;
1488 * Simulate a be_Perm.
1490 * @param state the x87 state
1491 * @param irn the node that should be simulated (and patched)
1493 * @return NO_NODE_ADDED
1495 static int sim_Perm(x87_state *state, ir_node *irn)
1498 ir_node *pred = get_irn_n(irn, 0);
1501 /* handle only floating point Perms */
1502 if (! mode_is_float(get_irn_mode(pred)))
1503 return NO_NODE_ADDED;
1505 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1507 /* Perm is a pure virtual instruction on x87.
1508 All inputs must be on the FPU stack and are pairwise
1509 different from each other.
1510 So, all we need to do is to permutate the stack state. */
1511 n = get_irn_arity(irn);
1512 NEW_ARR_A(int, stack_pos, n);
1514 /* collect old stack positions */
1515 for (i = 0; i < n; ++i) {
1516 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1517 int idx = x87_on_stack(state, inreg->index);
1519 assert(idx >= 0 && "Perm argument not on x87 stack");
1523 /* now do the permutation */
1524 foreach_out_edge(irn, edge) {
1525 ir_node *proj = get_edge_src_irn(edge);
1526 const arch_register_t *out = x87_get_irn_register(proj);
1527 long num = get_Proj_proj(proj);
1529 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1530 x87_set_st(state, out->index, proj, stack_pos[(unsigned)num]);
1532 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1534 return NO_NODE_ADDED;
1538 * Kill any dead registers at block start by popping them from the stack.
1540 * @param sim the simulator handle
1541 * @param block the current block
1542 * @param state the x87 state at the begin of the block
1544 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1546 ir_node *first_insn = sched_first(block);
1547 ir_node *keep = NULL;
1548 unsigned live = fp_live_args_after(sim, block, 0);
1553 depth = x87_get_depth(state);
1554 for (i = depth - 1; i >= 0; --i) {
1555 int reg = x87_get_st_reg(state, i);
1557 if (! is_fp_live(reg, live))
1558 kill_mask |= (1 << i);
1562 DB((dbg, LEVEL_1, "Killing deads:\n"));
1563 DEBUG_ONLY(fp_dump_live(live);)
1564 DEBUG_ONLY(x87_dump_stack(state);)
1566 if (kill_mask != 0 && live == 0) {
1567 /* special case: kill all registers */
1568 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1569 if (ia32_cg_config.use_femms) {
1570 /* use FEMMS on AMD processors to clear all */
1571 keep = new_bd_ia32_femms(NULL, block);
1573 /* use EMMS to clear all */
1574 keep = new_bd_ia32_emms(NULL, block);
1576 sched_add_before(first_insn, keep);
1582 /* now kill registers */
1584 /* we can only kill from TOS, so bring them up */
1585 if (! (kill_mask & 1)) {
1586 /* search from behind, because we can to a double-pop */
1587 for (i = depth - 1; i >= 0; --i) {
1588 if (kill_mask & (1 << i)) {
1589 kill_mask &= ~(1 << i);
1596 x87_set_st(state, -1, keep, i);
1597 x87_create_fxch(state, first_insn, i);
1602 keep = x87_create_fpop(state, first_insn, 0);
1609 * Run a simulation and fix all virtual instructions for a block.
1611 * @param sim the simulator handle
1612 * @param block the current block
1614 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1617 blk_state *bl_state = x87_get_bl_state(sim, block);
1618 x87_state *state = bl_state->begin;
1619 ir_node *start_block;
1621 assert(state != NULL);
1622 /* already processed? */
1623 if (bl_state->end != NULL)
1626 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1627 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1628 DEBUG_ONLY(x87_dump_stack(state);)
1630 /* create a new state, will be changed */
1631 state = x87_clone_state(sim, state);
1632 /* at block begin, kill all dead registers */
1633 x87_kill_deads(sim, block, state);
1635 /* beware, n might change */
1636 for (n = sched_first(block); !sched_is_end(n); n = next) {
1639 ir_op *op = get_irn_op(n);
1642 * get the next node to be simulated here.
1643 * n might be completely removed from the schedule-
1645 next = sched_next(n);
1646 if (op->ops.generic != NULL) {
1647 func = (sim_func)op->ops.generic;
1650 node_inserted = (*func)(state, n);
1653 * sim_func might have added an additional node after n,
1654 * so update next node
1655 * beware: n must not be changed by sim_func
1656 * (i.e. removed from schedule) in this case
1658 if (node_inserted != NO_NODE_ADDED)
1659 next = sched_next(n);
1663 start_block = get_irg_start_block(get_irn_irg(block));
1665 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1667 /* check if the state must be shuffled */
1668 foreach_block_succ(block, edge) {
1669 ir_node *succ = get_edge_src_irn(edge);
1670 blk_state *succ_state;
1672 if (succ == start_block)
1675 succ_state = x87_get_bl_state(sim, succ);
1677 if (succ_state->begin == NULL) {
1678 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
1679 DEBUG_ONLY(x87_dump_stack(state);)
1680 succ_state->begin = state;
1682 waitq_put(sim->worklist, succ);
1684 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
1685 /* There is already a begin state for the successor, bad.
1686 Do the necessary permutations.
1687 Note that critical edges are removed, so this is always possible:
1688 If the successor has more than one possible input, then it must
1691 x87_shuffle(block, state, succ_state->begin);
1694 bl_state->end = state;
1698 * Register a simulator function.
1700 * @param op the opcode to simulate
1701 * @param func the simulator function for the opcode
1703 static void register_sim(ir_op *op, sim_func func)
1705 assert(op->ops.generic == NULL);
1706 op->ops.generic = (op_func) func;
1710 * Create a new x87 simulator.
1712 * @param sim a simulator handle, will be initialized
1713 * @param irg the current graph
1715 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
1717 obstack_init(&sim->obst);
1718 sim->blk_states = pmap_create();
1719 sim->n_idx = get_irg_last_idx(irg);
1720 sim->live = OALLOCN(&sim->obst, fp_liveness, sim->n_idx);
1722 DB((dbg, LEVEL_1, "--------------------------------\n"
1723 "x87 Simulator started for %+F\n", irg));
1725 /* set the generic function pointer of instruction we must simulate */
1726 ir_clear_opcodes_generic_func();
1728 register_sim(op_ia32_Asm, sim_Asm);
1729 register_sim(op_ia32_Call, sim_Call);
1730 register_sim(op_ia32_fld, sim_load);
1731 register_sim(op_ia32_fild, sim_load);
1732 register_sim(op_ia32_fld1, sim_load);
1733 register_sim(op_ia32_fldz, sim_load);
1734 register_sim(op_ia32_fadd, sim_binop);
1735 register_sim(op_ia32_fsub, sim_binop);
1736 register_sim(op_ia32_fmul, sim_binop);
1737 register_sim(op_ia32_fdiv, sim_binop);
1738 register_sim(op_ia32_fprem, sim_fprem);
1739 register_sim(op_ia32_fabs, sim_unop);
1740 register_sim(op_ia32_fchs, sim_unop);
1741 register_sim(op_ia32_fist, sim_store);
1742 register_sim(op_ia32_fisttp, sim_fisttp);
1743 register_sim(op_ia32_fst, sim_store);
1744 register_sim(op_ia32_FtstFnstsw, sim_FtstFnstsw);
1745 register_sim(op_ia32_FucomFnstsw, sim_Fucom);
1746 register_sim(op_ia32_Fucomi, sim_Fucom);
1747 register_sim(op_be_Copy, sim_Copy);
1748 register_sim(op_be_Return, sim_Return);
1749 register_sim(op_be_Perm, sim_Perm);
1750 register_sim(op_be_Keep, sim_Keep);
1754 * Destroy a x87 simulator.
1756 * @param sim the simulator handle
1758 static void x87_destroy_simulator(x87_simulator *sim)
1760 pmap_destroy(sim->blk_states);
1761 obstack_free(&sim->obst, NULL);
1762 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
1766 * Pre-block walker: calculate the liveness information for the block
1767 * and store it into the sim->live cache.
1769 static void update_liveness_walker(ir_node *block, void *data)
1771 x87_simulator *sim = (x87_simulator*)data;
1772 update_liveness(sim, block);
1776 * Run a simulation and fix all virtual instructions for a graph.
1777 * Replaces all virtual floating point instructions and registers
1780 void ia32_x87_simulate_graph(ir_graph *irg)
1782 /* TODO improve code quality (less executed fxch) by using execfreqs */
1784 ir_node *block, *start_block;
1785 blk_state *bl_state;
1788 /* create the simulator */
1789 x87_init_simulator(&sim, irg);
1791 start_block = get_irg_start_block(irg);
1792 bl_state = x87_get_bl_state(&sim, start_block);
1794 /* start with the empty state */
1796 bl_state->begin = ∅
1798 sim.worklist = new_waitq();
1799 waitq_put(sim.worklist, start_block);
1801 be_assure_live_sets(irg);
1802 sim.lv = be_get_irg_liveness(irg);
1804 /* Calculate the liveness for all nodes. We must precalculate this info,
1805 * because the simulator adds new nodes (possible before Phi nodes) which
1806 * would let a lazy calculation fail.
1807 * On the other hand we reduce the computation amount due to
1808 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
1810 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
1814 block = (ir_node*)waitq_get(sim.worklist);
1815 x87_simulate_block(&sim, block);
1816 } while (! waitq_empty(sim.worklist));
1819 del_waitq(sim.worklist);
1820 x87_destroy_simulator(&sim);
1823 /* Initializes the x87 simulator. */
1824 void ia32_init_x87(void)
1826 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");