2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define N_FLOAT_REGS (N_ia32_fp_REGS-1) // exclude NOREG
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An entry on the simulated x87 stack.
66 typedef struct st_entry {
67 int reg_idx; /**< the virtual register index of this stack value */
68 ir_node *node; /**< the node that produced this value */
74 typedef struct x87_state {
75 st_entry st[N_FLOAT_REGS]; /**< the register stack */
76 int depth; /**< the current stack depth */
77 x87_simulator *sim; /**< The simulator. */
80 /** An empty state, used for blocks without fp instructions. */
81 static x87_state empty = { { {0, NULL}, }, 0, NULL };
84 * Return values of the instruction simulator functions.
87 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
88 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
89 in the schedule AFTER the current node. */
93 * The type of an instruction simulator function.
95 * @param state the x87 state
96 * @param n the node to be simulated
98 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
100 * NO_NODE_ADDED otherwise
102 typedef int (*sim_func)(x87_state *state, ir_node *n);
105 * A block state: Every block has a x87 state at the beginning and at the end.
107 typedef struct blk_state {
108 x87_state *begin; /**< state at the begin or NULL if not assigned */
109 x87_state *end; /**< state at the end or NULL if not assigned */
112 /** liveness bitset for fp registers. */
113 typedef unsigned char fp_liveness;
118 struct x87_simulator {
119 struct obstack obst; /**< An obstack for fast allocating. */
120 pmap *blk_states; /**< Map blocks to states. */
121 be_lv_t *lv; /**< intrablock liveness. */
122 fp_liveness *live; /**< Liveness information. */
123 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
124 waitq *worklist; /**< Worklist of blocks that must be processed. */
128 * Returns the current stack depth.
130 * @param state the x87 state
132 * @return the x87 stack depth
134 static int x87_get_depth(const x87_state *state)
139 static st_entry *x87_get_entry(x87_state *const state, int const pos)
141 assert(0 <= pos && pos < state->depth);
142 return &state->st[N_FLOAT_REGS - state->depth + pos];
146 * Return the virtual register index at st(pos).
148 * @param state the x87 state
149 * @param pos a stack position
151 * @return the fp register index that produced the value at st(pos)
153 static int x87_get_st_reg(const x87_state *state, int pos)
155 return x87_get_entry((x87_state*)state, pos)->reg_idx;
160 * Dump the stack for debugging.
162 * @param state the x87 state
164 static void x87_dump_stack(const x87_state *state)
166 for (int i = state->depth; i-- != 0;) {
167 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
168 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
170 DB((dbg, LEVEL_2, "<-- TOS\n"));
172 #endif /* DEBUG_libfirm */
175 * Set a virtual register to st(pos).
177 * @param state the x87 state
178 * @param reg_idx the fp register index that should be set
179 * @param node the IR node that produces the value of the fp register
180 * @param pos the stack position where the new value should be entered
182 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
184 st_entry *const entry = x87_get_entry(state, pos);
185 entry->reg_idx = reg_idx;
188 DB((dbg, LEVEL_2, "After SET_REG: "));
189 DEBUG_ONLY(x87_dump_stack(state);)
193 * Swap st(0) with st(pos).
195 * @param state the x87 state
196 * @param pos the stack position to change the tos with
198 static void x87_fxch(x87_state *state, int pos)
200 st_entry *const a = x87_get_entry(state, pos);
201 st_entry *const b = x87_get_entry(state, 0);
202 st_entry const t = *a;
206 DB((dbg, LEVEL_2, "After FXCH: "));
207 DEBUG_ONLY(x87_dump_stack(state);)
211 * Convert a virtual register to the stack index.
213 * @param state the x87 state
214 * @param reg_idx the register fp index
216 * @return the stack position where the register is stacked
217 * or -1 if the virtual register was not found
219 static int x87_on_stack(const x87_state *state, int reg_idx)
221 for (int i = 0; i < state->depth; ++i) {
222 if (x87_get_st_reg(state, i) == reg_idx)
229 * Push a virtual Register onto the stack, double pushes are NOT allowed.
231 * @param state the x87 state
232 * @param reg_idx the register fp index
233 * @param node the node that produces the value of the fp register
235 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
237 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
238 assert(state->depth < N_FLOAT_REGS && "stack overrun");
241 st_entry *const entry = x87_get_entry(state, 0);
242 entry->reg_idx = reg_idx;
245 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
249 * Pop a virtual Register from the stack.
251 * @param state the x87 state
253 static void x87_pop(x87_state *state)
255 assert(state->depth > 0 && "stack underrun");
259 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
263 * Empty the fpu stack
265 * @param state the x87 state
267 static void x87_emms(x87_state *state)
273 * Returns the block state of a block.
275 * @param sim the x87 simulator handle
276 * @param block the current block
278 * @return the block state
280 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
282 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
285 res = OALLOC(&sim->obst, blk_state);
289 pmap_insert(sim->blk_states, block, res);
298 * @param sim the x87 simulator handle
299 * @param src the x87 state that will be cloned
301 * @return a cloned copy of the src state
303 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
305 x87_state *const res = OALLOC(&sim->obst, x87_state);
311 * Returns the first Proj of a mode_T node having a given mode.
313 * @param n the mode_T node
314 * @param m the desired mode of the Proj
315 * @return The first Proj of mode @p m found.
317 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
319 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
321 foreach_out_edge(n, edge) {
322 ir_node *proj = get_edge_src_irn(edge);
323 if (get_irn_mode(proj) == m)
327 panic("Proj not found");
331 * Wrap the arch_* function here so we can check for errors.
333 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
335 const arch_register_t *res = arch_get_irn_register(irn);
337 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
341 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
344 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
346 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
350 static inline const arch_register_t *get_st_reg(int index)
352 return &ia32_registers[REG_ST0 + index];
356 * Create a fxch node before another node.
358 * @param state the x87 state
359 * @param n the node after the fxch
360 * @param pos exchange st(pos) with st(0)
362 static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
364 x87_fxch(state, pos);
366 ir_node *const block = get_nodes_block(n);
367 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
368 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
369 attr->reg = get_st_reg(pos);
373 sched_add_before(n, fxch);
374 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fxch), attr->reg->name));
377 /* -------------- x87 perm --------------- */
380 * Calculate the necessary permutations to reach dst_state.
382 * These permutations are done with fxch instructions and placed
383 * at the end of the block.
385 * Note that critical edges are removed here, so we need only
386 * a shuffle if the current block has only one successor.
388 * @param block the current block
389 * @param state the current x87 stack state, might be modified
390 * @param dst_state destination state
394 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
396 int i, n_cycles, k, ri;
397 unsigned cycles[4], all_mask;
398 char cycle_idx[4][8];
400 assert(state->depth == dst_state->depth);
402 /* Some mathematics here:
403 * If we have a cycle of length n that includes the tos,
404 * we need n-1 exchange operations.
405 * We can always add the tos and restore it, so we need
406 * n+1 exchange operations for a cycle not containing the tos.
407 * So, the maximum of needed operations is for a cycle of 7
408 * not including the tos == 8.
409 * This is the same number of ops we would need for using stores,
410 * so exchange is cheaper (we save the loads).
411 * On the other hand, we might need an additional exchange
412 * in the next block to bring one operand on top, so the
413 * number of ops in the first case is identical.
414 * Further, no more than 4 cycles can exists (4 x 2). */
415 all_mask = (1 << (state->depth)) - 1;
417 for (n_cycles = 0; all_mask; ++n_cycles) {
418 int src_idx, dst_idx;
420 /* find the first free slot */
421 for (i = 0; i < state->depth; ++i) {
422 if (all_mask & (1 << i)) {
423 all_mask &= ~(1 << i);
425 /* check if there are differences here */
426 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
432 /* no more cycles found */
437 cycles[n_cycles] = (1 << i);
438 cycle_idx[n_cycles][k++] = i;
439 for (src_idx = i; ; src_idx = dst_idx) {
440 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
442 if ((all_mask & (1 << dst_idx)) == 0)
445 cycle_idx[n_cycles][k++] = dst_idx;
446 cycles[n_cycles] |= (1 << dst_idx);
447 all_mask &= ~(1 << dst_idx);
449 cycle_idx[n_cycles][k] = -1;
453 /* no permutation needed */
457 /* Hmm: permutation needed */
458 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
459 DEBUG_ONLY(x87_dump_stack(state);)
460 DB((dbg, LEVEL_2, " to\n"));
461 DEBUG_ONLY(x87_dump_stack(dst_state);)
465 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
466 for (ri = 0; ri < n_cycles; ++ri) {
467 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
468 for (k = 0; cycle_idx[ri][k] != -1; ++k)
469 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
470 DB((dbg, LEVEL_2, "\n"));
475 * Find the place node must be insert.
476 * We have only one successor block, so the last instruction should
479 ir_node *const before = sched_last(block);
480 assert(is_cfop(before));
482 /* now do the permutations */
483 for (ri = 0; ri < n_cycles; ++ri) {
484 if ((cycles[ri] & 1) == 0) {
485 /* this cycle does not include the tos */
486 x87_create_fxch(state, before, cycle_idx[ri][0]);
488 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
489 x87_create_fxch(state, before, cycle_idx[ri][k]);
491 if ((cycles[ri] & 1) == 0) {
492 /* this cycle does not include the tos */
493 x87_create_fxch(state, before, cycle_idx[ri][0]);
500 * Create a fpush before node n.
502 * @param state the x87 state
503 * @param n the node after the fpush
504 * @param pos push st(pos) on stack
505 * @param val the value to push
507 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
509 x87_push(state, out_reg_idx, val);
511 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
512 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
513 attr->reg = get_st_reg(pos);
516 sched_add_before(n, fpush);
518 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpush), attr->reg->name));
522 * Create a fpop before node n.
523 * This overwrites st(pos) with st(0) and pops st(0).
525 * @param state the x87 state
526 * @param n the node after the fpop
527 * @param pos the index of the entry to remove the register stack
529 * @return the fpop node
531 static ir_node *x87_create_fpop(x87_state *const state, ir_node *const n, int const pos)
534 st_entry *const dst = x87_get_entry(state, pos);
535 st_entry *const src = x87_get_entry(state, 0);
539 ir_node *const block = get_nodes_block(n);
540 ir_node *const fpop = pos == 0 && ia32_cg_config.use_ffreep ?
541 new_bd_ia32_ffreep(NULL, block) :
542 new_bd_ia32_fpop( NULL, block);
543 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpop);
544 attr->reg = get_st_reg(pos);
547 sched_add_before(n, fpop);
548 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->reg->name));
552 /* --------------------------------- liveness ------------------------------------------ */
555 * The liveness transfer function.
556 * Updates a live set over a single step from a given node to its predecessor.
557 * Everything defined at the node is removed from the set, the uses of the node get inserted.
559 * @param irn The node at which liveness should be computed.
560 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
561 * the registers live after irn.
563 * @return The live bitset.
565 static fp_liveness fp_liveness_transfer(ir_node *irn, fp_liveness live)
568 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
570 be_foreach_definition(irn, cls, def,
571 const arch_register_t *reg = x87_get_irn_register(def);
572 live &= ~(1 << reg->index);
575 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
576 ir_node *op = get_irn_n(irn, i);
578 if (mode_is_float(get_irn_mode(op)) &&
579 arch_irn_consider_in_reg_alloc(cls, op)) {
580 const arch_register_t *reg = x87_get_irn_register(op);
581 live |= 1 << reg->index;
588 * Put all live virtual registers at the end of a block into a bitset.
590 * @param sim the simulator handle
591 * @param bl the block
593 * @return The live bitset at the end of this block
595 static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
597 fp_liveness live = 0;
598 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
599 const be_lv_t *lv = sim->lv;
601 be_lv_foreach_cls(lv, block, be_lv_state_end, cls, node) {
602 const arch_register_t *reg = x87_get_irn_register(node);
603 live |= 1 << reg->index;
609 /** get the register mask from an arch_register */
610 #define REGMASK(reg) (1 << (reg->index))
613 * Return a bitset of argument registers which are live at the end of a node.
615 * @param sim the simulator handle
616 * @param pos the node
617 * @param kill kill mask for the output registers
619 * @return The live bitset.
621 static unsigned fp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
623 unsigned idx = get_irn_idx(pos);
625 assert(idx < sim->n_idx);
626 return sim->live[idx] & ~kill;
630 * Calculate the liveness for a whole block and cache it.
632 * @param sim the simulator handle
633 * @param block the block
635 static void update_liveness(x87_simulator *sim, ir_node *block)
637 fp_liveness live = fp_liveness_end_of_block(sim, block);
640 /* now iterate through the block backward and cache the results */
641 sched_foreach_reverse(block, irn) {
642 /* stop at the first Phi: this produces the live-in */
646 idx = get_irn_idx(irn);
647 sim->live[idx] = live;
649 live = fp_liveness_transfer(irn, live);
651 idx = get_irn_idx(block);
652 sim->live[idx] = live;
656 * Returns true if a register is live in a set.
658 * @param reg_idx the fp register index
659 * @param live a live bitset
661 #define is_fp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
665 * Dump liveness info.
667 * @param live the live bitset
669 static void fp_dump_live(fp_liveness live)
673 DB((dbg, LEVEL_2, "Live after: "));
674 for (i = 0; i < 8; ++i) {
675 if (live & (1 << i)) {
676 DB((dbg, LEVEL_2, "vf%d ", i));
679 DB((dbg, LEVEL_2, "\n"));
681 #endif /* DEBUG_libfirm */
683 /* --------------------------------- simulators ---------------------------------------- */
686 * Simulate a virtual binop.
688 * @param state the x87 state
689 * @param n the node that should be simulated (and patched)
691 * @return NO_NODE_ADDED
693 static int sim_binop(x87_state *const state, ir_node *const n)
695 x87_simulator *sim = state->sim;
696 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
697 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
698 const arch_register_t *op1_reg = x87_get_irn_register(op1);
699 const arch_register_t *op2_reg = x87_get_irn_register(op2);
700 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
701 int reg_index_1 = op1_reg->index;
702 int reg_index_2 = op2_reg->index;
703 fp_liveness live = fp_live_args_after(sim, n, REGMASK(out));
707 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, op1_reg->name, op2_reg->name, out->name));
708 DEBUG_ONLY(fp_dump_live(live);)
709 DB((dbg, LEVEL_1, "Stack before: "));
710 DEBUG_ONLY(x87_dump_stack(state);)
712 int op1_idx = x87_on_stack(state, reg_index_1);
713 assert(op1_idx >= 0);
714 op1_live_after = is_fp_live(reg_index_1, live);
719 int const out_reg_idx = out->index;
720 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
721 if (reg_index_2 != REG_FP_FP_NOREG) {
722 /* second operand is a fp register */
723 op2_idx = x87_on_stack(state, reg_index_2);
724 assert(op2_idx >= 0);
725 op2_live_after = is_fp_live(reg_index_2, live);
727 if (op2_live_after) {
728 /* Second operand is live. */
730 if (op1_live_after) {
731 /* Both operands are live: push the first one.
732 * This works even for op1 == op2. */
733 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
734 /* now do fxxx (tos=tos X op) */
739 /* Second live, first operand is dead: Overwrite first. */
740 if (op1_idx != 0 && op2_idx != 0) {
741 /* Bring one operand to tos. */
742 x87_create_fxch(state, n, op1_idx);
748 /* Second operand is dead. */
749 if (op1_live_after) {
750 /* First operand is live, second is dead: Overwrite second. */
751 if (op1_idx != 0 && op2_idx != 0) {
752 /* Bring one operand to tos. */
753 x87_create_fxch(state, n, op2_idx);
758 /* Both operands are dead. */
759 if (op1_idx == op2_idx) {
760 /* Operands are identical: no pop. */
762 x87_create_fxch(state, n, op1_idx);
767 if (op1_idx != 0 && op2_idx != 0) {
768 /* Bring one operand to tos. Heuristically swap the operand not at
769 * st(1) to tos. This way, if any operand was at st(1), the result
770 * will end up in the new st(0) after the implicit pop. If the next
771 * operation uses the result, then no fxch will be necessary. */
773 x87_create_fxch(state, n, op1_idx);
776 x87_create_fxch(state, n, op2_idx);
782 out_idx = op1_idx != 0 ? op1_idx : op2_idx;
786 /* second operand is an address mode */
787 if (op1_live_after) {
788 /* first operand is live: push it here */
789 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
791 /* first operand is dead: bring it to tos */
793 x87_create_fxch(state, n, op1_idx);
796 op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
797 op2_idx = attr->attr.data.ins_permuted ? 0 : -1;
800 assert(op1_idx == 0 || op2_idx == 0);
801 assert(out_idx == op1_idx || out_idx == op2_idx);
803 x87_set_st(state, out_reg_idx, n, out_idx);
807 /* patch the operation */
808 int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
809 attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
810 attr->attr.data.ins_permuted = op1_idx != 0;
811 attr->res_in_reg = out_idx != 0;
815 char const *const l = op1_idx >= 0 ? get_st_reg(op1_idx)->name : "[AM]";
816 char const *const r = op2_idx >= 0 ? get_st_reg(op2_idx)->name : "[AM]";
817 char const *const o = get_st_reg(out_idx)->name;
818 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), l, r, o));
821 return NO_NODE_ADDED;
825 * Simulate a virtual Unop.
827 * @param state the x87 state
828 * @param n the node that should be simulated (and patched)
830 * @return NO_NODE_ADDED
832 static int sim_unop(x87_state *state, ir_node *n)
834 arch_register_t const *const out = x87_get_irn_register(n);
835 unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
836 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
837 DEBUG_ONLY(fp_dump_live(live);)
839 ir_node *const op1 = get_irn_n(n, 0);
840 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
841 int const op1_reg_idx = op1_reg->index;
842 int const op1_idx = x87_on_stack(state, op1_reg_idx);
843 int const out_reg_idx = out->index;
844 if (is_fp_live(op1_reg_idx, live)) {
845 /* push the operand here */
846 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
848 /* operand is dead, bring it to tos */
850 x87_create_fxch(state, n, op1_idx);
854 x87_set_st(state, out_reg_idx, n, 0);
855 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
857 return NO_NODE_ADDED;
861 * Simulate a virtual Load instruction.
863 * @param state the x87 state
864 * @param n the node that should be simulated (and patched)
866 * @return NO_NODE_ADDED
868 static int sim_load(x87_state *state, ir_node *n)
870 assert((int)pn_ia32_fld_res == (int)pn_ia32_fild_res
871 && (int)pn_ia32_fld_res == (int)pn_ia32_fld1_res
872 && (int)pn_ia32_fld_res == (int)pn_ia32_fldz_res);
873 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_fld_res);
875 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
876 x87_push(state, out->index, n);
877 assert(out == x87_irn_get_register(n, pn_ia32_fld_res));
878 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
880 return NO_NODE_ADDED;
884 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
886 * @param store The store
887 * @param old_val The former value
888 * @param new_val The new value
890 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
892 foreach_out_edge_safe(old_val, edge) {
893 ir_node *user = get_edge_src_irn(edge);
894 /* if the user is scheduled after the store: rewire */
895 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
896 set_irn_n(user, get_edge_src_pos(edge), new_val);
902 * Simulate a virtual Store.
904 * @param state the x87 state
905 * @param n the node that should be simulated (and patched)
907 static int sim_store(x87_state *state, ir_node *n)
909 ir_node *const val = get_irn_n(n, n_ia32_fst_val);
910 arch_register_t const *const op2 = x87_get_irn_register(val);
911 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
914 int insn = NO_NODE_ADDED;
915 int const op2_reg_idx = op2->index;
916 int const op2_idx = x87_on_stack(state, op2_reg_idx);
917 unsigned const live = fp_live_args_after(state->sim, n, 0);
918 int const live_after_node = is_fp_live(op2_reg_idx, live);
919 assert(op2_idx >= 0);
920 if (live_after_node) {
921 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
922 * fist doesn't support 64bit mode, only fistp
924 * - stack not full: push value and fstp
925 * - stack full: fstp value and load again
926 * Note that we cannot test on mode_E, because floats might be 80bit ... */
927 ir_mode *const mode = get_ia32_ls_mode(n);
928 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
929 if (x87_get_depth(state) < N_FLOAT_REGS) {
930 /* ok, we have a free register: push + fstp */
931 x87_create_fpush(state, n, op2_idx, REG_FP_FP_NOREG, val);
934 /* stack full here: need fstp + load */
937 ir_node *const block = get_nodes_block(n);
938 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
939 ir_node *const vfld = new_bd_ia32_fld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
941 /* copy all attributes */
942 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
943 if (is_ia32_use_frame(n))
944 set_ia32_use_frame(vfld);
945 set_ia32_op_type(vfld, ia32_AddrModeS);
946 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
947 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
948 set_ia32_ls_mode(vfld, mode);
950 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_fld_res);
951 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_fld_M);
953 arch_set_irn_register(rproj, op2);
955 /* reroute all former users of the store memory to the load memory */
956 edges_reroute_except(mem, mproj, vfld);
958 sched_add_after(n, vfld);
960 /* rewire all users, scheduled after the store, to the loaded value */
961 collect_and_rewire_users(n, val, rproj);
966 /* we can only store the tos to memory */
968 x87_create_fxch(state, n, op2_idx);
971 /* we can only store the tos to memory */
973 x87_create_fxch(state, n, op2_idx);
981 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
983 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
988 static int sim_fprem(x87_state *const state, ir_node *const n)
992 panic("TODO implement");
993 return NO_NODE_ADDED;
997 * Simulate a virtual fisttp.
999 * @param state the x87 state
1000 * @param n the node that should be simulated (and patched)
1002 * @return NO_NODE_ADDED
1004 static int sim_fisttp(x87_state *state, ir_node *n)
1006 ir_node *val = get_irn_n(n, n_ia32_fst_val);
1007 const arch_register_t *op2 = x87_get_irn_register(val);
1009 int const op2_idx = x87_on_stack(state, op2->index);
1010 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
1011 assert(op2_idx >= 0);
1013 /* Note: although the value is still live here, it is destroyed because
1014 of the pop. The register allocator is aware of that and introduced a copy
1015 if the value must be alive. */
1017 /* we can only store the tos to memory */
1019 x87_create_fxch(state, n, op2_idx);
1023 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
1025 return NO_NODE_ADDED;
1029 * Simulate a virtual FtstFnstsw.
1031 * @param state the x87 state
1032 * @param n the node that should be simulated (and patched)
1034 * @return NO_NODE_ADDED
1036 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1038 x87_simulator *sim = state->sim;
1039 ir_node *op1_node = get_irn_n(n, n_ia32_FtstFnstsw_left);
1040 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1041 int reg_index_1 = reg1->index;
1042 int op1_idx = x87_on_stack(state, reg_index_1);
1043 unsigned live = fp_live_args_after(sim, n, 0);
1045 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, reg1->name));
1046 DEBUG_ONLY(fp_dump_live(live);)
1047 DB((dbg, LEVEL_1, "Stack before: "));
1048 DEBUG_ONLY(x87_dump_stack(state);)
1049 assert(op1_idx >= 0);
1052 /* bring the value to tos */
1053 x87_create_fxch(state, n, op1_idx);
1056 if (!is_fp_live(reg_index_1, live))
1057 x87_create_fpop(state, sched_next(n), 0);
1059 return NO_NODE_ADDED;
1065 * @param state the x87 state
1066 * @param n the node that should be simulated (and patched)
1068 * @return NO_NODE_ADDED
1070 static int sim_Fucom(x87_state *state, ir_node *n)
1072 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1073 x87_simulator *sim = state->sim;
1074 ir_node *op1_node = get_irn_n(n, n_ia32_FucomFnstsw_left);
1075 ir_node *op2_node = get_irn_n(n, n_ia32_FucomFnstsw_right);
1076 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1077 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1078 int reg_index_1 = op1->index;
1079 int reg_index_2 = op2->index;
1080 unsigned live = fp_live_args_after(sim, n, 0);
1082 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, op1->name, op2->name));
1083 DEBUG_ONLY(fp_dump_live(live);)
1084 DB((dbg, LEVEL_1, "Stack before: "));
1085 DEBUG_ONLY(x87_dump_stack(state);)
1087 int op1_idx = x87_on_stack(state, reg_index_1);
1088 assert(op1_idx >= 0);
1092 /* BEWARE: check for comp a,a cases, they might happen */
1093 if (reg_index_2 != REG_FP_FP_NOREG) {
1094 /* second operand is a fp register */
1095 op2_idx = x87_on_stack(state, reg_index_2);
1096 assert(op2_idx >= 0);
1098 if (is_fp_live(reg_index_2, live)) {
1099 /* second operand is live */
1101 if (is_fp_live(reg_index_1, live)) {
1102 /* both operands are live */
1103 if (op1_idx != 0 && op2_idx != 0) {
1104 /* bring the first one to tos */
1105 x87_create_fxch(state, n, op1_idx);
1106 if (op1_idx == op2_idx)
1109 /* res = tos X op */
1112 /* second live, first operand is dead here, bring it to tos.
1113 This means further, op1_idx != op2_idx. */
1114 assert(op1_idx != op2_idx);
1116 x87_create_fxch(state, n, op1_idx);
1121 /* res = tos X op, pop */
1125 /* second operand is dead */
1126 if (is_fp_live(reg_index_1, live)) {
1127 /* first operand is live: bring second to tos.
1128 This means further, op1_idx != op2_idx. */
1129 assert(op1_idx != op2_idx);
1131 x87_create_fxch(state, n, op2_idx);
1136 /* res = op X tos, pop */
1139 /* both operands are dead here, check first for identity. */
1140 if (op1_idx == op2_idx) {
1141 /* identically, one pop needed */
1143 x87_create_fxch(state, n, op1_idx);
1147 /* res = tos X op, pop */
1150 if (op1_idx != 0 && op2_idx != 0) {
1151 /* Both not at tos: Move one operand to tos. Move the one not at
1152 * pos 1, so we get a chance to use fucompp. */
1154 x87_create_fxch(state, n, op1_idx);
1157 x87_create_fxch(state, n, op2_idx);
1166 /* second operand is an address mode */
1168 x87_create_fxch(state, n, op1_idx);
1169 /* Pop first operand, if it is dead. */
1170 if (!is_fp_live(reg_index_1, live))
1173 op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
1174 op2_idx = attr->attr.data.ins_permuted ? 0 : -1;
1176 assert(op1_idx == 0 || op2_idx == 0);
1178 /* patch the operation */
1179 if (is_ia32_FucomFnstsw(n) && pops == 2
1180 && (op1_idx == 1 || op2_idx == 1)) {
1181 set_irn_op(n, op_ia32_FucomppFnstsw);
1188 int const idx = (op1_idx != 0 ? op1_idx : op2_idx) - 1 /* Due to prior pop. */;
1189 x87_create_fpop(state, sched_next(n), idx);
1193 int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
1194 attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
1195 attr->attr.data.ins_permuted = op1_idx != 0;
1196 attr->pop = pops != 0;
1199 char const *const l = op1_idx >= 0 ? get_st_reg(op1_idx)->name : "[AM]";
1200 char const *const r = op2_idx >= 0 ? get_st_reg(op2_idx)->name : "[AM]";
1201 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n), l, r));
1204 return NO_NODE_ADDED;
1210 * @param state the x87 state
1211 * @param n the node that should be simulated (and patched)
1213 * @return NO_NODE_ADDED
1215 static int sim_Keep(x87_state *state, ir_node *node)
1218 const arch_register_t *op_reg;
1224 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1226 arity = get_irn_arity(node);
1227 for (i = 0; i < arity; ++i) {
1228 op = get_irn_n(node, i);
1229 op_reg = arch_get_irn_register(op);
1230 if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_fp])
1233 reg_id = op_reg->index;
1234 live = fp_live_args_after(state->sim, node, 0);
1236 op_stack_idx = x87_on_stack(state, reg_id);
1237 if (op_stack_idx >= 0 && !is_fp_live(reg_id, live))
1238 x87_create_fpop(state, sched_next(node), 0);
1241 DB((dbg, LEVEL_1, "Stack after: "));
1242 DEBUG_ONLY(x87_dump_stack(state);)
1244 return NO_NODE_ADDED;
1248 * Keep the given node alive by adding a be_Keep.
1250 * @param node the node to kept alive
1252 static void keep_float_node_alive(ir_node *node)
1254 ir_node *block = get_nodes_block(node);
1255 ir_node *keep = be_new_Keep(block, 1, &node);
1256 sched_add_after(node, keep);
1260 * Create a copy of a node. Recreate the node if it's a constant.
1262 * @param state the x87 state
1263 * @param n the node to be copied
1265 * @return the copy of n
1267 static ir_node *create_Copy(x87_state *state, ir_node *n)
1269 dbg_info *n_dbg = get_irn_dbg_info(n);
1270 ir_mode *mode = get_irn_mode(n);
1271 ir_node *block = get_nodes_block(n);
1272 ir_node *pred = get_irn_n(n, 0);
1273 ir_node *(*cnstr)(dbg_info *, ir_node *) = NULL;
1275 const arch_register_t *out;
1276 const arch_register_t *op1;
1278 /* Do not copy constants, recreate them. */
1279 switch (get_ia32_irn_opcode(pred)) {
1281 cnstr = new_bd_ia32_fldz;
1284 cnstr = new_bd_ia32_fld1;
1286 case iro_ia32_fldpi:
1287 cnstr = new_bd_ia32_fldpi;
1289 case iro_ia32_fldl2e:
1290 cnstr = new_bd_ia32_fldl2e;
1292 case iro_ia32_fldl2t:
1293 cnstr = new_bd_ia32_fldl2t;
1295 case iro_ia32_fldlg2:
1296 cnstr = new_bd_ia32_fldlg2;
1298 case iro_ia32_fldln2:
1299 cnstr = new_bd_ia32_fldln2;
1305 out = x87_get_irn_register(n);
1306 op1 = x87_get_irn_register(pred);
1308 if (cnstr != NULL) {
1309 /* copy a constant */
1310 res = (*cnstr)(n_dbg, block);
1312 x87_push(state, out->index, res);
1314 int op1_idx = x87_on_stack(state, op1->index);
1316 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1318 x87_push(state, out->index, res);
1320 ia32_x87_attr_t *const attr = get_ia32_x87_attr(res);
1321 attr->reg = get_st_reg(op1_idx);
1323 arch_set_irn_register(res, out);
1329 * Simulate a be_Copy.
1331 * @param state the x87 state
1332 * @param n the node that should be simulated (and patched)
1334 * @return NO_NODE_ADDED
1336 static int sim_Copy(x87_state *state, ir_node *n)
1338 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1339 if (cls != &ia32_reg_classes[CLASS_ia32_fp])
1340 return NO_NODE_ADDED;
1342 ir_node *const pred = be_get_Copy_op(n);
1343 arch_register_t const *const op1 = x87_get_irn_register(pred);
1344 arch_register_t const *const out = x87_get_irn_register(n);
1345 unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
1347 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, op1->name, out->name));
1348 DEBUG_ONLY(fp_dump_live(live);)
1350 if (is_fp_live(op1->index, live)) {
1351 /* Operand is still live, a real copy. We need here an fpush that can
1352 hold a a register, so use the fpushCopy or recreate constants */
1353 ir_node *const node = create_Copy(state, n);
1355 /* We have to make sure the old value doesn't go dead (which can happen
1356 * when we recreate constants). As the simulator expected that value in
1357 * the pred blocks. This is unfortunate as removing it would save us 1
1358 * instruction, but we would have to rerun all the simulation to get
1361 ir_node *const next = sched_next(n);
1364 sched_add_before(next, node);
1366 if (get_irn_n_edges(pred) == 0) {
1367 keep_float_node_alive(pred);
1370 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1372 /* Just a virtual copy. */
1373 int const op1_idx = x87_on_stack(state, op1->index);
1374 x87_set_st(state, out->index, n, op1_idx);
1376 return NO_NODE_ADDED;
1380 * Returns the vf0 result Proj of a Call.
1382 * @para call the Call node
1384 static ir_node *get_call_result_proj(ir_node *call)
1386 /* search the result proj */
1387 foreach_out_edge(call, edge) {
1388 ir_node *proj = get_edge_src_irn(edge);
1389 long pn = get_Proj_proj(proj);
1391 if (pn == pn_ia32_Call_st0)
1395 panic("result Proj missing");
1398 static int sim_Asm(x87_state *const state, ir_node *const n)
1402 for (size_t i = get_irn_arity(n); i-- != 0;) {
1403 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1404 if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
1405 panic("cannot handle %+F with x87 constraints", n);
1408 be_foreach_out(n, i) {
1409 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1410 if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
1411 panic("cannot handle %+F with x87 constraints", n);
1414 return NO_NODE_ADDED;
1418 * Simulate a ia32_Call.
1420 * @param state the x87 state
1421 * @param n the node that should be simulated (and patched)
1423 * @return NO_NODE_ADDED
1425 static int sim_Call(x87_state *state, ir_node *n)
1427 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1429 /* at the begin of a call the x87 state should be empty */
1430 assert(state->depth == 0 && "stack not empty before call");
1432 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1433 if (get_method_n_ress(call_tp) != 0) {
1434 /* If the called function returns a float, it is returned in st(0).
1435 * This even happens if the return value is NOT used.
1436 * Moreover, only one return result is supported. */
1437 ir_type *const res_type = get_method_res_type(call_tp, 0);
1438 ir_mode *const mode = get_type_mode(res_type);
1439 if (mode && mode_is_float(mode)) {
1440 ir_node *const resproj = get_call_result_proj(n);
1441 arch_register_t const *const reg = x87_get_irn_register(resproj);
1442 x87_push(state, reg->index, resproj);
1445 DB((dbg, LEVEL_1, "Stack after: "));
1446 DEBUG_ONLY(x87_dump_stack(state);)
1448 return NO_NODE_ADDED;
1452 * Simulate a be_Return.
1454 * @param state the x87 state
1455 * @param n the node that should be simulated (and patched)
1457 * @return NO_NODE_ADDED
1459 static int sim_Return(x87_state *state, ir_node *n)
1461 #ifdef DEBUG_libfirm
1462 /* only floating point return values must reside on stack */
1463 int n_float_res = 0;
1464 int const n_res = be_Return_get_n_rets(n);
1465 for (int i = 0; i < n_res; ++i) {
1466 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1467 if (mode_is_float(get_irn_mode(res)))
1470 assert(x87_get_depth(state) == n_float_res);
1473 /* pop them virtually */
1475 return NO_NODE_ADDED;
1479 * Simulate a be_Perm.
1481 * @param state the x87 state
1482 * @param irn the node that should be simulated (and patched)
1484 * @return NO_NODE_ADDED
1486 static int sim_Perm(x87_state *state, ir_node *irn)
1489 ir_node *pred = get_irn_n(irn, 0);
1492 /* handle only floating point Perms */
1493 if (! mode_is_float(get_irn_mode(pred)))
1494 return NO_NODE_ADDED;
1496 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1498 /* Perm is a pure virtual instruction on x87.
1499 All inputs must be on the FPU stack and are pairwise
1500 different from each other.
1501 So, all we need to do is to permutate the stack state. */
1502 n = get_irn_arity(irn);
1503 NEW_ARR_A(int, stack_pos, n);
1505 /* collect old stack positions */
1506 for (i = 0; i < n; ++i) {
1507 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1508 int idx = x87_on_stack(state, inreg->index);
1510 assert(idx >= 0 && "Perm argument not on x87 stack");
1514 /* now do the permutation */
1515 foreach_out_edge(irn, edge) {
1516 ir_node *proj = get_edge_src_irn(edge);
1517 const arch_register_t *out = x87_get_irn_register(proj);
1518 long num = get_Proj_proj(proj);
1520 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1521 x87_set_st(state, out->index, proj, stack_pos[(unsigned)num]);
1523 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1525 return NO_NODE_ADDED;
1529 * Kill any dead registers at block start by popping them from the stack.
1531 * @param sim the simulator handle
1532 * @param block the current block
1533 * @param state the x87 state at the begin of the block
1535 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1537 ir_node *first_insn = sched_first(block);
1538 ir_node *keep = NULL;
1539 unsigned live = fp_live_args_after(sim, block, 0);
1544 depth = x87_get_depth(state);
1545 for (i = depth - 1; i >= 0; --i) {
1546 int reg = x87_get_st_reg(state, i);
1548 if (! is_fp_live(reg, live))
1549 kill_mask |= (1 << i);
1553 DB((dbg, LEVEL_1, "Killing deads:\n"));
1554 DEBUG_ONLY(fp_dump_live(live);)
1555 DEBUG_ONLY(x87_dump_stack(state);)
1557 if (kill_mask != 0 && live == 0) {
1558 /* special case: kill all registers */
1559 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1560 if (ia32_cg_config.use_femms) {
1561 /* use FEMMS on AMD processors to clear all */
1562 keep = new_bd_ia32_femms(NULL, block);
1564 /* use EMMS to clear all */
1565 keep = new_bd_ia32_emms(NULL, block);
1567 sched_add_before(first_insn, keep);
1573 /* now kill registers */
1575 /* we can only kill from TOS, so bring them up */
1576 if (! (kill_mask & 1)) {
1577 /* search from behind, because we can to a double-pop */
1578 for (i = depth - 1; i >= 0; --i) {
1579 if (kill_mask & (1 << i)) {
1580 kill_mask &= ~(1 << i);
1587 x87_set_st(state, -1, keep, i);
1588 x87_create_fxch(state, first_insn, i);
1593 keep = x87_create_fpop(state, first_insn, 0);
1600 * Run a simulation and fix all virtual instructions for a block.
1602 * @param sim the simulator handle
1603 * @param block the current block
1605 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1608 blk_state *bl_state = x87_get_bl_state(sim, block);
1609 x87_state *state = bl_state->begin;
1610 ir_node *start_block;
1612 assert(state != NULL);
1613 /* already processed? */
1614 if (bl_state->end != NULL)
1617 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1618 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1619 DEBUG_ONLY(x87_dump_stack(state);)
1621 /* create a new state, will be changed */
1622 state = x87_clone_state(sim, state);
1623 /* at block begin, kill all dead registers */
1624 x87_kill_deads(sim, block, state);
1626 /* beware, n might change */
1627 for (n = sched_first(block); !sched_is_end(n); n = next) {
1630 ir_op *op = get_irn_op(n);
1633 * get the next node to be simulated here.
1634 * n might be completely removed from the schedule-
1636 next = sched_next(n);
1637 if (op->ops.generic != NULL) {
1638 func = (sim_func)op->ops.generic;
1641 node_inserted = (*func)(state, n);
1644 * sim_func might have added an additional node after n,
1645 * so update next node
1646 * beware: n must not be changed by sim_func
1647 * (i.e. removed from schedule) in this case
1649 if (node_inserted != NO_NODE_ADDED)
1650 next = sched_next(n);
1654 start_block = get_irg_start_block(get_irn_irg(block));
1656 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1658 /* check if the state must be shuffled */
1659 foreach_block_succ(block, edge) {
1660 ir_node *succ = get_edge_src_irn(edge);
1661 blk_state *succ_state;
1663 if (succ == start_block)
1666 succ_state = x87_get_bl_state(sim, succ);
1668 if (succ_state->begin == NULL) {
1669 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
1670 DEBUG_ONLY(x87_dump_stack(state);)
1671 succ_state->begin = state;
1673 waitq_put(sim->worklist, succ);
1675 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
1676 /* There is already a begin state for the successor, bad.
1677 Do the necessary permutations.
1678 Note that critical edges are removed, so this is always possible:
1679 If the successor has more than one possible input, then it must
1682 x87_shuffle(block, state, succ_state->begin);
1685 bl_state->end = state;
1689 * Register a simulator function.
1691 * @param op the opcode to simulate
1692 * @param func the simulator function for the opcode
1694 static void register_sim(ir_op *op, sim_func func)
1696 assert(op->ops.generic == NULL);
1697 op->ops.generic = (op_func) func;
1701 * Create a new x87 simulator.
1703 * @param sim a simulator handle, will be initialized
1704 * @param irg the current graph
1706 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
1708 obstack_init(&sim->obst);
1709 sim->blk_states = pmap_create();
1710 sim->n_idx = get_irg_last_idx(irg);
1711 sim->live = OALLOCN(&sim->obst, fp_liveness, sim->n_idx);
1713 DB((dbg, LEVEL_1, "--------------------------------\n"
1714 "x87 Simulator started for %+F\n", irg));
1716 /* set the generic function pointer of instruction we must simulate */
1717 ir_clear_opcodes_generic_func();
1719 register_sim(op_ia32_Asm, sim_Asm);
1720 register_sim(op_ia32_Call, sim_Call);
1721 register_sim(op_ia32_fld, sim_load);
1722 register_sim(op_ia32_fild, sim_load);
1723 register_sim(op_ia32_fld1, sim_load);
1724 register_sim(op_ia32_fldz, sim_load);
1725 register_sim(op_ia32_fadd, sim_binop);
1726 register_sim(op_ia32_fsub, sim_binop);
1727 register_sim(op_ia32_fmul, sim_binop);
1728 register_sim(op_ia32_fdiv, sim_binop);
1729 register_sim(op_ia32_fprem, sim_fprem);
1730 register_sim(op_ia32_fabs, sim_unop);
1731 register_sim(op_ia32_fchs, sim_unop);
1732 register_sim(op_ia32_fist, sim_store);
1733 register_sim(op_ia32_fisttp, sim_fisttp);
1734 register_sim(op_ia32_fst, sim_store);
1735 register_sim(op_ia32_FtstFnstsw, sim_FtstFnstsw);
1736 register_sim(op_ia32_FucomFnstsw, sim_Fucom);
1737 register_sim(op_ia32_Fucomi, sim_Fucom);
1738 register_sim(op_be_Copy, sim_Copy);
1739 register_sim(op_be_Return, sim_Return);
1740 register_sim(op_be_Perm, sim_Perm);
1741 register_sim(op_be_Keep, sim_Keep);
1745 * Destroy a x87 simulator.
1747 * @param sim the simulator handle
1749 static void x87_destroy_simulator(x87_simulator *sim)
1751 pmap_destroy(sim->blk_states);
1752 obstack_free(&sim->obst, NULL);
1753 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
1757 * Pre-block walker: calculate the liveness information for the block
1758 * and store it into the sim->live cache.
1760 static void update_liveness_walker(ir_node *block, void *data)
1762 x87_simulator *sim = (x87_simulator*)data;
1763 update_liveness(sim, block);
1767 * Run a simulation and fix all virtual instructions for a graph.
1768 * Replaces all virtual floating point instructions and registers
1771 void ia32_x87_simulate_graph(ir_graph *irg)
1773 /* TODO improve code quality (less executed fxch) by using execfreqs */
1775 ir_node *block, *start_block;
1776 blk_state *bl_state;
1779 /* create the simulator */
1780 x87_init_simulator(&sim, irg);
1782 start_block = get_irg_start_block(irg);
1783 bl_state = x87_get_bl_state(&sim, start_block);
1785 /* start with the empty state */
1787 bl_state->begin = ∅
1789 sim.worklist = new_waitq();
1790 waitq_put(sim.worklist, start_block);
1792 be_assure_live_sets(irg);
1793 sim.lv = be_get_irg_liveness(irg);
1795 /* Calculate the liveness for all nodes. We must precalculate this info,
1796 * because the simulator adds new nodes (possible before Phi nodes) which
1797 * would let a lazy calculation fail.
1798 * On the other hand we reduce the computation amount due to
1799 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
1801 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
1805 block = (ir_node*)waitq_get(sim.worklist);
1806 x87_simulate_block(&sim, block);
1807 } while (! waitq_empty(sim.worklist));
1810 del_waitq(sim.worklist);
1811 x87_destroy_simulator(&sim);
1814 /* Initializes the x87 simulator. */
1815 void ia32_init_x87(void)
1817 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");