2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 /** the debug handle */
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 /* Forward declaration. */
59 typedef struct x87_simulator x87_simulator;
62 * An entry on the simulated x87 stack.
64 typedef struct st_entry {
65 int reg_idx; /**< the virtual register index of this stack value */
66 ir_node *node; /**< the node that produced this value */
72 typedef struct x87_state {
73 st_entry st[N_ia32_st_REGS]; /**< the register stack */
74 int depth; /**< the current stack depth */
75 x87_simulator *sim; /**< The simulator. */
78 /** An empty state, used for blocks without fp instructions. */
79 static x87_state empty = { { {0, NULL}, }, 0, NULL };
82 * Return values of the instruction simulator functions.
85 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
86 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
87 in the schedule AFTER the current node. */
91 * The type of an instruction simulator function.
93 * @param state the x87 state
94 * @param n the node to be simulated
96 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
98 * NO_NODE_ADDED otherwise
100 typedef int (*sim_func)(x87_state *state, ir_node *n);
103 * A block state: Every block has a x87 state at the beginning and at the end.
105 typedef struct blk_state {
106 x87_state *begin; /**< state at the begin or NULL if not assigned */
107 x87_state *end; /**< state at the end or NULL if not assigned */
110 /** liveness bitset for vfp registers. */
111 typedef unsigned char vfp_liveness;
116 struct x87_simulator {
117 struct obstack obst; /**< An obstack for fast allocating. */
118 pmap *blk_states; /**< Map blocks to states. */
119 be_lv_t *lv; /**< intrablock liveness. */
120 vfp_liveness *live; /**< Liveness information. */
121 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
122 waitq *worklist; /**< Worklist of blocks that must be processed. */
126 * Returns the current stack depth.
128 * @param state the x87 state
130 * @return the x87 stack depth
132 static int x87_get_depth(const x87_state *state)
137 static st_entry *x87_get_entry(x87_state *const state, int const pos)
139 assert(0 <= pos && pos < state->depth);
140 return &state->st[N_ia32_st_REGS - state->depth + pos];
144 * Return the virtual register index at st(pos).
146 * @param state the x87 state
147 * @param pos a stack position
149 * @return the vfp register index that produced the value at st(pos)
151 static int x87_get_st_reg(const x87_state *state, int pos)
153 return x87_get_entry((x87_state*)state, pos)->reg_idx;
158 * Dump the stack for debugging.
160 * @param state the x87 state
162 static void x87_dump_stack(const x87_state *state)
164 for (int i = state->depth; i-- != 0;) {
165 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
166 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
168 DB((dbg, LEVEL_2, "<-- TOS\n"));
170 #endif /* DEBUG_libfirm */
173 * Set a virtual register to st(pos).
175 * @param state the x87 state
176 * @param reg_idx the vfp register index that should be set
177 * @param node the IR node that produces the value of the vfp register
178 * @param pos the stack position where the new value should be entered
180 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
182 st_entry *const entry = x87_get_entry(state, pos);
183 entry->reg_idx = reg_idx;
186 DB((dbg, LEVEL_2, "After SET_REG: "));
187 DEBUG_ONLY(x87_dump_stack(state);)
191 * Swap st(0) with st(pos).
193 * @param state the x87 state
194 * @param pos the stack position to change the tos with
196 static void x87_fxch(x87_state *state, int pos)
198 st_entry *const a = x87_get_entry(state, pos);
199 st_entry *const b = x87_get_entry(state, 0);
200 st_entry const t = *a;
204 DB((dbg, LEVEL_2, "After FXCH: "));
205 DEBUG_ONLY(x87_dump_stack(state);)
209 * Convert a virtual register to the stack index.
211 * @param state the x87 state
212 * @param reg_idx the register vfp index
214 * @return the stack position where the register is stacked
215 * or -1 if the virtual register was not found
217 static int x87_on_stack(const x87_state *state, int reg_idx)
219 for (int i = 0; i < state->depth; ++i) {
220 if (x87_get_st_reg(state, i) == reg_idx)
227 * Push a virtual Register onto the stack, double pushes are NOT allowed.
229 * @param state the x87 state
230 * @param reg_idx the register vfp index
231 * @param node the node that produces the value of the vfp register
233 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
235 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
236 assert(state->depth < N_ia32_st_REGS && "stack overrun");
239 st_entry *const entry = x87_get_entry(state, 0);
240 entry->reg_idx = reg_idx;
243 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
247 * Pop a virtual Register from the stack.
249 * @param state the x87 state
251 static void x87_pop(x87_state *state)
253 assert(state->depth > 0 && "stack underrun");
257 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
261 * Empty the fpu stack
263 * @param state the x87 state
265 static void x87_emms(x87_state *state)
271 * Returns the block state of a block.
273 * @param sim the x87 simulator handle
274 * @param block the current block
276 * @return the block state
278 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
280 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
283 res = OALLOC(&sim->obst, blk_state);
287 pmap_insert(sim->blk_states, block, res);
296 * @param sim the x87 simulator handle
297 * @param src the x87 state that will be cloned
299 * @return a cloned copy of the src state
301 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
303 x87_state *const res = OALLOC(&sim->obst, x87_state);
309 * Patch a virtual instruction into a x87 one and return
310 * the node representing the result value.
312 * @param n the IR node to patch
313 * @param op the x87 opcode to patch in
315 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
317 ir_mode *mode = get_irn_mode(n);
322 if (mode == mode_T) {
323 /* patch all Proj's */
324 foreach_out_edge(n, edge) {
325 ir_node *proj = get_edge_src_irn(edge);
327 mode = get_irn_mode(proj);
328 if (mode_is_float(mode)) {
330 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
334 } else if (mode_is_float(mode))
335 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
340 * Returns the first Proj of a mode_T node having a given mode.
342 * @param n the mode_T node
343 * @param m the desired mode of the Proj
344 * @return The first Proj of mode @p m found.
346 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
348 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
350 foreach_out_edge(n, edge) {
351 ir_node *proj = get_edge_src_irn(edge);
352 if (get_irn_mode(proj) == m)
356 panic("Proj not found");
360 * Wrap the arch_* function here so we can check for errors.
362 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
364 const arch_register_t *res = arch_get_irn_register(irn);
366 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
370 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
373 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
375 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
379 static inline const arch_register_t *get_st_reg(int index)
381 return &ia32_registers[REG_ST0 + index];
385 * Create a fxch node before another node.
387 * @param state the x87 state
388 * @param n the node after the fxch
389 * @param pos exchange st(pos) with st(0)
391 static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
393 x87_fxch(state, pos);
395 ir_node *const block = get_nodes_block(n);
396 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
397 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
398 attr->x87[0] = get_st_reg(pos);
399 attr->x87[2] = get_st_reg(0);
403 sched_add_before(n, fxch);
404 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
407 /* -------------- x87 perm --------------- */
410 * Calculate the necessary permutations to reach dst_state.
412 * These permutations are done with fxch instructions and placed
413 * at the end of the block.
415 * Note that critical edges are removed here, so we need only
416 * a shuffle if the current block has only one successor.
418 * @param block the current block
419 * @param state the current x87 stack state, might be modified
420 * @param dst_state destination state
424 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
426 int i, n_cycles, k, ri;
427 unsigned cycles[4], all_mask;
428 char cycle_idx[4][8];
430 assert(state->depth == dst_state->depth);
432 /* Some mathematics here:
433 * If we have a cycle of length n that includes the tos,
434 * we need n-1 exchange operations.
435 * We can always add the tos and restore it, so we need
436 * n+1 exchange operations for a cycle not containing the tos.
437 * So, the maximum of needed operations is for a cycle of 7
438 * not including the tos == 8.
439 * This is the same number of ops we would need for using stores,
440 * so exchange is cheaper (we save the loads).
441 * On the other hand, we might need an additional exchange
442 * in the next block to bring one operand on top, so the
443 * number of ops in the first case is identical.
444 * Further, no more than 4 cycles can exists (4 x 2). */
445 all_mask = (1 << (state->depth)) - 1;
447 for (n_cycles = 0; all_mask; ++n_cycles) {
448 int src_idx, dst_idx;
450 /* find the first free slot */
451 for (i = 0; i < state->depth; ++i) {
452 if (all_mask & (1 << i)) {
453 all_mask &= ~(1 << i);
455 /* check if there are differences here */
456 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
462 /* no more cycles found */
467 cycles[n_cycles] = (1 << i);
468 cycle_idx[n_cycles][k++] = i;
469 for (src_idx = i; ; src_idx = dst_idx) {
470 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
472 if ((all_mask & (1 << dst_idx)) == 0)
475 cycle_idx[n_cycles][k++] = dst_idx;
476 cycles[n_cycles] |= (1 << dst_idx);
477 all_mask &= ~(1 << dst_idx);
479 cycle_idx[n_cycles][k] = -1;
483 /* no permutation needed */
487 /* Hmm: permutation needed */
488 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
489 DEBUG_ONLY(x87_dump_stack(state);)
490 DB((dbg, LEVEL_2, " to\n"));
491 DEBUG_ONLY(x87_dump_stack(dst_state);)
495 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
496 for (ri = 0; ri < n_cycles; ++ri) {
497 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
498 for (k = 0; cycle_idx[ri][k] != -1; ++k)
499 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
500 DB((dbg, LEVEL_2, "\n"));
505 * Find the place node must be insert.
506 * We have only one successor block, so the last instruction should
509 ir_node *const before = sched_last(block);
510 assert(is_cfop(before));
512 /* now do the permutations */
513 for (ri = 0; ri < n_cycles; ++ri) {
514 if ((cycles[ri] & 1) == 0) {
515 /* this cycle does not include the tos */
516 x87_create_fxch(state, before, cycle_idx[ri][0]);
518 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
519 x87_create_fxch(state, before, cycle_idx[ri][k]);
521 if ((cycles[ri] & 1) == 0) {
522 /* this cycle does not include the tos */
523 x87_create_fxch(state, before, cycle_idx[ri][0]);
530 * Create a fpush before node n.
532 * @param state the x87 state
533 * @param n the node after the fpush
534 * @param pos push st(pos) on stack
535 * @param val the value to push
537 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
539 x87_push(state, out_reg_idx, val);
541 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
542 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
543 attr->x87[0] = get_st_reg(pos);
544 attr->x87[2] = get_st_reg(0);
547 sched_add_before(n, fpush);
549 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
553 * Create a fpop before node n.
555 * @param state the x87 state
556 * @param n the node after the fpop
557 * @param num pop 1 or 2 values
559 * @return the fpop node
561 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
563 ir_node *fpop = NULL;
564 ia32_x87_attr_t *attr;
569 if (ia32_cg_config.use_ffreep)
570 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
572 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
573 attr = get_ia32_x87_attr(fpop);
574 attr->x87[0] = get_st_reg(0);
575 attr->x87[1] = get_st_reg(0);
576 attr->x87[2] = get_st_reg(0);
579 sched_add_before(n, fpop);
580 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
585 /* --------------------------------- liveness ------------------------------------------ */
588 * The liveness transfer function.
589 * Updates a live set over a single step from a given node to its predecessor.
590 * Everything defined at the node is removed from the set, the uses of the node get inserted.
592 * @param irn The node at which liveness should be computed.
593 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
594 * the registers live after irn.
596 * @return The live bitset.
598 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
601 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
603 if (get_irn_mode(irn) == mode_T) {
604 foreach_out_edge(irn, edge) {
605 ir_node *proj = get_edge_src_irn(edge);
607 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
608 const arch_register_t *reg = x87_get_irn_register(proj);
609 live &= ~(1 << arch_register_get_index(reg));
612 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
613 const arch_register_t *reg = x87_get_irn_register(irn);
614 live &= ~(1 << arch_register_get_index(reg));
617 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
618 ir_node *op = get_irn_n(irn, i);
620 if (mode_is_float(get_irn_mode(op)) &&
621 arch_irn_consider_in_reg_alloc(cls, op)) {
622 const arch_register_t *reg = x87_get_irn_register(op);
623 live |= 1 << arch_register_get_index(reg);
630 * Put all live virtual registers at the end of a block into a bitset.
632 * @param sim the simulator handle
633 * @param bl the block
635 * @return The live bitset at the end of this block
637 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
639 vfp_liveness live = 0;
640 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
641 const be_lv_t *lv = sim->lv;
643 be_lv_foreach(lv, block, be_lv_state_end, node) {
644 const arch_register_t *reg;
645 if (!arch_irn_consider_in_reg_alloc(cls, node))
648 reg = x87_get_irn_register(node);
649 live |= 1 << arch_register_get_index(reg);
655 /** get the register mask from an arch_register */
656 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
659 * Return a bitset of argument registers which are live at the end of a node.
661 * @param sim the simulator handle
662 * @param pos the node
663 * @param kill kill mask for the output registers
665 * @return The live bitset.
667 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
669 unsigned idx = get_irn_idx(pos);
671 assert(idx < sim->n_idx);
672 return sim->live[idx] & ~kill;
676 * Calculate the liveness for a whole block and cache it.
678 * @param sim the simulator handle
679 * @param block the block
681 static void update_liveness(x87_simulator *sim, ir_node *block)
683 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
686 /* now iterate through the block backward and cache the results */
687 sched_foreach_reverse(block, irn) {
688 /* stop at the first Phi: this produces the live-in */
692 idx = get_irn_idx(irn);
693 sim->live[idx] = live;
695 live = vfp_liveness_transfer(irn, live);
697 idx = get_irn_idx(block);
698 sim->live[idx] = live;
702 * Returns true if a register is live in a set.
704 * @param reg_idx the vfp register index
705 * @param live a live bitset
707 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
711 * Dump liveness info.
713 * @param live the live bitset
715 static void vfp_dump_live(vfp_liveness live)
719 DB((dbg, LEVEL_2, "Live after: "));
720 for (i = 0; i < 8; ++i) {
721 if (live & (1 << i)) {
722 DB((dbg, LEVEL_2, "vf%d ", i));
725 DB((dbg, LEVEL_2, "\n"));
727 #endif /* DEBUG_libfirm */
729 /* --------------------------------- simulators ---------------------------------------- */
732 * Simulate a virtual binop.
734 * @param state the x87 state
735 * @param n the node that should be simulated (and patched)
737 * @return NO_NODE_ADDED
739 static int sim_binop(x87_state *const state, ir_node *const n, ir_op *const op)
741 int op2_idx = 0, op1_idx;
742 int out_idx, do_pop = 0;
743 ia32_x87_attr_t *attr;
745 ir_node *patched_insn;
746 x87_simulator *sim = state->sim;
747 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
748 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
749 const arch_register_t *op1_reg = x87_get_irn_register(op1);
750 const arch_register_t *op2_reg = x87_get_irn_register(op2);
751 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
752 int reg_index_1 = arch_register_get_index(op1_reg);
753 int reg_index_2 = arch_register_get_index(op2_reg);
754 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
758 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
759 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
760 arch_register_get_name(out)));
761 DEBUG_ONLY(vfp_dump_live(live);)
762 DB((dbg, LEVEL_1, "Stack before: "));
763 DEBUG_ONLY(x87_dump_stack(state);)
765 op1_idx = x87_on_stack(state, reg_index_1);
766 assert(op1_idx >= 0);
767 op1_live_after = is_vfp_live(reg_index_1, live);
769 attr = get_ia32_x87_attr(n);
770 permuted = attr->attr.data.ins_permuted;
772 int const out_reg_idx = arch_register_get_index(out);
773 if (reg_index_2 != REG_VFP_VFP_NOREG) {
776 /* second operand is a vfp register */
777 op2_idx = x87_on_stack(state, reg_index_2);
778 assert(op2_idx >= 0);
779 op2_live_after = is_vfp_live(reg_index_2, live);
781 if (op2_live_after) {
782 /* Second operand is live. */
784 if (op1_live_after) {
785 /* Both operands are live: push the first one.
786 This works even for op1 == op2. */
787 x87_create_fpush(state, n, op1_idx, out_reg_idx, op2);
788 /* now do fxxx (tos=tos X op) */
793 /* Second live, first operand is dead here, bring it to tos. */
795 x87_create_fxch(state, n, op1_idx);
800 /* now do fxxx (tos=tos X op) */
804 /* Second operand is dead. */
805 if (op1_live_after) {
806 /* First operand is live: bring second to tos. */
808 x87_create_fxch(state, n, op2_idx);
813 /* now do fxxxr (tos = op X tos) */
816 /* Both operands are dead here, pop them from the stack. */
819 /* Both are identically and on tos, no pop needed. */
820 /* here fxxx (tos = tos X tos) */
823 /* now do fxxxp (op = op X tos, pop) */
827 } else if (op1_idx == 0) {
828 assert(op1_idx != op2_idx);
829 /* now do fxxxrp (op = tos X op, pop) */
833 /* Bring the second on top. */
834 x87_create_fxch(state, n, op2_idx);
835 if (op1_idx == op2_idx) {
836 /* Both are identically and on tos now, no pop needed. */
839 /* use fxxx (tos = tos X tos) */
842 /* op2 is on tos now */
844 /* use fxxxp (op = op X tos, pop) */
852 /* second operand is an address mode */
853 if (op1_live_after) {
854 /* first operand is live: push it here */
855 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
858 /* first operand is dead: bring it to tos */
860 x87_create_fxch(state, n, op1_idx);
865 /* use fxxx (tos = tos X mem) */
869 patched_insn = x87_patch_insn(n, op);
870 x87_set_st(state, out_reg_idx, patched_insn, out_idx);
875 /* patch the operation */
877 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
878 if (reg_index_2 != REG_VFP_VFP_NOREG) {
879 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
881 attr->x87[2] = out = get_st_reg(out_idx);
883 if (reg_index_2 != REG_VFP_VFP_NOREG) {
884 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
885 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
886 arch_register_get_name(out)));
888 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
889 arch_register_get_name(op1_reg),
890 arch_register_get_name(out)));
893 return NO_NODE_ADDED;
897 * Simulate a virtual Unop.
899 * @param state the x87 state
900 * @param n the node that should be simulated (and patched)
901 * @param op the x87 opcode that will replace n's opcode
903 * @return NO_NODE_ADDED
905 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
907 arch_register_t const *const out = x87_get_irn_register(n);
908 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
909 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
910 DEBUG_ONLY(vfp_dump_live(live);)
912 ir_node *const op1 = get_irn_n(n, 0);
913 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
914 int const op1_reg_idx = arch_register_get_index(op1_reg);
915 int const op1_idx = x87_on_stack(state, op1_reg_idx);
916 int const out_reg_idx = arch_register_get_index(out);
917 if (is_vfp_live(op1_reg_idx, live)) {
918 /* push the operand here */
919 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
921 /* operand is dead, bring it to tos */
923 x87_create_fxch(state, n, op1_idx);
927 x87_set_st(state, out_reg_idx, x87_patch_insn(n, op), 0);
928 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
929 attr->x87[2] = attr->x87[0] = get_st_reg(0);
930 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), attr->x87[2]->name));
932 return NO_NODE_ADDED;
936 * Simulate a virtual Load instruction.
938 * @param state the x87 state
939 * @param n the node that should be simulated (and patched)
940 * @param op the x87 opcode that will replace n's opcode
942 * @return NO_NODE_ADDED
944 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
946 const arch_register_t *out = x87_irn_get_register(n, res_pos);
947 ia32_x87_attr_t *attr;
949 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
950 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
951 assert(out == x87_irn_get_register(n, res_pos));
952 attr = get_ia32_x87_attr(n);
953 attr->x87[2] = out = get_st_reg(0);
954 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
956 return NO_NODE_ADDED;
960 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
962 * @param store The store
963 * @param old_val The former value
964 * @param new_val The new value
966 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
968 foreach_out_edge_safe(old_val, edge) {
969 ir_node *user = get_edge_src_irn(edge);
970 /* if the user is scheduled after the store: rewire */
971 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
972 set_irn_n(user, get_edge_src_pos(edge), new_val);
978 * Simulate a virtual Store.
980 * @param state the x87 state
981 * @param n the node that should be simulated (and patched)
982 * @param op the x87 store opcode
984 static int sim_store(x87_state *state, ir_node *n, ir_op *op)
986 ir_node *const val = get_irn_n(n, n_ia32_vfst_val);
987 arch_register_t const *const op2 = x87_get_irn_register(val);
988 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
991 int insn = NO_NODE_ADDED;
992 int const op2_reg_idx = arch_register_get_index(op2);
993 int const op2_idx = x87_on_stack(state, op2_reg_idx);
994 unsigned const live = vfp_live_args_after(state->sim, n, 0);
995 int const live_after_node = is_vfp_live(op2_reg_idx, live);
996 assert(op2_idx >= 0);
997 if (live_after_node) {
998 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
999 * fist doesn't support 64bit mode, only fistp
1001 * - stack not full: push value and fstp
1002 * - stack full: fstp value and load again
1003 * Note that we cannot test on mode_E, because floats might be 80bit ... */
1004 ir_mode *const mode = get_ia32_ls_mode(n);
1005 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
1006 if (x87_get_depth(state) < N_ia32_st_REGS) {
1007 /* ok, we have a free register: push + fstp */
1008 x87_create_fpush(state, n, op2_idx, REG_VFP_VFP_NOREG, val);
1009 x87_patch_insn(n, op);
1012 /* stack full here: need fstp + load */
1013 x87_patch_insn(n, op);
1016 ir_node *const block = get_nodes_block(n);
1017 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
1018 ir_node *const vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
1020 /* copy all attributes */
1021 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1022 if (is_ia32_use_frame(n))
1023 set_ia32_use_frame(vfld);
1024 set_ia32_op_type(vfld, ia32_AddrModeS);
1025 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1026 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1027 set_ia32_ls_mode(vfld, mode);
1029 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_vfld_res);
1030 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1032 arch_set_irn_register(rproj, op2);
1034 /* reroute all former users of the store memory to the load memory */
1035 edges_reroute_except(mem, mproj, vfld);
1037 sched_add_after(n, vfld);
1039 /* rewire all users, scheduled after the store, to the loaded value */
1040 collect_and_rewire_users(n, val, rproj);
1045 /* we can only store the tos to memory */
1047 x87_create_fxch(state, n, op2_idx);
1049 /* mode size 64 or smaller -> use normal fst */
1050 x87_patch_insn(n, op);
1053 /* we can only store the tos to memory */
1055 x87_create_fxch(state, n, op2_idx);
1057 x87_patch_insn(n, op);
1064 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
1066 attr->x87[1] = get_st_reg(0);
1067 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(attr->x87[1])));
1072 #define GEN_BINOP(op) \
1073 static int sim_##op(x87_state *state, ir_node *n) { \
1074 return sim_binop(state, n, op_ia32_##op); \
1077 #define GEN_LOAD(op) \
1078 static int sim_##op(x87_state *state, ir_node *n) { \
1079 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1082 #define GEN_UNOP(op) \
1083 static int sim_##op(x87_state *state, ir_node *n) { \
1084 return sim_unop(state, n, op_ia32_##op); \
1087 #define GEN_STORE(op) \
1088 static int sim_##op(x87_state *state, ir_node *n) { \
1089 return sim_store(state, n, op_ia32_##op); \
1109 static int sim_fprem(x87_state *const state, ir_node *const n)
1113 panic("TODO implement");
1114 return NO_NODE_ADDED;
1118 * Simulate a virtual fisttp.
1120 * @param state the x87 state
1121 * @param n the node that should be simulated (and patched)
1123 * @return NO_NODE_ADDED
1125 static int sim_fisttp(x87_state *state, ir_node *n)
1127 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1128 const arch_register_t *op2 = x87_get_irn_register(val);
1129 ia32_x87_attr_t *attr;
1130 int op2_reg_idx, op2_idx;
1132 op2_reg_idx = arch_register_get_index(op2);
1133 op2_idx = x87_on_stack(state, op2_reg_idx);
1134 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1135 assert(op2_idx >= 0);
1137 /* Note: although the value is still live here, it is destroyed because
1138 of the pop. The register allocator is aware of that and introduced a copy
1139 if the value must be alive. */
1141 /* we can only store the tos to memory */
1143 x87_create_fxch(state, n, op2_idx);
1146 x87_patch_insn(n, op_ia32_fisttp);
1148 attr = get_ia32_x87_attr(n);
1149 attr->x87[1] = op2 = get_st_reg(0);
1150 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1152 return NO_NODE_ADDED;
1156 * Simulate a virtual FtstFnstsw.
1158 * @param state the x87 state
1159 * @param n the node that should be simulated (and patched)
1161 * @return NO_NODE_ADDED
1163 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1165 x87_simulator *sim = state->sim;
1166 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1167 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1168 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1169 int reg_index_1 = arch_register_get_index(reg1);
1170 int op1_idx = x87_on_stack(state, reg_index_1);
1171 unsigned live = vfp_live_args_after(sim, n, 0);
1173 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1174 DEBUG_ONLY(vfp_dump_live(live);)
1175 DB((dbg, LEVEL_1, "Stack before: "));
1176 DEBUG_ONLY(x87_dump_stack(state);)
1177 assert(op1_idx >= 0);
1180 /* bring the value to tos */
1181 x87_create_fxch(state, n, op1_idx);
1185 /* patch the operation */
1186 x87_patch_insn(n, op_ia32_FtstFnstsw);
1187 reg1 = get_st_reg(op1_idx);
1188 attr->x87[0] = reg1;
1189 attr->x87[1] = NULL;
1190 attr->x87[2] = NULL;
1192 if (!is_vfp_live(reg_index_1, live))
1193 x87_create_fpop(state, sched_next(n), 1);
1195 return NO_NODE_ADDED;
1201 * @param state the x87 state
1202 * @param n the node that should be simulated (and patched)
1204 * @return NO_NODE_ADDED
1206 static int sim_Fucom(x87_state *state, ir_node *n)
1210 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1212 x87_simulator *sim = state->sim;
1213 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1214 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1215 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1216 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1217 int reg_index_1 = arch_register_get_index(op1);
1218 int reg_index_2 = arch_register_get_index(op2);
1219 unsigned live = vfp_live_args_after(sim, n, 0);
1220 bool permuted = attr->attr.data.ins_permuted;
1224 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1225 arch_register_get_name(op1), arch_register_get_name(op2)));
1226 DEBUG_ONLY(vfp_dump_live(live);)
1227 DB((dbg, LEVEL_1, "Stack before: "));
1228 DEBUG_ONLY(x87_dump_stack(state);)
1230 op1_idx = x87_on_stack(state, reg_index_1);
1231 assert(op1_idx >= 0);
1233 /* BEWARE: check for comp a,a cases, they might happen */
1234 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1235 /* second operand is a vfp register */
1236 op2_idx = x87_on_stack(state, reg_index_2);
1237 assert(op2_idx >= 0);
1239 if (is_vfp_live(reg_index_2, live)) {
1240 /* second operand is live */
1242 if (is_vfp_live(reg_index_1, live)) {
1243 /* both operands are live */
1246 /* res = tos X op */
1247 } else if (op2_idx == 0) {
1248 /* res = op X tos */
1249 permuted = !permuted;
1252 /* bring the first one to tos */
1253 x87_create_fxch(state, n, op1_idx);
1254 if (op1_idx == op2_idx) {
1256 } else if (op2_idx == 0) {
1260 /* res = tos X op */
1263 /* second live, first operand is dead here, bring it to tos.
1264 This means further, op1_idx != op2_idx. */
1265 assert(op1_idx != op2_idx);
1267 x87_create_fxch(state, n, op1_idx);
1272 /* res = tos X op, pop */
1276 /* second operand is dead */
1277 if (is_vfp_live(reg_index_1, live)) {
1278 /* first operand is live: bring second to tos.
1279 This means further, op1_idx != op2_idx. */
1280 assert(op1_idx != op2_idx);
1282 x87_create_fxch(state, n, op2_idx);
1287 /* res = op X tos, pop */
1289 permuted = !permuted;
1292 /* both operands are dead here, check first for identity. */
1293 if (op1_idx == op2_idx) {
1294 /* identically, one pop needed */
1296 x87_create_fxch(state, n, op1_idx);
1300 /* res = tos X op, pop */
1303 /* different, move them to st and st(1) and pop both.
1304 The tricky part is to get one into st(1).*/
1305 else if (op2_idx == 1) {
1306 /* good, second operand is already in the right place, move the first */
1308 /* bring the first on top */
1309 x87_create_fxch(state, n, op1_idx);
1310 assert(op2_idx != 0);
1313 /* res = tos X op, pop, pop */
1315 } else if (op1_idx == 1) {
1316 /* good, first operand is already in the right place, move the second */
1318 /* bring the first on top */
1319 x87_create_fxch(state, n, op2_idx);
1320 assert(op1_idx != 0);
1323 /* res = op X tos, pop, pop */
1324 permuted = !permuted;
1328 /* if one is already the TOS, we need two fxch */
1330 /* first one is TOS, move to st(1) */
1331 x87_create_fxch(state, n, 1);
1332 assert(op2_idx != 1);
1334 x87_create_fxch(state, n, op2_idx);
1336 /* res = op X tos, pop, pop */
1338 permuted = !permuted;
1340 } else if (op2_idx == 0) {
1341 /* second one is TOS, move to st(1) */
1342 x87_create_fxch(state, n, 1);
1343 assert(op1_idx != 1);
1345 x87_create_fxch(state, n, op1_idx);
1347 /* res = tos X op, pop, pop */
1350 /* none of them is either TOS or st(1), 3 fxch needed */
1351 x87_create_fxch(state, n, op2_idx);
1352 assert(op1_idx != 0);
1353 x87_create_fxch(state, n, 1);
1355 x87_create_fxch(state, n, op1_idx);
1357 /* res = tos X op, pop, pop */
1364 /* second operand is an address mode */
1365 if (is_vfp_live(reg_index_1, live)) {
1366 /* first operand is live: bring it to TOS */
1368 x87_create_fxch(state, n, op1_idx);
1372 /* first operand is dead: bring it to tos */
1374 x87_create_fxch(state, n, op1_idx);
1381 /* patch the operation */
1382 if (is_ia32_vFucomFnstsw(n)) {
1386 case 1: attr->pop = true; /* FALLTHROUGH */
1387 case 0: dst = op_ia32_FucomFnstsw; break;
1388 case 2: dst = op_ia32_FucomppFnstsw; break;
1389 default: panic("invalid popcount");
1392 for (i = 0; i < pops; ++i) {
1395 } else if (is_ia32_vFucomi(n)) {
1396 dst = op_ia32_Fucomi;
1399 case 1: attr->pop = true; x87_pop(state); break;
1403 x87_create_fpop(state, sched_next(n), 1);
1405 default: panic("invalid popcount");
1408 panic("invalid operation %+F", n);
1411 x87_patch_insn(n, dst);
1418 op1 = get_st_reg(op1_idx);
1421 op2 = get_st_reg(op2_idx);
1424 attr->x87[2] = NULL;
1425 attr->attr.data.ins_permuted = permuted;
1428 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1429 arch_register_get_name(op1), arch_register_get_name(op2)));
1431 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1432 arch_register_get_name(op1)));
1435 return NO_NODE_ADDED;
1441 * @param state the x87 state
1442 * @param n the node that should be simulated (and patched)
1444 * @return NO_NODE_ADDED
1446 static int sim_Keep(x87_state *state, ir_node *node)
1449 const arch_register_t *op_reg;
1455 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1457 arity = get_irn_arity(node);
1458 for (i = 0; i < arity; ++i) {
1459 op = get_irn_n(node, i);
1460 op_reg = arch_get_irn_register(op);
1461 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1464 reg_id = arch_register_get_index(op_reg);
1465 live = vfp_live_args_after(state->sim, node, 0);
1467 op_stack_idx = x87_on_stack(state, reg_id);
1468 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1469 x87_create_fpop(state, sched_next(node), 1);
1472 DB((dbg, LEVEL_1, "Stack after: "));
1473 DEBUG_ONLY(x87_dump_stack(state);)
1475 return NO_NODE_ADDED;
1479 * Keep the given node alive by adding a be_Keep.
1481 * @param node the node to kept alive
1483 static void keep_float_node_alive(ir_node *node)
1485 ir_node *block = get_nodes_block(node);
1486 ir_node *keep = be_new_Keep(block, 1, &node);
1487 sched_add_after(node, keep);
1491 * Create a copy of a node. Recreate the node if it's a constant.
1493 * @param state the x87 state
1494 * @param n the node to be copied
1496 * @return the copy of n
1498 static ir_node *create_Copy(x87_state *state, ir_node *n)
1500 dbg_info *n_dbg = get_irn_dbg_info(n);
1501 ir_mode *mode = get_irn_mode(n);
1502 ir_node *block = get_nodes_block(n);
1503 ir_node *pred = get_irn_n(n, 0);
1504 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1506 const arch_register_t *out;
1507 const arch_register_t *op1;
1508 ia32_x87_attr_t *attr;
1510 /* Do not copy constants, recreate them. */
1511 switch (get_ia32_irn_opcode(pred)) {
1513 cnstr = new_bd_ia32_fldz;
1516 cnstr = new_bd_ia32_fld1;
1518 case iro_ia32_fldpi:
1519 cnstr = new_bd_ia32_fldpi;
1521 case iro_ia32_fldl2e:
1522 cnstr = new_bd_ia32_fldl2e;
1524 case iro_ia32_fldl2t:
1525 cnstr = new_bd_ia32_fldl2t;
1527 case iro_ia32_fldlg2:
1528 cnstr = new_bd_ia32_fldlg2;
1530 case iro_ia32_fldln2:
1531 cnstr = new_bd_ia32_fldln2;
1537 out = x87_get_irn_register(n);
1538 op1 = x87_get_irn_register(pred);
1540 if (cnstr != NULL) {
1541 /* copy a constant */
1542 res = (*cnstr)(n_dbg, block, mode);
1544 x87_push(state, arch_register_get_index(out), res);
1546 attr = get_ia32_x87_attr(res);
1547 attr->x87[2] = get_st_reg(0);
1549 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1551 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1553 x87_push(state, arch_register_get_index(out), res);
1555 attr = get_ia32_x87_attr(res);
1556 attr->x87[0] = get_st_reg(op1_idx);
1557 attr->x87[2] = get_st_reg(0);
1559 arch_set_irn_register(res, out);
1565 * Simulate a be_Copy.
1567 * @param state the x87 state
1568 * @param n the node that should be simulated (and patched)
1570 * @return NO_NODE_ADDED
1572 static int sim_Copy(x87_state *state, ir_node *n)
1574 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1575 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1576 return NO_NODE_ADDED;
1578 ir_node *const pred = be_get_Copy_op(n);
1579 arch_register_t const *const op1 = x87_get_irn_register(pred);
1580 arch_register_t const *const out = x87_get_irn_register(n);
1581 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
1583 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1584 arch_register_get_name(op1), arch_register_get_name(out)));
1585 DEBUG_ONLY(vfp_dump_live(live);)
1587 if (is_vfp_live(arch_register_get_index(op1), live)) {
1588 /* Operand is still live, a real copy. We need here an fpush that can
1589 hold a a register, so use the fpushCopy or recreate constants */
1590 ir_node *const node = create_Copy(state, n);
1592 /* We have to make sure the old value doesn't go dead (which can happen
1593 * when we recreate constants). As the simulator expected that value in
1594 * the pred blocks. This is unfortunate as removing it would save us 1
1595 * instruction, but we would have to rerun all the simulation to get
1598 ir_node *const next = sched_next(n);
1601 sched_add_before(next, node);
1603 if (get_irn_n_edges(pred) == 0) {
1604 keep_float_node_alive(pred);
1607 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1609 /* Just a virtual copy. */
1610 int const op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1611 x87_set_st(state, arch_register_get_index(out), n, op1_idx);
1613 return NO_NODE_ADDED;
1617 * Returns the vf0 result Proj of a Call.
1619 * @para call the Call node
1621 static ir_node *get_call_result_proj(ir_node *call)
1623 /* search the result proj */
1624 foreach_out_edge(call, edge) {
1625 ir_node *proj = get_edge_src_irn(edge);
1626 long pn = get_Proj_proj(proj);
1628 if (pn == pn_ia32_Call_vf0)
1632 panic("result Proj missing");
1635 static int sim_Asm(x87_state *const state, ir_node *const n)
1639 for (size_t i = get_irn_arity(n); i-- != 0;) {
1640 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1641 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1642 panic("cannot handle %+F with x87 constraints", n);
1645 for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
1646 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1647 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1648 panic("cannot handle %+F with x87 constraints", n);
1651 return NO_NODE_ADDED;
1655 * Simulate a ia32_Call.
1657 * @param state the x87 state
1658 * @param n the node that should be simulated (and patched)
1660 * @return NO_NODE_ADDED
1662 static int sim_Call(x87_state *state, ir_node *n)
1664 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1666 /* at the begin of a call the x87 state should be empty */
1667 assert(state->depth == 0 && "stack not empty before call");
1669 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1670 if (get_method_n_ress(call_tp) != 0) {
1671 /* If the called function returns a float, it is returned in st(0).
1672 * This even happens if the return value is NOT used.
1673 * Moreover, only one return result is supported. */
1674 ir_type *const res_type = get_method_res_type(call_tp, 0);
1675 ir_mode *const mode = get_type_mode(res_type);
1676 if (mode && mode_is_float(mode)) {
1677 ir_node *const resproj = get_call_result_proj(n);
1678 arch_register_t const *const reg = x87_get_irn_register(resproj);
1679 x87_push(state, arch_register_get_index(reg), resproj);
1682 DB((dbg, LEVEL_1, "Stack after: "));
1683 DEBUG_ONLY(x87_dump_stack(state);)
1685 return NO_NODE_ADDED;
1689 * Simulate a be_Return.
1691 * @param state the x87 state
1692 * @param n the node that should be simulated (and patched)
1694 * @return NO_NODE_ADDED
1696 static int sim_Return(x87_state *state, ir_node *n)
1698 #ifdef DEBUG_libfirm
1699 /* only floating point return values must reside on stack */
1700 int n_float_res = 0;
1701 int const n_res = be_Return_get_n_rets(n);
1702 for (int i = 0; i < n_res; ++i) {
1703 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1704 if (mode_is_float(get_irn_mode(res)))
1707 assert(x87_get_depth(state) == n_float_res);
1710 /* pop them virtually */
1712 return NO_NODE_ADDED;
1716 * Simulate a be_Perm.
1718 * @param state the x87 state
1719 * @param irn the node that should be simulated (and patched)
1721 * @return NO_NODE_ADDED
1723 static int sim_Perm(x87_state *state, ir_node *irn)
1726 ir_node *pred = get_irn_n(irn, 0);
1729 /* handle only floating point Perms */
1730 if (! mode_is_float(get_irn_mode(pred)))
1731 return NO_NODE_ADDED;
1733 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1735 /* Perm is a pure virtual instruction on x87.
1736 All inputs must be on the FPU stack and are pairwise
1737 different from each other.
1738 So, all we need to do is to permutate the stack state. */
1739 n = get_irn_arity(irn);
1740 NEW_ARR_A(int, stack_pos, n);
1742 /* collect old stack positions */
1743 for (i = 0; i < n; ++i) {
1744 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1745 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1747 assert(idx >= 0 && "Perm argument not on x87 stack");
1751 /* now do the permutation */
1752 foreach_out_edge(irn, edge) {
1753 ir_node *proj = get_edge_src_irn(edge);
1754 const arch_register_t *out = x87_get_irn_register(proj);
1755 long num = get_Proj_proj(proj);
1757 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1758 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1760 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1762 return NO_NODE_ADDED;
1766 * Kill any dead registers at block start by popping them from the stack.
1768 * @param sim the simulator handle
1769 * @param block the current block
1770 * @param state the x87 state at the begin of the block
1772 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1774 ir_node *first_insn = sched_first(block);
1775 ir_node *keep = NULL;
1776 unsigned live = vfp_live_args_after(sim, block, 0);
1778 int i, depth, num_pop;
1781 depth = x87_get_depth(state);
1782 for (i = depth - 1; i >= 0; --i) {
1783 int reg = x87_get_st_reg(state, i);
1785 if (! is_vfp_live(reg, live))
1786 kill_mask |= (1 << i);
1790 DB((dbg, LEVEL_1, "Killing deads:\n"));
1791 DEBUG_ONLY(vfp_dump_live(live);)
1792 DEBUG_ONLY(x87_dump_stack(state);)
1794 if (kill_mask != 0 && live == 0) {
1795 /* special case: kill all registers */
1796 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1797 if (ia32_cg_config.use_femms) {
1798 /* use FEMMS on AMD processors to clear all */
1799 keep = new_bd_ia32_femms(NULL, block);
1801 /* use EMMS to clear all */
1802 keep = new_bd_ia32_emms(NULL, block);
1804 sched_add_before(first_insn, keep);
1810 /* now kill registers */
1812 /* we can only kill from TOS, so bring them up */
1813 if (! (kill_mask & 1)) {
1814 /* search from behind, because we can to a double-pop */
1815 for (i = depth - 1; i >= 0; --i) {
1816 if (kill_mask & (1 << i)) {
1817 kill_mask &= ~(1 << i);
1824 x87_set_st(state, -1, keep, i);
1825 x87_create_fxch(state, first_insn, i);
1828 if ((kill_mask & 3) == 3) {
1829 /* we can do a double-pop */
1833 /* only a single pop */
1838 kill_mask >>= num_pop;
1839 keep = x87_create_fpop(state, first_insn, num_pop);
1846 * Run a simulation and fix all virtual instructions for a block.
1848 * @param sim the simulator handle
1849 * @param block the current block
1851 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1854 blk_state *bl_state = x87_get_bl_state(sim, block);
1855 x87_state *state = bl_state->begin;
1856 ir_node *start_block;
1858 assert(state != NULL);
1859 /* already processed? */
1860 if (bl_state->end != NULL)
1863 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1864 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1865 DEBUG_ONLY(x87_dump_stack(state);)
1867 /* create a new state, will be changed */
1868 state = x87_clone_state(sim, state);
1869 /* at block begin, kill all dead registers */
1870 x87_kill_deads(sim, block, state);
1872 /* beware, n might change */
1873 for (n = sched_first(block); !sched_is_end(n); n = next) {
1876 ir_op *op = get_irn_op(n);
1879 * get the next node to be simulated here.
1880 * n might be completely removed from the schedule-
1882 next = sched_next(n);
1883 if (op->ops.generic != NULL) {
1884 func = (sim_func)op->ops.generic;
1887 node_inserted = (*func)(state, n);
1890 * sim_func might have added an additional node after n,
1891 * so update next node
1892 * beware: n must not be changed by sim_func
1893 * (i.e. removed from schedule) in this case
1895 if (node_inserted != NO_NODE_ADDED)
1896 next = sched_next(n);
1900 start_block = get_irg_start_block(get_irn_irg(block));
1902 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1904 /* check if the state must be shuffled */
1905 foreach_block_succ(block, edge) {
1906 ir_node *succ = get_edge_src_irn(edge);
1907 blk_state *succ_state;
1909 if (succ == start_block)
1912 succ_state = x87_get_bl_state(sim, succ);
1914 if (succ_state->begin == NULL) {
1915 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
1916 DEBUG_ONLY(x87_dump_stack(state);)
1917 succ_state->begin = state;
1919 waitq_put(sim->worklist, succ);
1921 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
1922 /* There is already a begin state for the successor, bad.
1923 Do the necessary permutations.
1924 Note that critical edges are removed, so this is always possible:
1925 If the successor has more than one possible input, then it must
1928 x87_shuffle(block, state, succ_state->begin);
1931 bl_state->end = state;
1935 * Register a simulator function.
1937 * @param op the opcode to simulate
1938 * @param func the simulator function for the opcode
1940 static void register_sim(ir_op *op, sim_func func)
1942 assert(op->ops.generic == NULL);
1943 op->ops.generic = (op_func) func;
1947 * Create a new x87 simulator.
1949 * @param sim a simulator handle, will be initialized
1950 * @param irg the current graph
1952 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
1954 obstack_init(&sim->obst);
1955 sim->blk_states = pmap_create();
1956 sim->n_idx = get_irg_last_idx(irg);
1957 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
1959 DB((dbg, LEVEL_1, "--------------------------------\n"
1960 "x87 Simulator started for %+F\n", irg));
1962 /* set the generic function pointer of instruction we must simulate */
1963 ir_clear_opcodes_generic_func();
1965 register_sim(op_ia32_Asm, sim_Asm);
1966 register_sim(op_ia32_Call, sim_Call);
1967 register_sim(op_ia32_vfld, sim_fld);
1968 register_sim(op_ia32_vfild, sim_fild);
1969 register_sim(op_ia32_vfld1, sim_fld1);
1970 register_sim(op_ia32_vfldz, sim_fldz);
1971 register_sim(op_ia32_vfadd, sim_fadd);
1972 register_sim(op_ia32_vfsub, sim_fsub);
1973 register_sim(op_ia32_vfmul, sim_fmul);
1974 register_sim(op_ia32_vfdiv, sim_fdiv);
1975 register_sim(op_ia32_vfprem, sim_fprem);
1976 register_sim(op_ia32_vfabs, sim_fabs);
1977 register_sim(op_ia32_vfchs, sim_fchs);
1978 register_sim(op_ia32_vfist, sim_fist);
1979 register_sim(op_ia32_vfisttp, sim_fisttp);
1980 register_sim(op_ia32_vfst, sim_fst);
1981 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
1982 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
1983 register_sim(op_ia32_vFucomi, sim_Fucom);
1984 register_sim(op_be_Copy, sim_Copy);
1985 register_sim(op_be_Return, sim_Return);
1986 register_sim(op_be_Perm, sim_Perm);
1987 register_sim(op_be_Keep, sim_Keep);
1991 * Destroy a x87 simulator.
1993 * @param sim the simulator handle
1995 static void x87_destroy_simulator(x87_simulator *sim)
1997 pmap_destroy(sim->blk_states);
1998 obstack_free(&sim->obst, NULL);
1999 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2003 * Pre-block walker: calculate the liveness information for the block
2004 * and store it into the sim->live cache.
2006 static void update_liveness_walker(ir_node *block, void *data)
2008 x87_simulator *sim = (x87_simulator*)data;
2009 update_liveness(sim, block);
2013 * Run a simulation and fix all virtual instructions for a graph.
2014 * Replaces all virtual floating point instructions and registers
2017 void ia32_x87_simulate_graph(ir_graph *irg)
2019 /* TODO improve code quality (less executed fxch) by using execfreqs */
2021 ir_node *block, *start_block;
2022 blk_state *bl_state;
2025 /* create the simulator */
2026 x87_init_simulator(&sim, irg);
2028 start_block = get_irg_start_block(irg);
2029 bl_state = x87_get_bl_state(&sim, start_block);
2031 /* start with the empty state */
2033 bl_state->begin = ∅
2035 sim.worklist = new_waitq();
2036 waitq_put(sim.worklist, start_block);
2038 be_assure_live_sets(irg);
2039 sim.lv = be_get_irg_liveness(irg);
2041 /* Calculate the liveness for all nodes. We must precalculate this info,
2042 * because the simulator adds new nodes (possible before Phi nodes) which
2043 * would let a lazy calculation fail.
2044 * On the other hand we reduce the computation amount due to
2045 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2047 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2051 block = (ir_node*)waitq_get(sim.worklist);
2052 x87_simulate_block(&sim, block);
2053 } while (! waitq_empty(sim.worklist));
2056 del_waitq(sim.worklist);
2057 x87_destroy_simulator(&sim);
2060 /* Initializes the x87 simulator. */
2061 void ia32_init_x87(void)
2063 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");