2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 /** the debug handle */
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 /* Forward declaration. */
59 typedef struct x87_simulator x87_simulator;
62 * An exchange template.
63 * Note that our virtual functions have the same inputs
64 * and attributes as the real ones, so we can simple exchange
66 * Further, x87 supports inverse instructions, so we can handle them.
68 typedef struct exchange_tmpl {
69 ir_op *normal_op; /**< the normal one */
70 ir_op *reverse_op; /**< the reverse one if exists */
71 ir_op *normal_pop_op; /**< the normal one with tos pop */
72 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
76 * An entry on the simulated x87 stack.
78 typedef struct st_entry {
79 int reg_idx; /**< the virtual register index of this stack value */
80 ir_node *node; /**< the node that produced this value */
86 typedef struct x87_state {
87 st_entry st[N_ia32_st_REGS]; /**< the register stack */
88 int depth; /**< the current stack depth */
89 x87_simulator *sim; /**< The simulator. */
92 /** An empty state, used for blocks without fp instructions. */
93 static x87_state empty = { { {0, NULL}, }, 0, NULL };
96 * Return values of the instruction simulator functions.
99 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
100 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
101 in the schedule AFTER the current node. */
105 * The type of an instruction simulator function.
107 * @param state the x87 state
108 * @param n the node to be simulated
110 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
112 * NO_NODE_ADDED otherwise
114 typedef int (*sim_func)(x87_state *state, ir_node *n);
117 * A block state: Every block has a x87 state at the beginning and at the end.
119 typedef struct blk_state {
120 x87_state *begin; /**< state at the begin or NULL if not assigned */
121 x87_state *end; /**< state at the end or NULL if not assigned */
124 /** liveness bitset for vfp registers. */
125 typedef unsigned char vfp_liveness;
130 struct x87_simulator {
131 struct obstack obst; /**< An obstack for fast allocating. */
132 pmap *blk_states; /**< Map blocks to states. */
133 be_lv_t *lv; /**< intrablock liveness. */
134 vfp_liveness *live; /**< Liveness information. */
135 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
136 waitq *worklist; /**< Worklist of blocks that must be processed. */
140 * Returns the current stack depth.
142 * @param state the x87 state
144 * @return the x87 stack depth
146 static int x87_get_depth(const x87_state *state)
151 static st_entry *x87_get_entry(x87_state *const state, int const pos)
153 assert(0 <= pos && pos < state->depth);
154 return &state->st[N_ia32_st_REGS - state->depth + pos];
158 * Return the virtual register index at st(pos).
160 * @param state the x87 state
161 * @param pos a stack position
163 * @return the vfp register index that produced the value at st(pos)
165 static int x87_get_st_reg(const x87_state *state, int pos)
167 return x87_get_entry((x87_state*)state, pos)->reg_idx;
172 * Dump the stack for debugging.
174 * @param state the x87 state
176 static void x87_dump_stack(const x87_state *state)
178 for (int i = state->depth; i-- != 0;) {
179 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
180 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
182 DB((dbg, LEVEL_2, "<-- TOS\n"));
184 #endif /* DEBUG_libfirm */
187 * Set a virtual register to st(pos).
189 * @param state the x87 state
190 * @param reg_idx the vfp register index that should be set
191 * @param node the IR node that produces the value of the vfp register
192 * @param pos the stack position where the new value should be entered
194 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
196 st_entry *const entry = x87_get_entry(state, pos);
197 entry->reg_idx = reg_idx;
200 DB((dbg, LEVEL_2, "After SET_REG: "));
201 DEBUG_ONLY(x87_dump_stack(state);)
205 * Set the tos virtual register.
207 * @param state the x87 state
208 * @param reg_idx the vfp register index that should be set
209 * @param node the IR node that produces the value of the vfp register
211 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
213 x87_set_st(state, reg_idx, node, 0);
217 * Swap st(0) with st(pos).
219 * @param state the x87 state
220 * @param pos the stack position to change the tos with
222 static void x87_fxch(x87_state *state, int pos)
224 st_entry *const a = x87_get_entry(state, pos);
225 st_entry *const b = x87_get_entry(state, 0);
226 st_entry const t = *a;
230 DB((dbg, LEVEL_2, "After FXCH: "));
231 DEBUG_ONLY(x87_dump_stack(state);)
235 * Convert a virtual register to the stack index.
237 * @param state the x87 state
238 * @param reg_idx the register vfp index
240 * @return the stack position where the register is stacked
241 * or -1 if the virtual register was not found
243 static int x87_on_stack(const x87_state *state, int reg_idx)
245 for (int i = 0; i < state->depth; ++i) {
246 if (x87_get_st_reg(state, i) == reg_idx)
253 * Push a virtual Register onto the stack, double pushes are NOT allowed.
255 * @param state the x87 state
256 * @param reg_idx the register vfp index
257 * @param node the node that produces the value of the vfp register
259 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
261 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
262 assert(state->depth < N_ia32_st_REGS && "stack overrun");
265 st_entry *const entry = x87_get_entry(state, 0);
266 entry->reg_idx = reg_idx;
269 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
273 * Pop a virtual Register from the stack.
275 * @param state the x87 state
277 static void x87_pop(x87_state *state)
279 assert(state->depth > 0 && "stack underrun");
283 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
287 * Empty the fpu stack
289 * @param state the x87 state
291 static void x87_emms(x87_state *state)
297 * Returns the block state of a block.
299 * @param sim the x87 simulator handle
300 * @param block the current block
302 * @return the block state
304 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
306 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
309 res = OALLOC(&sim->obst, blk_state);
313 pmap_insert(sim->blk_states, block, res);
322 * @param sim the x87 simulator handle
323 * @param src the x87 state that will be cloned
325 * @return a cloned copy of the src state
327 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
329 x87_state *const res = OALLOC(&sim->obst, x87_state);
335 * Patch a virtual instruction into a x87 one and return
336 * the node representing the result value.
338 * @param n the IR node to patch
339 * @param op the x87 opcode to patch in
341 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
343 ir_mode *mode = get_irn_mode(n);
348 if (mode == mode_T) {
349 /* patch all Proj's */
350 foreach_out_edge(n, edge) {
351 ir_node *proj = get_edge_src_irn(edge);
353 mode = get_irn_mode(proj);
354 if (mode_is_float(mode)) {
356 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
360 } else if (mode_is_float(mode))
361 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
366 * Returns the first Proj of a mode_T node having a given mode.
368 * @param n the mode_T node
369 * @param m the desired mode of the Proj
370 * @return The first Proj of mode @p m found.
372 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
374 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
376 foreach_out_edge(n, edge) {
377 ir_node *proj = get_edge_src_irn(edge);
378 if (get_irn_mode(proj) == m)
382 panic("Proj not found");
386 * Wrap the arch_* function here so we can check for errors.
388 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
390 const arch_register_t *res = arch_get_irn_register(irn);
392 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
396 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
399 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
401 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
405 static inline const arch_register_t *get_st_reg(int index)
407 return &ia32_registers[REG_ST0 + index];
411 * Create a fxch node before another node.
413 * @param state the x87 state
414 * @param n the node after the fxch
415 * @param pos exchange st(pos) with st(0)
417 static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
419 x87_fxch(state, pos);
421 ir_node *const block = get_nodes_block(n);
422 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
423 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
424 attr->x87[0] = get_st_reg(pos);
425 attr->x87[2] = get_st_reg(0);
429 sched_add_before(n, fxch);
430 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
433 /* -------------- x87 perm --------------- */
436 * Calculate the necessary permutations to reach dst_state.
438 * These permutations are done with fxch instructions and placed
439 * at the end of the block.
441 * Note that critical edges are removed here, so we need only
442 * a shuffle if the current block has only one successor.
444 * @param block the current block
445 * @param state the current x87 stack state, might be modified
446 * @param dst_state destination state
450 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
452 int i, n_cycles, k, ri;
453 unsigned cycles[4], all_mask;
454 char cycle_idx[4][8];
456 assert(state->depth == dst_state->depth);
458 /* Some mathematics here:
459 * If we have a cycle of length n that includes the tos,
460 * we need n-1 exchange operations.
461 * We can always add the tos and restore it, so we need
462 * n+1 exchange operations for a cycle not containing the tos.
463 * So, the maximum of needed operations is for a cycle of 7
464 * not including the tos == 8.
465 * This is the same number of ops we would need for using stores,
466 * so exchange is cheaper (we save the loads).
467 * On the other hand, we might need an additional exchange
468 * in the next block to bring one operand on top, so the
469 * number of ops in the first case is identical.
470 * Further, no more than 4 cycles can exists (4 x 2). */
471 all_mask = (1 << (state->depth)) - 1;
473 for (n_cycles = 0; all_mask; ++n_cycles) {
474 int src_idx, dst_idx;
476 /* find the first free slot */
477 for (i = 0; i < state->depth; ++i) {
478 if (all_mask & (1 << i)) {
479 all_mask &= ~(1 << i);
481 /* check if there are differences here */
482 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
488 /* no more cycles found */
493 cycles[n_cycles] = (1 << i);
494 cycle_idx[n_cycles][k++] = i;
495 for (src_idx = i; ; src_idx = dst_idx) {
496 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
498 if ((all_mask & (1 << dst_idx)) == 0)
501 cycle_idx[n_cycles][k++] = dst_idx;
502 cycles[n_cycles] |= (1 << dst_idx);
503 all_mask &= ~(1 << dst_idx);
505 cycle_idx[n_cycles][k] = -1;
509 /* no permutation needed */
513 /* Hmm: permutation needed */
514 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
515 DEBUG_ONLY(x87_dump_stack(state);)
516 DB((dbg, LEVEL_2, " to\n"));
517 DEBUG_ONLY(x87_dump_stack(dst_state);)
521 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
522 for (ri = 0; ri < n_cycles; ++ri) {
523 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
524 for (k = 0; cycle_idx[ri][k] != -1; ++k)
525 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
526 DB((dbg, LEVEL_2, "\n"));
531 * Find the place node must be insert.
532 * We have only one successor block, so the last instruction should
535 ir_node *const before = sched_last(block);
536 assert(is_cfop(before));
538 /* now do the permutations */
539 for (ri = 0; ri < n_cycles; ++ri) {
540 if ((cycles[ri] & 1) == 0) {
541 /* this cycle does not include the tos */
542 x87_create_fxch(state, before, cycle_idx[ri][0]);
544 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
545 x87_create_fxch(state, before, cycle_idx[ri][k]);
547 if ((cycles[ri] & 1) == 0) {
548 /* this cycle does not include the tos */
549 x87_create_fxch(state, before, cycle_idx[ri][0]);
556 * Create a fpush before node n.
558 * @param state the x87 state
559 * @param n the node after the fpush
560 * @param pos push st(pos) on stack
561 * @param val the value to push
563 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
565 x87_push(state, out_reg_idx, val);
567 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
568 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
569 attr->x87[0] = get_st_reg(pos);
570 attr->x87[2] = get_st_reg(0);
573 sched_add_before(n, fpush);
575 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
579 * Create a fpop before node n.
581 * @param state the x87 state
582 * @param n the node after the fpop
583 * @param num pop 1 or 2 values
585 * @return the fpop node
587 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
589 ir_node *fpop = NULL;
590 ia32_x87_attr_t *attr;
595 if (ia32_cg_config.use_ffreep)
596 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
598 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
599 attr = get_ia32_x87_attr(fpop);
600 attr->x87[0] = get_st_reg(0);
601 attr->x87[1] = get_st_reg(0);
602 attr->x87[2] = get_st_reg(0);
605 sched_add_before(n, fpop);
606 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
611 /* --------------------------------- liveness ------------------------------------------ */
614 * The liveness transfer function.
615 * Updates a live set over a single step from a given node to its predecessor.
616 * Everything defined at the node is removed from the set, the uses of the node get inserted.
618 * @param irn The node at which liveness should be computed.
619 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
620 * the registers live after irn.
622 * @return The live bitset.
624 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
627 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
629 if (get_irn_mode(irn) == mode_T) {
630 foreach_out_edge(irn, edge) {
631 ir_node *proj = get_edge_src_irn(edge);
633 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
634 const arch_register_t *reg = x87_get_irn_register(proj);
635 live &= ~(1 << arch_register_get_index(reg));
638 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
639 const arch_register_t *reg = x87_get_irn_register(irn);
640 live &= ~(1 << arch_register_get_index(reg));
643 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
644 ir_node *op = get_irn_n(irn, i);
646 if (mode_is_float(get_irn_mode(op)) &&
647 arch_irn_consider_in_reg_alloc(cls, op)) {
648 const arch_register_t *reg = x87_get_irn_register(op);
649 live |= 1 << arch_register_get_index(reg);
656 * Put all live virtual registers at the end of a block into a bitset.
658 * @param sim the simulator handle
659 * @param bl the block
661 * @return The live bitset at the end of this block
663 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
665 vfp_liveness live = 0;
666 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
667 const be_lv_t *lv = sim->lv;
669 be_lv_foreach(lv, block, be_lv_state_end, node) {
670 const arch_register_t *reg;
671 if (!arch_irn_consider_in_reg_alloc(cls, node))
674 reg = x87_get_irn_register(node);
675 live |= 1 << arch_register_get_index(reg);
681 /** get the register mask from an arch_register */
682 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
685 * Return a bitset of argument registers which are live at the end of a node.
687 * @param sim the simulator handle
688 * @param pos the node
689 * @param kill kill mask for the output registers
691 * @return The live bitset.
693 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
695 unsigned idx = get_irn_idx(pos);
697 assert(idx < sim->n_idx);
698 return sim->live[idx] & ~kill;
702 * Calculate the liveness for a whole block and cache it.
704 * @param sim the simulator handle
705 * @param block the block
707 static void update_liveness(x87_simulator *sim, ir_node *block)
709 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
712 /* now iterate through the block backward and cache the results */
713 sched_foreach_reverse(block, irn) {
714 /* stop at the first Phi: this produces the live-in */
718 idx = get_irn_idx(irn);
719 sim->live[idx] = live;
721 live = vfp_liveness_transfer(irn, live);
723 idx = get_irn_idx(block);
724 sim->live[idx] = live;
728 * Returns true if a register is live in a set.
730 * @param reg_idx the vfp register index
731 * @param live a live bitset
733 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
737 * Dump liveness info.
739 * @param live the live bitset
741 static void vfp_dump_live(vfp_liveness live)
745 DB((dbg, LEVEL_2, "Live after: "));
746 for (i = 0; i < 8; ++i) {
747 if (live & (1 << i)) {
748 DB((dbg, LEVEL_2, "vf%d ", i));
751 DB((dbg, LEVEL_2, "\n"));
753 #endif /* DEBUG_libfirm */
755 /* --------------------------------- simulators ---------------------------------------- */
758 * Simulate a virtual binop.
760 * @param state the x87 state
761 * @param n the node that should be simulated (and patched)
762 * @param tmpl the template containing the 4 possible x87 opcodes
764 * @return NO_NODE_ADDED
766 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
768 int op2_idx = 0, op1_idx;
769 int out_idx, do_pop = 0;
770 ia32_x87_attr_t *attr;
772 ir_node *patched_insn;
774 x87_simulator *sim = state->sim;
775 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
776 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
777 const arch_register_t *op1_reg = x87_get_irn_register(op1);
778 const arch_register_t *op2_reg = x87_get_irn_register(op2);
779 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
780 int reg_index_1 = arch_register_get_index(op1_reg);
781 int reg_index_2 = arch_register_get_index(op2_reg);
782 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
786 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
787 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
788 arch_register_get_name(out)));
789 DEBUG_ONLY(vfp_dump_live(live);)
790 DB((dbg, LEVEL_1, "Stack before: "));
791 DEBUG_ONLY(x87_dump_stack(state);)
793 op1_idx = x87_on_stack(state, reg_index_1);
794 assert(op1_idx >= 0);
795 op1_live_after = is_vfp_live(reg_index_1, live);
797 attr = get_ia32_x87_attr(n);
798 permuted = attr->attr.data.ins_permuted;
800 int const out_reg_idx = arch_register_get_index(out);
801 if (reg_index_2 != REG_VFP_VFP_NOREG) {
804 /* second operand is a vfp register */
805 op2_idx = x87_on_stack(state, reg_index_2);
806 assert(op2_idx >= 0);
807 op2_live_after = is_vfp_live(reg_index_2, live);
809 if (op2_live_after) {
810 /* Second operand is live. */
812 if (op1_live_after) {
813 /* Both operands are live: push the first one.
814 This works even for op1 == op2. */
815 x87_create_fpush(state, n, op1_idx, out_reg_idx, op2);
816 /* now do fxxx (tos=tos X op) */
820 dst = tmpl->normal_op;
822 /* Second live, first operand is dead here, bring it to tos. */
824 x87_create_fxch(state, n, op1_idx);
829 /* now do fxxx (tos=tos X op) */
831 dst = tmpl->normal_op;
834 /* Second operand is dead. */
835 if (op1_live_after) {
836 /* First operand is live: bring second to tos. */
838 x87_create_fxch(state, n, op2_idx);
843 /* now do fxxxr (tos = op X tos) */
845 dst = tmpl->reverse_op;
847 /* Both operands are dead here, pop them from the stack. */
850 /* Both are identically and on tos, no pop needed. */
851 /* here fxxx (tos = tos X tos) */
852 dst = tmpl->normal_op;
855 /* now do fxxxp (op = op X tos, pop) */
856 dst = tmpl->normal_pop_op;
860 } else if (op1_idx == 0) {
861 assert(op1_idx != op2_idx);
862 /* now do fxxxrp (op = tos X op, pop) */
863 dst = tmpl->reverse_pop_op;
867 /* Bring the second on top. */
868 x87_create_fxch(state, n, op2_idx);
869 if (op1_idx == op2_idx) {
870 /* Both are identically and on tos now, no pop needed. */
873 /* use fxxx (tos = tos X tos) */
874 dst = tmpl->normal_op;
877 /* op2 is on tos now */
879 /* use fxxxp (op = op X tos, pop) */
880 dst = tmpl->normal_pop_op;
888 /* second operand is an address mode */
889 if (op1_live_after) {
890 /* first operand is live: push it here */
891 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
894 /* first operand is dead: bring it to tos */
896 x87_create_fxch(state, n, op1_idx);
901 /* use fxxx (tos = tos X mem) */
902 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
906 patched_insn = x87_patch_insn(n, dst);
907 x87_set_st(state, out_reg_idx, patched_insn, out_idx);
912 /* patch the operation */
913 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
914 if (reg_index_2 != REG_VFP_VFP_NOREG) {
915 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
917 attr->x87[2] = out = get_st_reg(out_idx);
919 if (reg_index_2 != REG_VFP_VFP_NOREG) {
920 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
921 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
922 arch_register_get_name(out)));
924 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
925 arch_register_get_name(op1_reg),
926 arch_register_get_name(out)));
929 return NO_NODE_ADDED;
933 * Simulate a virtual Unop.
935 * @param state the x87 state
936 * @param n the node that should be simulated (and patched)
937 * @param op the x87 opcode that will replace n's opcode
939 * @return NO_NODE_ADDED
941 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
943 arch_register_t const *const out = x87_get_irn_register(n);
944 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
945 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
946 DEBUG_ONLY(vfp_dump_live(live);)
948 ir_node *const op1 = get_irn_n(n, 0);
949 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
950 int const op1_reg_idx = arch_register_get_index(op1_reg);
951 int const op1_idx = x87_on_stack(state, op1_reg_idx);
952 int const out_reg_idx = arch_register_get_index(out);
953 if (is_vfp_live(op1_reg_idx, live)) {
954 /* push the operand here */
955 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
957 /* operand is dead, bring it to tos */
959 x87_create_fxch(state, n, op1_idx);
963 x87_set_tos(state, out_reg_idx, x87_patch_insn(n, op));
964 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
965 attr->x87[2] = attr->x87[0] = get_st_reg(0);
966 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), attr->x87[2]->name));
968 return NO_NODE_ADDED;
972 * Simulate a virtual Load instruction.
974 * @param state the x87 state
975 * @param n the node that should be simulated (and patched)
976 * @param op the x87 opcode that will replace n's opcode
978 * @return NO_NODE_ADDED
980 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
982 const arch_register_t *out = x87_irn_get_register(n, res_pos);
983 ia32_x87_attr_t *attr;
985 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
986 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
987 assert(out == x87_irn_get_register(n, res_pos));
988 attr = get_ia32_x87_attr(n);
989 attr->x87[2] = out = get_st_reg(0);
990 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
992 return NO_NODE_ADDED;
996 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
998 * @param store The store
999 * @param old_val The former value
1000 * @param new_val The new value
1002 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
1004 foreach_out_edge_safe(old_val, edge) {
1005 ir_node *user = get_edge_src_irn(edge);
1006 /* if the user is scheduled after the store: rewire */
1007 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1008 set_irn_n(user, get_edge_src_pos(edge), new_val);
1014 * Simulate a virtual Store.
1016 * @param state the x87 state
1017 * @param n the node that should be simulated (and patched)
1018 * @param op the x87 store opcode
1019 * @param op_p the x87 store and pop opcode
1021 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1023 ir_node *const val = get_irn_n(n, n_ia32_vfst_val);
1024 arch_register_t const *const op2 = x87_get_irn_register(val);
1025 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1027 int insn = NO_NODE_ADDED;
1028 int const op2_reg_idx = arch_register_get_index(op2);
1029 int const op2_idx = x87_on_stack(state, op2_reg_idx);
1030 unsigned const live = vfp_live_args_after(state->sim, n, 0);
1031 int const live_after_node = is_vfp_live(op2_reg_idx, live);
1032 assert(op2_idx >= 0);
1033 if (live_after_node) {
1034 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
1035 * fist doesn't support 64bit mode, only fistp
1037 * - stack not full: push value and fstp
1038 * - stack full: fstp value and load again
1039 * Note that we cannot test on mode_E, because floats might be 80bit ... */
1040 ir_mode *const mode = get_ia32_ls_mode(n);
1041 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
1042 if (x87_get_depth(state) < N_ia32_st_REGS) {
1043 /* ok, we have a free register: push + fstp */
1044 x87_create_fpush(state, n, op2_idx, REG_VFP_VFP_NOREG, val);
1046 x87_patch_insn(n, op_p);
1048 /* stack full here: need fstp + load */
1050 x87_patch_insn(n, op_p);
1052 ir_node *const block = get_nodes_block(n);
1053 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
1054 ir_node *const vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
1056 /* copy all attributes */
1057 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1058 if (is_ia32_use_frame(n))
1059 set_ia32_use_frame(vfld);
1060 set_ia32_op_type(vfld, ia32_AddrModeS);
1061 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1062 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1063 set_ia32_ls_mode(vfld, mode);
1065 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_vfld_res);
1066 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1068 arch_set_irn_register(rproj, op2);
1070 /* reroute all former users of the store memory to the load memory */
1071 edges_reroute_except(mem, mproj, vfld);
1073 sched_add_after(n, vfld);
1075 /* rewire all users, scheduled after the store, to the loaded value */
1076 collect_and_rewire_users(n, val, rproj);
1081 /* we can only store the tos to memory */
1083 x87_create_fxch(state, n, op2_idx);
1085 /* mode size 64 or smaller -> use normal fst */
1086 x87_patch_insn(n, op);
1089 /* we can only store the tos to memory */
1091 x87_create_fxch(state, n, op2_idx);
1094 x87_patch_insn(n, op_p);
1097 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
1098 attr->x87[1] = get_st_reg(0);
1099 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(attr->x87[1])));
1104 #define _GEN_BINOP(op, rev) \
1105 static int sim_##op(x87_state *state, ir_node *n) { \
1106 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1107 return sim_binop(state, n, &tmpl); \
1110 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1111 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1113 #define GEN_LOAD(op) \
1114 static int sim_##op(x87_state *state, ir_node *n) { \
1115 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1118 #define GEN_UNOP(op) \
1119 static int sim_##op(x87_state *state, ir_node *n) { \
1120 return sim_unop(state, n, op_ia32_##op); \
1123 #define GEN_STORE(op) \
1124 static int sim_##op(x87_state *state, ir_node *n) { \
1125 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1147 * Simulate a virtual fisttp.
1149 * @param state the x87 state
1150 * @param n the node that should be simulated (and patched)
1152 * @return NO_NODE_ADDED
1154 static int sim_fisttp(x87_state *state, ir_node *n)
1156 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1157 const arch_register_t *op2 = x87_get_irn_register(val);
1158 ia32_x87_attr_t *attr;
1159 int op2_reg_idx, op2_idx;
1161 op2_reg_idx = arch_register_get_index(op2);
1162 op2_idx = x87_on_stack(state, op2_reg_idx);
1163 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1164 assert(op2_idx >= 0);
1166 /* Note: although the value is still live here, it is destroyed because
1167 of the pop. The register allocator is aware of that and introduced a copy
1168 if the value must be alive. */
1170 /* we can only store the tos to memory */
1172 x87_create_fxch(state, n, op2_idx);
1175 x87_patch_insn(n, op_ia32_fisttp);
1177 attr = get_ia32_x87_attr(n);
1178 attr->x87[1] = op2 = get_st_reg(0);
1179 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1181 return NO_NODE_ADDED;
1185 * Simulate a virtual FtstFnstsw.
1187 * @param state the x87 state
1188 * @param n the node that should be simulated (and patched)
1190 * @return NO_NODE_ADDED
1192 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1194 x87_simulator *sim = state->sim;
1195 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1196 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1197 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1198 int reg_index_1 = arch_register_get_index(reg1);
1199 int op1_idx = x87_on_stack(state, reg_index_1);
1200 unsigned live = vfp_live_args_after(sim, n, 0);
1202 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1203 DEBUG_ONLY(vfp_dump_live(live);)
1204 DB((dbg, LEVEL_1, "Stack before: "));
1205 DEBUG_ONLY(x87_dump_stack(state);)
1206 assert(op1_idx >= 0);
1209 /* bring the value to tos */
1210 x87_create_fxch(state, n, op1_idx);
1214 /* patch the operation */
1215 x87_patch_insn(n, op_ia32_FtstFnstsw);
1216 reg1 = get_st_reg(op1_idx);
1217 attr->x87[0] = reg1;
1218 attr->x87[1] = NULL;
1219 attr->x87[2] = NULL;
1221 if (!is_vfp_live(reg_index_1, live))
1222 x87_create_fpop(state, sched_next(n), 1);
1224 return NO_NODE_ADDED;
1230 * @param state the x87 state
1231 * @param n the node that should be simulated (and patched)
1233 * @return NO_NODE_ADDED
1235 static int sim_Fucom(x87_state *state, ir_node *n)
1239 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1241 x87_simulator *sim = state->sim;
1242 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1243 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1244 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1245 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1246 int reg_index_1 = arch_register_get_index(op1);
1247 int reg_index_2 = arch_register_get_index(op2);
1248 unsigned live = vfp_live_args_after(sim, n, 0);
1249 bool permuted = attr->attr.data.ins_permuted;
1253 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1254 arch_register_get_name(op1), arch_register_get_name(op2)));
1255 DEBUG_ONLY(vfp_dump_live(live);)
1256 DB((dbg, LEVEL_1, "Stack before: "));
1257 DEBUG_ONLY(x87_dump_stack(state);)
1259 op1_idx = x87_on_stack(state, reg_index_1);
1260 assert(op1_idx >= 0);
1262 /* BEWARE: check for comp a,a cases, they might happen */
1263 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1264 /* second operand is a vfp register */
1265 op2_idx = x87_on_stack(state, reg_index_2);
1266 assert(op2_idx >= 0);
1268 if (is_vfp_live(reg_index_2, live)) {
1269 /* second operand is live */
1271 if (is_vfp_live(reg_index_1, live)) {
1272 /* both operands are live */
1275 /* res = tos X op */
1276 } else if (op2_idx == 0) {
1277 /* res = op X tos */
1278 permuted = !permuted;
1281 /* bring the first one to tos */
1282 x87_create_fxch(state, n, op1_idx);
1283 if (op1_idx == op2_idx) {
1285 } else if (op2_idx == 0) {
1289 /* res = tos X op */
1292 /* second live, first operand is dead here, bring it to tos.
1293 This means further, op1_idx != op2_idx. */
1294 assert(op1_idx != op2_idx);
1296 x87_create_fxch(state, n, op1_idx);
1301 /* res = tos X op, pop */
1305 /* second operand is dead */
1306 if (is_vfp_live(reg_index_1, live)) {
1307 /* first operand is live: bring second to tos.
1308 This means further, op1_idx != op2_idx. */
1309 assert(op1_idx != op2_idx);
1311 x87_create_fxch(state, n, op2_idx);
1316 /* res = op X tos, pop */
1318 permuted = !permuted;
1321 /* both operands are dead here, check first for identity. */
1322 if (op1_idx == op2_idx) {
1323 /* identically, one pop needed */
1325 x87_create_fxch(state, n, op1_idx);
1329 /* res = tos X op, pop */
1332 /* different, move them to st and st(1) and pop both.
1333 The tricky part is to get one into st(1).*/
1334 else if (op2_idx == 1) {
1335 /* good, second operand is already in the right place, move the first */
1337 /* bring the first on top */
1338 x87_create_fxch(state, n, op1_idx);
1339 assert(op2_idx != 0);
1342 /* res = tos X op, pop, pop */
1344 } else if (op1_idx == 1) {
1345 /* good, first operand is already in the right place, move the second */
1347 /* bring the first on top */
1348 x87_create_fxch(state, n, op2_idx);
1349 assert(op1_idx != 0);
1352 /* res = op X tos, pop, pop */
1353 permuted = !permuted;
1357 /* if one is already the TOS, we need two fxch */
1359 /* first one is TOS, move to st(1) */
1360 x87_create_fxch(state, n, 1);
1361 assert(op2_idx != 1);
1363 x87_create_fxch(state, n, op2_idx);
1365 /* res = op X tos, pop, pop */
1367 permuted = !permuted;
1369 } else if (op2_idx == 0) {
1370 /* second one is TOS, move to st(1) */
1371 x87_create_fxch(state, n, 1);
1372 assert(op1_idx != 1);
1374 x87_create_fxch(state, n, op1_idx);
1376 /* res = tos X op, pop, pop */
1379 /* none of them is either TOS or st(1), 3 fxch needed */
1380 x87_create_fxch(state, n, op2_idx);
1381 assert(op1_idx != 0);
1382 x87_create_fxch(state, n, 1);
1384 x87_create_fxch(state, n, op1_idx);
1386 /* res = tos X op, pop, pop */
1393 /* second operand is an address mode */
1394 if (is_vfp_live(reg_index_1, live)) {
1395 /* first operand is live: bring it to TOS */
1397 x87_create_fxch(state, n, op1_idx);
1401 /* first operand is dead: bring it to tos */
1403 x87_create_fxch(state, n, op1_idx);
1410 /* patch the operation */
1411 if (is_ia32_vFucomFnstsw(n)) {
1415 case 0: dst = op_ia32_FucomFnstsw; break;
1416 case 1: dst = op_ia32_FucompFnstsw; break;
1417 case 2: dst = op_ia32_FucomppFnstsw; break;
1418 default: panic("invalid popcount");
1421 for (i = 0; i < pops; ++i) {
1424 } else if (is_ia32_vFucomi(n)) {
1426 case 0: dst = op_ia32_Fucomi; break;
1427 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1429 dst = op_ia32_Fucompi;
1431 x87_create_fpop(state, sched_next(n), 1);
1433 default: panic("invalid popcount");
1436 panic("invalid operation %+F", n);
1439 x87_patch_insn(n, dst);
1446 op1 = get_st_reg(op1_idx);
1449 op2 = get_st_reg(op2_idx);
1452 attr->x87[2] = NULL;
1453 attr->attr.data.ins_permuted = permuted;
1456 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1457 arch_register_get_name(op1), arch_register_get_name(op2)));
1459 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1460 arch_register_get_name(op1)));
1463 return NO_NODE_ADDED;
1469 * @param state the x87 state
1470 * @param n the node that should be simulated (and patched)
1472 * @return NO_NODE_ADDED
1474 static int sim_Keep(x87_state *state, ir_node *node)
1477 const arch_register_t *op_reg;
1483 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1485 arity = get_irn_arity(node);
1486 for (i = 0; i < arity; ++i) {
1487 op = get_irn_n(node, i);
1488 op_reg = arch_get_irn_register(op);
1489 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1492 reg_id = arch_register_get_index(op_reg);
1493 live = vfp_live_args_after(state->sim, node, 0);
1495 op_stack_idx = x87_on_stack(state, reg_id);
1496 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1497 x87_create_fpop(state, sched_next(node), 1);
1500 DB((dbg, LEVEL_1, "Stack after: "));
1501 DEBUG_ONLY(x87_dump_stack(state);)
1503 return NO_NODE_ADDED;
1507 * Keep the given node alive by adding a be_Keep.
1509 * @param node the node to kept alive
1511 static void keep_float_node_alive(ir_node *node)
1513 ir_node *block = get_nodes_block(node);
1514 ir_node *keep = be_new_Keep(block, 1, &node);
1515 sched_add_after(node, keep);
1519 * Create a copy of a node. Recreate the node if it's a constant.
1521 * @param state the x87 state
1522 * @param n the node to be copied
1524 * @return the copy of n
1526 static ir_node *create_Copy(x87_state *state, ir_node *n)
1528 dbg_info *n_dbg = get_irn_dbg_info(n);
1529 ir_mode *mode = get_irn_mode(n);
1530 ir_node *block = get_nodes_block(n);
1531 ir_node *pred = get_irn_n(n, 0);
1532 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1534 const arch_register_t *out;
1535 const arch_register_t *op1;
1536 ia32_x87_attr_t *attr;
1538 /* Do not copy constants, recreate them. */
1539 switch (get_ia32_irn_opcode(pred)) {
1541 cnstr = new_bd_ia32_fldz;
1544 cnstr = new_bd_ia32_fld1;
1546 case iro_ia32_fldpi:
1547 cnstr = new_bd_ia32_fldpi;
1549 case iro_ia32_fldl2e:
1550 cnstr = new_bd_ia32_fldl2e;
1552 case iro_ia32_fldl2t:
1553 cnstr = new_bd_ia32_fldl2t;
1555 case iro_ia32_fldlg2:
1556 cnstr = new_bd_ia32_fldlg2;
1558 case iro_ia32_fldln2:
1559 cnstr = new_bd_ia32_fldln2;
1565 out = x87_get_irn_register(n);
1566 op1 = x87_get_irn_register(pred);
1568 if (cnstr != NULL) {
1569 /* copy a constant */
1570 res = (*cnstr)(n_dbg, block, mode);
1572 x87_push(state, arch_register_get_index(out), res);
1574 attr = get_ia32_x87_attr(res);
1575 attr->x87[2] = get_st_reg(0);
1577 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1579 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1581 x87_push(state, arch_register_get_index(out), res);
1583 attr = get_ia32_x87_attr(res);
1584 attr->x87[0] = get_st_reg(op1_idx);
1585 attr->x87[2] = get_st_reg(0);
1587 arch_set_irn_register(res, out);
1593 * Simulate a be_Copy.
1595 * @param state the x87 state
1596 * @param n the node that should be simulated (and patched)
1598 * @return NO_NODE_ADDED
1600 static int sim_Copy(x87_state *state, ir_node *n)
1602 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1603 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1604 return NO_NODE_ADDED;
1606 ir_node *const pred = be_get_Copy_op(n);
1607 arch_register_t const *const op1 = x87_get_irn_register(pred);
1608 arch_register_t const *const out = x87_get_irn_register(n);
1609 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
1611 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1612 arch_register_get_name(op1), arch_register_get_name(out)));
1613 DEBUG_ONLY(vfp_dump_live(live);)
1615 if (is_vfp_live(arch_register_get_index(op1), live)) {
1616 /* Operand is still live, a real copy. We need here an fpush that can
1617 hold a a register, so use the fpushCopy or recreate constants */
1618 ir_node *const node = create_Copy(state, n);
1620 /* We have to make sure the old value doesn't go dead (which can happen
1621 * when we recreate constants). As the simulator expected that value in
1622 * the pred blocks. This is unfortunate as removing it would save us 1
1623 * instruction, but we would have to rerun all the simulation to get
1626 ir_node *const next = sched_next(n);
1629 sched_add_before(next, node);
1631 if (get_irn_n_edges(pred) == 0) {
1632 keep_float_node_alive(pred);
1635 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1637 /* Just a virtual copy. */
1638 int const op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1639 x87_set_st(state, arch_register_get_index(out), n, op1_idx);
1641 return NO_NODE_ADDED;
1645 * Returns the vf0 result Proj of a Call.
1647 * @para call the Call node
1649 static ir_node *get_call_result_proj(ir_node *call)
1651 /* search the result proj */
1652 foreach_out_edge(call, edge) {
1653 ir_node *proj = get_edge_src_irn(edge);
1654 long pn = get_Proj_proj(proj);
1656 if (pn == pn_ia32_Call_vf0)
1660 panic("result Proj missing");
1663 static int sim_Asm(x87_state *const state, ir_node *const n)
1667 for (size_t i = get_irn_arity(n); i-- != 0;) {
1668 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1669 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1670 panic("cannot handle %+F with x87 constraints", n);
1673 for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
1674 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1675 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1676 panic("cannot handle %+F with x87 constraints", n);
1679 return NO_NODE_ADDED;
1683 * Simulate a ia32_Call.
1685 * @param state the x87 state
1686 * @param n the node that should be simulated (and patched)
1688 * @return NO_NODE_ADDED
1690 static int sim_Call(x87_state *state, ir_node *n)
1692 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1694 /* at the begin of a call the x87 state should be empty */
1695 assert(state->depth == 0 && "stack not empty before call");
1697 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1698 if (get_method_n_ress(call_tp) != 0) {
1699 /* If the called function returns a float, it is returned in st(0).
1700 * This even happens if the return value is NOT used.
1701 * Moreover, only one return result is supported. */
1702 ir_type *const res_type = get_method_res_type(call_tp, 0);
1703 ir_mode *const mode = get_type_mode(res_type);
1704 if (mode && mode_is_float(mode)) {
1705 ir_node *const resproj = get_call_result_proj(n);
1706 arch_register_t const *const reg = x87_get_irn_register(resproj);
1707 x87_push(state, arch_register_get_index(reg), resproj);
1710 DB((dbg, LEVEL_1, "Stack after: "));
1711 DEBUG_ONLY(x87_dump_stack(state);)
1713 return NO_NODE_ADDED;
1717 * Simulate a be_Return.
1719 * @param state the x87 state
1720 * @param n the node that should be simulated (and patched)
1722 * @return NO_NODE_ADDED
1724 static int sim_Return(x87_state *state, ir_node *n)
1726 #ifdef DEBUG_libfirm
1727 /* only floating point return values must reside on stack */
1728 int n_float_res = 0;
1729 int const n_res = be_Return_get_n_rets(n);
1730 for (int i = 0; i < n_res; ++i) {
1731 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1732 if (mode_is_float(get_irn_mode(res)))
1735 assert(x87_get_depth(state) == n_float_res);
1738 /* pop them virtually */
1740 return NO_NODE_ADDED;
1744 * Simulate a be_Perm.
1746 * @param state the x87 state
1747 * @param irn the node that should be simulated (and patched)
1749 * @return NO_NODE_ADDED
1751 static int sim_Perm(x87_state *state, ir_node *irn)
1754 ir_node *pred = get_irn_n(irn, 0);
1757 /* handle only floating point Perms */
1758 if (! mode_is_float(get_irn_mode(pred)))
1759 return NO_NODE_ADDED;
1761 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1763 /* Perm is a pure virtual instruction on x87.
1764 All inputs must be on the FPU stack and are pairwise
1765 different from each other.
1766 So, all we need to do is to permutate the stack state. */
1767 n = get_irn_arity(irn);
1768 NEW_ARR_A(int, stack_pos, n);
1770 /* collect old stack positions */
1771 for (i = 0; i < n; ++i) {
1772 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1773 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1775 assert(idx >= 0 && "Perm argument not on x87 stack");
1779 /* now do the permutation */
1780 foreach_out_edge(irn, edge) {
1781 ir_node *proj = get_edge_src_irn(edge);
1782 const arch_register_t *out = x87_get_irn_register(proj);
1783 long num = get_Proj_proj(proj);
1785 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1786 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1788 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1790 return NO_NODE_ADDED;
1794 * Kill any dead registers at block start by popping them from the stack.
1796 * @param sim the simulator handle
1797 * @param block the current block
1798 * @param state the x87 state at the begin of the block
1800 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1802 ir_node *first_insn = sched_first(block);
1803 ir_node *keep = NULL;
1804 unsigned live = vfp_live_args_after(sim, block, 0);
1806 int i, depth, num_pop;
1809 depth = x87_get_depth(state);
1810 for (i = depth - 1; i >= 0; --i) {
1811 int reg = x87_get_st_reg(state, i);
1813 if (! is_vfp_live(reg, live))
1814 kill_mask |= (1 << i);
1818 DB((dbg, LEVEL_1, "Killing deads:\n"));
1819 DEBUG_ONLY(vfp_dump_live(live);)
1820 DEBUG_ONLY(x87_dump_stack(state);)
1822 if (kill_mask != 0 && live == 0) {
1823 /* special case: kill all registers */
1824 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1825 if (ia32_cg_config.use_femms) {
1826 /* use FEMMS on AMD processors to clear all */
1827 keep = new_bd_ia32_femms(NULL, block);
1829 /* use EMMS to clear all */
1830 keep = new_bd_ia32_emms(NULL, block);
1832 sched_add_before(first_insn, keep);
1838 /* now kill registers */
1840 /* we can only kill from TOS, so bring them up */
1841 if (! (kill_mask & 1)) {
1842 /* search from behind, because we can to a double-pop */
1843 for (i = depth - 1; i >= 0; --i) {
1844 if (kill_mask & (1 << i)) {
1845 kill_mask &= ~(1 << i);
1852 x87_set_st(state, -1, keep, i);
1853 x87_create_fxch(state, first_insn, i);
1856 if ((kill_mask & 3) == 3) {
1857 /* we can do a double-pop */
1861 /* only a single pop */
1866 kill_mask >>= num_pop;
1867 keep = x87_create_fpop(state, first_insn, num_pop);
1874 * Run a simulation and fix all virtual instructions for a block.
1876 * @param sim the simulator handle
1877 * @param block the current block
1879 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1882 blk_state *bl_state = x87_get_bl_state(sim, block);
1883 x87_state *state = bl_state->begin;
1884 ir_node *start_block;
1886 assert(state != NULL);
1887 /* already processed? */
1888 if (bl_state->end != NULL)
1891 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1892 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1893 DEBUG_ONLY(x87_dump_stack(state);)
1895 /* create a new state, will be changed */
1896 state = x87_clone_state(sim, state);
1897 /* at block begin, kill all dead registers */
1898 x87_kill_deads(sim, block, state);
1900 /* beware, n might change */
1901 for (n = sched_first(block); !sched_is_end(n); n = next) {
1904 ir_op *op = get_irn_op(n);
1907 * get the next node to be simulated here.
1908 * n might be completely removed from the schedule-
1910 next = sched_next(n);
1911 if (op->ops.generic != NULL) {
1912 func = (sim_func)op->ops.generic;
1915 node_inserted = (*func)(state, n);
1918 * sim_func might have added an additional node after n,
1919 * so update next node
1920 * beware: n must not be changed by sim_func
1921 * (i.e. removed from schedule) in this case
1923 if (node_inserted != NO_NODE_ADDED)
1924 next = sched_next(n);
1928 start_block = get_irg_start_block(get_irn_irg(block));
1930 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1932 /* check if the state must be shuffled */
1933 foreach_block_succ(block, edge) {
1934 ir_node *succ = get_edge_src_irn(edge);
1935 blk_state *succ_state;
1937 if (succ == start_block)
1940 succ_state = x87_get_bl_state(sim, succ);
1942 if (succ_state->begin == NULL) {
1943 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
1944 DEBUG_ONLY(x87_dump_stack(state);)
1945 succ_state->begin = state;
1947 waitq_put(sim->worklist, succ);
1949 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
1950 /* There is already a begin state for the successor, bad.
1951 Do the necessary permutations.
1952 Note that critical edges are removed, so this is always possible:
1953 If the successor has more than one possible input, then it must
1956 x87_shuffle(block, state, succ_state->begin);
1959 bl_state->end = state;
1963 * Register a simulator function.
1965 * @param op the opcode to simulate
1966 * @param func the simulator function for the opcode
1968 static void register_sim(ir_op *op, sim_func func)
1970 assert(op->ops.generic == NULL);
1971 op->ops.generic = (op_func) func;
1975 * Create a new x87 simulator.
1977 * @param sim a simulator handle, will be initialized
1978 * @param irg the current graph
1980 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
1982 obstack_init(&sim->obst);
1983 sim->blk_states = pmap_create();
1984 sim->n_idx = get_irg_last_idx(irg);
1985 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
1987 DB((dbg, LEVEL_1, "--------------------------------\n"
1988 "x87 Simulator started for %+F\n", irg));
1990 /* set the generic function pointer of instruction we must simulate */
1991 ir_clear_opcodes_generic_func();
1993 register_sim(op_ia32_Asm, sim_Asm);
1994 register_sim(op_ia32_Call, sim_Call);
1995 register_sim(op_ia32_vfld, sim_fld);
1996 register_sim(op_ia32_vfild, sim_fild);
1997 register_sim(op_ia32_vfld1, sim_fld1);
1998 register_sim(op_ia32_vfldz, sim_fldz);
1999 register_sim(op_ia32_vfadd, sim_fadd);
2000 register_sim(op_ia32_vfsub, sim_fsub);
2001 register_sim(op_ia32_vfmul, sim_fmul);
2002 register_sim(op_ia32_vfdiv, sim_fdiv);
2003 register_sim(op_ia32_vfprem, sim_fprem);
2004 register_sim(op_ia32_vfabs, sim_fabs);
2005 register_sim(op_ia32_vfchs, sim_fchs);
2006 register_sim(op_ia32_vfist, sim_fist);
2007 register_sim(op_ia32_vfisttp, sim_fisttp);
2008 register_sim(op_ia32_vfst, sim_fst);
2009 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2010 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2011 register_sim(op_ia32_vFucomi, sim_Fucom);
2012 register_sim(op_be_Copy, sim_Copy);
2013 register_sim(op_be_Return, sim_Return);
2014 register_sim(op_be_Perm, sim_Perm);
2015 register_sim(op_be_Keep, sim_Keep);
2019 * Destroy a x87 simulator.
2021 * @param sim the simulator handle
2023 static void x87_destroy_simulator(x87_simulator *sim)
2025 pmap_destroy(sim->blk_states);
2026 obstack_free(&sim->obst, NULL);
2027 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2031 * Pre-block walker: calculate the liveness information for the block
2032 * and store it into the sim->live cache.
2034 static void update_liveness_walker(ir_node *block, void *data)
2036 x87_simulator *sim = (x87_simulator*)data;
2037 update_liveness(sim, block);
2041 * Run a simulation and fix all virtual instructions for a graph.
2042 * Replaces all virtual floating point instructions and registers
2045 void ia32_x87_simulate_graph(ir_graph *irg)
2047 /* TODO improve code quality (less executed fxch) by using execfreqs */
2049 ir_node *block, *start_block;
2050 blk_state *bl_state;
2053 /* create the simulator */
2054 x87_init_simulator(&sim, irg);
2056 start_block = get_irg_start_block(irg);
2057 bl_state = x87_get_bl_state(&sim, start_block);
2059 /* start with the empty state */
2061 bl_state->begin = ∅
2063 sim.worklist = new_waitq();
2064 waitq_put(sim.worklist, start_block);
2066 be_assure_live_sets(irg);
2067 sim.lv = be_get_irg_liveness(irg);
2069 /* Calculate the liveness for all nodes. We must precalculate this info,
2070 * because the simulator adds new nodes (possible before Phi nodes) which
2071 * would let a lazy calculation fail.
2072 * On the other hand we reduce the computation amount due to
2073 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2075 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2079 block = (ir_node*)waitq_get(sim.worklist);
2080 x87_simulate_block(&sim, block);
2081 } while (! waitq_empty(sim.worklist));
2084 del_waitq(sim.worklist);
2085 x87_destroy_simulator(&sim);
2088 /* Initializes the x87 simulator. */
2089 void ia32_init_x87(void)
2091 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");