2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 /** the debug handle */
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 /* Forward declaration. */
59 typedef struct x87_simulator x87_simulator;
62 * An exchange template.
63 * Note that our virtual functions have the same inputs
64 * and attributes as the real ones, so we can simple exchange
66 * Further, x87 supports inverse instructions, so we can handle them.
68 typedef struct exchange_tmpl {
69 ir_op *normal_op; /**< the normal one */
70 ir_op *reverse_op; /**< the reverse one if exists */
71 ir_op *normal_pop_op; /**< the normal one with tos pop */
72 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
76 * An entry on the simulated x87 stack.
78 typedef struct st_entry {
79 int reg_idx; /**< the virtual register index of this stack value */
80 ir_node *node; /**< the node that produced this value */
86 typedef struct x87_state {
87 st_entry st[N_ia32_st_REGS]; /**< the register stack */
88 int depth; /**< the current stack depth */
89 x87_simulator *sim; /**< The simulator. */
92 /** An empty state, used for blocks without fp instructions. */
93 static x87_state empty = { { {0, NULL}, }, 0, NULL };
96 * Return values of the instruction simulator functions.
99 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
100 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
101 in the schedule AFTER the current node. */
105 * The type of an instruction simulator function.
107 * @param state the x87 state
108 * @param n the node to be simulated
110 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
112 * NO_NODE_ADDED otherwise
114 typedef int (*sim_func)(x87_state *state, ir_node *n);
117 * A block state: Every block has a x87 state at the beginning and at the end.
119 typedef struct blk_state {
120 x87_state *begin; /**< state at the begin or NULL if not assigned */
121 x87_state *end; /**< state at the end or NULL if not assigned */
124 /** liveness bitset for vfp registers. */
125 typedef unsigned char vfp_liveness;
130 struct x87_simulator {
131 struct obstack obst; /**< An obstack for fast allocating. */
132 pmap *blk_states; /**< Map blocks to states. */
133 be_lv_t *lv; /**< intrablock liveness. */
134 vfp_liveness *live; /**< Liveness information. */
135 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
136 waitq *worklist; /**< Worklist of blocks that must be processed. */
140 * Returns the current stack depth.
142 * @param state the x87 state
144 * @return the x87 stack depth
146 static int x87_get_depth(const x87_state *state)
151 static st_entry *x87_get_entry(x87_state *const state, int const pos)
153 assert(0 <= pos && pos < state->depth);
154 return &state->st[N_ia32_st_REGS - state->depth + pos];
158 * Return the virtual register index at st(pos).
160 * @param state the x87 state
161 * @param pos a stack position
163 * @return the vfp register index that produced the value at st(pos)
165 static int x87_get_st_reg(const x87_state *state, int pos)
167 return x87_get_entry((x87_state*)state, pos)->reg_idx;
172 * Dump the stack for debugging.
174 * @param state the x87 state
176 static void x87_dump_stack(const x87_state *state)
178 for (int i = state->depth; i-- != 0;) {
179 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
180 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
182 DB((dbg, LEVEL_2, "<-- TOS\n"));
184 #endif /* DEBUG_libfirm */
187 * Set a virtual register to st(pos).
189 * @param state the x87 state
190 * @param reg_idx the vfp register index that should be set
191 * @param node the IR node that produces the value of the vfp register
192 * @param pos the stack position where the new value should be entered
194 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
196 st_entry *const entry = x87_get_entry(state, pos);
197 entry->reg_idx = reg_idx;
200 DB((dbg, LEVEL_2, "After SET_REG: "));
201 DEBUG_ONLY(x87_dump_stack(state);)
205 * Set the tos virtual register.
207 * @param state the x87 state
208 * @param reg_idx the vfp register index that should be set
209 * @param node the IR node that produces the value of the vfp register
211 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
213 x87_set_st(state, reg_idx, node, 0);
217 * Swap st(0) with st(pos).
219 * @param state the x87 state
220 * @param pos the stack position to change the tos with
222 static void x87_fxch(x87_state *state, int pos)
224 st_entry *const a = x87_get_entry(state, pos);
225 st_entry *const b = x87_get_entry(state, 0);
226 st_entry const t = *a;
230 DB((dbg, LEVEL_2, "After FXCH: "));
231 DEBUG_ONLY(x87_dump_stack(state);)
235 * Convert a virtual register to the stack index.
237 * @param state the x87 state
238 * @param reg_idx the register vfp index
240 * @return the stack position where the register is stacked
241 * or -1 if the virtual register was not found
243 static int x87_on_stack(const x87_state *state, int reg_idx)
245 for (int i = 0; i < state->depth; ++i) {
246 if (x87_get_st_reg(state, i) == reg_idx)
253 * Push a virtual Register onto the stack, double pushed allowed.
255 * @param state the x87 state
256 * @param reg_idx the register vfp index
257 * @param node the node that produces the value of the vfp register
259 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
261 assert(state->depth < N_ia32_st_REGS && "stack overrun");
264 st_entry *const entry = x87_get_entry(state, 0);
265 entry->reg_idx = reg_idx;
268 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
272 * Push a virtual Register onto the stack, double pushes are NOT allowed.
274 * @param state the x87 state
275 * @param reg_idx the register vfp index
276 * @param node the node that produces the value of the vfp register
278 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
280 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
282 x87_push_dbl(state, reg_idx, node);
286 * Pop a virtual Register from the stack.
288 * @param state the x87 state
290 static void x87_pop(x87_state *state)
292 assert(state->depth > 0 && "stack underrun");
296 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
300 * Empty the fpu stack
302 * @param state the x87 state
304 static void x87_emms(x87_state *state)
310 * Returns the block state of a block.
312 * @param sim the x87 simulator handle
313 * @param block the current block
315 * @return the block state
317 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
319 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
322 res = OALLOC(&sim->obst, blk_state);
326 pmap_insert(sim->blk_states, block, res);
335 * @param sim the x87 simulator handle
336 * @param src the x87 state that will be cloned
338 * @return a cloned copy of the src state
340 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
342 x87_state *const res = OALLOC(&sim->obst, x87_state);
348 * Patch a virtual instruction into a x87 one and return
349 * the node representing the result value.
351 * @param n the IR node to patch
352 * @param op the x87 opcode to patch in
354 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
356 ir_mode *mode = get_irn_mode(n);
361 if (mode == mode_T) {
362 /* patch all Proj's */
363 foreach_out_edge(n, edge) {
364 ir_node *proj = get_edge_src_irn(edge);
366 mode = get_irn_mode(proj);
367 if (mode_is_float(mode)) {
369 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
373 } else if (mode_is_float(mode))
374 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
379 * Returns the first Proj of a mode_T node having a given mode.
381 * @param n the mode_T node
382 * @param m the desired mode of the Proj
383 * @return The first Proj of mode @p m found.
385 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
387 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
389 foreach_out_edge(n, edge) {
390 ir_node *proj = get_edge_src_irn(edge);
391 if (get_irn_mode(proj) == m)
395 panic("Proj not found");
399 * Wrap the arch_* function here so we can check for errors.
401 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
403 const arch_register_t *res = arch_get_irn_register(irn);
405 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
409 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
412 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
414 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
418 static inline const arch_register_t *get_st_reg(int index)
420 return &ia32_registers[REG_ST0 + index];
424 * Create a fxch node before another node.
426 * @param state the x87 state
427 * @param n the node after the fxch
428 * @param pos exchange st(pos) with st(0)
432 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
434 x87_fxch(state, pos);
436 ir_node *const block = get_nodes_block(n);
437 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
438 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
439 attr->x87[0] = get_st_reg(pos);
440 attr->x87[2] = get_st_reg(0);
444 sched_add_before(n, fxch);
445 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
449 /* -------------- x87 perm --------------- */
452 * Calculate the necessary permutations to reach dst_state.
454 * These permutations are done with fxch instructions and placed
455 * at the end of the block.
457 * Note that critical edges are removed here, so we need only
458 * a shuffle if the current block has only one successor.
460 * @param block the current block
461 * @param state the current x87 stack state, might be modified
462 * @param dst_state destination state
466 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
468 int i, n_cycles, k, ri;
469 unsigned cycles[4], all_mask;
470 char cycle_idx[4][8];
472 assert(state->depth == dst_state->depth);
474 /* Some mathematics here:
475 * If we have a cycle of length n that includes the tos,
476 * we need n-1 exchange operations.
477 * We can always add the tos and restore it, so we need
478 * n+1 exchange operations for a cycle not containing the tos.
479 * So, the maximum of needed operations is for a cycle of 7
480 * not including the tos == 8.
481 * This is the same number of ops we would need for using stores,
482 * so exchange is cheaper (we save the loads).
483 * On the other hand, we might need an additional exchange
484 * in the next block to bring one operand on top, so the
485 * number of ops in the first case is identical.
486 * Further, no more than 4 cycles can exists (4 x 2). */
487 all_mask = (1 << (state->depth)) - 1;
489 for (n_cycles = 0; all_mask; ++n_cycles) {
490 int src_idx, dst_idx;
492 /* find the first free slot */
493 for (i = 0; i < state->depth; ++i) {
494 if (all_mask & (1 << i)) {
495 all_mask &= ~(1 << i);
497 /* check if there are differences here */
498 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
504 /* no more cycles found */
509 cycles[n_cycles] = (1 << i);
510 cycle_idx[n_cycles][k++] = i;
511 for (src_idx = i; ; src_idx = dst_idx) {
512 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
514 if ((all_mask & (1 << dst_idx)) == 0)
517 cycle_idx[n_cycles][k++] = dst_idx;
518 cycles[n_cycles] |= (1 << dst_idx);
519 all_mask &= ~(1 << dst_idx);
521 cycle_idx[n_cycles][k] = -1;
525 /* no permutation needed */
529 /* Hmm: permutation needed */
530 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
531 DEBUG_ONLY(x87_dump_stack(state);)
532 DB((dbg, LEVEL_2, " to\n"));
533 DEBUG_ONLY(x87_dump_stack(dst_state);)
537 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
538 for (ri = 0; ri < n_cycles; ++ri) {
539 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
540 for (k = 0; cycle_idx[ri][k] != -1; ++k)
541 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
542 DB((dbg, LEVEL_2, "\n"));
547 * Find the place node must be insert.
548 * We have only one successor block, so the last instruction should
551 ir_node *const before = sched_last(block);
552 assert(is_cfop(before));
554 /* now do the permutations */
555 for (ri = 0; ri < n_cycles; ++ri) {
556 if ((cycles[ri] & 1) == 0) {
557 /* this cycle does not include the tos */
558 x87_create_fxch(state, before, cycle_idx[ri][0]);
560 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
561 x87_create_fxch(state, before, cycle_idx[ri][k]);
563 if ((cycles[ri] & 1) == 0) {
564 /* this cycle does not include the tos */
565 x87_create_fxch(state, before, cycle_idx[ri][0]);
572 * Create a fpush before node n.
574 * @param state the x87 state
575 * @param n the node after the fpush
576 * @param pos push st(pos) on stack
577 * @param val the value to push
579 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, ir_node *const val)
581 arch_register_t const *const out = x87_get_irn_register(val);
582 x87_push_dbl(state, arch_register_get_index(out), val);
584 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
585 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
586 attr->x87[0] = get_st_reg(pos);
587 attr->x87[2] = get_st_reg(0);
590 sched_add_before(n, fpush);
592 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
596 * Create a fpop before node n.
598 * @param state the x87 state
599 * @param n the node after the fpop
600 * @param num pop 1 or 2 values
602 * @return the fpop node
604 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
606 ir_node *fpop = NULL;
607 ia32_x87_attr_t *attr;
612 if (ia32_cg_config.use_ffreep)
613 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
615 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
616 attr = get_ia32_x87_attr(fpop);
617 attr->x87[0] = get_st_reg(0);
618 attr->x87[1] = get_st_reg(0);
619 attr->x87[2] = get_st_reg(0);
622 sched_add_before(n, fpop);
623 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
628 /* --------------------------------- liveness ------------------------------------------ */
631 * The liveness transfer function.
632 * Updates a live set over a single step from a given node to its predecessor.
633 * Everything defined at the node is removed from the set, the uses of the node get inserted.
635 * @param irn The node at which liveness should be computed.
636 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
637 * the registers live after irn.
639 * @return The live bitset.
641 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
644 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
646 if (get_irn_mode(irn) == mode_T) {
647 foreach_out_edge(irn, edge) {
648 ir_node *proj = get_edge_src_irn(edge);
650 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
651 const arch_register_t *reg = x87_get_irn_register(proj);
652 live &= ~(1 << arch_register_get_index(reg));
655 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
656 const arch_register_t *reg = x87_get_irn_register(irn);
657 live &= ~(1 << arch_register_get_index(reg));
660 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
661 ir_node *op = get_irn_n(irn, i);
663 if (mode_is_float(get_irn_mode(op)) &&
664 arch_irn_consider_in_reg_alloc(cls, op)) {
665 const arch_register_t *reg = x87_get_irn_register(op);
666 live |= 1 << arch_register_get_index(reg);
673 * Put all live virtual registers at the end of a block into a bitset.
675 * @param sim the simulator handle
676 * @param bl the block
678 * @return The live bitset at the end of this block
680 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
682 vfp_liveness live = 0;
683 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
684 const be_lv_t *lv = sim->lv;
686 be_lv_foreach(lv, block, be_lv_state_end, node) {
687 const arch_register_t *reg;
688 if (!arch_irn_consider_in_reg_alloc(cls, node))
691 reg = x87_get_irn_register(node);
692 live |= 1 << arch_register_get_index(reg);
698 /** get the register mask from an arch_register */
699 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
702 * Return a bitset of argument registers which are live at the end of a node.
704 * @param sim the simulator handle
705 * @param pos the node
706 * @param kill kill mask for the output registers
708 * @return The live bitset.
710 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
712 unsigned idx = get_irn_idx(pos);
714 assert(idx < sim->n_idx);
715 return sim->live[idx] & ~kill;
719 * Calculate the liveness for a whole block and cache it.
721 * @param sim the simulator handle
722 * @param block the block
724 static void update_liveness(x87_simulator *sim, ir_node *block)
726 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
729 /* now iterate through the block backward and cache the results */
730 sched_foreach_reverse(block, irn) {
731 /* stop at the first Phi: this produces the live-in */
735 idx = get_irn_idx(irn);
736 sim->live[idx] = live;
738 live = vfp_liveness_transfer(irn, live);
740 idx = get_irn_idx(block);
741 sim->live[idx] = live;
745 * Returns true if a register is live in a set.
747 * @param reg_idx the vfp register index
748 * @param live a live bitset
750 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
754 * Dump liveness info.
756 * @param live the live bitset
758 static void vfp_dump_live(vfp_liveness live)
762 DB((dbg, LEVEL_2, "Live after: "));
763 for (i = 0; i < 8; ++i) {
764 if (live & (1 << i)) {
765 DB((dbg, LEVEL_2, "vf%d ", i));
768 DB((dbg, LEVEL_2, "\n"));
770 #endif /* DEBUG_libfirm */
772 /* --------------------------------- simulators ---------------------------------------- */
775 * Simulate a virtual binop.
777 * @param state the x87 state
778 * @param n the node that should be simulated (and patched)
779 * @param tmpl the template containing the 4 possible x87 opcodes
781 * @return NO_NODE_ADDED
783 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
785 int op2_idx = 0, op1_idx;
786 int out_idx, do_pop = 0;
787 ia32_x87_attr_t *attr;
789 ir_node *patched_insn;
791 x87_simulator *sim = state->sim;
792 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
793 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
794 const arch_register_t *op1_reg = x87_get_irn_register(op1);
795 const arch_register_t *op2_reg = x87_get_irn_register(op2);
796 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
797 int reg_index_1 = arch_register_get_index(op1_reg);
798 int reg_index_2 = arch_register_get_index(op2_reg);
799 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
803 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
804 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
805 arch_register_get_name(out)));
806 DEBUG_ONLY(vfp_dump_live(live);)
807 DB((dbg, LEVEL_1, "Stack before: "));
808 DEBUG_ONLY(x87_dump_stack(state);)
810 op1_idx = x87_on_stack(state, reg_index_1);
811 assert(op1_idx >= 0);
812 op1_live_after = is_vfp_live(reg_index_1, live);
814 attr = get_ia32_x87_attr(n);
815 permuted = attr->attr.data.ins_permuted;
817 if (reg_index_2 != REG_VFP_VFP_NOREG) {
820 /* second operand is a vfp register */
821 op2_idx = x87_on_stack(state, reg_index_2);
822 assert(op2_idx >= 0);
823 op2_live_after = is_vfp_live(reg_index_2, live);
825 if (op2_live_after) {
826 /* Second operand is live. */
828 if (op1_live_after) {
829 /* Both operands are live: push the first one.
830 This works even for op1 == op2. */
831 x87_create_fpush(state, n, op1_idx, op2);
832 /* now do fxxx (tos=tos X op) */
836 dst = tmpl->normal_op;
838 /* Second live, first operand is dead here, bring it to tos. */
840 x87_create_fxch(state, n, op1_idx);
845 /* now do fxxx (tos=tos X op) */
847 dst = tmpl->normal_op;
850 /* Second operand is dead. */
851 if (op1_live_after) {
852 /* First operand is live: bring second to tos. */
854 x87_create_fxch(state, n, op2_idx);
859 /* now do fxxxr (tos = op X tos) */
861 dst = tmpl->reverse_op;
863 /* Both operands are dead here, pop them from the stack. */
866 /* Both are identically and on tos, no pop needed. */
867 /* here fxxx (tos = tos X tos) */
868 dst = tmpl->normal_op;
871 /* now do fxxxp (op = op X tos, pop) */
872 dst = tmpl->normal_pop_op;
876 } else if (op1_idx == 0) {
877 assert(op1_idx != op2_idx);
878 /* now do fxxxrp (op = tos X op, pop) */
879 dst = tmpl->reverse_pop_op;
883 /* Bring the second on top. */
884 x87_create_fxch(state, n, op2_idx);
885 if (op1_idx == op2_idx) {
886 /* Both are identically and on tos now, no pop needed. */
889 /* use fxxx (tos = tos X tos) */
890 dst = tmpl->normal_op;
893 /* op2 is on tos now */
895 /* use fxxxp (op = op X tos, pop) */
896 dst = tmpl->normal_pop_op;
904 /* second operand is an address mode */
905 if (op1_live_after) {
906 /* first operand is live: push it here */
907 x87_create_fpush(state, n, op1_idx, op1);
910 /* first operand is dead: bring it to tos */
912 x87_create_fxch(state, n, op1_idx);
917 /* use fxxx (tos = tos X mem) */
918 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
922 patched_insn = x87_patch_insn(n, dst);
923 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
928 /* patch the operation */
929 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
930 if (reg_index_2 != REG_VFP_VFP_NOREG) {
931 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
933 attr->x87[2] = out = get_st_reg(out_idx);
935 if (reg_index_2 != REG_VFP_VFP_NOREG) {
936 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
937 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
938 arch_register_get_name(out)));
940 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
941 arch_register_get_name(op1_reg),
942 arch_register_get_name(out)));
945 return NO_NODE_ADDED;
949 * Simulate a virtual Unop.
951 * @param state the x87 state
952 * @param n the node that should be simulated (and patched)
953 * @param op the x87 opcode that will replace n's opcode
955 * @return NO_NODE_ADDED
957 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
959 arch_register_t const *const out = x87_get_irn_register(n);
960 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
961 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
962 DEBUG_ONLY(vfp_dump_live(live);)
964 ir_node *const op1 = get_irn_n(n, 0);
965 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
966 int const op1_reg_idx = arch_register_get_index(op1_reg);
967 int const op1_idx = x87_on_stack(state, op1_reg_idx);
968 if (is_vfp_live(op1_reg_idx, live)) {
969 /* push the operand here */
970 x87_create_fpush(state, n, op1_idx, op1);
972 /* operand is dead, bring it to tos */
974 x87_create_fxch(state, n, op1_idx);
978 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
979 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
980 attr->x87[2] = attr->x87[0] = get_st_reg(0);
981 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), attr->x87[2]->name));
983 return NO_NODE_ADDED;
987 * Simulate a virtual Load instruction.
989 * @param state the x87 state
990 * @param n the node that should be simulated (and patched)
991 * @param op the x87 opcode that will replace n's opcode
993 * @return NO_NODE_ADDED
995 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
997 const arch_register_t *out = x87_irn_get_register(n, res_pos);
998 ia32_x87_attr_t *attr;
1000 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1001 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1002 assert(out == x87_irn_get_register(n, res_pos));
1003 attr = get_ia32_x87_attr(n);
1004 attr->x87[2] = out = get_st_reg(0);
1005 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1007 return NO_NODE_ADDED;
1011 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1013 * @param store The store
1014 * @param old_val The former value
1015 * @param new_val The new value
1017 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
1019 foreach_out_edge_safe(old_val, edge) {
1020 ir_node *user = get_edge_src_irn(edge);
1021 /* if the user is scheduled after the store: rewire */
1022 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1023 set_irn_n(user, get_edge_src_pos(edge), new_val);
1029 * Simulate a virtual Store.
1031 * @param state the x87 state
1032 * @param n the node that should be simulated (and patched)
1033 * @param op the x87 store opcode
1034 * @param op_p the x87 store and pop opcode
1036 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1038 ir_node *const val = get_irn_n(n, n_ia32_vfst_val);
1039 arch_register_t const *const op2 = x87_get_irn_register(val);
1040 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1042 int insn = NO_NODE_ADDED;
1043 int const op2_reg_idx = arch_register_get_index(op2);
1044 int const op2_idx = x87_on_stack(state, op2_reg_idx);
1045 unsigned const live = vfp_live_args_after(state->sim, n, 0);
1046 int const live_after_node = is_vfp_live(op2_reg_idx, live);
1047 assert(op2_idx >= 0);
1048 if (live_after_node) {
1049 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
1050 * fist doesn't support 64bit mode, only fistp
1052 * - stack not full: push value and fstp
1053 * - stack full: fstp value and load again
1054 * Note that we cannot test on mode_E, because floats might be 80bit ... */
1055 ir_mode *const mode = get_ia32_ls_mode(n);
1056 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
1057 if (x87_get_depth(state) < N_ia32_st_REGS) {
1058 /* ok, we have a free register: push + fstp */
1059 x87_create_fpush(state, n, op2_idx, val);
1061 x87_patch_insn(n, op_p);
1063 /* stack full here: need fstp + load */
1065 x87_patch_insn(n, op_p);
1067 ir_node *const block = get_nodes_block(n);
1068 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
1069 ir_node *const vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
1071 /* copy all attributes */
1072 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1073 if (is_ia32_use_frame(n))
1074 set_ia32_use_frame(vfld);
1075 set_ia32_op_type(vfld, ia32_AddrModeS);
1076 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1077 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1078 set_ia32_ls_mode(vfld, mode);
1080 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_vfld_res);
1081 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1083 arch_set_irn_register(rproj, op2);
1085 /* reroute all former users of the store memory to the load memory */
1086 edges_reroute_except(mem, mproj, vfld);
1088 sched_add_after(n, vfld);
1089 sched_add_after(vfld, rproj);
1091 /* rewire all users, scheduled after the store, to the loaded value */
1092 collect_and_rewire_users(n, val, rproj);
1097 /* we can only store the tos to memory */
1099 x87_create_fxch(state, n, op2_idx);
1101 /* mode size 64 or smaller -> use normal fst */
1102 x87_patch_insn(n, op);
1105 /* we can only store the tos to memory */
1107 x87_create_fxch(state, n, op2_idx);
1110 x87_patch_insn(n, op_p);
1113 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
1114 attr->x87[1] = get_st_reg(0);
1115 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(attr->x87[1])));
1120 #define _GEN_BINOP(op, rev) \
1121 static int sim_##op(x87_state *state, ir_node *n) { \
1122 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1123 return sim_binop(state, n, &tmpl); \
1126 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1127 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1129 #define GEN_LOAD(op) \
1130 static int sim_##op(x87_state *state, ir_node *n) { \
1131 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1134 #define GEN_UNOP(op) \
1135 static int sim_##op(x87_state *state, ir_node *n) { \
1136 return sim_unop(state, n, op_ia32_##op); \
1139 #define GEN_STORE(op) \
1140 static int sim_##op(x87_state *state, ir_node *n) { \
1141 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1163 * Simulate a virtual fisttp.
1165 * @param state the x87 state
1166 * @param n the node that should be simulated (and patched)
1168 * @return NO_NODE_ADDED
1170 static int sim_fisttp(x87_state *state, ir_node *n)
1172 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1173 const arch_register_t *op2 = x87_get_irn_register(val);
1174 ia32_x87_attr_t *attr;
1175 int op2_reg_idx, op2_idx;
1177 op2_reg_idx = arch_register_get_index(op2);
1178 op2_idx = x87_on_stack(state, op2_reg_idx);
1179 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1180 assert(op2_idx >= 0);
1182 /* Note: although the value is still live here, it is destroyed because
1183 of the pop. The register allocator is aware of that and introduced a copy
1184 if the value must be alive. */
1186 /* we can only store the tos to memory */
1188 x87_create_fxch(state, n, op2_idx);
1191 x87_patch_insn(n, op_ia32_fisttp);
1193 attr = get_ia32_x87_attr(n);
1194 attr->x87[1] = op2 = get_st_reg(0);
1195 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1197 return NO_NODE_ADDED;
1201 * Simulate a virtual FtstFnstsw.
1203 * @param state the x87 state
1204 * @param n the node that should be simulated (and patched)
1206 * @return NO_NODE_ADDED
1208 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1210 x87_simulator *sim = state->sim;
1211 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1212 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1213 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1214 int reg_index_1 = arch_register_get_index(reg1);
1215 int op1_idx = x87_on_stack(state, reg_index_1);
1216 unsigned live = vfp_live_args_after(sim, n, 0);
1218 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1219 DEBUG_ONLY(vfp_dump_live(live);)
1220 DB((dbg, LEVEL_1, "Stack before: "));
1221 DEBUG_ONLY(x87_dump_stack(state);)
1222 assert(op1_idx >= 0);
1225 /* bring the value to tos */
1226 x87_create_fxch(state, n, op1_idx);
1230 /* patch the operation */
1231 x87_patch_insn(n, op_ia32_FtstFnstsw);
1232 reg1 = get_st_reg(op1_idx);
1233 attr->x87[0] = reg1;
1234 attr->x87[1] = NULL;
1235 attr->x87[2] = NULL;
1237 if (!is_vfp_live(reg_index_1, live))
1238 x87_create_fpop(state, sched_next(n), 1);
1240 return NO_NODE_ADDED;
1246 * @param state the x87 state
1247 * @param n the node that should be simulated (and patched)
1249 * @return NO_NODE_ADDED
1251 static int sim_Fucom(x87_state *state, ir_node *n)
1255 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1257 x87_simulator *sim = state->sim;
1258 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1259 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1260 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1261 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1262 int reg_index_1 = arch_register_get_index(op1);
1263 int reg_index_2 = arch_register_get_index(op2);
1264 unsigned live = vfp_live_args_after(sim, n, 0);
1265 bool permuted = attr->attr.data.ins_permuted;
1269 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1270 arch_register_get_name(op1), arch_register_get_name(op2)));
1271 DEBUG_ONLY(vfp_dump_live(live);)
1272 DB((dbg, LEVEL_1, "Stack before: "));
1273 DEBUG_ONLY(x87_dump_stack(state);)
1275 op1_idx = x87_on_stack(state, reg_index_1);
1276 assert(op1_idx >= 0);
1278 /* BEWARE: check for comp a,a cases, they might happen */
1279 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1280 /* second operand is a vfp register */
1281 op2_idx = x87_on_stack(state, reg_index_2);
1282 assert(op2_idx >= 0);
1284 if (is_vfp_live(reg_index_2, live)) {
1285 /* second operand is live */
1287 if (is_vfp_live(reg_index_1, live)) {
1288 /* both operands are live */
1291 /* res = tos X op */
1292 } else if (op2_idx == 0) {
1293 /* res = op X tos */
1294 permuted = !permuted;
1297 /* bring the first one to tos */
1298 x87_create_fxch(state, n, op1_idx);
1299 if (op1_idx == op2_idx) {
1301 } else if (op2_idx == 0) {
1305 /* res = tos X op */
1308 /* second live, first operand is dead here, bring it to tos.
1309 This means further, op1_idx != op2_idx. */
1310 assert(op1_idx != op2_idx);
1312 x87_create_fxch(state, n, op1_idx);
1317 /* res = tos X op, pop */
1321 /* second operand is dead */
1322 if (is_vfp_live(reg_index_1, live)) {
1323 /* first operand is live: bring second to tos.
1324 This means further, op1_idx != op2_idx. */
1325 assert(op1_idx != op2_idx);
1327 x87_create_fxch(state, n, op2_idx);
1332 /* res = op X tos, pop */
1334 permuted = !permuted;
1337 /* both operands are dead here, check first for identity. */
1338 if (op1_idx == op2_idx) {
1339 /* identically, one pop needed */
1341 x87_create_fxch(state, n, op1_idx);
1345 /* res = tos X op, pop */
1348 /* different, move them to st and st(1) and pop both.
1349 The tricky part is to get one into st(1).*/
1350 else if (op2_idx == 1) {
1351 /* good, second operand is already in the right place, move the first */
1353 /* bring the first on top */
1354 x87_create_fxch(state, n, op1_idx);
1355 assert(op2_idx != 0);
1358 /* res = tos X op, pop, pop */
1360 } else if (op1_idx == 1) {
1361 /* good, first operand is already in the right place, move the second */
1363 /* bring the first on top */
1364 x87_create_fxch(state, n, op2_idx);
1365 assert(op1_idx != 0);
1368 /* res = op X tos, pop, pop */
1369 permuted = !permuted;
1373 /* if one is already the TOS, we need two fxch */
1375 /* first one is TOS, move to st(1) */
1376 x87_create_fxch(state, n, 1);
1377 assert(op2_idx != 1);
1379 x87_create_fxch(state, n, op2_idx);
1381 /* res = op X tos, pop, pop */
1383 permuted = !permuted;
1385 } else if (op2_idx == 0) {
1386 /* second one is TOS, move to st(1) */
1387 x87_create_fxch(state, n, 1);
1388 assert(op1_idx != 1);
1390 x87_create_fxch(state, n, op1_idx);
1392 /* res = tos X op, pop, pop */
1395 /* none of them is either TOS or st(1), 3 fxch needed */
1396 x87_create_fxch(state, n, op2_idx);
1397 assert(op1_idx != 0);
1398 x87_create_fxch(state, n, 1);
1400 x87_create_fxch(state, n, op1_idx);
1402 /* res = tos X op, pop, pop */
1409 /* second operand is an address mode */
1410 if (is_vfp_live(reg_index_1, live)) {
1411 /* first operand is live: bring it to TOS */
1413 x87_create_fxch(state, n, op1_idx);
1417 /* first operand is dead: bring it to tos */
1419 x87_create_fxch(state, n, op1_idx);
1426 /* patch the operation */
1427 if (is_ia32_vFucomFnstsw(n)) {
1431 case 0: dst = op_ia32_FucomFnstsw; break;
1432 case 1: dst = op_ia32_FucompFnstsw; break;
1433 case 2: dst = op_ia32_FucomppFnstsw; break;
1434 default: panic("invalid popcount");
1437 for (i = 0; i < pops; ++i) {
1440 } else if (is_ia32_vFucomi(n)) {
1442 case 0: dst = op_ia32_Fucomi; break;
1443 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1445 dst = op_ia32_Fucompi;
1447 x87_create_fpop(state, sched_next(n), 1);
1449 default: panic("invalid popcount");
1452 panic("invalid operation %+F", n);
1455 x87_patch_insn(n, dst);
1462 op1 = get_st_reg(op1_idx);
1465 op2 = get_st_reg(op2_idx);
1468 attr->x87[2] = NULL;
1469 attr->attr.data.ins_permuted = permuted;
1472 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1473 arch_register_get_name(op1), arch_register_get_name(op2)));
1475 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1476 arch_register_get_name(op1)));
1479 return NO_NODE_ADDED;
1485 * @param state the x87 state
1486 * @param n the node that should be simulated (and patched)
1488 * @return NO_NODE_ADDED
1490 static int sim_Keep(x87_state *state, ir_node *node)
1493 const arch_register_t *op_reg;
1499 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1501 arity = get_irn_arity(node);
1502 for (i = 0; i < arity; ++i) {
1503 op = get_irn_n(node, i);
1504 op_reg = arch_get_irn_register(op);
1505 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1508 reg_id = arch_register_get_index(op_reg);
1509 live = vfp_live_args_after(state->sim, node, 0);
1511 op_stack_idx = x87_on_stack(state, reg_id);
1512 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1513 x87_create_fpop(state, sched_next(node), 1);
1516 DB((dbg, LEVEL_1, "Stack after: "));
1517 DEBUG_ONLY(x87_dump_stack(state);)
1519 return NO_NODE_ADDED;
1523 * Keep the given node alive by adding a be_Keep.
1525 * @param node the node to kept alive
1527 static void keep_float_node_alive(ir_node *node)
1529 ir_node *block = get_nodes_block(node);
1530 ir_node *keep = be_new_Keep(block, 1, &node);
1532 assert(sched_is_scheduled(node));
1533 sched_add_after(node, keep);
1537 * Create a copy of a node. Recreate the node if it's a constant.
1539 * @param state the x87 state
1540 * @param n the node to be copied
1542 * @return the copy of n
1544 static ir_node *create_Copy(x87_state *state, ir_node *n)
1546 dbg_info *n_dbg = get_irn_dbg_info(n);
1547 ir_mode *mode = get_irn_mode(n);
1548 ir_node *block = get_nodes_block(n);
1549 ir_node *pred = get_irn_n(n, 0);
1550 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1552 const arch_register_t *out;
1553 const arch_register_t *op1;
1554 ia32_x87_attr_t *attr;
1556 /* Do not copy constants, recreate them. */
1557 switch (get_ia32_irn_opcode(pred)) {
1559 cnstr = new_bd_ia32_fldz;
1562 cnstr = new_bd_ia32_fld1;
1564 case iro_ia32_fldpi:
1565 cnstr = new_bd_ia32_fldpi;
1567 case iro_ia32_fldl2e:
1568 cnstr = new_bd_ia32_fldl2e;
1570 case iro_ia32_fldl2t:
1571 cnstr = new_bd_ia32_fldl2t;
1573 case iro_ia32_fldlg2:
1574 cnstr = new_bd_ia32_fldlg2;
1576 case iro_ia32_fldln2:
1577 cnstr = new_bd_ia32_fldln2;
1583 out = x87_get_irn_register(n);
1584 op1 = x87_get_irn_register(pred);
1586 if (cnstr != NULL) {
1587 /* copy a constant */
1588 res = (*cnstr)(n_dbg, block, mode);
1590 x87_push(state, arch_register_get_index(out), res);
1592 attr = get_ia32_x87_attr(res);
1593 attr->x87[2] = get_st_reg(0);
1595 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1597 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1599 x87_push(state, arch_register_get_index(out), res);
1601 attr = get_ia32_x87_attr(res);
1602 attr->x87[0] = get_st_reg(op1_idx);
1603 attr->x87[2] = get_st_reg(0);
1605 arch_set_irn_register(res, out);
1611 * Simulate a be_Copy.
1613 * @param state the x87 state
1614 * @param n the node that should be simulated (and patched)
1616 * @return NO_NODE_ADDED
1618 static int sim_Copy(x87_state *state, ir_node *n)
1620 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1621 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1622 return NO_NODE_ADDED;
1624 ir_node *const pred = be_get_Copy_op(n);
1625 arch_register_t const *const op1 = x87_get_irn_register(pred);
1626 arch_register_t const *const out = x87_get_irn_register(n);
1627 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
1629 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1630 arch_register_get_name(op1), arch_register_get_name(out)));
1631 DEBUG_ONLY(vfp_dump_live(live);)
1633 if (is_vfp_live(arch_register_get_index(op1), live)) {
1634 /* Operand is still live, a real copy. We need here an fpush that can
1635 hold a a register, so use the fpushCopy or recreate constants */
1636 ir_node *const node = create_Copy(state, n);
1638 /* We have to make sure the old value doesn't go dead (which can happen
1639 * when we recreate constants). As the simulator expected that value in
1640 * the pred blocks. This is unfortunate as removing it would save us 1
1641 * instruction, but we would have to rerun all the simulation to get
1644 ir_node *const next = sched_next(n);
1647 sched_add_before(next, node);
1649 if (get_irn_n_edges(pred) == 0) {
1650 keep_float_node_alive(pred);
1653 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1655 int const op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1656 int const out_idx = x87_on_stack(state, arch_register_get_index(out));
1657 if (out_idx >= 0 && out_idx != op1_idx) {
1658 /* Matze: out already on stack? how can this happen? */
1659 panic("invalid stack state");
1662 /* op1 must be killed and placed where out is */
1664 ia32_x87_attr_t *attr;
1665 /* best case, simple remove and rename */
1666 x87_patch_insn(n, op_ia32_Pop);
1667 attr = get_ia32_x87_attr(n);
1668 attr->x87[0] = op1 = get_st_reg(0);
1671 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1673 ia32_x87_attr_t *attr;
1674 /* move op1 to tos, store and pop it */
1676 x87_create_fxch(state, n, op1_idx);
1679 x87_patch_insn(n, op_ia32_Pop);
1680 attr = get_ia32_x87_attr(n);
1681 attr->x87[0] = op1 = get_st_reg(out_idx);
1684 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1686 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1689 /* just a virtual copy */
1690 x87_set_st(state, arch_register_get_index(out), pred, op1_idx);
1691 /* don't remove the node to keep the verifier quiet :),
1692 the emitter won't emit any code for the node */
1695 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1700 return NO_NODE_ADDED;
1704 * Returns the vf0 result Proj of a Call.
1706 * @para call the Call node
1708 static ir_node *get_call_result_proj(ir_node *call)
1710 /* search the result proj */
1711 foreach_out_edge(call, edge) {
1712 ir_node *proj = get_edge_src_irn(edge);
1713 long pn = get_Proj_proj(proj);
1715 if (pn == pn_ia32_Call_vf0)
1719 panic("result Proj missing");
1722 static int sim_Asm(x87_state *const state, ir_node *const n)
1726 for (size_t i = get_irn_arity(n); i-- != 0;) {
1727 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1728 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1729 panic("cannot handle %+F with x87 constraints", n);
1732 for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
1733 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1734 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1735 panic("cannot handle %+F with x87 constraints", n);
1738 return NO_NODE_ADDED;
1742 * Simulate a ia32_Call.
1744 * @param state the x87 state
1745 * @param n the node that should be simulated (and patched)
1747 * @return NO_NODE_ADDED
1749 static int sim_Call(x87_state *state, ir_node *n)
1751 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1753 /* at the begin of a call the x87 state should be empty */
1754 assert(state->depth == 0 && "stack not empty before call");
1756 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1757 if (get_method_n_ress(call_tp) != 0) {
1758 /* If the called function returns a float, it is returned in st(0).
1759 * This even happens if the return value is NOT used.
1760 * Moreover, only one return result is supported. */
1761 ir_type *const res_type = get_method_res_type(call_tp, 0);
1762 ir_mode *const mode = get_type_mode(res_type);
1763 if (mode && mode_is_float(mode)) {
1764 ir_node *const resproj = get_call_result_proj(n);
1765 arch_register_t const *const reg = x87_get_irn_register(resproj);
1766 x87_push(state, arch_register_get_index(reg), resproj);
1769 DB((dbg, LEVEL_1, "Stack after: "));
1770 DEBUG_ONLY(x87_dump_stack(state);)
1772 return NO_NODE_ADDED;
1776 * Simulate a be_Return.
1778 * @param state the x87 state
1779 * @param n the node that should be simulated (and patched)
1781 * @return NO_NODE_ADDED
1783 static int sim_Return(x87_state *state, ir_node *n)
1785 #ifdef DEBUG_libfirm
1786 /* only floating point return values must reside on stack */
1787 int n_float_res = 0;
1788 int const n_res = be_Return_get_n_rets(n);
1789 for (int i = 0; i < n_res; ++i) {
1790 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1791 if (mode_is_float(get_irn_mode(res)))
1794 assert(x87_get_depth(state) == n_float_res);
1797 /* pop them virtually */
1799 return NO_NODE_ADDED;
1803 * Simulate a be_Perm.
1805 * @param state the x87 state
1806 * @param irn the node that should be simulated (and patched)
1808 * @return NO_NODE_ADDED
1810 static int sim_Perm(x87_state *state, ir_node *irn)
1813 ir_node *pred = get_irn_n(irn, 0);
1816 /* handle only floating point Perms */
1817 if (! mode_is_float(get_irn_mode(pred)))
1818 return NO_NODE_ADDED;
1820 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1822 /* Perm is a pure virtual instruction on x87.
1823 All inputs must be on the FPU stack and are pairwise
1824 different from each other.
1825 So, all we need to do is to permutate the stack state. */
1826 n = get_irn_arity(irn);
1827 NEW_ARR_A(int, stack_pos, n);
1829 /* collect old stack positions */
1830 for (i = 0; i < n; ++i) {
1831 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1832 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1834 assert(idx >= 0 && "Perm argument not on x87 stack");
1838 /* now do the permutation */
1839 foreach_out_edge(irn, edge) {
1840 ir_node *proj = get_edge_src_irn(edge);
1841 const arch_register_t *out = x87_get_irn_register(proj);
1842 long num = get_Proj_proj(proj);
1844 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1845 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1847 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1849 return NO_NODE_ADDED;
1853 * Kill any dead registers at block start by popping them from the stack.
1855 * @param sim the simulator handle
1856 * @param block the current block
1857 * @param state the x87 state at the begin of the block
1859 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1861 ir_node *first_insn = sched_first(block);
1862 ir_node *keep = NULL;
1863 unsigned live = vfp_live_args_after(sim, block, 0);
1865 int i, depth, num_pop;
1868 depth = x87_get_depth(state);
1869 for (i = depth - 1; i >= 0; --i) {
1870 int reg = x87_get_st_reg(state, i);
1872 if (! is_vfp_live(reg, live))
1873 kill_mask |= (1 << i);
1877 DB((dbg, LEVEL_1, "Killing deads:\n"));
1878 DEBUG_ONLY(vfp_dump_live(live);)
1879 DEBUG_ONLY(x87_dump_stack(state);)
1881 if (kill_mask != 0 && live == 0) {
1882 /* special case: kill all registers */
1883 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1884 if (ia32_cg_config.use_femms) {
1885 /* use FEMMS on AMD processors to clear all */
1886 keep = new_bd_ia32_femms(NULL, block);
1888 /* use EMMS to clear all */
1889 keep = new_bd_ia32_emms(NULL, block);
1891 sched_add_before(first_insn, keep);
1897 /* now kill registers */
1899 /* we can only kill from TOS, so bring them up */
1900 if (! (kill_mask & 1)) {
1901 /* search from behind, because we can to a double-pop */
1902 for (i = depth - 1; i >= 0; --i) {
1903 if (kill_mask & (1 << i)) {
1904 kill_mask &= ~(1 << i);
1911 x87_set_st(state, -1, keep, i);
1912 x87_create_fxch(state, first_insn, i);
1915 if ((kill_mask & 3) == 3) {
1916 /* we can do a double-pop */
1920 /* only a single pop */
1925 kill_mask >>= num_pop;
1926 keep = x87_create_fpop(state, first_insn, num_pop);
1933 * Run a simulation and fix all virtual instructions for a block.
1935 * @param sim the simulator handle
1936 * @param block the current block
1938 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1941 blk_state *bl_state = x87_get_bl_state(sim, block);
1942 x87_state *state = bl_state->begin;
1943 ir_node *start_block;
1945 assert(state != NULL);
1946 /* already processed? */
1947 if (bl_state->end != NULL)
1950 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1951 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1952 DEBUG_ONLY(x87_dump_stack(state);)
1954 /* create a new state, will be changed */
1955 state = x87_clone_state(sim, state);
1956 /* at block begin, kill all dead registers */
1957 x87_kill_deads(sim, block, state);
1959 /* beware, n might change */
1960 for (n = sched_first(block); !sched_is_end(n); n = next) {
1963 ir_op *op = get_irn_op(n);
1966 * get the next node to be simulated here.
1967 * n might be completely removed from the schedule-
1969 next = sched_next(n);
1970 if (op->ops.generic != NULL) {
1971 func = (sim_func)op->ops.generic;
1974 node_inserted = (*func)(state, n);
1977 * sim_func might have added an additional node after n,
1978 * so update next node
1979 * beware: n must not be changed by sim_func
1980 * (i.e. removed from schedule) in this case
1982 if (node_inserted != NO_NODE_ADDED)
1983 next = sched_next(n);
1987 start_block = get_irg_start_block(get_irn_irg(block));
1989 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1991 /* check if the state must be shuffled */
1992 foreach_block_succ(block, edge) {
1993 ir_node *succ = get_edge_src_irn(edge);
1994 blk_state *succ_state;
1996 if (succ == start_block)
1999 succ_state = x87_get_bl_state(sim, succ);
2001 if (succ_state->begin == NULL) {
2002 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2003 DEBUG_ONLY(x87_dump_stack(state);)
2004 succ_state->begin = state;
2006 waitq_put(sim->worklist, succ);
2008 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2009 /* There is already a begin state for the successor, bad.
2010 Do the necessary permutations.
2011 Note that critical edges are removed, so this is always possible:
2012 If the successor has more than one possible input, then it must
2015 x87_shuffle(block, state, succ_state->begin);
2018 bl_state->end = state;
2022 * Register a simulator function.
2024 * @param op the opcode to simulate
2025 * @param func the simulator function for the opcode
2027 static void register_sim(ir_op *op, sim_func func)
2029 assert(op->ops.generic == NULL);
2030 op->ops.generic = (op_func) func;
2034 * Create a new x87 simulator.
2036 * @param sim a simulator handle, will be initialized
2037 * @param irg the current graph
2039 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
2041 obstack_init(&sim->obst);
2042 sim->blk_states = pmap_create();
2043 sim->n_idx = get_irg_last_idx(irg);
2044 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
2046 DB((dbg, LEVEL_1, "--------------------------------\n"
2047 "x87 Simulator started for %+F\n", irg));
2049 /* set the generic function pointer of instruction we must simulate */
2050 ir_clear_opcodes_generic_func();
2052 register_sim(op_ia32_Asm, sim_Asm);
2053 register_sim(op_ia32_Call, sim_Call);
2054 register_sim(op_ia32_vfld, sim_fld);
2055 register_sim(op_ia32_vfild, sim_fild);
2056 register_sim(op_ia32_vfld1, sim_fld1);
2057 register_sim(op_ia32_vfldz, sim_fldz);
2058 register_sim(op_ia32_vfadd, sim_fadd);
2059 register_sim(op_ia32_vfsub, sim_fsub);
2060 register_sim(op_ia32_vfmul, sim_fmul);
2061 register_sim(op_ia32_vfdiv, sim_fdiv);
2062 register_sim(op_ia32_vfprem, sim_fprem);
2063 register_sim(op_ia32_vfabs, sim_fabs);
2064 register_sim(op_ia32_vfchs, sim_fchs);
2065 register_sim(op_ia32_vfist, sim_fist);
2066 register_sim(op_ia32_vfisttp, sim_fisttp);
2067 register_sim(op_ia32_vfst, sim_fst);
2068 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2069 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2070 register_sim(op_ia32_vFucomi, sim_Fucom);
2071 register_sim(op_be_Copy, sim_Copy);
2072 register_sim(op_be_Return, sim_Return);
2073 register_sim(op_be_Perm, sim_Perm);
2074 register_sim(op_be_Keep, sim_Keep);
2078 * Destroy a x87 simulator.
2080 * @param sim the simulator handle
2082 static void x87_destroy_simulator(x87_simulator *sim)
2084 pmap_destroy(sim->blk_states);
2085 obstack_free(&sim->obst, NULL);
2086 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2090 * Pre-block walker: calculate the liveness information for the block
2091 * and store it into the sim->live cache.
2093 static void update_liveness_walker(ir_node *block, void *data)
2095 x87_simulator *sim = (x87_simulator*)data;
2096 update_liveness(sim, block);
2100 * Run a simulation and fix all virtual instructions for a graph.
2101 * Replaces all virtual floating point instructions and registers
2104 void ia32_x87_simulate_graph(ir_graph *irg)
2106 /* TODO improve code quality (less executed fxch) by using execfreqs */
2108 ir_node *block, *start_block;
2109 blk_state *bl_state;
2112 /* create the simulator */
2113 x87_init_simulator(&sim, irg);
2115 start_block = get_irg_start_block(irg);
2116 bl_state = x87_get_bl_state(&sim, start_block);
2118 /* start with the empty state */
2120 bl_state->begin = ∅
2122 sim.worklist = new_waitq();
2123 waitq_put(sim.worklist, start_block);
2125 be_assure_live_sets(irg);
2126 sim.lv = be_get_irg_liveness(irg);
2128 /* Calculate the liveness for all nodes. We must precalculate this info,
2129 * because the simulator adds new nodes (possible before Phi nodes) which
2130 * would let a lazy calculation fail.
2131 * On the other hand we reduce the computation amount due to
2132 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2134 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2138 block = (ir_node*)waitq_get(sim.worklist);
2139 x87_simulate_block(&sim, block);
2140 } while (! waitq_empty(sim.worklist));
2143 del_waitq(sim.worklist);
2144 x87_destroy_simulator(&sim);
2147 /* Initializes the x87 simulator. */
2148 void ia32_init_x87(void)
2150 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");