2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1))
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An exchange template.
65 * Note that our virtual functions have the same inputs
66 * and attributes as the real ones, so we can simple exchange
68 * Further, x87 supports inverse instructions, so we can handle them.
70 typedef struct exchange_tmpl {
71 ir_op *normal_op; /**< the normal one */
72 ir_op *reverse_op; /**< the reverse one if exists */
73 ir_op *normal_pop_op; /**< the normal one with tos pop */
74 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
78 * An entry on the simulated x87 stack.
80 typedef struct st_entry {
81 int reg_idx; /**< the virtual register index of this stack value */
82 ir_node *node; /**< the node that produced this value */
88 typedef struct x87_state {
89 st_entry st[N_ia32_st_REGS]; /**< the register stack */
90 int depth; /**< the current stack depth */
91 int tos; /**< position of the tos */
92 x87_simulator *sim; /**< The simulator. */
95 /** An empty state, used for blocks without fp instructions. */
96 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
97 static x87_state *empty = (x87_state *)&_empty;
100 * Return values of the instruction simulator functions.
103 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
104 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
105 in the schedule AFTER the current node. */
109 * The type of an instruction simulator function.
111 * @param state the x87 state
112 * @param n the node to be simulated
114 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
116 * NO_NODE_ADDED otherwise
118 typedef int (*sim_func)(x87_state *state, ir_node *n);
121 * A block state: Every block has a x87 state at the beginning and at the end.
123 typedef struct blk_state {
124 x87_state *begin; /**< state at the begin or NULL if not assigned */
125 x87_state *end; /**< state at the end or NULL if not assigned */
128 /** liveness bitset for vfp registers. */
129 typedef unsigned char vfp_liveness;
134 struct x87_simulator {
135 struct obstack obst; /**< An obstack for fast allocating. */
136 pmap *blk_states; /**< Map blocks to states. */
137 be_lv_t *lv; /**< intrablock liveness. */
138 vfp_liveness *live; /**< Liveness information. */
139 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
140 waitq *worklist; /**< Worklist of blocks that must be processed. */
141 ia32_isa_t *isa; /**< the ISA object */
145 * Returns the current stack depth.
147 * @param state the x87 state
149 * @return the x87 stack depth
151 static int x87_get_depth(const x87_state *state)
157 * Return the virtual register index at st(pos).
159 * @param state the x87 state
160 * @param pos a stack position
162 * @return the vfp register index that produced the value at st(pos)
164 static int x87_get_st_reg(const x87_state *state, int pos)
166 assert(pos < state->depth);
167 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
172 * Return the node at st(pos).
174 * @param state the x87 state
175 * @param pos a stack position
177 * @return the IR node that produced the value at st(pos)
179 static ir_node *x87_get_st_node(const x87_state *state, int pos)
181 assert(pos < state->depth);
182 return state->st[MASK_TOS(state->tos + pos)].node;
186 * Dump the stack for debugging.
188 * @param state the x87 state
190 static void x87_dump_stack(const x87_state *state)
194 for (i = state->depth - 1; i >= 0; --i) {
195 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
196 x87_get_st_node(state, i)));
198 DB((dbg, LEVEL_2, "<-- TOS\n"));
200 #endif /* DEBUG_libfirm */
203 * Set a virtual register to st(pos).
205 * @param state the x87 state
206 * @param reg_idx the vfp register index that should be set
207 * @param node the IR node that produces the value of the vfp register
208 * @param pos the stack position where the new value should be entered
210 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
212 assert(0 < state->depth);
213 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
214 state->st[MASK_TOS(state->tos + pos)].node = node;
216 DB((dbg, LEVEL_2, "After SET_REG: "));
217 DEBUG_ONLY(x87_dump_stack(state);)
221 * Set the tos virtual register.
223 * @param state the x87 state
224 * @param reg_idx the vfp register index that should be set
225 * @param node the IR node that produces the value of the vfp register
227 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
229 x87_set_st(state, reg_idx, node, 0);
233 * Swap st(0) with st(pos).
235 * @param state the x87 state
236 * @param pos the stack position to change the tos with
238 static void x87_fxch(x87_state *state, int pos)
241 assert(pos < state->depth);
243 entry = state->st[MASK_TOS(state->tos + pos)];
244 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
245 state->st[MASK_TOS(state->tos)] = entry;
247 DB((dbg, LEVEL_2, "After FXCH: "));
248 DEBUG_ONLY(x87_dump_stack(state);)
252 * Convert a virtual register to the stack index.
254 * @param state the x87 state
255 * @param reg_idx the register vfp index
257 * @return the stack position where the register is stacked
258 * or -1 if the virtual register was not found
260 static int x87_on_stack(const x87_state *state, int reg_idx)
262 int i, tos = state->tos;
264 for (i = 0; i < state->depth; ++i)
265 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
271 * Push a virtual Register onto the stack, double pushed allowed.
273 * @param state the x87 state
274 * @param reg_idx the register vfp index
275 * @param node the node that produces the value of the vfp register
277 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
279 assert(state->depth < N_ia32_st_REGS && "stack overrun");
282 state->tos = MASK_TOS(state->tos - 1);
283 state->st[state->tos].reg_idx = reg_idx;
284 state->st[state->tos].node = node;
286 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
290 * Push a virtual Register onto the stack, double pushes are NOT allowed.
292 * @param state the x87 state
293 * @param reg_idx the register vfp index
294 * @param node the node that produces the value of the vfp register
295 * @param dbl_push if != 0 double pushes are allowed
297 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
299 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
301 x87_push_dbl(state, reg_idx, node);
305 * Pop a virtual Register from the stack.
307 * @param state the x87 state
309 static void x87_pop(x87_state *state)
311 assert(state->depth > 0 && "stack underrun");
314 state->tos = MASK_TOS(state->tos + 1);
316 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
320 * Empty the fpu stack
322 * @param state the x87 state
324 static void x87_emms(x87_state *state)
331 * Returns the block state of a block.
333 * @param sim the x87 simulator handle
334 * @param block the current block
336 * @return the block state
338 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
340 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
343 res = OALLOC(&sim->obst, blk_state);
347 pmap_insert(sim->blk_states, block, res);
354 * Creates a new x87 state.
356 * @param sim the x87 simulator handle
358 * @return a new x87 state
360 static x87_state *x87_alloc_state(x87_simulator *sim)
362 x87_state *res = OALLOC(&sim->obst, x87_state);
371 * @param sim the x87 simulator handle
372 * @param src the x87 state that will be cloned
374 * @return a cloned copy of the src state
376 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
378 x87_state *res = x87_alloc_state(sim);
385 * Patch a virtual instruction into a x87 one and return
386 * the node representing the result value.
388 * @param n the IR node to patch
389 * @param op the x87 opcode to patch in
391 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
393 ir_mode *mode = get_irn_mode(n);
398 if (mode == mode_T) {
399 /* patch all Proj's */
400 foreach_out_edge(n, edge) {
401 ir_node *proj = get_edge_src_irn(edge);
403 mode = get_irn_mode(proj);
404 if (mode_is_float(mode)) {
406 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
410 } else if (mode_is_float(mode))
411 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
416 * Returns the first Proj of a mode_T node having a given mode.
418 * @param n the mode_T node
419 * @param m the desired mode of the Proj
420 * @return The first Proj of mode @p m found or NULL.
422 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
424 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
426 foreach_out_edge(n, edge) {
427 ir_node *proj = get_edge_src_irn(edge);
428 if (get_irn_mode(proj) == m)
436 * Wrap the arch_* function here so we can check for errors.
438 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
440 const arch_register_t *res = arch_get_irn_register(irn);
442 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
446 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
449 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
451 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
455 static inline const arch_register_t *get_st_reg(int index)
457 return &ia32_registers[REG_ST0 + index];
460 /* -------------- x87 perm --------------- */
463 * Creates a fxch for shuffle.
465 * @param state the x87 state
466 * @param pos parameter for fxch
467 * @param block the block were fxch is inserted
469 * Creates a new fxch node and reroute the user of the old node
472 * @return the fxch node
474 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
477 ia32_x87_attr_t *attr;
479 fxch = new_bd_ia32_fxch(NULL, block);
480 attr = get_ia32_x87_attr(fxch);
481 attr->x87[0] = get_st_reg(pos);
482 attr->x87[2] = get_st_reg(0);
486 x87_fxch(state, pos);
491 * Calculate the necessary permutations to reach dst_state.
493 * These permutations are done with fxch instructions and placed
494 * at the end of the block.
496 * Note that critical edges are removed here, so we need only
497 * a shuffle if the current block has only one successor.
499 * @param sim the simulator handle
500 * @param block the current block
501 * @param state the current x87 stack state, might be modified
502 * @param dst_block the destination block
503 * @param dst_state destination state
507 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
508 x87_state *state, ir_node *dst_block,
509 const x87_state *dst_state)
511 int i, n_cycles, k, ri;
512 unsigned cycles[4], all_mask;
513 char cycle_idx[4][8];
514 ir_node *fxch, *before, *after;
518 assert(state->depth == dst_state->depth);
520 /* Some mathematics here:
521 If we have a cycle of length n that includes the tos,
522 we need n-1 exchange operations.
523 We can always add the tos and restore it, so we need
524 n+1 exchange operations for a cycle not containing the tos.
525 So, the maximum of needed operations is for a cycle of 7
526 not including the tos == 8.
527 This is the same number of ops we would need for using stores,
528 so exchange is cheaper (we save the loads).
529 On the other hand, we might need an additional exchange
530 in the next block to bring one operand on top, so the
531 number of ops in the first case is identical.
532 Further, no more than 4 cycles can exists (4 x 2).
534 all_mask = (1 << (state->depth)) - 1;
536 for (n_cycles = 0; all_mask; ++n_cycles) {
537 int src_idx, dst_idx;
539 /* find the first free slot */
540 for (i = 0; i < state->depth; ++i) {
541 if (all_mask & (1 << i)) {
542 all_mask &= ~(1 << i);
544 /* check if there are differences here */
545 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
551 /* no more cycles found */
556 cycles[n_cycles] = (1 << i);
557 cycle_idx[n_cycles][k++] = i;
558 for (src_idx = i; ; src_idx = dst_idx) {
559 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
561 if ((all_mask & (1 << dst_idx)) == 0)
564 cycle_idx[n_cycles][k++] = dst_idx;
565 cycles[n_cycles] |= (1 << dst_idx);
566 all_mask &= ~(1 << dst_idx);
568 cycle_idx[n_cycles][k] = -1;
572 /* no permutation needed */
576 /* Hmm: permutation needed */
577 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
578 DEBUG_ONLY(x87_dump_stack(state);)
579 DB((dbg, LEVEL_2, " to\n"));
580 DEBUG_ONLY(x87_dump_stack(dst_state);)
584 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
585 for (ri = 0; ri < n_cycles; ++ri) {
586 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
587 for (k = 0; cycle_idx[ri][k] != -1; ++k)
588 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
589 DB((dbg, LEVEL_2, "\n"));
596 * Find the place node must be insert.
597 * We have only one successor block, so the last instruction should
600 before = sched_last(block);
601 assert(is_cfop(before));
603 /* now do the permutations */
604 for (ri = 0; ri < n_cycles; ++ri) {
605 if ((cycles[ri] & 1) == 0) {
606 /* this cycle does not include the tos */
607 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
609 sched_add_after(after, fxch);
611 sched_add_before(before, fxch);
614 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
615 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
617 sched_add_after(after, fxch);
619 sched_add_before(before, fxch);
622 if ((cycles[ri] & 1) == 0) {
623 /* this cycle does not include the tos */
624 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
625 sched_add_after(after, fxch);
632 * Create a fxch node before another node.
634 * @param state the x87 state
635 * @param n the node after the fxch
636 * @param pos exchange st(pos) with st(0)
640 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
643 ia32_x87_attr_t *attr;
644 ir_node *block = get_nodes_block(n);
646 x87_fxch(state, pos);
648 fxch = new_bd_ia32_fxch(NULL, block);
649 attr = get_ia32_x87_attr(fxch);
650 attr->x87[0] = get_st_reg(pos);
651 attr->x87[2] = get_st_reg(0);
655 sched_add_before(n, fxch);
656 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
661 * Create a fpush before node n.
663 * @param state the x87 state
664 * @param n the node after the fpush
665 * @param pos push st(pos) on stack
666 * @param op_idx replace input op_idx of n with the fpush result
668 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
670 ir_node *fpush, *pred = get_irn_n(n, op_idx);
671 ia32_x87_attr_t *attr;
672 const arch_register_t *out = x87_get_irn_register(pred);
674 x87_push_dbl(state, arch_register_get_index(out), pred);
676 fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
677 attr = get_ia32_x87_attr(fpush);
678 attr->x87[0] = get_st_reg(pos);
679 attr->x87[2] = get_st_reg(0);
682 sched_add_before(n, fpush);
684 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
688 * Create a fpop before node n.
690 * @param state the x87 state
691 * @param n the node after the fpop
692 * @param num pop 1 or 2 values
694 * @return the fpop node
696 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
698 ir_node *fpop = NULL;
699 ia32_x87_attr_t *attr;
704 if (ia32_cg_config.use_ffreep)
705 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
707 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
708 attr = get_ia32_x87_attr(fpop);
709 attr->x87[0] = get_st_reg(0);
710 attr->x87[1] = get_st_reg(0);
711 attr->x87[2] = get_st_reg(0);
714 sched_add_before(n, fpop);
715 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
720 /* --------------------------------- liveness ------------------------------------------ */
723 * The liveness transfer function.
724 * Updates a live set over a single step from a given node to its predecessor.
725 * Everything defined at the node is removed from the set, the uses of the node get inserted.
727 * @param irn The node at which liveness should be computed.
728 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
729 * the registers live after irn.
731 * @return The live bitset.
733 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
736 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
738 if (get_irn_mode(irn) == mode_T) {
739 foreach_out_edge(irn, edge) {
740 ir_node *proj = get_edge_src_irn(edge);
742 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
743 const arch_register_t *reg = x87_get_irn_register(proj);
744 live &= ~(1 << arch_register_get_index(reg));
747 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
748 const arch_register_t *reg = x87_get_irn_register(irn);
749 live &= ~(1 << arch_register_get_index(reg));
752 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
753 ir_node *op = get_irn_n(irn, i);
755 if (mode_is_float(get_irn_mode(op)) &&
756 arch_irn_consider_in_reg_alloc(cls, op)) {
757 const arch_register_t *reg = x87_get_irn_register(op);
758 live |= 1 << arch_register_get_index(reg);
765 * Put all live virtual registers at the end of a block into a bitset.
767 * @param sim the simulator handle
768 * @param lv the liveness information
769 * @param bl the block
771 * @return The live bitset at the end of this block
773 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
776 vfp_liveness live = 0;
777 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
778 const be_lv_t *lv = sim->lv;
780 be_lv_foreach(lv, block, be_lv_state_end, i) {
781 const arch_register_t *reg;
782 const ir_node *node = be_lv_get_irn(lv, block, i);
783 if (!arch_irn_consider_in_reg_alloc(cls, node))
786 reg = x87_get_irn_register(node);
787 live |= 1 << arch_register_get_index(reg);
793 /** get the register mask from an arch_register */
794 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
797 * Return a bitset of argument registers which are live at the end of a node.
799 * @param sim the simulator handle
800 * @param pos the node
801 * @param kill kill mask for the output registers
803 * @return The live bitset.
805 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
807 unsigned idx = get_irn_idx(pos);
809 assert(idx < sim->n_idx);
810 return sim->live[idx] & ~kill;
814 * Calculate the liveness for a whole block and cache it.
816 * @param sim the simulator handle
817 * @param lv the liveness handle
818 * @param block the block
820 static void update_liveness(x87_simulator *sim, ir_node *block)
822 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
825 /* now iterate through the block backward and cache the results */
826 sched_foreach_reverse(block, irn) {
827 /* stop at the first Phi: this produces the live-in */
831 idx = get_irn_idx(irn);
832 sim->live[idx] = live;
834 live = vfp_liveness_transfer(irn, live);
836 idx = get_irn_idx(block);
837 sim->live[idx] = live;
841 * Returns true if a register is live in a set.
843 * @param reg_idx the vfp register index
844 * @param live a live bitset
846 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
850 * Dump liveness info.
852 * @param live the live bitset
854 static void vfp_dump_live(vfp_liveness live)
858 DB((dbg, LEVEL_2, "Live after: "));
859 for (i = 0; i < 8; ++i) {
860 if (live & (1 << i)) {
861 DB((dbg, LEVEL_2, "vf%d ", i));
864 DB((dbg, LEVEL_2, "\n"));
866 #endif /* DEBUG_libfirm */
868 /* --------------------------------- simulators ---------------------------------------- */
871 * Simulate a virtual binop.
873 * @param state the x87 state
874 * @param n the node that should be simulated (and patched)
875 * @param tmpl the template containing the 4 possible x87 opcodes
877 * @return NO_NODE_ADDED
879 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
881 int op2_idx = 0, op1_idx;
882 int out_idx, do_pop = 0;
883 ia32_x87_attr_t *attr;
885 ir_node *patched_insn;
887 x87_simulator *sim = state->sim;
888 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
889 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
890 const arch_register_t *op1_reg = x87_get_irn_register(op1);
891 const arch_register_t *op2_reg = x87_get_irn_register(op2);
892 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
893 int reg_index_1 = arch_register_get_index(op1_reg);
894 int reg_index_2 = arch_register_get_index(op2_reg);
895 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
899 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
900 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
901 arch_register_get_name(out)));
902 DEBUG_ONLY(vfp_dump_live(live);)
903 DB((dbg, LEVEL_1, "Stack before: "));
904 DEBUG_ONLY(x87_dump_stack(state);)
906 op1_idx = x87_on_stack(state, reg_index_1);
907 assert(op1_idx >= 0);
908 op1_live_after = is_vfp_live(reg_index_1, live);
910 attr = get_ia32_x87_attr(n);
911 permuted = attr->attr.data.ins_permuted;
913 if (reg_index_2 != REG_VFP_VFP_NOREG) {
916 /* second operand is a vfp register */
917 op2_idx = x87_on_stack(state, reg_index_2);
918 assert(op2_idx >= 0);
919 op2_live_after = is_vfp_live(reg_index_2, live);
921 if (op2_live_after) {
922 /* Second operand is live. */
924 if (op1_live_after) {
925 /* Both operands are live: push the first one.
926 This works even for op1 == op2. */
927 x87_create_fpush(state, n, op1_idx, n_ia32_binary_right);
928 /* now do fxxx (tos=tos X op) */
932 dst = tmpl->normal_op;
934 /* Second live, first operand is dead here, bring it to tos. */
936 x87_create_fxch(state, n, op1_idx);
941 /* now do fxxx (tos=tos X op) */
943 dst = tmpl->normal_op;
946 /* Second operand is dead. */
947 if (op1_live_after) {
948 /* First operand is live: bring second to tos. */
950 x87_create_fxch(state, n, op2_idx);
955 /* now do fxxxr (tos = op X tos) */
957 dst = tmpl->reverse_op;
959 /* Both operands are dead here, pop them from the stack. */
962 /* Both are identically and on tos, no pop needed. */
963 /* here fxxx (tos = tos X tos) */
964 dst = tmpl->normal_op;
967 /* now do fxxxp (op = op X tos, pop) */
968 dst = tmpl->normal_pop_op;
972 } else if (op1_idx == 0) {
973 assert(op1_idx != op2_idx);
974 /* now do fxxxrp (op = tos X op, pop) */
975 dst = tmpl->reverse_pop_op;
979 /* Bring the second on top. */
980 x87_create_fxch(state, n, op2_idx);
981 if (op1_idx == op2_idx) {
982 /* Both are identically and on tos now, no pop needed. */
985 /* use fxxx (tos = tos X tos) */
986 dst = tmpl->normal_op;
989 /* op2 is on tos now */
991 /* use fxxxp (op = op X tos, pop) */
992 dst = tmpl->normal_pop_op;
1000 /* second operand is an address mode */
1001 if (op1_live_after) {
1002 /* first operand is live: push it here */
1003 x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
1006 /* first operand is dead: bring it to tos */
1008 x87_create_fxch(state, n, op1_idx);
1013 /* use fxxx (tos = tos X mem) */
1014 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
1018 patched_insn = x87_patch_insn(n, dst);
1019 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1024 /* patch the operation */
1025 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
1026 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1027 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
1029 attr->x87[2] = out = get_st_reg(out_idx);
1031 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1032 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1033 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
1034 arch_register_get_name(out)));
1036 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1037 arch_register_get_name(op1_reg),
1038 arch_register_get_name(out)));
1041 return NO_NODE_ADDED;
1045 * Simulate a virtual Unop.
1047 * @param state the x87 state
1048 * @param n the node that should be simulated (and patched)
1049 * @param op the x87 opcode that will replace n's opcode
1051 * @return NO_NODE_ADDED
1053 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
1056 x87_simulator *sim = state->sim;
1057 const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
1058 const arch_register_t *out = x87_get_irn_register(n);
1059 ia32_x87_attr_t *attr;
1060 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1062 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1063 DEBUG_ONLY(vfp_dump_live(live);)
1065 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1067 if (is_vfp_live(arch_register_get_index(op1), live)) {
1068 /* push the operand here */
1069 x87_create_fpush(state, n, op1_idx, 0);
1073 /* operand is dead, bring it to tos */
1075 x87_create_fxch(state, n, op1_idx);
1080 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1081 attr = get_ia32_x87_attr(n);
1082 attr->x87[0] = op1 = get_st_reg(0);
1083 attr->x87[2] = out = get_st_reg(0);
1084 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1086 return NO_NODE_ADDED;
1090 * Simulate a virtual Load instruction.
1092 * @param state the x87 state
1093 * @param n the node that should be simulated (and patched)
1094 * @param op the x87 opcode that will replace n's opcode
1096 * @return NO_NODE_ADDED
1098 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
1100 const arch_register_t *out = x87_irn_get_register(n, res_pos);
1101 ia32_x87_attr_t *attr;
1103 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1104 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1105 assert(out == x87_irn_get_register(n, res_pos));
1106 attr = get_ia32_x87_attr(n);
1107 attr->x87[2] = out = get_st_reg(0);
1108 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1110 return NO_NODE_ADDED;
1114 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1116 * @param store The store
1117 * @param old_val The former value
1118 * @param new_val The new value
1120 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
1122 foreach_out_edge_safe(old_val, edge) {
1123 ir_node *user = get_edge_src_irn(edge);
1125 if (! user || user == store)
1128 /* if the user is scheduled after the store: rewire */
1129 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1131 /* find the input of the user pointing to the old value */
1132 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1133 if (get_irn_n(user, i) == old_val)
1134 set_irn_n(user, i, new_val);
1141 * Simulate a virtual Store.
1143 * @param state the x87 state
1144 * @param n the node that should be simulated (and patched)
1145 * @param op the x87 store opcode
1146 * @param op_p the x87 store and pop opcode
1148 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1150 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1151 const arch_register_t *op2 = x87_get_irn_register(val);
1152 unsigned live = vfp_live_args_after(state->sim, n, 0);
1153 int insn = NO_NODE_ADDED;
1154 ia32_x87_attr_t *attr;
1155 int op2_reg_idx, op2_idx, depth;
1156 int live_after_node;
1159 op2_reg_idx = arch_register_get_index(op2);
1160 op2_idx = x87_on_stack(state, op2_reg_idx);
1161 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1162 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1163 assert(op2_idx >= 0);
1165 mode = get_ia32_ls_mode(n);
1166 depth = x87_get_depth(state);
1168 if (live_after_node) {
1170 Problem: fst doesn't support 96bit modes (spills), only fstp does
1171 fist doesn't support 64bit mode, only fistp
1173 - stack not full: push value and fstp
1174 - stack full: fstp value and load again
1175 Note that we cannot test on mode_E, because floats might be 96bit ...
1177 if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
1178 if (depth < N_ia32_st_REGS) {
1179 /* ok, we have a free register: push + fstp */
1180 x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
1182 x87_patch_insn(n, op_p);
1184 ir_node *vfld, *mem, *block, *rproj, *mproj;
1185 ir_graph *irg = get_irn_irg(n);
1186 ir_node *nomem = get_irg_no_mem(irg);
1188 /* stack full here: need fstp + load */
1190 x87_patch_insn(n, op_p);
1192 block = get_nodes_block(n);
1193 vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n));
1195 /* copy all attributes */
1196 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1197 if (is_ia32_use_frame(n))
1198 set_ia32_use_frame(vfld);
1199 set_ia32_op_type(vfld, ia32_AddrModeS);
1200 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1201 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1202 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1204 rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1205 mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1206 mem = get_irn_Proj_for_mode(n, mode_M);
1208 assert(mem && "Store memory not found");
1210 arch_set_irn_register(rproj, op2);
1212 /* reroute all former users of the store memory to the load memory */
1213 edges_reroute(mem, mproj);
1214 /* set the memory input of the load to the store memory */
1215 set_irn_n(vfld, n_ia32_vfld_mem, mem);
1217 sched_add_after(n, vfld);
1218 sched_add_after(vfld, rproj);
1220 /* rewire all users, scheduled after the store, to the loaded value */
1221 collect_and_rewire_users(n, val, rproj);
1226 /* we can only store the tos to memory */
1228 x87_create_fxch(state, n, op2_idx);
1230 /* mode size 64 or smaller -> use normal fst */
1231 x87_patch_insn(n, op);
1234 /* we can only store the tos to memory */
1236 x87_create_fxch(state, n, op2_idx);
1239 x87_patch_insn(n, op_p);
1242 attr = get_ia32_x87_attr(n);
1243 attr->x87[1] = op2 = get_st_reg(0);
1244 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1249 #define _GEN_BINOP(op, rev) \
1250 static int sim_##op(x87_state *state, ir_node *n) { \
1251 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1252 return sim_binop(state, n, &tmpl); \
1255 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1256 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1258 #define GEN_LOAD(op) \
1259 static int sim_##op(x87_state *state, ir_node *n) { \
1260 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1263 #define GEN_UNOP(op) \
1264 static int sim_##op(x87_state *state, ir_node *n) { \
1265 return sim_unop(state, n, op_ia32_##op); \
1268 #define GEN_STORE(op) \
1269 static int sim_##op(x87_state *state, ir_node *n) { \
1270 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1292 * Simulate a virtual fisttp.
1294 * @param state the x87 state
1295 * @param n the node that should be simulated (and patched)
1297 * @return NO_NODE_ADDED
1299 static int sim_fisttp(x87_state *state, ir_node *n)
1301 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1302 const arch_register_t *op2 = x87_get_irn_register(val);
1303 ia32_x87_attr_t *attr;
1304 int op2_reg_idx, op2_idx;
1306 op2_reg_idx = arch_register_get_index(op2);
1307 op2_idx = x87_on_stack(state, op2_reg_idx);
1308 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1309 assert(op2_idx >= 0);
1311 /* Note: although the value is still live here, it is destroyed because
1312 of the pop. The register allocator is aware of that and introduced a copy
1313 if the value must be alive. */
1315 /* we can only store the tos to memory */
1317 x87_create_fxch(state, n, op2_idx);
1320 x87_patch_insn(n, op_ia32_fisttp);
1322 attr = get_ia32_x87_attr(n);
1323 attr->x87[1] = op2 = get_st_reg(0);
1324 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1326 return NO_NODE_ADDED;
1330 * Simulate a virtual FtstFnstsw.
1332 * @param state the x87 state
1333 * @param n the node that should be simulated (and patched)
1335 * @return NO_NODE_ADDED
1337 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1339 x87_simulator *sim = state->sim;
1340 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1341 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1342 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1343 int reg_index_1 = arch_register_get_index(reg1);
1344 int op1_idx = x87_on_stack(state, reg_index_1);
1345 unsigned live = vfp_live_args_after(sim, n, 0);
1347 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1348 DEBUG_ONLY(vfp_dump_live(live);)
1349 DB((dbg, LEVEL_1, "Stack before: "));
1350 DEBUG_ONLY(x87_dump_stack(state);)
1351 assert(op1_idx >= 0);
1354 /* bring the value to tos */
1355 x87_create_fxch(state, n, op1_idx);
1359 /* patch the operation */
1360 x87_patch_insn(n, op_ia32_FtstFnstsw);
1361 reg1 = get_st_reg(op1_idx);
1362 attr->x87[0] = reg1;
1363 attr->x87[1] = NULL;
1364 attr->x87[2] = NULL;
1366 if (!is_vfp_live(reg_index_1, live))
1367 x87_create_fpop(state, sched_next(n), 1);
1369 return NO_NODE_ADDED;
1375 * @param state the x87 state
1376 * @param n the node that should be simulated (and patched)
1378 * @return NO_NODE_ADDED
1380 static int sim_Fucom(x87_state *state, ir_node *n)
1384 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1386 x87_simulator *sim = state->sim;
1387 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1388 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1389 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1390 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1391 int reg_index_1 = arch_register_get_index(op1);
1392 int reg_index_2 = arch_register_get_index(op2);
1393 unsigned live = vfp_live_args_after(sim, n, 0);
1394 bool permuted = attr->attr.data.ins_permuted;
1398 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1399 arch_register_get_name(op1), arch_register_get_name(op2)));
1400 DEBUG_ONLY(vfp_dump_live(live);)
1401 DB((dbg, LEVEL_1, "Stack before: "));
1402 DEBUG_ONLY(x87_dump_stack(state);)
1404 op1_idx = x87_on_stack(state, reg_index_1);
1405 assert(op1_idx >= 0);
1407 /* BEWARE: check for comp a,a cases, they might happen */
1408 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1409 /* second operand is a vfp register */
1410 op2_idx = x87_on_stack(state, reg_index_2);
1411 assert(op2_idx >= 0);
1413 if (is_vfp_live(reg_index_2, live)) {
1414 /* second operand is live */
1416 if (is_vfp_live(reg_index_1, live)) {
1417 /* both operands are live */
1420 /* res = tos X op */
1421 } else if (op2_idx == 0) {
1422 /* res = op X tos */
1423 permuted = !permuted;
1426 /* bring the first one to tos */
1427 x87_create_fxch(state, n, op1_idx);
1428 if (op1_idx == op2_idx) {
1430 } else if (op2_idx == 0) {
1434 /* res = tos X op */
1437 /* second live, first operand is dead here, bring it to tos.
1438 This means further, op1_idx != op2_idx. */
1439 assert(op1_idx != op2_idx);
1441 x87_create_fxch(state, n, op1_idx);
1446 /* res = tos X op, pop */
1450 /* second operand is dead */
1451 if (is_vfp_live(reg_index_1, live)) {
1452 /* first operand is live: bring second to tos.
1453 This means further, op1_idx != op2_idx. */
1454 assert(op1_idx != op2_idx);
1456 x87_create_fxch(state, n, op2_idx);
1461 /* res = op X tos, pop */
1463 permuted = !permuted;
1466 /* both operands are dead here, check first for identity. */
1467 if (op1_idx == op2_idx) {
1468 /* identically, one pop needed */
1470 x87_create_fxch(state, n, op1_idx);
1474 /* res = tos X op, pop */
1477 /* different, move them to st and st(1) and pop both.
1478 The tricky part is to get one into st(1).*/
1479 else if (op2_idx == 1) {
1480 /* good, second operand is already in the right place, move the first */
1482 /* bring the first on top */
1483 x87_create_fxch(state, n, op1_idx);
1484 assert(op2_idx != 0);
1487 /* res = tos X op, pop, pop */
1489 } else if (op1_idx == 1) {
1490 /* good, first operand is already in the right place, move the second */
1492 /* bring the first on top */
1493 x87_create_fxch(state, n, op2_idx);
1494 assert(op1_idx != 0);
1497 /* res = op X tos, pop, pop */
1498 permuted = !permuted;
1502 /* if one is already the TOS, we need two fxch */
1504 /* first one is TOS, move to st(1) */
1505 x87_create_fxch(state, n, 1);
1506 assert(op2_idx != 1);
1508 x87_create_fxch(state, n, op2_idx);
1510 /* res = op X tos, pop, pop */
1512 permuted = !permuted;
1514 } else if (op2_idx == 0) {
1515 /* second one is TOS, move to st(1) */
1516 x87_create_fxch(state, n, 1);
1517 assert(op1_idx != 1);
1519 x87_create_fxch(state, n, op1_idx);
1521 /* res = tos X op, pop, pop */
1524 /* none of them is either TOS or st(1), 3 fxch needed */
1525 x87_create_fxch(state, n, op2_idx);
1526 assert(op1_idx != 0);
1527 x87_create_fxch(state, n, 1);
1529 x87_create_fxch(state, n, op1_idx);
1531 /* res = tos X op, pop, pop */
1538 /* second operand is an address mode */
1539 if (is_vfp_live(reg_index_1, live)) {
1540 /* first operand is live: bring it to TOS */
1542 x87_create_fxch(state, n, op1_idx);
1546 /* first operand is dead: bring it to tos */
1548 x87_create_fxch(state, n, op1_idx);
1555 /* patch the operation */
1556 if (is_ia32_vFucomFnstsw(n)) {
1560 case 0: dst = op_ia32_FucomFnstsw; break;
1561 case 1: dst = op_ia32_FucompFnstsw; break;
1562 case 2: dst = op_ia32_FucomppFnstsw; break;
1563 default: panic("invalid popcount in sim_Fucom");
1566 for (i = 0; i < pops; ++i) {
1569 } else if (is_ia32_vFucomi(n)) {
1571 case 0: dst = op_ia32_Fucomi; break;
1572 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1574 dst = op_ia32_Fucompi;
1576 x87_create_fpop(state, sched_next(n), 1);
1578 default: panic("invalid popcount in sim_Fucom");
1581 panic("invalid operation %+F in sim_FucomFnstsw", n);
1584 x87_patch_insn(n, dst);
1591 op1 = get_st_reg(op1_idx);
1594 op2 = get_st_reg(op2_idx);
1597 attr->x87[2] = NULL;
1598 attr->attr.data.ins_permuted = permuted;
1601 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1602 arch_register_get_name(op1), arch_register_get_name(op2)));
1604 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1605 arch_register_get_name(op1)));
1608 return NO_NODE_ADDED;
1614 * @param state the x87 state
1615 * @param n the node that should be simulated (and patched)
1617 * @return NO_NODE_ADDED
1619 static int sim_Keep(x87_state *state, ir_node *node)
1622 const arch_register_t *op_reg;
1628 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1630 arity = get_irn_arity(node);
1631 for (i = 0; i < arity; ++i) {
1632 op = get_irn_n(node, i);
1633 op_reg = arch_get_irn_register(op);
1634 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1637 reg_id = arch_register_get_index(op_reg);
1638 live = vfp_live_args_after(state->sim, node, 0);
1640 op_stack_idx = x87_on_stack(state, reg_id);
1641 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1642 x87_create_fpop(state, sched_next(node), 1);
1645 DB((dbg, LEVEL_1, "Stack after: "));
1646 DEBUG_ONLY(x87_dump_stack(state);)
1648 return NO_NODE_ADDED;
1652 * Keep the given node alive by adding a be_Keep.
1654 * @param node the node to kept alive
1656 static void keep_float_node_alive(ir_node *node)
1658 ir_node *block = get_nodes_block(node);
1659 ir_node *keep = be_new_Keep(block, 1, &node);
1661 assert(sched_is_scheduled(node));
1662 sched_add_after(node, keep);
1666 * Create a copy of a node. Recreate the node if it's a constant.
1668 * @param state the x87 state
1669 * @param n the node to be copied
1671 * @return the copy of n
1673 static ir_node *create_Copy(x87_state *state, ir_node *n)
1675 dbg_info *n_dbg = get_irn_dbg_info(n);
1676 ir_mode *mode = get_irn_mode(n);
1677 ir_node *block = get_nodes_block(n);
1678 ir_node *pred = get_irn_n(n, 0);
1679 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1681 const arch_register_t *out;
1682 const arch_register_t *op1;
1683 ia32_x87_attr_t *attr;
1685 /* Do not copy constants, recreate them. */
1686 switch (get_ia32_irn_opcode(pred)) {
1688 cnstr = new_bd_ia32_fldz;
1691 cnstr = new_bd_ia32_fld1;
1693 case iro_ia32_fldpi:
1694 cnstr = new_bd_ia32_fldpi;
1696 case iro_ia32_fldl2e:
1697 cnstr = new_bd_ia32_fldl2e;
1699 case iro_ia32_fldl2t:
1700 cnstr = new_bd_ia32_fldl2t;
1702 case iro_ia32_fldlg2:
1703 cnstr = new_bd_ia32_fldlg2;
1705 case iro_ia32_fldln2:
1706 cnstr = new_bd_ia32_fldln2;
1712 out = x87_get_irn_register(n);
1713 op1 = x87_get_irn_register(pred);
1715 if (cnstr != NULL) {
1716 /* copy a constant */
1717 res = (*cnstr)(n_dbg, block, mode);
1719 x87_push(state, arch_register_get_index(out), res);
1721 attr = get_ia32_x87_attr(res);
1722 attr->x87[2] = get_st_reg(0);
1724 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1726 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1728 x87_push(state, arch_register_get_index(out), res);
1730 attr = get_ia32_x87_attr(res);
1731 attr->x87[0] = get_st_reg(op1_idx);
1732 attr->x87[2] = get_st_reg(0);
1734 arch_set_irn_register(res, out);
1740 * Simulate a be_Copy.
1742 * @param state the x87 state
1743 * @param n the node that should be simulated (and patched)
1745 * @return NO_NODE_ADDED
1747 static int sim_Copy(x87_state *state, ir_node *n)
1750 const arch_register_t *out;
1751 const arch_register_t *op1;
1752 const arch_register_class_t *cls;
1753 ir_node *node, *next;
1754 int op1_idx, out_idx;
1757 cls = arch_get_irn_reg_class(n);
1758 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1761 pred = get_irn_n(n, 0);
1762 out = x87_get_irn_register(n);
1763 op1 = x87_get_irn_register(pred);
1764 live = vfp_live_args_after(state->sim, n, REGMASK(out));
1766 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1767 arch_register_get_name(op1), arch_register_get_name(out)));
1768 DEBUG_ONLY(vfp_dump_live(live);)
1770 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1772 if (is_vfp_live(arch_register_get_index(op1), live)) {
1773 /* Operand is still live, a real copy. We need here an fpush that can
1774 hold a a register, so use the fpushCopy or recreate constants */
1775 node = create_Copy(state, n);
1777 /* We have to make sure the old value doesn't go dead (which can happen
1778 * when we recreate constants). As the simulator expected that value in
1779 * the pred blocks. This is unfortunate as removing it would save us 1
1780 * instruction, but we would have to rerun all the simulation to get
1783 next = sched_next(n);
1786 sched_add_before(next, node);
1788 if (get_irn_n_edges(pred) == 0) {
1789 keep_float_node_alive(pred);
1792 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1794 out_idx = x87_on_stack(state, arch_register_get_index(out));
1796 if (out_idx >= 0 && out_idx != op1_idx) {
1797 /* Matze: out already on stack? how can this happen? */
1798 panic("invalid stack state in x87 simulator");
1801 /* op1 must be killed and placed where out is */
1803 ia32_x87_attr_t *attr;
1804 /* best case, simple remove and rename */
1805 x87_patch_insn(n, op_ia32_Pop);
1806 attr = get_ia32_x87_attr(n);
1807 attr->x87[0] = op1 = get_st_reg(0);
1810 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1812 ia32_x87_attr_t *attr;
1813 /* move op1 to tos, store and pop it */
1815 x87_create_fxch(state, n, op1_idx);
1818 x87_patch_insn(n, op_ia32_Pop);
1819 attr = get_ia32_x87_attr(n);
1820 attr->x87[0] = op1 = get_st_reg(out_idx);
1823 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1825 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1828 /* just a virtual copy */
1829 x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
1830 /* don't remove the node to keep the verifier quiet :),
1831 the emitter won't emit any code for the node */
1834 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1835 exchange(n, get_unop_op(n));
1839 return NO_NODE_ADDED;
1843 * Returns the vf0 result Proj of a Call.
1845 * @para call the Call node
1847 static ir_node *get_call_result_proj(ir_node *call)
1849 /* search the result proj */
1850 foreach_out_edge(call, edge) {
1851 ir_node *proj = get_edge_src_irn(edge);
1852 long pn = get_Proj_proj(proj);
1854 if (pn == pn_ia32_Call_vf0)
1862 * Simulate a ia32_Call.
1864 * @param state the x87 state
1865 * @param n the node that should be simulated (and patched)
1867 * @return NO_NODE_ADDED
1869 static int sim_Call(x87_state *state, ir_node *n)
1871 ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp;
1875 const arch_register_t *reg;
1877 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1879 /* at the begin of a call the x87 state should be empty */
1880 assert(state->depth == 0 && "stack not empty before call");
1882 if (get_method_n_ress(call_tp) <= 0)
1886 * If the called function returns a float, it is returned in st(0).
1887 * This even happens if the return value is NOT used.
1888 * Moreover, only one return result is supported.
1890 res_type = get_method_res_type(call_tp, 0);
1891 mode = get_type_mode(res_type);
1893 if (mode == NULL || !mode_is_float(mode))
1896 resproj = get_call_result_proj(n);
1897 assert(resproj != NULL);
1899 reg = x87_get_irn_register(resproj);
1900 x87_push(state, arch_register_get_index(reg), resproj);
1903 DB((dbg, LEVEL_1, "Stack after: "));
1904 DEBUG_ONLY(x87_dump_stack(state);)
1906 return NO_NODE_ADDED;
1910 * Simulate a be_Return.
1912 * @param state the x87 state
1913 * @param n the node that should be simulated (and patched)
1915 * @return NO_NODE_ADDED
1917 static int sim_Return(x87_state *state, ir_node *n)
1919 int n_res = be_Return_get_n_rets(n);
1920 int i, n_float_res = 0;
1922 /* only floating point return values must reside on stack */
1923 for (i = 0; i < n_res; ++i) {
1924 ir_node *res = get_irn_n(n, n_be_Return_val + i);
1926 if (mode_is_float(get_irn_mode(res)))
1929 assert(x87_get_depth(state) == n_float_res);
1931 /* pop them virtually */
1932 for (i = n_float_res - 1; i >= 0; --i)
1935 return NO_NODE_ADDED;
1938 typedef struct perm_data_t {
1939 const arch_register_t *in;
1940 const arch_register_t *out;
1944 * Simulate a be_Perm.
1946 * @param state the x87 state
1947 * @param irn the node that should be simulated (and patched)
1949 * @return NO_NODE_ADDED
1951 static int sim_Perm(x87_state *state, ir_node *irn)
1954 ir_node *pred = get_irn_n(irn, 0);
1957 /* handle only floating point Perms */
1958 if (! mode_is_float(get_irn_mode(pred)))
1959 return NO_NODE_ADDED;
1961 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1963 /* Perm is a pure virtual instruction on x87.
1964 All inputs must be on the FPU stack and are pairwise
1965 different from each other.
1966 So, all we need to do is to permutate the stack state. */
1967 n = get_irn_arity(irn);
1968 NEW_ARR_A(int, stack_pos, n);
1970 /* collect old stack positions */
1971 for (i = 0; i < n; ++i) {
1972 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1973 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1975 assert(idx >= 0 && "Perm argument not on x87 stack");
1979 /* now do the permutation */
1980 foreach_out_edge(irn, edge) {
1981 ir_node *proj = get_edge_src_irn(edge);
1982 const arch_register_t *out = x87_get_irn_register(proj);
1983 long num = get_Proj_proj(proj);
1985 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1986 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1988 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1990 return NO_NODE_ADDED;
1994 * Kill any dead registers at block start by popping them from the stack.
1996 * @param sim the simulator handle
1997 * @param block the current block
1998 * @param start_state the x87 state at the begin of the block
2000 * @return the x87 state after dead register killed
2002 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
2004 x87_state *state = start_state;
2005 ir_node *first_insn = sched_first(block);
2006 ir_node *keep = NULL;
2007 unsigned live = vfp_live_args_after(sim, block, 0);
2009 int i, depth, num_pop;
2012 depth = x87_get_depth(state);
2013 for (i = depth - 1; i >= 0; --i) {
2014 int reg = x87_get_st_reg(state, i);
2016 if (! is_vfp_live(reg, live))
2017 kill_mask |= (1 << i);
2021 /* create a new state, will be changed */
2022 state = x87_clone_state(sim, state);
2024 DB((dbg, LEVEL_1, "Killing deads:\n"));
2025 DEBUG_ONLY(vfp_dump_live(live);)
2026 DEBUG_ONLY(x87_dump_stack(state);)
2028 if (kill_mask != 0 && live == 0) {
2029 /* special case: kill all registers */
2030 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
2031 if (ia32_cg_config.use_femms) {
2032 /* use FEMMS on AMD processors to clear all */
2033 keep = new_bd_ia32_femms(NULL, block);
2035 /* use EMMS to clear all */
2036 keep = new_bd_ia32_emms(NULL, block);
2038 sched_add_before(first_insn, keep);
2044 /* now kill registers */
2046 /* we can only kill from TOS, so bring them up */
2047 if (! (kill_mask & 1)) {
2048 /* search from behind, because we can to a double-pop */
2049 for (i = depth - 1; i >= 0; --i) {
2050 if (kill_mask & (1 << i)) {
2051 kill_mask &= ~(1 << i);
2058 x87_set_st(state, -1, keep, i);
2059 x87_create_fxch(state, first_insn, i);
2062 if ((kill_mask & 3) == 3) {
2063 /* we can do a double-pop */
2067 /* only a single pop */
2072 kill_mask >>= num_pop;
2073 keep = x87_create_fpop(state, first_insn, num_pop);
2081 * Run a simulation and fix all virtual instructions for a block.
2083 * @param sim the simulator handle
2084 * @param block the current block
2086 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
2089 blk_state *bl_state = x87_get_bl_state(sim, block);
2090 x87_state *state = bl_state->begin;
2091 ir_node *start_block;
2093 assert(state != NULL);
2094 /* already processed? */
2095 if (bl_state->end != NULL)
2098 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2099 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2100 DEBUG_ONLY(x87_dump_stack(state);)
2102 /* at block begin, kill all dead registers */
2103 state = x87_kill_deads(sim, block, state);
2104 /* create a new state, will be changed */
2105 state = x87_clone_state(sim, state);
2107 /* beware, n might change */
2108 for (n = sched_first(block); !sched_is_end(n); n = next) {
2111 ir_op *op = get_irn_op(n);
2114 * get the next node to be simulated here.
2115 * n might be completely removed from the schedule-
2117 next = sched_next(n);
2118 if (op->ops.generic != NULL) {
2119 func = (sim_func)op->ops.generic;
2122 node_inserted = (*func)(state, n);
2125 * sim_func might have added an additional node after n,
2126 * so update next node
2127 * beware: n must not be changed by sim_func
2128 * (i.e. removed from schedule) in this case
2130 if (node_inserted != NO_NODE_ADDED)
2131 next = sched_next(n);
2135 start_block = get_irg_start_block(get_irn_irg(block));
2137 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
2139 /* check if the state must be shuffled */
2140 foreach_block_succ(block, edge) {
2141 ir_node *succ = get_edge_src_irn(edge);
2142 blk_state *succ_state;
2144 if (succ == start_block)
2147 succ_state = x87_get_bl_state(sim, succ);
2149 if (succ_state->begin == NULL) {
2150 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2151 DEBUG_ONLY(x87_dump_stack(state);)
2152 succ_state->begin = state;
2154 waitq_put(sim->worklist, succ);
2156 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2157 /* There is already a begin state for the successor, bad.
2158 Do the necessary permutations.
2159 Note that critical edges are removed, so this is always possible:
2160 If the successor has more than one possible input, then it must
2163 x87_shuffle(sim, block, state, succ, succ_state->begin);
2166 bl_state->end = state;
2170 * Register a simulator function.
2172 * @param op the opcode to simulate
2173 * @param func the simulator function for the opcode
2175 static void register_sim(ir_op *op, sim_func func)
2177 assert(op->ops.generic == NULL);
2178 op->ops.generic = (op_func) func;
2182 * Create a new x87 simulator.
2184 * @param sim a simulator handle, will be initialized
2185 * @param irg the current graph
2187 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
2189 obstack_init(&sim->obst);
2190 sim->blk_states = pmap_create();
2191 sim->n_idx = get_irg_last_idx(irg);
2192 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
2194 DB((dbg, LEVEL_1, "--------------------------------\n"
2195 "x87 Simulator started for %+F\n", irg));
2197 /* set the generic function pointer of instruction we must simulate */
2198 ir_clear_opcodes_generic_func();
2200 register_sim(op_ia32_Call, sim_Call);
2201 register_sim(op_ia32_vfld, sim_fld);
2202 register_sim(op_ia32_vfild, sim_fild);
2203 register_sim(op_ia32_vfld1, sim_fld1);
2204 register_sim(op_ia32_vfldz, sim_fldz);
2205 register_sim(op_ia32_vfadd, sim_fadd);
2206 register_sim(op_ia32_vfsub, sim_fsub);
2207 register_sim(op_ia32_vfmul, sim_fmul);
2208 register_sim(op_ia32_vfdiv, sim_fdiv);
2209 register_sim(op_ia32_vfprem, sim_fprem);
2210 register_sim(op_ia32_vfabs, sim_fabs);
2211 register_sim(op_ia32_vfchs, sim_fchs);
2212 register_sim(op_ia32_vfist, sim_fist);
2213 register_sim(op_ia32_vfisttp, sim_fisttp);
2214 register_sim(op_ia32_vfst, sim_fst);
2215 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2216 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2217 register_sim(op_ia32_vFucomi, sim_Fucom);
2218 register_sim(op_be_Copy, sim_Copy);
2219 register_sim(op_be_Return, sim_Return);
2220 register_sim(op_be_Perm, sim_Perm);
2221 register_sim(op_be_Keep, sim_Keep);
2225 * Destroy a x87 simulator.
2227 * @param sim the simulator handle
2229 static void x87_destroy_simulator(x87_simulator *sim)
2231 pmap_destroy(sim->blk_states);
2232 obstack_free(&sim->obst, NULL);
2233 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2237 * Pre-block walker: calculate the liveness information for the block
2238 * and store it into the sim->live cache.
2240 static void update_liveness_walker(ir_node *block, void *data)
2242 x87_simulator *sim = (x87_simulator*)data;
2243 update_liveness(sim, block);
2247 * Run a simulation and fix all virtual instructions for a graph.
2248 * Replaces all virtual floating point instructions and registers
2251 void ia32_x87_simulate_graph(ir_graph *irg)
2253 /* TODO improve code quality (less executed fxch) by using execfreqs */
2255 ir_node *block, *start_block;
2256 blk_state *bl_state;
2259 /* create the simulator */
2260 x87_init_simulator(&sim, irg);
2262 start_block = get_irg_start_block(irg);
2263 bl_state = x87_get_bl_state(&sim, start_block);
2265 /* start with the empty state */
2266 bl_state->begin = empty;
2269 sim.worklist = new_waitq();
2270 waitq_put(sim.worklist, start_block);
2272 be_assure_live_sets(irg);
2273 sim.lv = be_get_irg_liveness(irg);
2275 /* Calculate the liveness for all nodes. We must precalculate this info,
2276 * because the simulator adds new nodes (possible before Phi nodes) which
2277 * would let a lazy calculation fail.
2278 * On the other hand we reduce the computation amount due to
2279 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2281 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2285 block = (ir_node*)waitq_get(sim.worklist);
2286 x87_simulate_block(&sim, block);
2287 } while (! waitq_empty(sim.worklist));
2290 del_waitq(sim.worklist);
2291 x87_destroy_simulator(&sim);
2294 /* Initializes the x87 simulator. */
2295 void ia32_init_x87(void)
2297 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");