2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1))
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An exchange template.
65 * Note that our virtual functions have the same inputs
66 * and attributes as the real ones, so we can simple exchange
68 * Further, x87 supports inverse instructions, so we can handle them.
70 typedef struct exchange_tmpl {
71 ir_op *normal_op; /**< the normal one */
72 ir_op *reverse_op; /**< the reverse one if exists */
73 ir_op *normal_pop_op; /**< the normal one with tos pop */
74 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
78 * An entry on the simulated x87 stack.
80 typedef struct st_entry {
81 int reg_idx; /**< the virtual register index of this stack value */
82 ir_node *node; /**< the node that produced this value */
88 typedef struct x87_state {
89 st_entry st[N_ia32_st_REGS]; /**< the register stack */
90 int depth; /**< the current stack depth */
91 int tos; /**< position of the tos */
92 x87_simulator *sim; /**< The simulator. */
95 /** An empty state, used for blocks without fp instructions. */
96 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
97 static x87_state *empty = (x87_state *)&_empty;
100 * Return values of the instruction simulator functions.
103 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
104 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
105 in the schedule AFTER the current node. */
109 * The type of an instruction simulator function.
111 * @param state the x87 state
112 * @param n the node to be simulated
114 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
116 * NO_NODE_ADDED otherwise
118 typedef int (*sim_func)(x87_state *state, ir_node *n);
121 * A block state: Every block has a x87 state at the beginning and at the end.
123 typedef struct blk_state {
124 x87_state *begin; /**< state at the begin or NULL if not assigned */
125 x87_state *end; /**< state at the end or NULL if not assigned */
128 /** liveness bitset for vfp registers. */
129 typedef unsigned char vfp_liveness;
134 struct x87_simulator {
135 struct obstack obst; /**< An obstack for fast allocating. */
136 pmap *blk_states; /**< Map blocks to states. */
137 be_lv_t *lv; /**< intrablock liveness. */
138 vfp_liveness *live; /**< Liveness information. */
139 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
140 waitq *worklist; /**< Worklist of blocks that must be processed. */
141 ia32_isa_t *isa; /**< the ISA object */
145 * Returns the current stack depth.
147 * @param state the x87 state
149 * @return the x87 stack depth
151 static int x87_get_depth(const x87_state *state)
157 * Return the virtual register index at st(pos).
159 * @param state the x87 state
160 * @param pos a stack position
162 * @return the vfp register index that produced the value at st(pos)
164 static int x87_get_st_reg(const x87_state *state, int pos)
166 assert(pos < state->depth);
167 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
172 * Return the node at st(pos).
174 * @param state the x87 state
175 * @param pos a stack position
177 * @return the IR node that produced the value at st(pos)
179 static ir_node *x87_get_st_node(const x87_state *state, int pos)
181 assert(pos < state->depth);
182 return state->st[MASK_TOS(state->tos + pos)].node;
186 * Dump the stack for debugging.
188 * @param state the x87 state
190 static void x87_dump_stack(const x87_state *state)
194 for (i = state->depth - 1; i >= 0; --i) {
195 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
196 x87_get_st_node(state, i)));
198 DB((dbg, LEVEL_2, "<-- TOS\n"));
200 #endif /* DEBUG_libfirm */
203 * Set a virtual register to st(pos).
205 * @param state the x87 state
206 * @param reg_idx the vfp register index that should be set
207 * @param node the IR node that produces the value of the vfp register
208 * @param pos the stack position where the new value should be entered
210 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
212 assert(0 < state->depth);
213 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
214 state->st[MASK_TOS(state->tos + pos)].node = node;
216 DB((dbg, LEVEL_2, "After SET_REG: "));
217 DEBUG_ONLY(x87_dump_stack(state);)
221 * Set the tos virtual register.
223 * @param state the x87 state
224 * @param reg_idx the vfp register index that should be set
225 * @param node the IR node that produces the value of the vfp register
227 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
229 x87_set_st(state, reg_idx, node, 0);
233 * Swap st(0) with st(pos).
235 * @param state the x87 state
236 * @param pos the stack position to change the tos with
238 static void x87_fxch(x87_state *state, int pos)
241 assert(pos < state->depth);
243 entry = state->st[MASK_TOS(state->tos + pos)];
244 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
245 state->st[MASK_TOS(state->tos)] = entry;
247 DB((dbg, LEVEL_2, "After FXCH: "));
248 DEBUG_ONLY(x87_dump_stack(state);)
252 * Convert a virtual register to the stack index.
254 * @param state the x87 state
255 * @param reg_idx the register vfp index
257 * @return the stack position where the register is stacked
258 * or -1 if the virtual register was not found
260 static int x87_on_stack(const x87_state *state, int reg_idx)
262 int i, tos = state->tos;
264 for (i = 0; i < state->depth; ++i)
265 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
271 * Push a virtual Register onto the stack, double pushed allowed.
273 * @param state the x87 state
274 * @param reg_idx the register vfp index
275 * @param node the node that produces the value of the vfp register
277 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
279 assert(state->depth < N_ia32_st_REGS && "stack overrun");
282 state->tos = MASK_TOS(state->tos - 1);
283 state->st[state->tos].reg_idx = reg_idx;
284 state->st[state->tos].node = node;
286 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
290 * Push a virtual Register onto the stack, double pushes are NOT allowed.
292 * @param state the x87 state
293 * @param reg_idx the register vfp index
294 * @param node the node that produces the value of the vfp register
295 * @param dbl_push if != 0 double pushes are allowed
297 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
299 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
301 x87_push_dbl(state, reg_idx, node);
305 * Pop a virtual Register from the stack.
307 * @param state the x87 state
309 static void x87_pop(x87_state *state)
311 assert(state->depth > 0 && "stack underrun");
314 state->tos = MASK_TOS(state->tos + 1);
316 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
320 * Empty the fpu stack
322 * @param state the x87 state
324 static void x87_emms(x87_state *state)
331 * Returns the block state of a block.
333 * @param sim the x87 simulator handle
334 * @param block the current block
336 * @return the block state
338 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
340 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
343 res = OALLOC(&sim->obst, blk_state);
347 pmap_insert(sim->blk_states, block, res);
354 * Creates a new x87 state.
356 * @param sim the x87 simulator handle
358 * @return a new x87 state
360 static x87_state *x87_alloc_state(x87_simulator *sim)
362 x87_state *res = OALLOC(&sim->obst, x87_state);
371 * @param sim the x87 simulator handle
372 * @param src the x87 state that will be cloned
374 * @return a cloned copy of the src state
376 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
378 x87_state *res = x87_alloc_state(sim);
385 * Patch a virtual instruction into a x87 one and return
386 * the node representing the result value.
388 * @param n the IR node to patch
389 * @param op the x87 opcode to patch in
391 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
393 ir_mode *mode = get_irn_mode(n);
398 if (mode == mode_T) {
399 /* patch all Proj's */
400 foreach_out_edge(n, edge) {
401 ir_node *proj = get_edge_src_irn(edge);
403 mode = get_irn_mode(proj);
404 if (mode_is_float(mode)) {
406 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
410 } else if (mode_is_float(mode))
411 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
416 * Returns the first Proj of a mode_T node having a given mode.
418 * @param n the mode_T node
419 * @param m the desired mode of the Proj
420 * @return The first Proj of mode @p m found or NULL.
422 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
424 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
426 foreach_out_edge(n, edge) {
427 ir_node *proj = get_edge_src_irn(edge);
428 if (get_irn_mode(proj) == m)
436 * Wrap the arch_* function here so we can check for errors.
438 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
440 const arch_register_t *res = arch_get_irn_register(irn);
442 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
446 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
449 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
451 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
455 static inline const arch_register_t *get_st_reg(int index)
457 return &ia32_registers[REG_ST0 + index];
460 /* -------------- x87 perm --------------- */
463 * Creates a fxch for shuffle.
465 * @param state the x87 state
466 * @param pos parameter for fxch
467 * @param block the block were fxch is inserted
469 * Creates a new fxch node and reroute the user of the old node
472 * @return the fxch node
474 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
477 ia32_x87_attr_t *attr;
479 fxch = new_bd_ia32_fxch(NULL, block);
480 attr = get_ia32_x87_attr(fxch);
481 attr->x87[0] = get_st_reg(pos);
482 attr->x87[2] = get_st_reg(0);
486 x87_fxch(state, pos);
491 * Calculate the necessary permutations to reach dst_state.
493 * These permutations are done with fxch instructions and placed
494 * at the end of the block.
496 * Note that critical edges are removed here, so we need only
497 * a shuffle if the current block has only one successor.
499 * @param sim the simulator handle
500 * @param block the current block
501 * @param state the current x87 stack state, might be modified
502 * @param dst_block the destination block
503 * @param dst_state destination state
507 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
508 x87_state *state, ir_node *dst_block,
509 const x87_state *dst_state)
511 int i, n_cycles, k, ri;
512 unsigned cycles[4], all_mask;
513 char cycle_idx[4][8];
514 ir_node *fxch, *before, *after;
518 assert(state->depth == dst_state->depth);
520 /* Some mathematics here:
521 If we have a cycle of length n that includes the tos,
522 we need n-1 exchange operations.
523 We can always add the tos and restore it, so we need
524 n+1 exchange operations for a cycle not containing the tos.
525 So, the maximum of needed operations is for a cycle of 7
526 not including the tos == 8.
527 This is the same number of ops we would need for using stores,
528 so exchange is cheaper (we save the loads).
529 On the other hand, we might need an additional exchange
530 in the next block to bring one operand on top, so the
531 number of ops in the first case is identical.
532 Further, no more than 4 cycles can exists (4 x 2).
534 all_mask = (1 << (state->depth)) - 1;
536 for (n_cycles = 0; all_mask; ++n_cycles) {
537 int src_idx, dst_idx;
539 /* find the first free slot */
540 for (i = 0; i < state->depth; ++i) {
541 if (all_mask & (1 << i)) {
542 all_mask &= ~(1 << i);
544 /* check if there are differences here */
545 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
551 /* no more cycles found */
556 cycles[n_cycles] = (1 << i);
557 cycle_idx[n_cycles][k++] = i;
558 for (src_idx = i; ; src_idx = dst_idx) {
559 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
561 if ((all_mask & (1 << dst_idx)) == 0)
564 cycle_idx[n_cycles][k++] = dst_idx;
565 cycles[n_cycles] |= (1 << dst_idx);
566 all_mask &= ~(1 << dst_idx);
568 cycle_idx[n_cycles][k] = -1;
572 /* no permutation needed */
576 /* Hmm: permutation needed */
577 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
578 DEBUG_ONLY(x87_dump_stack(state);)
579 DB((dbg, LEVEL_2, " to\n"));
580 DEBUG_ONLY(x87_dump_stack(dst_state);)
584 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
585 for (ri = 0; ri < n_cycles; ++ri) {
586 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
587 for (k = 0; cycle_idx[ri][k] != -1; ++k)
588 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
589 DB((dbg, LEVEL_2, "\n"));
596 * Find the place node must be insert.
597 * We have only one successor block, so the last instruction should
600 before = sched_last(block);
601 assert(is_cfop(before));
603 /* now do the permutations */
604 for (ri = 0; ri < n_cycles; ++ri) {
605 if ((cycles[ri] & 1) == 0) {
606 /* this cycle does not include the tos */
607 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
609 sched_add_after(after, fxch);
611 sched_add_before(before, fxch);
614 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
615 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
617 sched_add_after(after, fxch);
619 sched_add_before(before, fxch);
622 if ((cycles[ri] & 1) == 0) {
623 /* this cycle does not include the tos */
624 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
625 sched_add_after(after, fxch);
632 * Create a fxch node before another node.
634 * @param state the x87 state
635 * @param n the node after the fxch
636 * @param pos exchange st(pos) with st(0)
640 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
643 ia32_x87_attr_t *attr;
644 ir_node *block = get_nodes_block(n);
646 x87_fxch(state, pos);
648 fxch = new_bd_ia32_fxch(NULL, block);
649 attr = get_ia32_x87_attr(fxch);
650 attr->x87[0] = get_st_reg(pos);
651 attr->x87[2] = get_st_reg(0);
655 sched_add_before(n, fxch);
656 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
661 * Create a fpush before node n.
663 * @param state the x87 state
664 * @param n the node after the fpush
665 * @param pos push st(pos) on stack
666 * @param op_idx replace input op_idx of n with the fpush result
668 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
670 ir_node *fpush, *pred = get_irn_n(n, op_idx);
671 ia32_x87_attr_t *attr;
672 const arch_register_t *out = x87_get_irn_register(pred);
674 x87_push_dbl(state, arch_register_get_index(out), pred);
676 fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
677 attr = get_ia32_x87_attr(fpush);
678 attr->x87[0] = get_st_reg(pos);
679 attr->x87[2] = get_st_reg(0);
682 sched_add_before(n, fpush);
684 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
688 * Create a fpop before node n.
690 * @param state the x87 state
691 * @param n the node after the fpop
692 * @param num pop 1 or 2 values
694 * @return the fpop node
696 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
698 ir_node *fpop = NULL;
699 ia32_x87_attr_t *attr;
704 if (ia32_cg_config.use_ffreep)
705 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
707 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
708 attr = get_ia32_x87_attr(fpop);
709 attr->x87[0] = get_st_reg(0);
710 attr->x87[1] = get_st_reg(0);
711 attr->x87[2] = get_st_reg(0);
714 sched_add_before(n, fpop);
715 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
720 /* --------------------------------- liveness ------------------------------------------ */
723 * The liveness transfer function.
724 * Updates a live set over a single step from a given node to its predecessor.
725 * Everything defined at the node is removed from the set, the uses of the node get inserted.
727 * @param irn The node at which liveness should be computed.
728 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
729 * the registers live after irn.
731 * @return The live bitset.
733 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
736 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
738 if (get_irn_mode(irn) == mode_T) {
739 foreach_out_edge(irn, edge) {
740 ir_node *proj = get_edge_src_irn(edge);
742 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
743 const arch_register_t *reg = x87_get_irn_register(proj);
744 live &= ~(1 << arch_register_get_index(reg));
747 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
748 const arch_register_t *reg = x87_get_irn_register(irn);
749 live &= ~(1 << arch_register_get_index(reg));
752 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
753 ir_node *op = get_irn_n(irn, i);
755 if (mode_is_float(get_irn_mode(op)) &&
756 arch_irn_consider_in_reg_alloc(cls, op)) {
757 const arch_register_t *reg = x87_get_irn_register(op);
758 live |= 1 << arch_register_get_index(reg);
765 * Put all live virtual registers at the end of a block into a bitset.
767 * @param sim the simulator handle
768 * @param lv the liveness information
769 * @param bl the block
771 * @return The live bitset at the end of this block
773 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
775 vfp_liveness live = 0;
776 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
777 const be_lv_t *lv = sim->lv;
779 be_lv_foreach(lv, block, be_lv_state_end, node) {
780 const arch_register_t *reg;
781 if (!arch_irn_consider_in_reg_alloc(cls, node))
784 reg = x87_get_irn_register(node);
785 live |= 1 << arch_register_get_index(reg);
791 /** get the register mask from an arch_register */
792 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
795 * Return a bitset of argument registers which are live at the end of a node.
797 * @param sim the simulator handle
798 * @param pos the node
799 * @param kill kill mask for the output registers
801 * @return The live bitset.
803 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
805 unsigned idx = get_irn_idx(pos);
807 assert(idx < sim->n_idx);
808 return sim->live[idx] & ~kill;
812 * Calculate the liveness for a whole block and cache it.
814 * @param sim the simulator handle
815 * @param lv the liveness handle
816 * @param block the block
818 static void update_liveness(x87_simulator *sim, ir_node *block)
820 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
823 /* now iterate through the block backward and cache the results */
824 sched_foreach_reverse(block, irn) {
825 /* stop at the first Phi: this produces the live-in */
829 idx = get_irn_idx(irn);
830 sim->live[idx] = live;
832 live = vfp_liveness_transfer(irn, live);
834 idx = get_irn_idx(block);
835 sim->live[idx] = live;
839 * Returns true if a register is live in a set.
841 * @param reg_idx the vfp register index
842 * @param live a live bitset
844 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
848 * Dump liveness info.
850 * @param live the live bitset
852 static void vfp_dump_live(vfp_liveness live)
856 DB((dbg, LEVEL_2, "Live after: "));
857 for (i = 0; i < 8; ++i) {
858 if (live & (1 << i)) {
859 DB((dbg, LEVEL_2, "vf%d ", i));
862 DB((dbg, LEVEL_2, "\n"));
864 #endif /* DEBUG_libfirm */
866 /* --------------------------------- simulators ---------------------------------------- */
869 * Simulate a virtual binop.
871 * @param state the x87 state
872 * @param n the node that should be simulated (and patched)
873 * @param tmpl the template containing the 4 possible x87 opcodes
875 * @return NO_NODE_ADDED
877 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
879 int op2_idx = 0, op1_idx;
880 int out_idx, do_pop = 0;
881 ia32_x87_attr_t *attr;
883 ir_node *patched_insn;
885 x87_simulator *sim = state->sim;
886 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
887 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
888 const arch_register_t *op1_reg = x87_get_irn_register(op1);
889 const arch_register_t *op2_reg = x87_get_irn_register(op2);
890 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
891 int reg_index_1 = arch_register_get_index(op1_reg);
892 int reg_index_2 = arch_register_get_index(op2_reg);
893 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
897 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
898 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
899 arch_register_get_name(out)));
900 DEBUG_ONLY(vfp_dump_live(live);)
901 DB((dbg, LEVEL_1, "Stack before: "));
902 DEBUG_ONLY(x87_dump_stack(state);)
904 op1_idx = x87_on_stack(state, reg_index_1);
905 assert(op1_idx >= 0);
906 op1_live_after = is_vfp_live(reg_index_1, live);
908 attr = get_ia32_x87_attr(n);
909 permuted = attr->attr.data.ins_permuted;
911 if (reg_index_2 != REG_VFP_VFP_NOREG) {
914 /* second operand is a vfp register */
915 op2_idx = x87_on_stack(state, reg_index_2);
916 assert(op2_idx >= 0);
917 op2_live_after = is_vfp_live(reg_index_2, live);
919 if (op2_live_after) {
920 /* Second operand is live. */
922 if (op1_live_after) {
923 /* Both operands are live: push the first one.
924 This works even for op1 == op2. */
925 x87_create_fpush(state, n, op1_idx, n_ia32_binary_right);
926 /* now do fxxx (tos=tos X op) */
930 dst = tmpl->normal_op;
932 /* Second live, first operand is dead here, bring it to tos. */
934 x87_create_fxch(state, n, op1_idx);
939 /* now do fxxx (tos=tos X op) */
941 dst = tmpl->normal_op;
944 /* Second operand is dead. */
945 if (op1_live_after) {
946 /* First operand is live: bring second to tos. */
948 x87_create_fxch(state, n, op2_idx);
953 /* now do fxxxr (tos = op X tos) */
955 dst = tmpl->reverse_op;
957 /* Both operands are dead here, pop them from the stack. */
960 /* Both are identically and on tos, no pop needed. */
961 /* here fxxx (tos = tos X tos) */
962 dst = tmpl->normal_op;
965 /* now do fxxxp (op = op X tos, pop) */
966 dst = tmpl->normal_pop_op;
970 } else if (op1_idx == 0) {
971 assert(op1_idx != op2_idx);
972 /* now do fxxxrp (op = tos X op, pop) */
973 dst = tmpl->reverse_pop_op;
977 /* Bring the second on top. */
978 x87_create_fxch(state, n, op2_idx);
979 if (op1_idx == op2_idx) {
980 /* Both are identically and on tos now, no pop needed. */
983 /* use fxxx (tos = tos X tos) */
984 dst = tmpl->normal_op;
987 /* op2 is on tos now */
989 /* use fxxxp (op = op X tos, pop) */
990 dst = tmpl->normal_pop_op;
998 /* second operand is an address mode */
999 if (op1_live_after) {
1000 /* first operand is live: push it here */
1001 x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
1004 /* first operand is dead: bring it to tos */
1006 x87_create_fxch(state, n, op1_idx);
1011 /* use fxxx (tos = tos X mem) */
1012 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
1016 patched_insn = x87_patch_insn(n, dst);
1017 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1022 /* patch the operation */
1023 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
1024 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1025 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
1027 attr->x87[2] = out = get_st_reg(out_idx);
1029 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1030 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1031 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
1032 arch_register_get_name(out)));
1034 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1035 arch_register_get_name(op1_reg),
1036 arch_register_get_name(out)));
1039 return NO_NODE_ADDED;
1043 * Simulate a virtual Unop.
1045 * @param state the x87 state
1046 * @param n the node that should be simulated (and patched)
1047 * @param op the x87 opcode that will replace n's opcode
1049 * @return NO_NODE_ADDED
1051 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
1053 x87_simulator *sim = state->sim;
1054 const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
1055 const arch_register_t *out = x87_get_irn_register(n);
1056 ia32_x87_attr_t *attr;
1057 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1059 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1060 DEBUG_ONLY(vfp_dump_live(live);)
1062 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1064 if (is_vfp_live(arch_register_get_index(op1), live)) {
1065 /* push the operand here */
1066 x87_create_fpush(state, n, op1_idx, 0);
1069 /* operand is dead, bring it to tos */
1071 x87_create_fxch(state, n, op1_idx);
1075 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1076 attr = get_ia32_x87_attr(n);
1077 attr->x87[0] = op1 = get_st_reg(0);
1078 attr->x87[2] = out = get_st_reg(0);
1079 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1081 return NO_NODE_ADDED;
1085 * Simulate a virtual Load instruction.
1087 * @param state the x87 state
1088 * @param n the node that should be simulated (and patched)
1089 * @param op the x87 opcode that will replace n's opcode
1091 * @return NO_NODE_ADDED
1093 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
1095 const arch_register_t *out = x87_irn_get_register(n, res_pos);
1096 ia32_x87_attr_t *attr;
1098 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1099 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1100 assert(out == x87_irn_get_register(n, res_pos));
1101 attr = get_ia32_x87_attr(n);
1102 attr->x87[2] = out = get_st_reg(0);
1103 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1105 return NO_NODE_ADDED;
1109 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1111 * @param store The store
1112 * @param old_val The former value
1113 * @param new_val The new value
1115 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
1117 foreach_out_edge_safe(old_val, edge) {
1118 ir_node *user = get_edge_src_irn(edge);
1120 if (! user || user == store)
1123 /* if the user is scheduled after the store: rewire */
1124 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1126 /* find the input of the user pointing to the old value */
1127 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1128 if (get_irn_n(user, i) == old_val)
1129 set_irn_n(user, i, new_val);
1136 * Simulate a virtual Store.
1138 * @param state the x87 state
1139 * @param n the node that should be simulated (and patched)
1140 * @param op the x87 store opcode
1141 * @param op_p the x87 store and pop opcode
1143 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1145 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1146 const arch_register_t *op2 = x87_get_irn_register(val);
1147 unsigned live = vfp_live_args_after(state->sim, n, 0);
1148 int insn = NO_NODE_ADDED;
1149 ia32_x87_attr_t *attr;
1150 int op2_reg_idx, op2_idx, depth;
1151 int live_after_node;
1154 op2_reg_idx = arch_register_get_index(op2);
1155 op2_idx = x87_on_stack(state, op2_reg_idx);
1156 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1157 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1158 assert(op2_idx >= 0);
1160 mode = get_ia32_ls_mode(n);
1161 depth = x87_get_depth(state);
1163 if (live_after_node) {
1165 Problem: fst doesn't support 96bit modes (spills), only fstp does
1166 fist doesn't support 64bit mode, only fistp
1168 - stack not full: push value and fstp
1169 - stack full: fstp value and load again
1170 Note that we cannot test on mode_E, because floats might be 96bit ...
1172 if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
1173 if (depth < N_ia32_st_REGS) {
1174 /* ok, we have a free register: push + fstp */
1175 x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
1177 x87_patch_insn(n, op_p);
1179 ir_node *vfld, *mem, *block, *rproj, *mproj;
1180 ir_graph *irg = get_irn_irg(n);
1181 ir_node *nomem = get_irg_no_mem(irg);
1183 /* stack full here: need fstp + load */
1185 x87_patch_insn(n, op_p);
1187 block = get_nodes_block(n);
1188 vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n));
1190 /* copy all attributes */
1191 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1192 if (is_ia32_use_frame(n))
1193 set_ia32_use_frame(vfld);
1194 set_ia32_op_type(vfld, ia32_AddrModeS);
1195 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1196 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1197 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1199 rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1200 mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1201 mem = get_irn_Proj_for_mode(n, mode_M);
1203 assert(mem && "Store memory not found");
1205 arch_set_irn_register(rproj, op2);
1207 /* reroute all former users of the store memory to the load memory */
1208 edges_reroute(mem, mproj);
1209 /* set the memory input of the load to the store memory */
1210 set_irn_n(vfld, n_ia32_vfld_mem, mem);
1212 sched_add_after(n, vfld);
1213 sched_add_after(vfld, rproj);
1215 /* rewire all users, scheduled after the store, to the loaded value */
1216 collect_and_rewire_users(n, val, rproj);
1221 /* we can only store the tos to memory */
1223 x87_create_fxch(state, n, op2_idx);
1225 /* mode size 64 or smaller -> use normal fst */
1226 x87_patch_insn(n, op);
1229 /* we can only store the tos to memory */
1231 x87_create_fxch(state, n, op2_idx);
1234 x87_patch_insn(n, op_p);
1237 attr = get_ia32_x87_attr(n);
1238 attr->x87[1] = op2 = get_st_reg(0);
1239 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1244 #define _GEN_BINOP(op, rev) \
1245 static int sim_##op(x87_state *state, ir_node *n) { \
1246 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1247 return sim_binop(state, n, &tmpl); \
1250 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1251 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1253 #define GEN_LOAD(op) \
1254 static int sim_##op(x87_state *state, ir_node *n) { \
1255 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1258 #define GEN_UNOP(op) \
1259 static int sim_##op(x87_state *state, ir_node *n) { \
1260 return sim_unop(state, n, op_ia32_##op); \
1263 #define GEN_STORE(op) \
1264 static int sim_##op(x87_state *state, ir_node *n) { \
1265 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1287 * Simulate a virtual fisttp.
1289 * @param state the x87 state
1290 * @param n the node that should be simulated (and patched)
1292 * @return NO_NODE_ADDED
1294 static int sim_fisttp(x87_state *state, ir_node *n)
1296 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1297 const arch_register_t *op2 = x87_get_irn_register(val);
1298 ia32_x87_attr_t *attr;
1299 int op2_reg_idx, op2_idx;
1301 op2_reg_idx = arch_register_get_index(op2);
1302 op2_idx = x87_on_stack(state, op2_reg_idx);
1303 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1304 assert(op2_idx >= 0);
1306 /* Note: although the value is still live here, it is destroyed because
1307 of the pop. The register allocator is aware of that and introduced a copy
1308 if the value must be alive. */
1310 /* we can only store the tos to memory */
1312 x87_create_fxch(state, n, op2_idx);
1315 x87_patch_insn(n, op_ia32_fisttp);
1317 attr = get_ia32_x87_attr(n);
1318 attr->x87[1] = op2 = get_st_reg(0);
1319 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1321 return NO_NODE_ADDED;
1325 * Simulate a virtual FtstFnstsw.
1327 * @param state the x87 state
1328 * @param n the node that should be simulated (and patched)
1330 * @return NO_NODE_ADDED
1332 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1334 x87_simulator *sim = state->sim;
1335 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1336 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1337 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1338 int reg_index_1 = arch_register_get_index(reg1);
1339 int op1_idx = x87_on_stack(state, reg_index_1);
1340 unsigned live = vfp_live_args_after(sim, n, 0);
1342 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1343 DEBUG_ONLY(vfp_dump_live(live);)
1344 DB((dbg, LEVEL_1, "Stack before: "));
1345 DEBUG_ONLY(x87_dump_stack(state);)
1346 assert(op1_idx >= 0);
1349 /* bring the value to tos */
1350 x87_create_fxch(state, n, op1_idx);
1354 /* patch the operation */
1355 x87_patch_insn(n, op_ia32_FtstFnstsw);
1356 reg1 = get_st_reg(op1_idx);
1357 attr->x87[0] = reg1;
1358 attr->x87[1] = NULL;
1359 attr->x87[2] = NULL;
1361 if (!is_vfp_live(reg_index_1, live))
1362 x87_create_fpop(state, sched_next(n), 1);
1364 return NO_NODE_ADDED;
1370 * @param state the x87 state
1371 * @param n the node that should be simulated (and patched)
1373 * @return NO_NODE_ADDED
1375 static int sim_Fucom(x87_state *state, ir_node *n)
1379 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1381 x87_simulator *sim = state->sim;
1382 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1383 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1384 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1385 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1386 int reg_index_1 = arch_register_get_index(op1);
1387 int reg_index_2 = arch_register_get_index(op2);
1388 unsigned live = vfp_live_args_after(sim, n, 0);
1389 bool permuted = attr->attr.data.ins_permuted;
1393 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1394 arch_register_get_name(op1), arch_register_get_name(op2)));
1395 DEBUG_ONLY(vfp_dump_live(live);)
1396 DB((dbg, LEVEL_1, "Stack before: "));
1397 DEBUG_ONLY(x87_dump_stack(state);)
1399 op1_idx = x87_on_stack(state, reg_index_1);
1400 assert(op1_idx >= 0);
1402 /* BEWARE: check for comp a,a cases, they might happen */
1403 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1404 /* second operand is a vfp register */
1405 op2_idx = x87_on_stack(state, reg_index_2);
1406 assert(op2_idx >= 0);
1408 if (is_vfp_live(reg_index_2, live)) {
1409 /* second operand is live */
1411 if (is_vfp_live(reg_index_1, live)) {
1412 /* both operands are live */
1415 /* res = tos X op */
1416 } else if (op2_idx == 0) {
1417 /* res = op X tos */
1418 permuted = !permuted;
1421 /* bring the first one to tos */
1422 x87_create_fxch(state, n, op1_idx);
1423 if (op1_idx == op2_idx) {
1425 } else if (op2_idx == 0) {
1429 /* res = tos X op */
1432 /* second live, first operand is dead here, bring it to tos.
1433 This means further, op1_idx != op2_idx. */
1434 assert(op1_idx != op2_idx);
1436 x87_create_fxch(state, n, op1_idx);
1441 /* res = tos X op, pop */
1445 /* second operand is dead */
1446 if (is_vfp_live(reg_index_1, live)) {
1447 /* first operand is live: bring second to tos.
1448 This means further, op1_idx != op2_idx. */
1449 assert(op1_idx != op2_idx);
1451 x87_create_fxch(state, n, op2_idx);
1456 /* res = op X tos, pop */
1458 permuted = !permuted;
1461 /* both operands are dead here, check first for identity. */
1462 if (op1_idx == op2_idx) {
1463 /* identically, one pop needed */
1465 x87_create_fxch(state, n, op1_idx);
1469 /* res = tos X op, pop */
1472 /* different, move them to st and st(1) and pop both.
1473 The tricky part is to get one into st(1).*/
1474 else if (op2_idx == 1) {
1475 /* good, second operand is already in the right place, move the first */
1477 /* bring the first on top */
1478 x87_create_fxch(state, n, op1_idx);
1479 assert(op2_idx != 0);
1482 /* res = tos X op, pop, pop */
1484 } else if (op1_idx == 1) {
1485 /* good, first operand is already in the right place, move the second */
1487 /* bring the first on top */
1488 x87_create_fxch(state, n, op2_idx);
1489 assert(op1_idx != 0);
1492 /* res = op X tos, pop, pop */
1493 permuted = !permuted;
1497 /* if one is already the TOS, we need two fxch */
1499 /* first one is TOS, move to st(1) */
1500 x87_create_fxch(state, n, 1);
1501 assert(op2_idx != 1);
1503 x87_create_fxch(state, n, op2_idx);
1505 /* res = op X tos, pop, pop */
1507 permuted = !permuted;
1509 } else if (op2_idx == 0) {
1510 /* second one is TOS, move to st(1) */
1511 x87_create_fxch(state, n, 1);
1512 assert(op1_idx != 1);
1514 x87_create_fxch(state, n, op1_idx);
1516 /* res = tos X op, pop, pop */
1519 /* none of them is either TOS or st(1), 3 fxch needed */
1520 x87_create_fxch(state, n, op2_idx);
1521 assert(op1_idx != 0);
1522 x87_create_fxch(state, n, 1);
1524 x87_create_fxch(state, n, op1_idx);
1526 /* res = tos X op, pop, pop */
1533 /* second operand is an address mode */
1534 if (is_vfp_live(reg_index_1, live)) {
1535 /* first operand is live: bring it to TOS */
1537 x87_create_fxch(state, n, op1_idx);
1541 /* first operand is dead: bring it to tos */
1543 x87_create_fxch(state, n, op1_idx);
1550 /* patch the operation */
1551 if (is_ia32_vFucomFnstsw(n)) {
1555 case 0: dst = op_ia32_FucomFnstsw; break;
1556 case 1: dst = op_ia32_FucompFnstsw; break;
1557 case 2: dst = op_ia32_FucomppFnstsw; break;
1558 default: panic("invalid popcount");
1561 for (i = 0; i < pops; ++i) {
1564 } else if (is_ia32_vFucomi(n)) {
1566 case 0: dst = op_ia32_Fucomi; break;
1567 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1569 dst = op_ia32_Fucompi;
1571 x87_create_fpop(state, sched_next(n), 1);
1573 default: panic("invalid popcount");
1576 panic("invalid operation %+F", n);
1579 x87_patch_insn(n, dst);
1586 op1 = get_st_reg(op1_idx);
1589 op2 = get_st_reg(op2_idx);
1592 attr->x87[2] = NULL;
1593 attr->attr.data.ins_permuted = permuted;
1596 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1597 arch_register_get_name(op1), arch_register_get_name(op2)));
1599 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1600 arch_register_get_name(op1)));
1603 return NO_NODE_ADDED;
1609 * @param state the x87 state
1610 * @param n the node that should be simulated (and patched)
1612 * @return NO_NODE_ADDED
1614 static int sim_Keep(x87_state *state, ir_node *node)
1617 const arch_register_t *op_reg;
1623 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1625 arity = get_irn_arity(node);
1626 for (i = 0; i < arity; ++i) {
1627 op = get_irn_n(node, i);
1628 op_reg = arch_get_irn_register(op);
1629 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1632 reg_id = arch_register_get_index(op_reg);
1633 live = vfp_live_args_after(state->sim, node, 0);
1635 op_stack_idx = x87_on_stack(state, reg_id);
1636 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1637 x87_create_fpop(state, sched_next(node), 1);
1640 DB((dbg, LEVEL_1, "Stack after: "));
1641 DEBUG_ONLY(x87_dump_stack(state);)
1643 return NO_NODE_ADDED;
1647 * Keep the given node alive by adding a be_Keep.
1649 * @param node the node to kept alive
1651 static void keep_float_node_alive(ir_node *node)
1653 ir_node *block = get_nodes_block(node);
1654 ir_node *keep = be_new_Keep(block, 1, &node);
1656 assert(sched_is_scheduled(node));
1657 sched_add_after(node, keep);
1661 * Create a copy of a node. Recreate the node if it's a constant.
1663 * @param state the x87 state
1664 * @param n the node to be copied
1666 * @return the copy of n
1668 static ir_node *create_Copy(x87_state *state, ir_node *n)
1670 dbg_info *n_dbg = get_irn_dbg_info(n);
1671 ir_mode *mode = get_irn_mode(n);
1672 ir_node *block = get_nodes_block(n);
1673 ir_node *pred = get_irn_n(n, 0);
1674 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1676 const arch_register_t *out;
1677 const arch_register_t *op1;
1678 ia32_x87_attr_t *attr;
1680 /* Do not copy constants, recreate them. */
1681 switch (get_ia32_irn_opcode(pred)) {
1683 cnstr = new_bd_ia32_fldz;
1686 cnstr = new_bd_ia32_fld1;
1688 case iro_ia32_fldpi:
1689 cnstr = new_bd_ia32_fldpi;
1691 case iro_ia32_fldl2e:
1692 cnstr = new_bd_ia32_fldl2e;
1694 case iro_ia32_fldl2t:
1695 cnstr = new_bd_ia32_fldl2t;
1697 case iro_ia32_fldlg2:
1698 cnstr = new_bd_ia32_fldlg2;
1700 case iro_ia32_fldln2:
1701 cnstr = new_bd_ia32_fldln2;
1707 out = x87_get_irn_register(n);
1708 op1 = x87_get_irn_register(pred);
1710 if (cnstr != NULL) {
1711 /* copy a constant */
1712 res = (*cnstr)(n_dbg, block, mode);
1714 x87_push(state, arch_register_get_index(out), res);
1716 attr = get_ia32_x87_attr(res);
1717 attr->x87[2] = get_st_reg(0);
1719 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1721 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1723 x87_push(state, arch_register_get_index(out), res);
1725 attr = get_ia32_x87_attr(res);
1726 attr->x87[0] = get_st_reg(op1_idx);
1727 attr->x87[2] = get_st_reg(0);
1729 arch_set_irn_register(res, out);
1735 * Simulate a be_Copy.
1737 * @param state the x87 state
1738 * @param n the node that should be simulated (and patched)
1740 * @return NO_NODE_ADDED
1742 static int sim_Copy(x87_state *state, ir_node *n)
1745 const arch_register_t *out;
1746 const arch_register_t *op1;
1747 const arch_register_class_t *cls;
1748 ir_node *node, *next;
1749 int op1_idx, out_idx;
1752 cls = arch_get_irn_reg_class(n);
1753 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1756 pred = be_get_Copy_op(n);
1757 out = x87_get_irn_register(n);
1758 op1 = x87_get_irn_register(pred);
1759 live = vfp_live_args_after(state->sim, n, REGMASK(out));
1761 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1762 arch_register_get_name(op1), arch_register_get_name(out)));
1763 DEBUG_ONLY(vfp_dump_live(live);)
1765 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1767 if (is_vfp_live(arch_register_get_index(op1), live)) {
1768 /* Operand is still live, a real copy. We need here an fpush that can
1769 hold a a register, so use the fpushCopy or recreate constants */
1770 node = create_Copy(state, n);
1772 /* We have to make sure the old value doesn't go dead (which can happen
1773 * when we recreate constants). As the simulator expected that value in
1774 * the pred blocks. This is unfortunate as removing it would save us 1
1775 * instruction, but we would have to rerun all the simulation to get
1778 next = sched_next(n);
1781 sched_add_before(next, node);
1783 if (get_irn_n_edges(pred) == 0) {
1784 keep_float_node_alive(pred);
1787 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1789 out_idx = x87_on_stack(state, arch_register_get_index(out));
1791 if (out_idx >= 0 && out_idx != op1_idx) {
1792 /* Matze: out already on stack? how can this happen? */
1793 panic("invalid stack state");
1796 /* op1 must be killed and placed where out is */
1798 ia32_x87_attr_t *attr;
1799 /* best case, simple remove and rename */
1800 x87_patch_insn(n, op_ia32_Pop);
1801 attr = get_ia32_x87_attr(n);
1802 attr->x87[0] = op1 = get_st_reg(0);
1805 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1807 ia32_x87_attr_t *attr;
1808 /* move op1 to tos, store and pop it */
1810 x87_create_fxch(state, n, op1_idx);
1813 x87_patch_insn(n, op_ia32_Pop);
1814 attr = get_ia32_x87_attr(n);
1815 attr->x87[0] = op1 = get_st_reg(out_idx);
1818 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1820 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1823 /* just a virtual copy */
1824 x87_set_st(state, arch_register_get_index(out), pred, op1_idx);
1825 /* don't remove the node to keep the verifier quiet :),
1826 the emitter won't emit any code for the node */
1829 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1834 return NO_NODE_ADDED;
1838 * Returns the vf0 result Proj of a Call.
1840 * @para call the Call node
1842 static ir_node *get_call_result_proj(ir_node *call)
1844 /* search the result proj */
1845 foreach_out_edge(call, edge) {
1846 ir_node *proj = get_edge_src_irn(edge);
1847 long pn = get_Proj_proj(proj);
1849 if (pn == pn_ia32_Call_vf0)
1856 static int sim_Asm(x87_state *const state, ir_node *const n)
1860 for (size_t i = get_irn_arity(n); i-- != 0;) {
1861 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1862 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1863 panic("cannot handle %+F with x87 constraints", n);
1866 for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
1867 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1868 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1869 panic("cannot handle %+F with x87 constraints", n);
1872 return NO_NODE_ADDED;
1876 * Simulate a ia32_Call.
1878 * @param state the x87 state
1879 * @param n the node that should be simulated (and patched)
1881 * @return NO_NODE_ADDED
1883 static int sim_Call(x87_state *state, ir_node *n)
1885 ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp;
1889 const arch_register_t *reg;
1891 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1893 /* at the begin of a call the x87 state should be empty */
1894 assert(state->depth == 0 && "stack not empty before call");
1896 if (get_method_n_ress(call_tp) <= 0)
1900 * If the called function returns a float, it is returned in st(0).
1901 * This even happens if the return value is NOT used.
1902 * Moreover, only one return result is supported.
1904 res_type = get_method_res_type(call_tp, 0);
1905 mode = get_type_mode(res_type);
1907 if (mode == NULL || !mode_is_float(mode))
1910 resproj = get_call_result_proj(n);
1911 assert(resproj != NULL);
1913 reg = x87_get_irn_register(resproj);
1914 x87_push(state, arch_register_get_index(reg), resproj);
1917 DB((dbg, LEVEL_1, "Stack after: "));
1918 DEBUG_ONLY(x87_dump_stack(state);)
1920 return NO_NODE_ADDED;
1924 * Simulate a be_Return.
1926 * @param state the x87 state
1927 * @param n the node that should be simulated (and patched)
1929 * @return NO_NODE_ADDED
1931 static int sim_Return(x87_state *state, ir_node *n)
1933 int n_res = be_Return_get_n_rets(n);
1934 int i, n_float_res = 0;
1936 /* only floating point return values must reside on stack */
1937 for (i = 0; i < n_res; ++i) {
1938 ir_node *res = get_irn_n(n, n_be_Return_val + i);
1940 if (mode_is_float(get_irn_mode(res)))
1943 assert(x87_get_depth(state) == n_float_res);
1945 /* pop them virtually */
1946 for (i = n_float_res - 1; i >= 0; --i)
1949 return NO_NODE_ADDED;
1952 typedef struct perm_data_t {
1953 const arch_register_t *in;
1954 const arch_register_t *out;
1958 * Simulate a be_Perm.
1960 * @param state the x87 state
1961 * @param irn the node that should be simulated (and patched)
1963 * @return NO_NODE_ADDED
1965 static int sim_Perm(x87_state *state, ir_node *irn)
1968 ir_node *pred = get_irn_n(irn, 0);
1971 /* handle only floating point Perms */
1972 if (! mode_is_float(get_irn_mode(pred)))
1973 return NO_NODE_ADDED;
1975 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1977 /* Perm is a pure virtual instruction on x87.
1978 All inputs must be on the FPU stack and are pairwise
1979 different from each other.
1980 So, all we need to do is to permutate the stack state. */
1981 n = get_irn_arity(irn);
1982 NEW_ARR_A(int, stack_pos, n);
1984 /* collect old stack positions */
1985 for (i = 0; i < n; ++i) {
1986 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1987 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1989 assert(idx >= 0 && "Perm argument not on x87 stack");
1993 /* now do the permutation */
1994 foreach_out_edge(irn, edge) {
1995 ir_node *proj = get_edge_src_irn(edge);
1996 const arch_register_t *out = x87_get_irn_register(proj);
1997 long num = get_Proj_proj(proj);
1999 assert(0 <= num && num < n && "More Proj's than Perm inputs");
2000 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
2002 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
2004 return NO_NODE_ADDED;
2008 * Kill any dead registers at block start by popping them from the stack.
2010 * @param sim the simulator handle
2011 * @param block the current block
2012 * @param start_state the x87 state at the begin of the block
2014 * @return the x87 state after dead register killed
2016 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
2018 x87_state *state = start_state;
2019 ir_node *first_insn = sched_first(block);
2020 ir_node *keep = NULL;
2021 unsigned live = vfp_live_args_after(sim, block, 0);
2023 int i, depth, num_pop;
2026 depth = x87_get_depth(state);
2027 for (i = depth - 1; i >= 0; --i) {
2028 int reg = x87_get_st_reg(state, i);
2030 if (! is_vfp_live(reg, live))
2031 kill_mask |= (1 << i);
2035 /* create a new state, will be changed */
2036 state = x87_clone_state(sim, state);
2038 DB((dbg, LEVEL_1, "Killing deads:\n"));
2039 DEBUG_ONLY(vfp_dump_live(live);)
2040 DEBUG_ONLY(x87_dump_stack(state);)
2042 if (kill_mask != 0 && live == 0) {
2043 /* special case: kill all registers */
2044 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
2045 if (ia32_cg_config.use_femms) {
2046 /* use FEMMS on AMD processors to clear all */
2047 keep = new_bd_ia32_femms(NULL, block);
2049 /* use EMMS to clear all */
2050 keep = new_bd_ia32_emms(NULL, block);
2052 sched_add_before(first_insn, keep);
2058 /* now kill registers */
2060 /* we can only kill from TOS, so bring them up */
2061 if (! (kill_mask & 1)) {
2062 /* search from behind, because we can to a double-pop */
2063 for (i = depth - 1; i >= 0; --i) {
2064 if (kill_mask & (1 << i)) {
2065 kill_mask &= ~(1 << i);
2072 x87_set_st(state, -1, keep, i);
2073 x87_create_fxch(state, first_insn, i);
2076 if ((kill_mask & 3) == 3) {
2077 /* we can do a double-pop */
2081 /* only a single pop */
2086 kill_mask >>= num_pop;
2087 keep = x87_create_fpop(state, first_insn, num_pop);
2095 * Run a simulation and fix all virtual instructions for a block.
2097 * @param sim the simulator handle
2098 * @param block the current block
2100 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
2103 blk_state *bl_state = x87_get_bl_state(sim, block);
2104 x87_state *state = bl_state->begin;
2105 ir_node *start_block;
2107 assert(state != NULL);
2108 /* already processed? */
2109 if (bl_state->end != NULL)
2112 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2113 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2114 DEBUG_ONLY(x87_dump_stack(state);)
2116 /* at block begin, kill all dead registers */
2117 state = x87_kill_deads(sim, block, state);
2118 /* create a new state, will be changed */
2119 state = x87_clone_state(sim, state);
2121 /* beware, n might change */
2122 for (n = sched_first(block); !sched_is_end(n); n = next) {
2125 ir_op *op = get_irn_op(n);
2128 * get the next node to be simulated here.
2129 * n might be completely removed from the schedule-
2131 next = sched_next(n);
2132 if (op->ops.generic != NULL) {
2133 func = (sim_func)op->ops.generic;
2136 node_inserted = (*func)(state, n);
2139 * sim_func might have added an additional node after n,
2140 * so update next node
2141 * beware: n must not be changed by sim_func
2142 * (i.e. removed from schedule) in this case
2144 if (node_inserted != NO_NODE_ADDED)
2145 next = sched_next(n);
2149 start_block = get_irg_start_block(get_irn_irg(block));
2151 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
2153 /* check if the state must be shuffled */
2154 foreach_block_succ(block, edge) {
2155 ir_node *succ = get_edge_src_irn(edge);
2156 blk_state *succ_state;
2158 if (succ == start_block)
2161 succ_state = x87_get_bl_state(sim, succ);
2163 if (succ_state->begin == NULL) {
2164 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2165 DEBUG_ONLY(x87_dump_stack(state);)
2166 succ_state->begin = state;
2168 waitq_put(sim->worklist, succ);
2170 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2171 /* There is already a begin state for the successor, bad.
2172 Do the necessary permutations.
2173 Note that critical edges are removed, so this is always possible:
2174 If the successor has more than one possible input, then it must
2177 x87_shuffle(sim, block, state, succ, succ_state->begin);
2180 bl_state->end = state;
2184 * Register a simulator function.
2186 * @param op the opcode to simulate
2187 * @param func the simulator function for the opcode
2189 static void register_sim(ir_op *op, sim_func func)
2191 assert(op->ops.generic == NULL);
2192 op->ops.generic = (op_func) func;
2196 * Create a new x87 simulator.
2198 * @param sim a simulator handle, will be initialized
2199 * @param irg the current graph
2201 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
2203 obstack_init(&sim->obst);
2204 sim->blk_states = pmap_create();
2205 sim->n_idx = get_irg_last_idx(irg);
2206 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
2208 DB((dbg, LEVEL_1, "--------------------------------\n"
2209 "x87 Simulator started for %+F\n", irg));
2211 /* set the generic function pointer of instruction we must simulate */
2212 ir_clear_opcodes_generic_func();
2214 register_sim(op_ia32_Asm, sim_Asm);
2215 register_sim(op_ia32_Call, sim_Call);
2216 register_sim(op_ia32_vfld, sim_fld);
2217 register_sim(op_ia32_vfild, sim_fild);
2218 register_sim(op_ia32_vfld1, sim_fld1);
2219 register_sim(op_ia32_vfldz, sim_fldz);
2220 register_sim(op_ia32_vfadd, sim_fadd);
2221 register_sim(op_ia32_vfsub, sim_fsub);
2222 register_sim(op_ia32_vfmul, sim_fmul);
2223 register_sim(op_ia32_vfdiv, sim_fdiv);
2224 register_sim(op_ia32_vfprem, sim_fprem);
2225 register_sim(op_ia32_vfabs, sim_fabs);
2226 register_sim(op_ia32_vfchs, sim_fchs);
2227 register_sim(op_ia32_vfist, sim_fist);
2228 register_sim(op_ia32_vfisttp, sim_fisttp);
2229 register_sim(op_ia32_vfst, sim_fst);
2230 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2231 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2232 register_sim(op_ia32_vFucomi, sim_Fucom);
2233 register_sim(op_be_Copy, sim_Copy);
2234 register_sim(op_be_Return, sim_Return);
2235 register_sim(op_be_Perm, sim_Perm);
2236 register_sim(op_be_Keep, sim_Keep);
2240 * Destroy a x87 simulator.
2242 * @param sim the simulator handle
2244 static void x87_destroy_simulator(x87_simulator *sim)
2246 pmap_destroy(sim->blk_states);
2247 obstack_free(&sim->obst, NULL);
2248 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2252 * Pre-block walker: calculate the liveness information for the block
2253 * and store it into the sim->live cache.
2255 static void update_liveness_walker(ir_node *block, void *data)
2257 x87_simulator *sim = (x87_simulator*)data;
2258 update_liveness(sim, block);
2262 * Run a simulation and fix all virtual instructions for a graph.
2263 * Replaces all virtual floating point instructions and registers
2266 void ia32_x87_simulate_graph(ir_graph *irg)
2268 /* TODO improve code quality (less executed fxch) by using execfreqs */
2270 ir_node *block, *start_block;
2271 blk_state *bl_state;
2274 /* create the simulator */
2275 x87_init_simulator(&sim, irg);
2277 start_block = get_irg_start_block(irg);
2278 bl_state = x87_get_bl_state(&sim, start_block);
2280 /* start with the empty state */
2281 bl_state->begin = empty;
2284 sim.worklist = new_waitq();
2285 waitq_put(sim.worklist, start_block);
2287 be_assure_live_sets(irg);
2288 sim.lv = be_get_irg_liveness(irg);
2290 /* Calculate the liveness for all nodes. We must precalculate this info,
2291 * because the simulator adds new nodes (possible before Phi nodes) which
2292 * would let a lazy calculation fail.
2293 * On the other hand we reduce the computation amount due to
2294 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2296 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2300 block = (ir_node*)waitq_get(sim.worklist);
2301 x87_simulate_block(&sim, block);
2302 } while (! waitq_empty(sim.worklist));
2305 del_waitq(sim.worklist);
2306 x87_destroy_simulator(&sim);
2309 /* Initializes the x87 simulator. */
2310 void ia32_init_x87(void)
2312 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");