2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
36 #include "iredges_t.h"
47 #include "../belive_t.h"
48 #include "../besched_t.h"
49 #include "../benode_t.h"
50 #include "ia32_new_nodes.h"
51 #include "gen_ia32_new_nodes.h"
52 #include "gen_ia32_regalloc_if.h"
57 /* first and second binop index */
64 /* the store val index */
65 #define STORE_VAL_IDX 2
67 #define MASK_TOS(x) ((x) & (N_x87_REGS - 1))
69 /** the debug handle */
70 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
72 /* Forward declaration. */
73 typedef struct _x87_simulator x87_simulator;
76 * An exchange template.
77 * Note that our virtual functions have the same inputs
78 * and attributes as the real ones, so we can simple exchange
80 * Further, x87 supports inverse instructions, so we can handle them.
82 typedef struct _exchange_tmpl {
83 ir_op *normal_op; /**< the normal one */
84 ir_op *reverse_op; /**< the reverse one if exists */
85 ir_op *normal_pop_op; /**< the normal one with tos pop */
86 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
90 * An entry on the simulated x87 stack.
92 typedef struct _st_entry {
93 int reg_idx; /**< the virtual register index of this stack value */
94 ir_node *node; /**< the node that produced this value */
100 typedef struct _x87_state {
101 st_entry st[N_x87_REGS]; /**< the register stack */
102 int depth; /**< the current stack depth */
103 int tos; /**< position of the tos */
104 x87_simulator *sim; /**< The simulator. */
107 /** An empty state, used for blocks without fp instructions. */
108 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
109 static x87_state *empty = (x87_state *)&_empty;
112 NO_NODE_ADDED = 0, /**< No node was added. */
113 NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */
117 * The type of an instruction simulator function.
119 * @param state the x87 state
120 * @param n the node to be simulated
122 * @return NODE_ADDED if a node was added AFTER n in schedule,
125 typedef int (*sim_func)(x87_state *state, ir_node *n);
128 * A block state: Every block has a x87 state at the beginning and at the end.
130 typedef struct _blk_state {
131 x87_state *begin; /**< state at the begin or NULL if not assigned */
132 x87_state *end; /**< state at the end or NULL if not assigned */
135 #define PTR_TO_BLKSTATE(p) ((blk_state *)(p))
137 /** liveness bitset for vfp registers. */
138 typedef unsigned char vfp_liveness;
143 struct _x87_simulator {
144 struct obstack obst; /**< An obstack for fast allocating. */
145 pmap *blk_states; /**< Map blocks to states. */
146 const arch_env_t *arch_env; /**< The architecture environment. */
147 be_lv_t *lv; /**< intrablock liveness. */
148 vfp_liveness *live; /**< Liveness information. */
149 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
150 waitq *worklist; /**< Worklist of blocks that must be processed. */
154 * Returns the current stack depth.
156 * @param state the x87 state
158 * @return the x87 stack depth
160 static int x87_get_depth(const x87_state *state) {
162 } /* x87_get_depth */
165 * Return the virtual register index at st(pos).
167 * @param state the x87 state
168 * @param pos a stack position
170 * @return the vfp register index that produced the value at st(pos)
172 static int x87_get_st_reg(const x87_state *state, int pos) {
173 assert(pos < state->depth);
174 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
175 } /* x87_get_st_reg */
178 * Return the node at st(pos).
180 * @param state the x87 state
181 * @param pos a stack position
183 * @return the IR node that produced the value at st(pos)
185 static ir_node *x87_get_st_node(const x87_state *state, int pos) {
186 assert(pos < state->depth);
187 return state->st[MASK_TOS(state->tos + pos)].node;
188 } /* x87_get_st_node */
192 * Dump the stack for debugging.
194 * @param state the x87 state
196 static void x87_dump_stack(const x87_state *state) {
199 for (i = state->depth - 1; i >= 0; --i) {
200 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
201 x87_get_st_node(state, i)));
203 DB((dbg, LEVEL_2, "<-- TOS\n"));
204 } /* x87_dump_stack */
205 #endif /* DEBUG_libfirm */
208 * Set a virtual register to st(pos).
210 * @param state the x87 state
211 * @param reg_idx the vfp register index that should be set
212 * @param node the IR node that produces the value of the vfp register
213 * @param pos the stack position where the new value should be entered
215 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
216 assert(0 < state->depth);
217 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
218 state->st[MASK_TOS(state->tos + pos)].node = node;
220 DB((dbg, LEVEL_2, "After SET_REG: "));
221 DEBUG_ONLY(x87_dump_stack(state));
225 * Set the tos virtual register.
227 * @param state the x87 state
228 * @param reg_idx the vfp register index that should be set
229 * @param node the IR node that produces the value of the vfp register
231 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
232 x87_set_st(state, reg_idx, node, 0);
236 * Swap st(0) with st(pos).
238 * @param state the x87 state
239 * @param pos the stack position to change the tos with
241 static void x87_fxch(x87_state *state, int pos) {
243 assert(pos < state->depth);
245 entry = state->st[MASK_TOS(state->tos + pos)];
246 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
247 state->st[MASK_TOS(state->tos)] = entry;
249 DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state));
253 * Convert a virtual register to the stack index.
255 * @param state the x87 state
256 * @param reg_idx the register vfp index
258 * @return the stack position where the register is stacked
259 * or -1 if the virtual register was not found
261 static int x87_on_stack(const x87_state *state, int reg_idx) {
262 int i, tos = state->tos;
264 for (i = 0; i < state->depth; ++i)
265 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
271 * Push a virtual Register onto the stack, double pushed allowed.
273 * @param state the x87 state
274 * @param reg_idx the register vfp index
275 * @param node the node that produces the value of the vfp register
277 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
278 assert(state->depth < N_x87_REGS && "stack overrun");
281 state->tos = MASK_TOS(state->tos - 1);
282 state->st[state->tos].reg_idx = reg_idx;
283 state->st[state->tos].node = node;
285 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state));
289 * Push a virtual Register onto the stack, double pushes are NOT allowed.
291 * @param state the x87 state
292 * @param reg_idx the register vfp index
293 * @param node the node that produces the value of the vfp register
294 * @param dbl_push if != 0 double pushes are allowed
296 static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
297 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
299 x87_push_dbl(state, reg_idx, node);
303 * Pop a virtual Register from the stack.
305 * @param state the x87 state
307 static void x87_pop(x87_state *state) {
308 assert(state->depth > 0 && "stack underrun");
311 state->tos = MASK_TOS(state->tos + 1);
313 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state));
317 * Returns the block state of a block.
319 * @param sim the x87 simulator handle
320 * @param block the current block
322 * @return the block state
324 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
325 pmap_entry *entry = pmap_find(sim->blk_states, block);
328 blk_state *bl_state = obstack_alloc(&sim->obst, sizeof(*bl_state));
329 bl_state->begin = NULL;
330 bl_state->end = NULL;
332 pmap_insert(sim->blk_states, block, bl_state);
336 return PTR_TO_BLKSTATE(entry->value);
337 } /* x87_get_bl_state */
340 * Creates a new x87 state.
342 * @param sim the x87 simulator handle
344 * @return a new x87 state
346 static x87_state *x87_alloc_state(x87_simulator *sim) {
347 x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
351 } /* x87_alloc_state */
356 * @param sim the x87 simulator handle
357 * @param src the x87 state that will be cloned
359 * @return a cloned copy of the src state
361 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
362 x87_state *res = x87_alloc_state(sim);
364 memcpy(res, src, sizeof(*res));
366 } /* x87_clone_state */
369 * Patch a virtual instruction into a x87 one and return
370 * the node representing the result value.
372 * @param n the IR node to patch
373 * @param op the x87 opcode to patch in
375 static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
376 ir_mode *mode = get_irn_mode(n);
381 if (mode == mode_T) {
382 /* patch all Proj's */
383 const ir_edge_t *edge;
385 foreach_out_edge(n, edge) {
386 ir_node *proj = get_edge_src_irn(edge);
388 mode = get_irn_mode(proj);
389 if (mode_is_float(mode)) {
391 set_irn_mode(proj, mode_E);
395 } else if (mode_is_float(mode))
396 set_irn_mode(n, mode_E);
398 } /* x87_patch_insn */
401 * Returns the first Proj of a mode_T node having a given mode.
403 * @param n the mode_T node
404 * @param m the desired mode of the Proj
405 * @return The first Proj of mode @p m found or NULL.
407 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
408 const ir_edge_t *edge;
410 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
412 foreach_out_edge(n, edge) {
413 ir_node *proj = get_edge_src_irn(edge);
414 if (get_irn_mode(proj) == m)
419 } /* get_irn_Proj_for_mode */
422 * Wrap the arch_* function here so we can check for errors.
424 static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
425 const arch_register_t *res;
427 res = arch_get_irn_register(sim->arch_env, irn);
428 assert(res->reg_class->regs == ia32_vfp_regs);
430 } /* x87_get_irn_register */
432 /* -------------- x87 perm --------------- */
435 * Creates a fxch for shuffle.
437 * @param state the x87 state
438 * @param pos parameter for fxch
439 * @param block the block were fxch is inserted
441 * Creates a new fxch node and reroute the user of the old node
444 * @return the fxch node
446 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
448 ia32_x87_attr_t *attr;
450 fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E);
451 attr = get_ia32_x87_attr(fxch);
452 attr->x87[0] = &ia32_st_regs[pos];
453 attr->x87[2] = &ia32_st_regs[0];
457 x87_fxch(state, pos);
459 } /* x87_fxch_shuffle */
462 * Calculate the necessary permutations to reach dst_state.
464 * These permutations are done with fxch instructions and placed
465 * at the end of the block.
467 * Note that critical edges are removed here, so we need only
468 * a shuffle if the current block has only one successor.
470 * @param sim the simulator handle
471 * @param block the current block
472 * @param state the current x87 stack state, might be modified
473 * @param dst_block the destination block
474 * @param dst_state destination state
478 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
479 x87_state *state, ir_node *dst_block,
480 const x87_state *dst_state)
482 int i, n_cycles, k, ri;
483 unsigned cycles[4], all_mask;
484 char cycle_idx[4][8];
485 ir_node *fxch, *before, *after;
489 assert(state->depth == dst_state->depth);
491 /* Some mathematics here:
492 If we have a cycle of length n that includes the tos,
493 we need n-1 exchange operations.
494 We can always add the tos and restore it, so we need
495 n+1 exchange operations for a cycle not containing the tos.
496 So, the maximum of needed operations is for a cycle of 7
497 not including the tos == 8.
498 This is the same number of ops we would need for using stores,
499 so exchange is cheaper (we save the loads).
500 On the other hand, we might need an additional exchange
501 in the next block to bring one operand on top, so the
502 number of ops in the first case is identical.
503 Further, no more than 4 cycles can exists (4 x 2).
505 all_mask = (1 << (state->depth)) - 1;
507 for (n_cycles = 0; all_mask; ++n_cycles) {
508 int src_idx, dst_idx;
510 /* find the first free slot */
511 for (i = 0; i < state->depth; ++i) {
512 if (all_mask & (1 << i)) {
513 all_mask &= ~(1 << i);
515 /* check if there are differences here */
516 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
522 /* no more cycles found */
527 cycles[n_cycles] = (1 << i);
528 cycle_idx[n_cycles][k++] = i;
529 for (src_idx = i; ; src_idx = dst_idx) {
530 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
532 if ((all_mask & (1 << dst_idx)) == 0)
535 cycle_idx[n_cycles][k++] = dst_idx;
536 cycles[n_cycles] |= (1 << dst_idx);
537 all_mask &= ~(1 << dst_idx);
539 cycle_idx[n_cycles][k] = -1;
543 /* no permutation needed */
547 /* Hmm: permutation needed */
548 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
549 DEBUG_ONLY(x87_dump_stack(state));
550 DB((dbg, LEVEL_2, " to\n"));
551 DEBUG_ONLY(x87_dump_stack(dst_state));
555 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
556 for (ri = 0; ri < n_cycles; ++ri) {
557 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
558 for (k = 0; cycle_idx[ri][k] != -1; ++k)
559 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
560 DB((dbg, LEVEL_2, "\n"));
567 * Find the place node must be insert.
568 * We have only one successor block, so the last instruction should
571 before = sched_last(block);
572 assert(is_cfop(before));
574 /* now do the permutations */
575 for (ri = 0; ri < n_cycles; ++ri) {
576 if ((cycles[ri] & 1) == 0) {
577 /* this cycle does not include the tos */
578 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
580 sched_add_after(after, fxch);
582 sched_add_before(before, fxch);
585 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
586 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
588 sched_add_after(after, fxch);
590 sched_add_before(before, fxch);
593 if ((cycles[ri] & 1) == 0) {
594 /* this cycle does not include the tos */
595 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
596 sched_add_after(after, fxch);
603 * Create a fxch node before another node.
605 * @param state the x87 state
606 * @param n the node after the fxch
607 * @param pos exchange st(pos) with st(0)
611 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
614 ia32_x87_attr_t *attr;
615 ir_graph *irg = get_irn_irg(n);
616 ir_node *block = get_nodes_block(n);
618 x87_fxch(state, pos);
620 fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E);
621 attr = get_ia32_x87_attr(fxch);
622 attr->x87[0] = &ia32_st_regs[pos];
623 attr->x87[2] = &ia32_st_regs[0];
627 sched_add_before(n, fxch);
628 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
630 } /* x87_create_fxch */
633 * Create a fpush before node n.
635 * @param state the x87 state
636 * @param n the node after the fpush
637 * @param pos push st(pos) on stack
638 * @param op_idx replace input op_idx of n with the fpush result
640 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
641 ir_node *fpush, *pred = get_irn_n(n, op_idx);
642 ia32_x87_attr_t *attr;
643 const arch_register_t *out = x87_get_irn_register(state->sim, pred);
645 x87_push_dbl(state, arch_register_get_index(out), pred);
647 fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
648 attr = get_ia32_x87_attr(fpush);
649 attr->x87[0] = &ia32_st_regs[pos];
650 attr->x87[2] = &ia32_st_regs[0];
653 sched_add_before(n, fpush);
655 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
656 } /* x87_create_fpush */
659 * Create a fpop before node n.
661 * @param state the x87 state
662 * @param n the node after the fpop
663 * @param num pop 1 or 2 values
665 * @return the fpop node
667 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
670 ia32_x87_attr_t *attr;
674 fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
675 attr = get_ia32_x87_attr(fpop);
676 attr->x87[0] = &ia32_st_regs[0];
677 attr->x87[1] = &ia32_st_regs[0];
678 attr->x87[2] = &ia32_st_regs[0];
681 sched_add_before(n, fpop);
682 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
687 } /* x87_create_fpop */
690 * Creates an fldz before node n
692 * @param state the x87 state
693 * @param n the node after the fldz
695 * @return the fldz node
697 static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
698 ir_graph *irg = get_irn_irg(n);
699 ir_node *block = get_nodes_block(n);
702 fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
704 sched_add_before(n, fldz);
705 DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
708 x87_push(state, regidx, fldz);
713 /* --------------------------------- liveness ------------------------------------------ */
716 * The liveness transfer function.
717 * Updates a live set over a single step from a given node to its predecessor.
718 * Everything defined at the node is removed from the set, the uses of the node get inserted.
720 * @param sim The simulator handle.
721 * @param irn The node at which liveness should be computed.
722 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
723 * the registers live after irn.
725 * @return The live bitset.
727 static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live)
730 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
731 const arch_env_t *arch_env = sim->arch_env;
733 if (get_irn_mode(irn) == mode_T) {
734 const ir_edge_t *edge;
736 foreach_out_edge(irn, edge) {
737 ir_node *proj = get_edge_src_irn(edge);
739 if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
740 const arch_register_t *reg = x87_get_irn_register(sim, proj);
741 live &= ~(1 << arch_register_get_index(reg));
746 if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
747 const arch_register_t *reg = x87_get_irn_register(sim, irn);
748 live &= ~(1 << arch_register_get_index(reg));
751 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
752 ir_node *op = get_irn_n(irn, i);
754 if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
755 const arch_register_t *reg = x87_get_irn_register(sim, op);
756 live |= 1 << arch_register_get_index(reg);
760 } /* vfp_liveness_transfer */
763 * Put all live virtual registers at the end of a block into a bitset.
765 * @param sim the simulator handle
766 * @param lv the liveness information
767 * @param bl the block
769 * @return The live bitset at the end of this block
771 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
774 vfp_liveness live = 0;
775 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
776 const arch_env_t *arch_env = sim->arch_env;
777 const be_lv_t *lv = sim->lv;
779 be_lv_foreach(lv, block, be_lv_state_end, i) {
780 const arch_register_t *reg;
781 const ir_node *node = be_lv_get_irn(lv, block, i);
782 if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node))
785 reg = x87_get_irn_register(sim, node);
786 live |= 1 << arch_register_get_index(reg);
790 } /* vfp_liveness_end_of_block */
792 /** get the register mask from an arch_register */
793 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
796 * Return a bitset of argument registers which are live at the end of a node.
798 * @param sim the simulator handle
799 * @param pos the node
800 * @param kill kill mask for the output registers
802 * @return The live bitset.
804 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
806 unsigned idx = get_irn_idx(pos);
808 assert(idx < sim->n_idx);
809 return sim->live[idx] & ~kill;
810 } /* vfp_live_args_after */
813 * Calculate the liveness for a whole block and cache it.
815 * @param sim the simulator handle
816 * @param lv the liveness handle
817 * @param block the block
819 static void update_liveness(x87_simulator *sim, ir_node *block) {
820 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
824 /* now iterate through the block backward and cache the results */
825 sched_foreach_reverse(block, irn) {
826 /* stop at the first Phi: this produces the live-in */
830 idx = get_irn_idx(irn);
831 sim->live[idx] = live;
833 live = vfp_liveness_transfer(sim, irn, live);
835 idx = get_irn_idx(block);
836 sim->live[idx] = live;
837 } /* update_liveness */
840 * Returns true if a register is live in a set.
842 * @param reg_idx the vfp register index
843 * @param live a live bitset
845 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
849 * Dump liveness info.
851 * @param live the live bitset
853 static void vfp_dump_live(vfp_liveness live) {
856 DB((dbg, LEVEL_2, "Live after: "));
857 for (i = 0; i < 8; ++i) {
858 if (live & (1 << i)) {
859 DB((dbg, LEVEL_2, "vf%d ", i));
862 DB((dbg, LEVEL_2, "\n"));
863 } /* vfp_dump_live */
864 #endif /* DEBUG_libfirm */
866 /* --------------------------------- simulators ---------------------------------------- */
868 #define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0)
871 * Simulate a virtual binop.
873 * @param state the x87 state
874 * @param n the node that should be simulated (and patched)
875 * @param tmpl the template containing the 4 possible x87 opcodes
877 * @return NO_NODE_ADDED
879 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
880 int op2_idx = 0, op1_idx;
881 int out_idx, do_pop = 0;
882 ia32_x87_attr_t *attr;
883 ir_node *patched_insn;
885 x87_simulator *sim = state->sim;
886 const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
887 const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2));
888 const arch_register_t *out = x87_get_irn_register(sim, n);
889 int reg_index_1 = arch_register_get_index(op1);
890 int reg_index_2 = arch_register_get_index(op2);
891 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
893 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
894 arch_register_get_name(op1), arch_register_get_name(op2),
895 arch_register_get_name(out)));
896 DEBUG_ONLY(vfp_dump_live(live));
897 DB((dbg, LEVEL_1, "Stack before: "));
898 DEBUG_ONLY(x87_dump_stack(state));
900 op1_idx = x87_on_stack(state, reg_index_1);
901 assert(op1_idx >= 0);
903 if (reg_index_2 != REG_VFP_NOREG) {
904 /* second operand is a vfp register */
905 op2_idx = x87_on_stack(state, reg_index_2);
906 assert(op2_idx >= 0);
908 if (is_vfp_live(arch_register_get_index(op2), live)) {
909 /* Second operand is live. */
911 if (is_vfp_live(arch_register_get_index(op1), live)) {
912 /* Both operands are live: push the first one.
913 This works even for op1 == op2. */
914 x87_create_fpush(state, n, op1_idx, BINOP_IDX_2);
915 /* now do fxxx (tos=tos X op) */
919 dst = tmpl->normal_op;
921 /* Second live, first operand is dead here, bring it to tos. */
923 x87_create_fxch(state, n, op1_idx);
928 /* now do fxxx (tos=tos X op) */
930 dst = tmpl->normal_op;
933 /* Second operand is dead. */
934 if (is_vfp_live(arch_register_get_index(op1), live)) {
935 /* First operand is live: bring second to tos. */
937 x87_create_fxch(state, n, op2_idx);
942 /* now do fxxxr (tos = op X tos) */
944 dst = tmpl->reverse_op;
946 /* Both operands are dead here, pop them from the stack. */
949 /* Both are identically and on tos, no pop needed. */
950 /* here fxxx (tos = tos X tos) */
951 dst = tmpl->normal_op;
954 /* now do fxxxp (op = op X tos, pop) */
955 dst = tmpl->normal_pop_op;
959 } else if (op1_idx == 0) {
960 assert(op1_idx != op2_idx);
961 /* now do fxxxrp (op = tos X op, pop) */
962 dst = tmpl->reverse_pop_op;
966 /* Bring the second on top. */
967 x87_create_fxch(state, n, op2_idx);
968 if (op1_idx == op2_idx) {
969 /* Both are identically and on tos now, no pop needed. */
972 /* use fxxx (tos = tos X tos) */
973 dst = tmpl->normal_op;
976 /* op2 is on tos now */
978 /* use fxxxp (op = op X tos, pop) */
979 dst = tmpl->normal_pop_op;
987 /* second operand is an address mode */
988 if (is_vfp_live(arch_register_get_index(op1), live)) {
989 /* first operand is live: push it here */
990 x87_create_fpush(state, n, op1_idx, BINOP_IDX_1);
992 /* use fxxx (tos = tos X mem) */
993 dst = tmpl->normal_op;
996 /* first operand is dead: bring it to tos */
998 x87_create_fxch(state, n, op1_idx);
1002 /* use fxxxp (tos = tos X mem) */
1003 dst = tmpl->normal_op;
1008 patched_insn = x87_patch_insn(n, dst);
1009 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1014 /* patch the operation */
1015 attr = get_ia32_x87_attr(n);
1016 attr->x87[0] = op1 = &ia32_st_regs[op1_idx];
1017 if (reg_index_2 != REG_VFP_NOREG) {
1018 attr->x87[1] = op2 = &ia32_st_regs[op2_idx];
1020 attr->x87[2] = out = &ia32_st_regs[out_idx];
1022 if (reg_index_2 != REG_VFP_NOREG) {
1023 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1024 arch_register_get_name(op1), arch_register_get_name(op2),
1025 arch_register_get_name(out)));
1027 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1028 arch_register_get_name(op1),
1029 arch_register_get_name(out)));
1032 return NO_NODE_ADDED;
1036 * Simulate a virtual Unop.
1038 * @param state the x87 state
1039 * @param n the node that should be simulated (and patched)
1040 * @param op the x87 opcode that will replace n's opcode
1042 * @return NO_NODE_ADDED
1044 static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
1045 int op1_idx, out_idx;
1046 x87_simulator *sim = state->sim;
1047 const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
1048 const arch_register_t *out = x87_get_irn_register(sim, n);
1049 ia32_x87_attr_t *attr;
1050 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1052 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1053 DEBUG_ONLY(vfp_dump_live(live));
1055 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1057 if (is_vfp_live(arch_register_get_index(op1), live)) {
1058 /* push the operand here */
1059 x87_create_fpush(state, n, op1_idx, UNOP_IDX);
1063 /* operand is dead, bring it to tos */
1065 x87_create_fxch(state, n, op1_idx);
1070 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1072 attr = get_ia32_x87_attr(n);
1073 attr->x87[0] = op1 = &ia32_st_regs[0];
1074 attr->x87[2] = out = &ia32_st_regs[0];
1075 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1077 return NO_NODE_ADDED;
1081 * Simulate a virtual Load instruction.
1083 * @param state the x87 state
1084 * @param n the node that should be simulated (and patched)
1085 * @param op the x87 opcode that will replace n's opcode
1087 * @return NO_NODE_ADDED
1089 static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
1090 const arch_register_t *out = x87_get_irn_register(state->sim, n);
1091 ia32_x87_attr_t *attr;
1093 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1094 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1095 assert(out == x87_get_irn_register(state->sim, n));
1096 attr = get_ia32_x87_attr(n);
1097 attr->x87[2] = out = &ia32_st_regs[0];
1098 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1100 return NO_NODE_ADDED;
1104 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1106 * @param store The store
1107 * @param old_val The former value
1108 * @param new_val The new value
1110 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) {
1111 const ir_edge_t *edge, *ne;
1113 foreach_out_edge_safe(old_val, edge, ne) {
1114 ir_node *user = get_edge_src_irn(edge);
1116 if (! user || user == store)
1119 /* if the user is scheduled after the store: rewire */
1120 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1122 /* find the input of the user pointing to the old value */
1123 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1124 if (get_irn_n(user, i) == old_val)
1125 set_irn_n(user, i, new_val);
1129 } /* collect_and_rewire_users */
1132 * Simulate a virtual Store.
1134 * @param state the x87 state
1135 * @param n the node that should be simulated (and patched)
1136 * @param op the x87 store opcode
1137 * @param op_p the x87 store and pop opcode
1139 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
1140 x87_simulator *sim = state->sim;
1141 ir_node *val = get_irn_n(n, STORE_VAL_IDX);
1142 const arch_register_t *op2 = x87_get_irn_register(sim, val);
1143 unsigned live = vfp_live_args_after(sim, n, 0);
1144 int insn = NO_NODE_ADDED;
1145 ia32_x87_attr_t *attr;
1146 int op2_reg_idx, op2_idx, depth;
1147 int live_after_node;
1150 op2_reg_idx = arch_register_get_index(op2);
1151 if (op2_reg_idx == REG_VFP_UKNWN) {
1152 /* just take any value from stack */
1153 if(state->depth > 0) {
1155 DEBUG_ONLY(op2 = NULL);
1156 live_after_node = 1;
1158 /* produce a new value which we will consume immediately */
1159 x87_create_fldz(state, n, op2_reg_idx);
1160 live_after_node = 0;
1161 op2_idx = x87_on_stack(state, op2_reg_idx);
1162 assert(op2_idx >= 0);
1165 op2_idx = x87_on_stack(state, op2_reg_idx);
1166 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1167 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1168 assert(op2_idx >= 0);
1171 mode = get_ia32_ls_mode(n);
1172 depth = x87_get_depth(state);
1174 if (live_after_node) {
1176 Problem: fst doesn't support mode_E (spills), only fstp does
1178 - stack not full: push value and fstp
1179 - stack full: fstp value and load again
1181 if (mode == mode_E) {
1182 if (depth < N_x87_REGS) {
1183 /* ok, we have a free register: push + fstp */
1184 x87_create_fpush(state, n, op2_idx, STORE_VAL_IDX);
1186 x87_patch_insn(n, op_p);
1188 ir_node *vfld, *mem, *block, *rproj, *mproj;
1191 /* stack full here: need fstp + load */
1193 x87_patch_insn(n, op_p);
1195 block = get_nodes_block(n);
1196 irg = get_irn_irg(n);
1197 vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
1199 /* copy all attributes */
1200 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1201 if (is_ia32_use_frame(n))
1202 set_ia32_use_frame(vfld);
1203 set_ia32_am_flavour(vfld, get_ia32_am_flavour(n));
1204 set_ia32_op_type(vfld, ia32_am_Source);
1205 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1206 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1207 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1209 rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1210 mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
1211 mem = get_irn_Proj_for_mode(n, mode_M);
1213 assert(mem && "Store memory not found");
1215 arch_set_irn_register(sim->arch_env, rproj, op2);
1217 /* reroute all former users of the store memory to the load memory */
1218 edges_reroute(mem, mproj, irg);
1219 /* set the memory input of the load to the store memory */
1220 set_irn_n(vfld, 2, mem);
1222 sched_add_after(n, vfld);
1223 sched_add_after(vfld, rproj);
1225 /* rewire all users, scheduled after the store, to the loaded value */
1226 collect_and_rewire_users(n, val, rproj);
1231 /* we can only store the tos to memory */
1233 x87_create_fxch(state, n, op2_idx);
1235 /* mode != mode_E -> use normal fst */
1236 x87_patch_insn(n, op);
1239 /* we can only store the tos to memory */
1241 x87_create_fxch(state, n, op2_idx);
1244 x87_patch_insn(n, op_p);
1247 attr = get_ia32_x87_attr(n);
1248 attr->x87[1] = op2 = &ia32_st_regs[0];
1249 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1254 #define _GEN_BINOP(op, rev) \
1255 static int sim_##op(x87_state *state, ir_node *n) { \
1256 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1257 return sim_binop(state, n, &tmpl); \
1260 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1261 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1263 #define GEN_LOAD2(op, nop) \
1264 static int sim_##op(x87_state *state, ir_node *n) { \
1265 return sim_load(state, n, op_ia32_##nop); \
1268 #define GEN_LOAD(op) GEN_LOAD2(op, op)
1270 #define GEN_UNOP(op) \
1271 static int sim_##op(x87_state *state, ir_node *n) { \
1272 return sim_unop(state, n, op_ia32_##op); \
1275 #define GEN_STORE(op) \
1276 static int sim_##op(x87_state *state, ir_node *n) { \
1277 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1299 * Simulate a fCondJmp.
1301 * @param state the x87 state
1302 * @param n the node that should be simulated (and patched)
1304 * @return NO_NODE_ADDED
1306 static int sim_fCondJmp(x87_state *state, ir_node *n) {
1310 ia32_x87_attr_t *attr;
1312 x87_simulator *sim = state->sim;
1313 ir_node *op1_node = get_irn_n(n, n_ia32_vfCondJmp_left);
1314 ir_node *op2_node = get_irn_n(n, n_ia32_vfCondJmp_right);
1315 const arch_register_t *op1 = x87_get_irn_register(sim, op1_node);
1316 const arch_register_t *op2 = x87_get_irn_register(sim, op2_node);
1317 int reg_index_1 = arch_register_get_index(op1);
1318 int reg_index_2 = arch_register_get_index(op2);
1319 unsigned live = vfp_live_args_after(sim, n, 0);
1321 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1322 arch_register_get_name(op1), arch_register_get_name(op2)));
1323 DEBUG_ONLY(vfp_dump_live(live));
1324 DB((dbg, LEVEL_1, "Stack before: "));
1325 DEBUG_ONLY(x87_dump_stack(state));
1327 op1_idx = x87_on_stack(state, reg_index_1);
1328 assert(op1_idx >= 0);
1330 /* BEWARE: check for comp a,a cases, they might happen */
1331 if (reg_index_2 != REG_VFP_NOREG) {
1332 /* second operand is a vfp register */
1333 op2_idx = x87_on_stack(state, reg_index_2);
1334 assert(op2_idx >= 0);
1336 if (is_vfp_live(arch_register_get_index(op2), live)) {
1337 /* second operand is live */
1339 if (is_vfp_live(arch_register_get_index(op1), live)) {
1340 /* both operands are live */
1343 /* res = tos X op */
1344 dst = op_ia32_fcomJmp;
1345 } else if (op2_idx == 0) {
1346 /* res = op X tos */
1347 dst = op_ia32_fcomrJmp;
1349 /* bring the first one to tos */
1350 x87_create_fxch(state, n, op1_idx);
1354 /* res = tos X op */
1355 dst = op_ia32_fcomJmp;
1358 /* second live, first operand is dead here, bring it to tos.
1359 This means further, op1_idx != op2_idx. */
1360 assert(op1_idx != op2_idx);
1362 x87_create_fxch(state, n, op1_idx);
1367 /* res = tos X op, pop */
1368 dst = op_ia32_fcompJmp;
1372 /* second operand is dead */
1373 if (is_vfp_live(arch_register_get_index(op1), live)) {
1374 /* first operand is live: bring second to tos.
1375 This means further, op1_idx != op2_idx. */
1376 assert(op1_idx != op2_idx);
1378 x87_create_fxch(state, n, op2_idx);
1383 /* res = op X tos, pop */
1384 dst = op_ia32_fcomrpJmp;
1387 /* both operands are dead here, check first for identity. */
1388 if (op1_idx == op2_idx) {
1389 /* identically, one pop needed */
1391 x87_create_fxch(state, n, op1_idx);
1395 /* res = tos X op, pop */
1396 dst = op_ia32_fcompJmp;
1399 /* different, move them to st and st(1) and pop both.
1400 The tricky part is to get one into st(1).*/
1401 else if (op2_idx == 1) {
1402 /* good, second operand is already in the right place, move the first */
1404 /* bring the first on top */
1405 x87_create_fxch(state, n, op1_idx);
1406 assert(op2_idx != 0);
1409 /* res = tos X op, pop, pop */
1410 dst = op_ia32_fcomppJmp;
1412 } else if (op1_idx == 1) {
1413 /* good, first operand is already in the right place, move the second */
1415 /* bring the first on top */
1416 x87_create_fxch(state, n, op2_idx);
1417 assert(op1_idx != 0);
1420 dst = op_ia32_fcomrppJmp;
1423 /* if one is already the TOS, we need two fxch */
1425 /* first one is TOS, move to st(1) */
1426 x87_create_fxch(state, n, 1);
1427 assert(op2_idx != 1);
1429 x87_create_fxch(state, n, op2_idx);
1431 /* res = op X tos, pop, pop */
1432 dst = op_ia32_fcomrppJmp;
1434 } else if (op2_idx == 0) {
1435 /* second one is TOS, move to st(1) */
1436 x87_create_fxch(state, n, 1);
1437 assert(op1_idx != 1);
1439 x87_create_fxch(state, n, op1_idx);
1441 /* res = tos X op, pop, pop */
1442 dst = op_ia32_fcomppJmp;
1445 /* none of them is either TOS or st(1), 3 fxch needed */
1446 x87_create_fxch(state, n, op2_idx);
1447 assert(op1_idx != 0);
1448 x87_create_fxch(state, n, 1);
1450 x87_create_fxch(state, n, op1_idx);
1452 /* res = tos X op, pop, pop */
1453 dst = op_ia32_fcomppJmp;
1460 /* second operand is an address mode */
1461 if (is_vfp_live(arch_register_get_index(op1), live)) {
1462 /* first operand is live: bring it to TOS */
1464 x87_create_fxch(state, n, op1_idx);
1467 dst = op_ia32_fcomJmp;
1469 /* first operand is dead: bring it to tos */
1471 x87_create_fxch(state, n, op1_idx);
1474 dst = op_ia32_fcompJmp;
1479 x87_patch_insn(n, dst);
1480 assert(pop_cnt < 3);
1486 /* patch the operation */
1487 attr = get_ia32_x87_attr(n);
1488 op1 = &ia32_st_regs[op1_idx];
1491 op2 = &ia32_st_regs[op2_idx];
1494 attr->x87[2] = NULL;
1497 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1498 arch_register_get_name(op1), arch_register_get_name(op2)));
1500 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1501 arch_register_get_name(op1)));
1503 return NO_NODE_ADDED;
1504 } /* sim_fCondJmp */
1507 int sim_Keep(x87_state *state, ir_node *node)
1510 const arch_register_t *op_reg;
1515 op = get_irn_n(node, 0);
1516 op_reg = arch_get_irn_register(state->sim->arch_env, op);
1517 if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1518 return NO_NODE_ADDED;
1520 reg_id = arch_register_get_index(op_reg);
1521 live = vfp_live_args_after(state->sim, node, 0);
1523 op_stack_idx = x87_on_stack(state, reg_id);
1524 if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
1525 x87_create_fpop(state, sched_next(node), 1);
1529 return NO_NODE_ADDED;
1533 void keep_float_node_alive(x87_state *state, ir_node *node)
1539 const arch_register_class_t *cls;
1541 irg = get_irn_irg(node);
1542 block = get_nodes_block(node);
1543 cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1);
1545 keep = be_new_Keep(cls, irg, block, 1, in);
1547 assert(sched_is_scheduled(node));
1548 sched_add_after(node, keep);
1552 * Create a copy of a node. Recreate the node if it's a constant.
1554 * @param state the x87 state
1555 * @param n the node to be copied
1557 * @return the copy of n
1559 static ir_node *create_Copy(x87_state *state, ir_node *n) {
1560 x87_simulator *sim = state->sim;
1561 ir_graph *irg = get_irn_irg(n);
1562 dbg_info *n_dbg = get_irn_dbg_info(n);
1563 ir_mode *mode = get_irn_mode(n);
1564 ir_node *block = get_nodes_block(n);
1565 ir_node *pred = get_irn_n(n, 0);
1566 ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
1568 const arch_register_t *out;
1569 const arch_register_t *op1;
1570 ia32_x87_attr_t *attr;
1572 /* Do not copy constants, recreate them. */
1573 switch (get_ia32_irn_opcode(pred)) {
1574 case iro_ia32_Unknown_VFP:
1576 cnstr = new_rd_ia32_fldz;
1579 cnstr = new_rd_ia32_fld1;
1581 case iro_ia32_fldpi:
1582 cnstr = new_rd_ia32_fldpi;
1584 case iro_ia32_fldl2e:
1585 cnstr = new_rd_ia32_fldl2e;
1587 case iro_ia32_fldl2t:
1588 cnstr = new_rd_ia32_fldl2t;
1590 case iro_ia32_fldlg2:
1591 cnstr = new_rd_ia32_fldlg2;
1593 case iro_ia32_fldln2:
1594 cnstr = new_rd_ia32_fldln2;
1600 out = x87_get_irn_register(sim, n);
1601 op1 = x87_get_irn_register(sim, pred);
1603 if (cnstr != NULL) {
1604 /* copy a constant */
1605 res = (*cnstr)(n_dbg, irg, block, mode);
1607 x87_push(state, arch_register_get_index(out), res);
1609 attr = get_ia32_x87_attr(res);
1610 attr->x87[2] = &ia32_st_regs[0];
1612 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1614 res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
1616 x87_push(state, arch_register_get_index(out), res);
1618 attr = get_ia32_x87_attr(res);
1619 attr->x87[0] = &ia32_st_regs[op1_idx];
1620 attr->x87[2] = &ia32_st_regs[0];
1622 arch_set_irn_register(sim->arch_env, res, out);
1628 * Simulate a be_Copy.
1630 * @param state the x87 state
1631 * @param n the node that should be simulated (and patched)
1633 * @return NO_NODE_ADDED
1635 static int sim_Copy(x87_state *state, ir_node *n) {
1638 const arch_register_t *out;
1639 const arch_register_t *op1;
1640 ir_node *node, *next;
1641 ia32_x87_attr_t *attr;
1642 int op1_idx, out_idx;
1645 ir_mode *mode = get_irn_mode(n);
1647 if (!mode_is_float(mode))
1651 pred = get_irn_n(n, 0);
1652 out = x87_get_irn_register(sim, n);
1653 op1 = x87_get_irn_register(sim, pred);
1654 live = vfp_live_args_after(sim, n, REGMASK(out));
1656 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1657 arch_register_get_name(op1), arch_register_get_name(out)));
1658 DEBUG_ONLY(vfp_dump_live(live));
1660 /* handle the infamous unknown value */
1661 if (arch_register_get_index(op1) == REG_VFP_UKNWN) {
1662 /* Operand is still live, a real copy. We need here an fpush that can
1663 hold a a register, so use the fpushCopy or recreate constants */
1664 node = create_Copy(state, n);
1666 assert(is_ia32_fldz(node));
1667 next = sched_next(n);
1670 sched_add_before(next, node);
1672 DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
1673 arch_get_irn_register(sim->arch_env, node)->name));
1674 return NO_NODE_ADDED;
1677 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1679 if (is_vfp_live(arch_register_get_index(op1), live)) {
1680 ir_node *pred = get_irn_n(n, 0);
1682 /* Operand is still live, a real copy. We need here an fpush that can
1683 hold a a register, so use the fpushCopy or recreate constants */
1684 node = create_Copy(state, n);
1686 /* We have to make sure the old value doesn't go dead (which can happen
1687 * when we recreate constants). As the simulator expected that value in
1688 * the pred blocks. This is unfortunate as removing it would save us 1
1689 * instruction, but we would have to rerun all the simulation to get
1692 next = sched_next(n);
1695 sched_add_before(next, node);
1697 if(get_irn_n_edges(pred) == 0) {
1698 keep_float_node_alive(state, pred);
1701 DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
1702 arch_get_irn_register(sim->arch_env, node)->name));
1704 out_idx = x87_on_stack(state, arch_register_get_index(out));
1706 if (out_idx >= 0 && out_idx != op1_idx) {
1707 /* Matze: out already on stack? how can this happen? */
1710 /* op1 must be killed and placed where out is */
1712 /* best case, simple remove and rename */
1713 x87_patch_insn(n, op_ia32_Pop);
1714 attr = get_ia32_x87_attr(n);
1715 attr->x87[0] = op1 = &ia32_st_regs[0];
1718 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1720 /* move op1 to tos, store and pop it */
1722 x87_create_fxch(state, n, op1_idx);
1725 x87_patch_insn(n, op_ia32_Pop);
1726 attr = get_ia32_x87_attr(n);
1727 attr->x87[0] = op1 = &ia32_st_regs[out_idx];
1730 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1732 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1734 /* just a virtual copy */
1735 x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
1736 /* don't remove the node to keep the verifier quiet :),
1737 the emitter won't emit any code for the node */
1740 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1741 exchange(n, get_unop_op(n));
1745 return NO_NODE_ADDED;
1749 * Returns the result proj of the call, or NULL if the result is not used
1751 static ir_node *get_call_result_proj(ir_node *call) {
1752 const ir_edge_t *edge;
1753 ir_node *resproj = NULL;
1755 /* search the result proj */
1756 foreach_out_edge(call, edge) {
1757 ir_node *proj = get_edge_src_irn(edge);
1758 long pn = get_Proj_proj(proj);
1760 if (pn == pn_be_Call_first_res) {
1765 if (resproj == NULL) {
1769 /* the result proj is connected to a Keep and maybe other nodes */
1770 foreach_out_edge(resproj, edge) {
1771 ir_node *pred = get_edge_src_irn(edge);
1772 if (!be_is_Keep(pred)) {
1777 /* only be_Keep found, so result is not used */
1779 } /* get_call_result_proj */
1782 * Simulate a be_Call.
1784 * @param state the x87 state
1785 * @param n the node that should be simulated
1786 * @param arch_env the architecture environment
1788 * @return NO_NODE_ADDED
1790 static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
1792 ir_type *call_tp = be_Call_get_type(n);
1796 const arch_register_t *reg;
1799 /* at the begin of a call the x87 state should be empty */
1800 assert(state->depth == 0 && "stack not empty before call");
1802 if (get_method_n_ress(call_tp) <= 0)
1803 return NO_NODE_ADDED;
1806 * If the called function returns a float, it is returned in st(0).
1807 * This even happens if the return value is NOT used.
1808 * Moreover, only one return result is supported.
1810 res_type = get_method_res_type(call_tp, 0);
1811 mode = get_type_mode(res_type);
1813 if (mode == NULL || !mode_is_float(mode))
1814 return NO_NODE_ADDED;
1816 resproj = get_call_result_proj(n);
1817 if (resproj == NULL)
1818 return NO_NODE_ADDED;
1820 reg = x87_get_irn_register(state->sim, resproj);
1821 x87_push(state, arch_register_get_index(reg), resproj);
1823 return NO_NODE_ADDED;
1827 * Simulate a be_Spill.
1829 * @param state the x87 state
1830 * @param n the node that should be simulated (and patched)
1832 * Should not happen, spills are lowered before x87 simulator see them.
1834 static int sim_Spill(x87_state *state, ir_node *n) {
1835 assert(0 && "Spill not lowered");
1836 return sim_fst(state, n);
1840 * Simulate a be_Reload.
1842 * @param state the x87 state
1843 * @param n the node that should be simulated (and patched)
1845 * Should not happen, reloads are lowered before x87 simulator see them.
1847 static int sim_Reload(x87_state *state, ir_node *n) {
1848 assert(0 && "Reload not lowered");
1849 return sim_fld(state, n);
1853 * Simulate a be_Return.
1855 * @param state the x87 state
1856 * @param n the node that should be simulated (and patched)
1858 * @return NO_NODE_ADDED
1860 static int sim_Return(x87_state *state, ir_node *n) {
1861 int n_res = be_Return_get_n_rets(n);
1862 int i, n_float_res = 0;
1864 /* only floating point return values must resist on stack */
1865 for (i = 0; i < n_res; ++i) {
1866 ir_node *res = get_irn_n(n, be_pos_Return_val + i);
1868 if (mode_is_float(get_irn_mode(res)))
1871 assert(x87_get_depth(state) == n_float_res);
1873 /* pop them virtually */
1874 for (i = n_float_res - 1; i >= 0; --i)
1877 return NO_NODE_ADDED;
1880 typedef struct _perm_data_t {
1881 const arch_register_t *in;
1882 const arch_register_t *out;
1886 * Simulate a be_Perm.
1888 * @param state the x87 state
1889 * @param irn the node that should be simulated (and patched)
1891 * @return NO_NODE_ADDED
1893 static int sim_Perm(x87_state *state, ir_node *irn) {
1895 x87_simulator *sim = state->sim;
1896 ir_node *pred = get_irn_n(irn, 0);
1898 const ir_edge_t *edge;
1900 /* handle only floating point Perms */
1901 if (! mode_is_float(get_irn_mode(pred)))
1902 return NO_NODE_ADDED;
1904 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1906 /* Perm is a pure virtual instruction on x87.
1907 All inputs must be on the FPU stack and are pairwise
1908 different from each other.
1909 So, all we need to do is to permutate the stack state. */
1910 n = get_irn_arity(irn);
1911 NEW_ARR_A(int, stack_pos, n);
1913 /* collect old stack positions */
1914 for (i = 0; i < n; ++i) {
1915 const arch_register_t *inreg = x87_get_irn_register(sim, get_irn_n(irn, i));
1916 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1918 assert(idx >= 0 && "Perm argument not on x87 stack");
1922 /* now do the permutation */
1923 foreach_out_edge(irn, edge) {
1924 ir_node *proj = get_edge_src_irn(edge);
1925 const arch_register_t *out = x87_get_irn_register(sim, proj);
1926 long num = get_Proj_proj(proj);
1928 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1929 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1931 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1933 return NO_NODE_ADDED;
1937 * Kill any dead registers at block start by popping them from the stack.
1939 * @param sim the simulator handle
1940 * @param block the current block
1941 * @param start_state the x87 state at the begin of the block
1943 * @return the x87 state after dead register killed
1945 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
1946 x87_state *state = start_state;
1947 ir_node *first_insn = sched_first(block);
1948 ir_node *keep = NULL;
1949 unsigned live = vfp_live_args_after(sim, block, 0);
1951 int i, depth, num_pop;
1954 depth = x87_get_depth(state);
1955 for (i = depth - 1; i >= 0; --i) {
1956 int reg = x87_get_st_reg(state, i);
1958 if (! is_vfp_live(reg, live))
1959 kill_mask |= (1 << i);
1963 /* create a new state, will be changed */
1964 state = x87_clone_state(sim, state);
1966 DB((dbg, LEVEL_1, "Killing deads:\n"));
1967 DEBUG_ONLY(vfp_dump_live(live));
1968 DEBUG_ONLY(x87_dump_stack(state));
1970 /* now kill registers */
1972 /* we can only kill from TOS, so bring them up */
1973 if (! (kill_mask & 1)) {
1974 /* search from behind, because we can to a double-pop */
1975 for (i = depth - 1; i >= 0; --i) {
1976 if (kill_mask & (1 << i)) {
1977 kill_mask &= ~(1 << i);
1984 x87_set_st(state, -1, keep, i);
1985 x87_create_fxch(state, first_insn, i);
1988 if ((kill_mask & 3) == 3) {
1989 /* we can do a double-pop */
1993 /* only a single pop */
1998 kill_mask >>= num_pop;
1999 keep = x87_create_fpop(state, first_insn, num_pop);
2004 } /* x87_kill_deads */
2007 * If we have PhiEs with unknown operands then we have to make sure that some
2008 * value is actually put onto the stack.
2010 static void fix_unknown_phis(x87_state *state, ir_node *block,
2011 ir_node *pred_block, int pos)
2015 sched_foreach(block, node) {
2017 const arch_register_t *reg;
2018 ia32_x87_attr_t *attr;
2023 op = get_Phi_pred(node, pos);
2024 if(!is_ia32_Unknown_VFP(op))
2027 reg = arch_get_irn_register(state->sim->arch_env, node);
2029 /* create a zero at end of pred block */
2030 zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
2031 x87_push(state, arch_register_get_index(reg), zero);
2033 attr = get_ia32_x87_attr(zero);
2034 attr->x87[2] = &ia32_st_regs[0];
2036 assert(is_ia32_fldz(zero));
2037 sched_add_before(sched_last(pred_block), zero);
2039 set_Phi_pred(node, pos, zero);
2044 * Run a simulation and fix all virtual instructions for a block.
2046 * @param sim the simulator handle
2047 * @param block the current block
2049 static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
2051 blk_state *bl_state = x87_get_bl_state(sim, block);
2052 x87_state *state = bl_state->begin;
2053 const ir_edge_t *edge;
2054 ir_node *start_block;
2056 assert(state != NULL);
2057 /* already processed? */
2058 if (bl_state->end != NULL)
2061 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2062 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2063 DEBUG_ONLY(x87_dump_stack(state));
2065 /* at block begin, kill all dead registers */
2066 state = x87_kill_deads(sim, block, state);
2067 /* create a new state, will be changed */
2068 state = x87_clone_state(sim, state);
2070 /* beware, n might change */
2071 for (n = sched_first(block); !sched_is_end(n); n = next) {
2074 ir_op *op = get_irn_op(n);
2076 next = sched_next(n);
2077 if (op->ops.generic == NULL)
2080 func = (sim_func)op->ops.generic;
2083 node_inserted = (*func)(state, n);
2086 sim_func might have added an additional node after n,
2088 beware: n must not be changed by sim_func
2089 (i.e. removed from schedule) in this case
2091 if (node_inserted != NO_NODE_ADDED)
2092 next = sched_next(n);
2095 start_block = get_irg_start_block(get_irn_irg(block));
2097 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state));
2099 /* check if the state must be shuffled */
2100 foreach_block_succ(block, edge) {
2101 ir_node *succ = get_edge_src_irn(edge);
2102 blk_state *succ_state;
2104 if (succ == start_block)
2107 succ_state = x87_get_bl_state(sim, succ);
2109 fix_unknown_phis(state, succ, block, get_edge_src_pos(edge));
2111 if (succ_state->begin == NULL) {
2112 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2113 DEBUG_ONLY(x87_dump_stack(state));
2114 succ_state->begin = state;
2116 waitq_put(sim->worklist, succ);
2118 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2119 /* There is already a begin state for the successor, bad.
2120 Do the necessary permutations.
2121 Note that critical edges are removed, so this is always possible:
2122 If the successor has more than one possible input, then it must
2125 x87_shuffle(sim, block, state, succ, succ_state->begin);
2128 bl_state->end = state;
2129 } /* x87_simulate_block */
2132 * Create a new x87 simulator.
2134 * @param sim a simulator handle, will be initialized
2135 * @param irg the current graph
2136 * @param arch_env the architecture environment
2138 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
2139 const arch_env_t *arch_env)
2141 obstack_init(&sim->obst);
2142 sim->blk_states = pmap_create();
2143 sim->arch_env = arch_env;
2144 sim->n_idx = get_irg_last_idx(irg);
2145 sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
2147 DB((dbg, LEVEL_1, "--------------------------------\n"
2148 "x87 Simulator started for %+F\n", irg));
2150 /* set the generic function pointer of instruction we must simulate */
2151 clear_irp_opcodes_generic_func();
2153 #define ASSOC(op) (op_ ## op)->ops.generic = (op_func)(sim_##op)
2154 #define ASSOC_IA32(op) (op_ia32_v ## op)->ops.generic = (op_func)(sim_##op)
2155 #define ASSOC_BE(op) (op_be_ ## op)->ops.generic = (op_func)(sim_##op)
2169 ASSOC_IA32(fCondJmp);
2180 } /* x87_init_simulator */
2183 * Destroy a x87 simulator.
2185 * @param sim the simulator handle
2187 static void x87_destroy_simulator(x87_simulator *sim) {
2188 pmap_destroy(sim->blk_states);
2189 obstack_free(&sim->obst, NULL);
2190 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2191 } /* x87_destroy_simulator */
2194 * Pre-block walker: calculate the liveness information for the block
2195 * and store it into the sim->live cache.
2197 static void update_liveness_walker(ir_node *block, void *data) {
2198 x87_simulator *sim = data;
2199 update_liveness(sim, block);
2200 } /* update_liveness_walker */
2203 * Run a simulation and fix all virtual instructions for a graph.
2205 * @param env the architecture environment
2206 * @param irg the current graph
2208 * Needs a block-schedule.
2210 void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
2211 ir_node *block, *start_block;
2212 blk_state *bl_state;
2214 ir_graph *irg = be_get_birg_irg(birg);
2216 /* create the simulator */
2217 x87_init_simulator(&sim, irg, arch_env);
2219 start_block = get_irg_start_block(irg);
2220 bl_state = x87_get_bl_state(&sim, start_block);
2222 /* start with the empty state */
2223 bl_state->begin = empty;
2226 sim.worklist = new_waitq();
2227 waitq_put(sim.worklist, start_block);
2229 be_assure_liveness(birg);
2230 sim.lv = be_get_birg_liveness(birg);
2231 // sim.lv = be_liveness(be_get_birg_irg(birg));
2232 be_liveness_assure_sets(sim.lv);
2234 /* Calculate the liveness for all nodes. We must precalculate this info,
2235 * because the simulator adds new nodes (possible before Phi nodes) which
2236 * would let a lazy calculation fail.
2237 * On the other hand we reduce the computation amount due to
2238 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2240 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2244 block = waitq_get(sim.worklist);
2245 x87_simulate_block(&sim, block);
2246 } while (! waitq_empty(sim.worklist));
2249 del_waitq(sim.worklist);
2250 x87_destroy_simulator(&sim);
2251 } /* x87_simulate_graph */
2253 void ia32_init_x87(void) {
2254 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
2255 } /* ia32_init_x87 */