2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1))
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An exchange template.
65 * Note that our virtual functions have the same inputs
66 * and attributes as the real ones, so we can simple exchange
68 * Further, x87 supports inverse instructions, so we can handle them.
70 typedef struct exchange_tmpl {
71 ir_op *normal_op; /**< the normal one */
72 ir_op *reverse_op; /**< the reverse one if exists */
73 ir_op *normal_pop_op; /**< the normal one with tos pop */
74 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
78 * An entry on the simulated x87 stack.
80 typedef struct st_entry {
81 int reg_idx; /**< the virtual register index of this stack value */
82 ir_node *node; /**< the node that produced this value */
88 typedef struct x87_state {
89 st_entry st[N_ia32_st_REGS]; /**< the register stack */
90 int depth; /**< the current stack depth */
91 int tos; /**< position of the tos */
92 x87_simulator *sim; /**< The simulator. */
95 /** An empty state, used for blocks without fp instructions. */
96 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
97 static x87_state *empty = (x87_state *)&_empty;
100 * Return values of the instruction simulator functions.
103 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
104 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
105 in the schedule AFTER the current node. */
109 * The type of an instruction simulator function.
111 * @param state the x87 state
112 * @param n the node to be simulated
114 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
116 * NO_NODE_ADDED otherwise
118 typedef int (*sim_func)(x87_state *state, ir_node *n);
121 * A block state: Every block has a x87 state at the beginning and at the end.
123 typedef struct blk_state {
124 x87_state *begin; /**< state at the begin or NULL if not assigned */
125 x87_state *end; /**< state at the end or NULL if not assigned */
128 /** liveness bitset for vfp registers. */
129 typedef unsigned char vfp_liveness;
134 struct x87_simulator {
135 struct obstack obst; /**< An obstack for fast allocating. */
136 pmap *blk_states; /**< Map blocks to states. */
137 be_lv_t *lv; /**< intrablock liveness. */
138 vfp_liveness *live; /**< Liveness information. */
139 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
140 waitq *worklist; /**< Worklist of blocks that must be processed. */
141 ia32_isa_t *isa; /**< the ISA object */
145 * Returns the current stack depth.
147 * @param state the x87 state
149 * @return the x87 stack depth
151 static int x87_get_depth(const x87_state *state)
157 * Return the virtual register index at st(pos).
159 * @param state the x87 state
160 * @param pos a stack position
162 * @return the vfp register index that produced the value at st(pos)
164 static int x87_get_st_reg(const x87_state *state, int pos)
166 assert(pos < state->depth);
167 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
172 * Return the node at st(pos).
174 * @param state the x87 state
175 * @param pos a stack position
177 * @return the IR node that produced the value at st(pos)
179 static ir_node *x87_get_st_node(const x87_state *state, int pos)
181 assert(pos < state->depth);
182 return state->st[MASK_TOS(state->tos + pos)].node;
186 * Dump the stack for debugging.
188 * @param state the x87 state
190 static void x87_dump_stack(const x87_state *state)
194 for (i = state->depth - 1; i >= 0; --i) {
195 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
196 x87_get_st_node(state, i)));
198 DB((dbg, LEVEL_2, "<-- TOS\n"));
200 #endif /* DEBUG_libfirm */
203 * Set a virtual register to st(pos).
205 * @param state the x87 state
206 * @param reg_idx the vfp register index that should be set
207 * @param node the IR node that produces the value of the vfp register
208 * @param pos the stack position where the new value should be entered
210 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
212 assert(0 < state->depth);
213 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
214 state->st[MASK_TOS(state->tos + pos)].node = node;
216 DB((dbg, LEVEL_2, "After SET_REG: "));
217 DEBUG_ONLY(x87_dump_stack(state);)
221 * Set the tos virtual register.
223 * @param state the x87 state
224 * @param reg_idx the vfp register index that should be set
225 * @param node the IR node that produces the value of the vfp register
227 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
229 x87_set_st(state, reg_idx, node, 0);
233 * Swap st(0) with st(pos).
235 * @param state the x87 state
236 * @param pos the stack position to change the tos with
238 static void x87_fxch(x87_state *state, int pos)
241 assert(pos < state->depth);
243 entry = state->st[MASK_TOS(state->tos + pos)];
244 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
245 state->st[MASK_TOS(state->tos)] = entry;
247 DB((dbg, LEVEL_2, "After FXCH: "));
248 DEBUG_ONLY(x87_dump_stack(state);)
252 * Convert a virtual register to the stack index.
254 * @param state the x87 state
255 * @param reg_idx the register vfp index
257 * @return the stack position where the register is stacked
258 * or -1 if the virtual register was not found
260 static int x87_on_stack(const x87_state *state, int reg_idx)
262 int i, tos = state->tos;
264 for (i = 0; i < state->depth; ++i)
265 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
271 * Push a virtual Register onto the stack, double pushed allowed.
273 * @param state the x87 state
274 * @param reg_idx the register vfp index
275 * @param node the node that produces the value of the vfp register
277 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
279 assert(state->depth < N_ia32_st_REGS && "stack overrun");
282 state->tos = MASK_TOS(state->tos - 1);
283 state->st[state->tos].reg_idx = reg_idx;
284 state->st[state->tos].node = node;
286 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
290 * Push a virtual Register onto the stack, double pushes are NOT allowed.
292 * @param state the x87 state
293 * @param reg_idx the register vfp index
294 * @param node the node that produces the value of the vfp register
295 * @param dbl_push if != 0 double pushes are allowed
297 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
299 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
301 x87_push_dbl(state, reg_idx, node);
305 * Pop a virtual Register from the stack.
307 * @param state the x87 state
309 static void x87_pop(x87_state *state)
311 assert(state->depth > 0 && "stack underrun");
314 state->tos = MASK_TOS(state->tos + 1);
316 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
320 * Empty the fpu stack
322 * @param state the x87 state
324 static void x87_emms(x87_state *state)
331 * Returns the block state of a block.
333 * @param sim the x87 simulator handle
334 * @param block the current block
336 * @return the block state
338 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
340 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
343 res = OALLOC(&sim->obst, blk_state);
347 pmap_insert(sim->blk_states, block, res);
354 * Creates a new x87 state.
356 * @param sim the x87 simulator handle
358 * @return a new x87 state
360 static x87_state *x87_alloc_state(x87_simulator *sim)
362 x87_state *res = OALLOC(&sim->obst, x87_state);
371 * @param sim the x87 simulator handle
372 * @param src the x87 state that will be cloned
374 * @return a cloned copy of the src state
376 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
378 x87_state *res = x87_alloc_state(sim);
385 * Patch a virtual instruction into a x87 one and return
386 * the node representing the result value.
388 * @param n the IR node to patch
389 * @param op the x87 opcode to patch in
391 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
393 ir_mode *mode = get_irn_mode(n);
398 if (mode == mode_T) {
399 /* patch all Proj's */
400 foreach_out_edge(n, edge) {
401 ir_node *proj = get_edge_src_irn(edge);
403 mode = get_irn_mode(proj);
404 if (mode_is_float(mode)) {
406 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
410 } else if (mode_is_float(mode))
411 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
416 * Returns the first Proj of a mode_T node having a given mode.
418 * @param n the mode_T node
419 * @param m the desired mode of the Proj
420 * @return The first Proj of mode @p m found or NULL.
422 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
424 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
426 foreach_out_edge(n, edge) {
427 ir_node *proj = get_edge_src_irn(edge);
428 if (get_irn_mode(proj) == m)
436 * Wrap the arch_* function here so we can check for errors.
438 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
440 const arch_register_t *res = arch_get_irn_register(irn);
442 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
446 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
449 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
451 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
455 static inline const arch_register_t *get_st_reg(int index)
457 return &ia32_registers[REG_ST0 + index];
460 /* -------------- x87 perm --------------- */
463 * Creates a fxch for shuffle.
465 * @param state the x87 state
466 * @param pos parameter for fxch
467 * @param block the block were fxch is inserted
469 * Creates a new fxch node and reroute the user of the old node
472 * @return the fxch node
474 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
477 ia32_x87_attr_t *attr;
479 fxch = new_bd_ia32_fxch(NULL, block);
480 attr = get_ia32_x87_attr(fxch);
481 attr->x87[0] = get_st_reg(pos);
482 attr->x87[2] = get_st_reg(0);
486 x87_fxch(state, pos);
491 * Calculate the necessary permutations to reach dst_state.
493 * These permutations are done with fxch instructions and placed
494 * at the end of the block.
496 * Note that critical edges are removed here, so we need only
497 * a shuffle if the current block has only one successor.
499 * @param sim the simulator handle
500 * @param block the current block
501 * @param state the current x87 stack state, might be modified
502 * @param dst_block the destination block
503 * @param dst_state destination state
507 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
508 x87_state *state, ir_node *dst_block,
509 const x87_state *dst_state)
511 int i, n_cycles, k, ri;
512 unsigned cycles[4], all_mask;
513 char cycle_idx[4][8];
514 ir_node *fxch, *before, *after;
518 assert(state->depth == dst_state->depth);
520 /* Some mathematics here:
521 If we have a cycle of length n that includes the tos,
522 we need n-1 exchange operations.
523 We can always add the tos and restore it, so we need
524 n+1 exchange operations for a cycle not containing the tos.
525 So, the maximum of needed operations is for a cycle of 7
526 not including the tos == 8.
527 This is the same number of ops we would need for using stores,
528 so exchange is cheaper (we save the loads).
529 On the other hand, we might need an additional exchange
530 in the next block to bring one operand on top, so the
531 number of ops in the first case is identical.
532 Further, no more than 4 cycles can exists (4 x 2).
534 all_mask = (1 << (state->depth)) - 1;
536 for (n_cycles = 0; all_mask; ++n_cycles) {
537 int src_idx, dst_idx;
539 /* find the first free slot */
540 for (i = 0; i < state->depth; ++i) {
541 if (all_mask & (1 << i)) {
542 all_mask &= ~(1 << i);
544 /* check if there are differences here */
545 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
551 /* no more cycles found */
556 cycles[n_cycles] = (1 << i);
557 cycle_idx[n_cycles][k++] = i;
558 for (src_idx = i; ; src_idx = dst_idx) {
559 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
561 if ((all_mask & (1 << dst_idx)) == 0)
564 cycle_idx[n_cycles][k++] = dst_idx;
565 cycles[n_cycles] |= (1 << dst_idx);
566 all_mask &= ~(1 << dst_idx);
568 cycle_idx[n_cycles][k] = -1;
572 /* no permutation needed */
576 /* Hmm: permutation needed */
577 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
578 DEBUG_ONLY(x87_dump_stack(state);)
579 DB((dbg, LEVEL_2, " to\n"));
580 DEBUG_ONLY(x87_dump_stack(dst_state);)
584 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
585 for (ri = 0; ri < n_cycles; ++ri) {
586 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
587 for (k = 0; cycle_idx[ri][k] != -1; ++k)
588 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
589 DB((dbg, LEVEL_2, "\n"));
596 * Find the place node must be insert.
597 * We have only one successor block, so the last instruction should
600 before = sched_last(block);
601 assert(is_cfop(before));
603 /* now do the permutations */
604 for (ri = 0; ri < n_cycles; ++ri) {
605 if ((cycles[ri] & 1) == 0) {
606 /* this cycle does not include the tos */
607 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
609 sched_add_after(after, fxch);
611 sched_add_before(before, fxch);
614 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
615 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
617 sched_add_after(after, fxch);
619 sched_add_before(before, fxch);
622 if ((cycles[ri] & 1) == 0) {
623 /* this cycle does not include the tos */
624 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
625 sched_add_after(after, fxch);
632 * Create a fxch node before another node.
634 * @param state the x87 state
635 * @param n the node after the fxch
636 * @param pos exchange st(pos) with st(0)
640 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
643 ia32_x87_attr_t *attr;
644 ir_node *block = get_nodes_block(n);
646 x87_fxch(state, pos);
648 fxch = new_bd_ia32_fxch(NULL, block);
649 attr = get_ia32_x87_attr(fxch);
650 attr->x87[0] = get_st_reg(pos);
651 attr->x87[2] = get_st_reg(0);
655 sched_add_before(n, fxch);
656 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
661 * Create a fpush before node n.
663 * @param state the x87 state
664 * @param n the node after the fpush
665 * @param pos push st(pos) on stack
666 * @param op_idx replace input op_idx of n with the fpush result
668 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
670 ir_node *fpush, *pred = get_irn_n(n, op_idx);
671 ia32_x87_attr_t *attr;
672 const arch_register_t *out = x87_get_irn_register(pred);
674 x87_push_dbl(state, arch_register_get_index(out), pred);
676 fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
677 attr = get_ia32_x87_attr(fpush);
678 attr->x87[0] = get_st_reg(pos);
679 attr->x87[2] = get_st_reg(0);
682 sched_add_before(n, fpush);
684 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
688 * Create a fpop before node n.
690 * @param state the x87 state
691 * @param n the node after the fpop
692 * @param num pop 1 or 2 values
694 * @return the fpop node
696 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
698 ir_node *fpop = NULL;
699 ia32_x87_attr_t *attr;
704 if (ia32_cg_config.use_ffreep)
705 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
707 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
708 attr = get_ia32_x87_attr(fpop);
709 attr->x87[0] = get_st_reg(0);
710 attr->x87[1] = get_st_reg(0);
711 attr->x87[2] = get_st_reg(0);
714 sched_add_before(n, fpop);
715 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
720 /* --------------------------------- liveness ------------------------------------------ */
723 * The liveness transfer function.
724 * Updates a live set over a single step from a given node to its predecessor.
725 * Everything defined at the node is removed from the set, the uses of the node get inserted.
727 * @param irn The node at which liveness should be computed.
728 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
729 * the registers live after irn.
731 * @return The live bitset.
733 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
736 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
738 if (get_irn_mode(irn) == mode_T) {
739 foreach_out_edge(irn, edge) {
740 ir_node *proj = get_edge_src_irn(edge);
742 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
743 const arch_register_t *reg = x87_get_irn_register(proj);
744 live &= ~(1 << arch_register_get_index(reg));
747 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
748 const arch_register_t *reg = x87_get_irn_register(irn);
749 live &= ~(1 << arch_register_get_index(reg));
752 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
753 ir_node *op = get_irn_n(irn, i);
755 if (mode_is_float(get_irn_mode(op)) &&
756 arch_irn_consider_in_reg_alloc(cls, op)) {
757 const arch_register_t *reg = x87_get_irn_register(op);
758 live |= 1 << arch_register_get_index(reg);
765 * Put all live virtual registers at the end of a block into a bitset.
767 * @param sim the simulator handle
768 * @param lv the liveness information
769 * @param bl the block
771 * @return The live bitset at the end of this block
773 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
775 vfp_liveness live = 0;
776 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
777 const be_lv_t *lv = sim->lv;
779 be_lv_foreach(lv, block, be_lv_state_end, node) {
780 const arch_register_t *reg;
781 if (!arch_irn_consider_in_reg_alloc(cls, node))
784 reg = x87_get_irn_register(node);
785 live |= 1 << arch_register_get_index(reg);
791 /** get the register mask from an arch_register */
792 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
795 * Return a bitset of argument registers which are live at the end of a node.
797 * @param sim the simulator handle
798 * @param pos the node
799 * @param kill kill mask for the output registers
801 * @return The live bitset.
803 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
805 unsigned idx = get_irn_idx(pos);
807 assert(idx < sim->n_idx);
808 return sim->live[idx] & ~kill;
812 * Calculate the liveness for a whole block and cache it.
814 * @param sim the simulator handle
815 * @param lv the liveness handle
816 * @param block the block
818 static void update_liveness(x87_simulator *sim, ir_node *block)
820 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
823 /* now iterate through the block backward and cache the results */
824 sched_foreach_reverse(block, irn) {
825 /* stop at the first Phi: this produces the live-in */
829 idx = get_irn_idx(irn);
830 sim->live[idx] = live;
832 live = vfp_liveness_transfer(irn, live);
834 idx = get_irn_idx(block);
835 sim->live[idx] = live;
839 * Returns true if a register is live in a set.
841 * @param reg_idx the vfp register index
842 * @param live a live bitset
844 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
848 * Dump liveness info.
850 * @param live the live bitset
852 static void vfp_dump_live(vfp_liveness live)
856 DB((dbg, LEVEL_2, "Live after: "));
857 for (i = 0; i < 8; ++i) {
858 if (live & (1 << i)) {
859 DB((dbg, LEVEL_2, "vf%d ", i));
862 DB((dbg, LEVEL_2, "\n"));
864 #endif /* DEBUG_libfirm */
866 /* --------------------------------- simulators ---------------------------------------- */
869 * Simulate a virtual binop.
871 * @param state the x87 state
872 * @param n the node that should be simulated (and patched)
873 * @param tmpl the template containing the 4 possible x87 opcodes
875 * @return NO_NODE_ADDED
877 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
879 int op2_idx = 0, op1_idx;
880 int out_idx, do_pop = 0;
881 ia32_x87_attr_t *attr;
883 ir_node *patched_insn;
885 x87_simulator *sim = state->sim;
886 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
887 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
888 const arch_register_t *op1_reg = x87_get_irn_register(op1);
889 const arch_register_t *op2_reg = x87_get_irn_register(op2);
890 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
891 int reg_index_1 = arch_register_get_index(op1_reg);
892 int reg_index_2 = arch_register_get_index(op2_reg);
893 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
897 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
898 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
899 arch_register_get_name(out)));
900 DEBUG_ONLY(vfp_dump_live(live);)
901 DB((dbg, LEVEL_1, "Stack before: "));
902 DEBUG_ONLY(x87_dump_stack(state);)
904 op1_idx = x87_on_stack(state, reg_index_1);
905 assert(op1_idx >= 0);
906 op1_live_after = is_vfp_live(reg_index_1, live);
908 attr = get_ia32_x87_attr(n);
909 permuted = attr->attr.data.ins_permuted;
911 if (reg_index_2 != REG_VFP_VFP_NOREG) {
914 /* second operand is a vfp register */
915 op2_idx = x87_on_stack(state, reg_index_2);
916 assert(op2_idx >= 0);
917 op2_live_after = is_vfp_live(reg_index_2, live);
919 if (op2_live_after) {
920 /* Second operand is live. */
922 if (op1_live_after) {
923 /* Both operands are live: push the first one.
924 This works even for op1 == op2. */
925 x87_create_fpush(state, n, op1_idx, n_ia32_binary_right);
926 /* now do fxxx (tos=tos X op) */
930 dst = tmpl->normal_op;
932 /* Second live, first operand is dead here, bring it to tos. */
934 x87_create_fxch(state, n, op1_idx);
939 /* now do fxxx (tos=tos X op) */
941 dst = tmpl->normal_op;
944 /* Second operand is dead. */
945 if (op1_live_after) {
946 /* First operand is live: bring second to tos. */
948 x87_create_fxch(state, n, op2_idx);
953 /* now do fxxxr (tos = op X tos) */
955 dst = tmpl->reverse_op;
957 /* Both operands are dead here, pop them from the stack. */
960 /* Both are identically and on tos, no pop needed. */
961 /* here fxxx (tos = tos X tos) */
962 dst = tmpl->normal_op;
965 /* now do fxxxp (op = op X tos, pop) */
966 dst = tmpl->normal_pop_op;
970 } else if (op1_idx == 0) {
971 assert(op1_idx != op2_idx);
972 /* now do fxxxrp (op = tos X op, pop) */
973 dst = tmpl->reverse_pop_op;
977 /* Bring the second on top. */
978 x87_create_fxch(state, n, op2_idx);
979 if (op1_idx == op2_idx) {
980 /* Both are identically and on tos now, no pop needed. */
983 /* use fxxx (tos = tos X tos) */
984 dst = tmpl->normal_op;
987 /* op2 is on tos now */
989 /* use fxxxp (op = op X tos, pop) */
990 dst = tmpl->normal_pop_op;
998 /* second operand is an address mode */
999 if (op1_live_after) {
1000 /* first operand is live: push it here */
1001 x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
1004 /* first operand is dead: bring it to tos */
1006 x87_create_fxch(state, n, op1_idx);
1011 /* use fxxx (tos = tos X mem) */
1012 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
1016 patched_insn = x87_patch_insn(n, dst);
1017 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1022 /* patch the operation */
1023 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
1024 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1025 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
1027 attr->x87[2] = out = get_st_reg(out_idx);
1029 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1030 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1031 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
1032 arch_register_get_name(out)));
1034 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1035 arch_register_get_name(op1_reg),
1036 arch_register_get_name(out)));
1039 return NO_NODE_ADDED;
1043 * Simulate a virtual Unop.
1045 * @param state the x87 state
1046 * @param n the node that should be simulated (and patched)
1047 * @param op the x87 opcode that will replace n's opcode
1049 * @return NO_NODE_ADDED
1051 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
1054 x87_simulator *sim = state->sim;
1055 const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
1056 const arch_register_t *out = x87_get_irn_register(n);
1057 ia32_x87_attr_t *attr;
1058 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1060 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1061 DEBUG_ONLY(vfp_dump_live(live);)
1063 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1065 if (is_vfp_live(arch_register_get_index(op1), live)) {
1066 /* push the operand here */
1067 x87_create_fpush(state, n, op1_idx, 0);
1071 /* operand is dead, bring it to tos */
1073 x87_create_fxch(state, n, op1_idx);
1078 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1079 attr = get_ia32_x87_attr(n);
1080 attr->x87[0] = op1 = get_st_reg(0);
1081 attr->x87[2] = out = get_st_reg(0);
1082 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1084 return NO_NODE_ADDED;
1088 * Simulate a virtual Load instruction.
1090 * @param state the x87 state
1091 * @param n the node that should be simulated (and patched)
1092 * @param op the x87 opcode that will replace n's opcode
1094 * @return NO_NODE_ADDED
1096 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
1098 const arch_register_t *out = x87_irn_get_register(n, res_pos);
1099 ia32_x87_attr_t *attr;
1101 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1102 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1103 assert(out == x87_irn_get_register(n, res_pos));
1104 attr = get_ia32_x87_attr(n);
1105 attr->x87[2] = out = get_st_reg(0);
1106 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1108 return NO_NODE_ADDED;
1112 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1114 * @param store The store
1115 * @param old_val The former value
1116 * @param new_val The new value
1118 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
1120 foreach_out_edge_safe(old_val, edge) {
1121 ir_node *user = get_edge_src_irn(edge);
1123 if (! user || user == store)
1126 /* if the user is scheduled after the store: rewire */
1127 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1129 /* find the input of the user pointing to the old value */
1130 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1131 if (get_irn_n(user, i) == old_val)
1132 set_irn_n(user, i, new_val);
1139 * Simulate a virtual Store.
1141 * @param state the x87 state
1142 * @param n the node that should be simulated (and patched)
1143 * @param op the x87 store opcode
1144 * @param op_p the x87 store and pop opcode
1146 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1148 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1149 const arch_register_t *op2 = x87_get_irn_register(val);
1150 unsigned live = vfp_live_args_after(state->sim, n, 0);
1151 int insn = NO_NODE_ADDED;
1152 ia32_x87_attr_t *attr;
1153 int op2_reg_idx, op2_idx, depth;
1154 int live_after_node;
1157 op2_reg_idx = arch_register_get_index(op2);
1158 op2_idx = x87_on_stack(state, op2_reg_idx);
1159 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1160 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1161 assert(op2_idx >= 0);
1163 mode = get_ia32_ls_mode(n);
1164 depth = x87_get_depth(state);
1166 if (live_after_node) {
1168 Problem: fst doesn't support 96bit modes (spills), only fstp does
1169 fist doesn't support 64bit mode, only fistp
1171 - stack not full: push value and fstp
1172 - stack full: fstp value and load again
1173 Note that we cannot test on mode_E, because floats might be 96bit ...
1175 if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
1176 if (depth < N_ia32_st_REGS) {
1177 /* ok, we have a free register: push + fstp */
1178 x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
1180 x87_patch_insn(n, op_p);
1182 ir_node *vfld, *mem, *block, *rproj, *mproj;
1183 ir_graph *irg = get_irn_irg(n);
1184 ir_node *nomem = get_irg_no_mem(irg);
1186 /* stack full here: need fstp + load */
1188 x87_patch_insn(n, op_p);
1190 block = get_nodes_block(n);
1191 vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n));
1193 /* copy all attributes */
1194 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1195 if (is_ia32_use_frame(n))
1196 set_ia32_use_frame(vfld);
1197 set_ia32_op_type(vfld, ia32_AddrModeS);
1198 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1199 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1200 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1202 rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1203 mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1204 mem = get_irn_Proj_for_mode(n, mode_M);
1206 assert(mem && "Store memory not found");
1208 arch_set_irn_register(rproj, op2);
1210 /* reroute all former users of the store memory to the load memory */
1211 edges_reroute(mem, mproj);
1212 /* set the memory input of the load to the store memory */
1213 set_irn_n(vfld, n_ia32_vfld_mem, mem);
1215 sched_add_after(n, vfld);
1216 sched_add_after(vfld, rproj);
1218 /* rewire all users, scheduled after the store, to the loaded value */
1219 collect_and_rewire_users(n, val, rproj);
1224 /* we can only store the tos to memory */
1226 x87_create_fxch(state, n, op2_idx);
1228 /* mode size 64 or smaller -> use normal fst */
1229 x87_patch_insn(n, op);
1232 /* we can only store the tos to memory */
1234 x87_create_fxch(state, n, op2_idx);
1237 x87_patch_insn(n, op_p);
1240 attr = get_ia32_x87_attr(n);
1241 attr->x87[1] = op2 = get_st_reg(0);
1242 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1247 #define _GEN_BINOP(op, rev) \
1248 static int sim_##op(x87_state *state, ir_node *n) { \
1249 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1250 return sim_binop(state, n, &tmpl); \
1253 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1254 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1256 #define GEN_LOAD(op) \
1257 static int sim_##op(x87_state *state, ir_node *n) { \
1258 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1261 #define GEN_UNOP(op) \
1262 static int sim_##op(x87_state *state, ir_node *n) { \
1263 return sim_unop(state, n, op_ia32_##op); \
1266 #define GEN_STORE(op) \
1267 static int sim_##op(x87_state *state, ir_node *n) { \
1268 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1290 * Simulate a virtual fisttp.
1292 * @param state the x87 state
1293 * @param n the node that should be simulated (and patched)
1295 * @return NO_NODE_ADDED
1297 static int sim_fisttp(x87_state *state, ir_node *n)
1299 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1300 const arch_register_t *op2 = x87_get_irn_register(val);
1301 ia32_x87_attr_t *attr;
1302 int op2_reg_idx, op2_idx;
1304 op2_reg_idx = arch_register_get_index(op2);
1305 op2_idx = x87_on_stack(state, op2_reg_idx);
1306 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1307 assert(op2_idx >= 0);
1309 /* Note: although the value is still live here, it is destroyed because
1310 of the pop. The register allocator is aware of that and introduced a copy
1311 if the value must be alive. */
1313 /* we can only store the tos to memory */
1315 x87_create_fxch(state, n, op2_idx);
1318 x87_patch_insn(n, op_ia32_fisttp);
1320 attr = get_ia32_x87_attr(n);
1321 attr->x87[1] = op2 = get_st_reg(0);
1322 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1324 return NO_NODE_ADDED;
1328 * Simulate a virtual FtstFnstsw.
1330 * @param state the x87 state
1331 * @param n the node that should be simulated (and patched)
1333 * @return NO_NODE_ADDED
1335 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1337 x87_simulator *sim = state->sim;
1338 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1339 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1340 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1341 int reg_index_1 = arch_register_get_index(reg1);
1342 int op1_idx = x87_on_stack(state, reg_index_1);
1343 unsigned live = vfp_live_args_after(sim, n, 0);
1345 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1346 DEBUG_ONLY(vfp_dump_live(live);)
1347 DB((dbg, LEVEL_1, "Stack before: "));
1348 DEBUG_ONLY(x87_dump_stack(state);)
1349 assert(op1_idx >= 0);
1352 /* bring the value to tos */
1353 x87_create_fxch(state, n, op1_idx);
1357 /* patch the operation */
1358 x87_patch_insn(n, op_ia32_FtstFnstsw);
1359 reg1 = get_st_reg(op1_idx);
1360 attr->x87[0] = reg1;
1361 attr->x87[1] = NULL;
1362 attr->x87[2] = NULL;
1364 if (!is_vfp_live(reg_index_1, live))
1365 x87_create_fpop(state, sched_next(n), 1);
1367 return NO_NODE_ADDED;
1373 * @param state the x87 state
1374 * @param n the node that should be simulated (and patched)
1376 * @return NO_NODE_ADDED
1378 static int sim_Fucom(x87_state *state, ir_node *n)
1382 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1384 x87_simulator *sim = state->sim;
1385 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1386 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1387 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1388 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1389 int reg_index_1 = arch_register_get_index(op1);
1390 int reg_index_2 = arch_register_get_index(op2);
1391 unsigned live = vfp_live_args_after(sim, n, 0);
1392 bool permuted = attr->attr.data.ins_permuted;
1396 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1397 arch_register_get_name(op1), arch_register_get_name(op2)));
1398 DEBUG_ONLY(vfp_dump_live(live);)
1399 DB((dbg, LEVEL_1, "Stack before: "));
1400 DEBUG_ONLY(x87_dump_stack(state);)
1402 op1_idx = x87_on_stack(state, reg_index_1);
1403 assert(op1_idx >= 0);
1405 /* BEWARE: check for comp a,a cases, they might happen */
1406 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1407 /* second operand is a vfp register */
1408 op2_idx = x87_on_stack(state, reg_index_2);
1409 assert(op2_idx >= 0);
1411 if (is_vfp_live(reg_index_2, live)) {
1412 /* second operand is live */
1414 if (is_vfp_live(reg_index_1, live)) {
1415 /* both operands are live */
1418 /* res = tos X op */
1419 } else if (op2_idx == 0) {
1420 /* res = op X tos */
1421 permuted = !permuted;
1424 /* bring the first one to tos */
1425 x87_create_fxch(state, n, op1_idx);
1426 if (op1_idx == op2_idx) {
1428 } else if (op2_idx == 0) {
1432 /* res = tos X op */
1435 /* second live, first operand is dead here, bring it to tos.
1436 This means further, op1_idx != op2_idx. */
1437 assert(op1_idx != op2_idx);
1439 x87_create_fxch(state, n, op1_idx);
1444 /* res = tos X op, pop */
1448 /* second operand is dead */
1449 if (is_vfp_live(reg_index_1, live)) {
1450 /* first operand is live: bring second to tos.
1451 This means further, op1_idx != op2_idx. */
1452 assert(op1_idx != op2_idx);
1454 x87_create_fxch(state, n, op2_idx);
1459 /* res = op X tos, pop */
1461 permuted = !permuted;
1464 /* both operands are dead here, check first for identity. */
1465 if (op1_idx == op2_idx) {
1466 /* identically, one pop needed */
1468 x87_create_fxch(state, n, op1_idx);
1472 /* res = tos X op, pop */
1475 /* different, move them to st and st(1) and pop both.
1476 The tricky part is to get one into st(1).*/
1477 else if (op2_idx == 1) {
1478 /* good, second operand is already in the right place, move the first */
1480 /* bring the first on top */
1481 x87_create_fxch(state, n, op1_idx);
1482 assert(op2_idx != 0);
1485 /* res = tos X op, pop, pop */
1487 } else if (op1_idx == 1) {
1488 /* good, first operand is already in the right place, move the second */
1490 /* bring the first on top */
1491 x87_create_fxch(state, n, op2_idx);
1492 assert(op1_idx != 0);
1495 /* res = op X tos, pop, pop */
1496 permuted = !permuted;
1500 /* if one is already the TOS, we need two fxch */
1502 /* first one is TOS, move to st(1) */
1503 x87_create_fxch(state, n, 1);
1504 assert(op2_idx != 1);
1506 x87_create_fxch(state, n, op2_idx);
1508 /* res = op X tos, pop, pop */
1510 permuted = !permuted;
1512 } else if (op2_idx == 0) {
1513 /* second one is TOS, move to st(1) */
1514 x87_create_fxch(state, n, 1);
1515 assert(op1_idx != 1);
1517 x87_create_fxch(state, n, op1_idx);
1519 /* res = tos X op, pop, pop */
1522 /* none of them is either TOS or st(1), 3 fxch needed */
1523 x87_create_fxch(state, n, op2_idx);
1524 assert(op1_idx != 0);
1525 x87_create_fxch(state, n, 1);
1527 x87_create_fxch(state, n, op1_idx);
1529 /* res = tos X op, pop, pop */
1536 /* second operand is an address mode */
1537 if (is_vfp_live(reg_index_1, live)) {
1538 /* first operand is live: bring it to TOS */
1540 x87_create_fxch(state, n, op1_idx);
1544 /* first operand is dead: bring it to tos */
1546 x87_create_fxch(state, n, op1_idx);
1553 /* patch the operation */
1554 if (is_ia32_vFucomFnstsw(n)) {
1558 case 0: dst = op_ia32_FucomFnstsw; break;
1559 case 1: dst = op_ia32_FucompFnstsw; break;
1560 case 2: dst = op_ia32_FucomppFnstsw; break;
1561 default: panic("invalid popcount in sim_Fucom");
1564 for (i = 0; i < pops; ++i) {
1567 } else if (is_ia32_vFucomi(n)) {
1569 case 0: dst = op_ia32_Fucomi; break;
1570 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1572 dst = op_ia32_Fucompi;
1574 x87_create_fpop(state, sched_next(n), 1);
1576 default: panic("invalid popcount in sim_Fucom");
1579 panic("invalid operation %+F in sim_FucomFnstsw", n);
1582 x87_patch_insn(n, dst);
1589 op1 = get_st_reg(op1_idx);
1592 op2 = get_st_reg(op2_idx);
1595 attr->x87[2] = NULL;
1596 attr->attr.data.ins_permuted = permuted;
1599 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1600 arch_register_get_name(op1), arch_register_get_name(op2)));
1602 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1603 arch_register_get_name(op1)));
1606 return NO_NODE_ADDED;
1612 * @param state the x87 state
1613 * @param n the node that should be simulated (and patched)
1615 * @return NO_NODE_ADDED
1617 static int sim_Keep(x87_state *state, ir_node *node)
1620 const arch_register_t *op_reg;
1626 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1628 arity = get_irn_arity(node);
1629 for (i = 0; i < arity; ++i) {
1630 op = get_irn_n(node, i);
1631 op_reg = arch_get_irn_register(op);
1632 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1635 reg_id = arch_register_get_index(op_reg);
1636 live = vfp_live_args_after(state->sim, node, 0);
1638 op_stack_idx = x87_on_stack(state, reg_id);
1639 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1640 x87_create_fpop(state, sched_next(node), 1);
1643 DB((dbg, LEVEL_1, "Stack after: "));
1644 DEBUG_ONLY(x87_dump_stack(state);)
1646 return NO_NODE_ADDED;
1650 * Keep the given node alive by adding a be_Keep.
1652 * @param node the node to kept alive
1654 static void keep_float_node_alive(ir_node *node)
1656 ir_node *block = get_nodes_block(node);
1657 ir_node *keep = be_new_Keep(block, 1, &node);
1659 assert(sched_is_scheduled(node));
1660 sched_add_after(node, keep);
1664 * Create a copy of a node. Recreate the node if it's a constant.
1666 * @param state the x87 state
1667 * @param n the node to be copied
1669 * @return the copy of n
1671 static ir_node *create_Copy(x87_state *state, ir_node *n)
1673 dbg_info *n_dbg = get_irn_dbg_info(n);
1674 ir_mode *mode = get_irn_mode(n);
1675 ir_node *block = get_nodes_block(n);
1676 ir_node *pred = get_irn_n(n, 0);
1677 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1679 const arch_register_t *out;
1680 const arch_register_t *op1;
1681 ia32_x87_attr_t *attr;
1683 /* Do not copy constants, recreate them. */
1684 switch (get_ia32_irn_opcode(pred)) {
1686 cnstr = new_bd_ia32_fldz;
1689 cnstr = new_bd_ia32_fld1;
1691 case iro_ia32_fldpi:
1692 cnstr = new_bd_ia32_fldpi;
1694 case iro_ia32_fldl2e:
1695 cnstr = new_bd_ia32_fldl2e;
1697 case iro_ia32_fldl2t:
1698 cnstr = new_bd_ia32_fldl2t;
1700 case iro_ia32_fldlg2:
1701 cnstr = new_bd_ia32_fldlg2;
1703 case iro_ia32_fldln2:
1704 cnstr = new_bd_ia32_fldln2;
1710 out = x87_get_irn_register(n);
1711 op1 = x87_get_irn_register(pred);
1713 if (cnstr != NULL) {
1714 /* copy a constant */
1715 res = (*cnstr)(n_dbg, block, mode);
1717 x87_push(state, arch_register_get_index(out), res);
1719 attr = get_ia32_x87_attr(res);
1720 attr->x87[2] = get_st_reg(0);
1722 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1724 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1726 x87_push(state, arch_register_get_index(out), res);
1728 attr = get_ia32_x87_attr(res);
1729 attr->x87[0] = get_st_reg(op1_idx);
1730 attr->x87[2] = get_st_reg(0);
1732 arch_set_irn_register(res, out);
1738 * Simulate a be_Copy.
1740 * @param state the x87 state
1741 * @param n the node that should be simulated (and patched)
1743 * @return NO_NODE_ADDED
1745 static int sim_Copy(x87_state *state, ir_node *n)
1748 const arch_register_t *out;
1749 const arch_register_t *op1;
1750 const arch_register_class_t *cls;
1751 ir_node *node, *next;
1752 int op1_idx, out_idx;
1755 cls = arch_get_irn_reg_class(n);
1756 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1759 pred = get_irn_n(n, 0);
1760 out = x87_get_irn_register(n);
1761 op1 = x87_get_irn_register(pred);
1762 live = vfp_live_args_after(state->sim, n, REGMASK(out));
1764 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1765 arch_register_get_name(op1), arch_register_get_name(out)));
1766 DEBUG_ONLY(vfp_dump_live(live);)
1768 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1770 if (is_vfp_live(arch_register_get_index(op1), live)) {
1771 /* Operand is still live, a real copy. We need here an fpush that can
1772 hold a a register, so use the fpushCopy or recreate constants */
1773 node = create_Copy(state, n);
1775 /* We have to make sure the old value doesn't go dead (which can happen
1776 * when we recreate constants). As the simulator expected that value in
1777 * the pred blocks. This is unfortunate as removing it would save us 1
1778 * instruction, but we would have to rerun all the simulation to get
1781 next = sched_next(n);
1784 sched_add_before(next, node);
1786 if (get_irn_n_edges(pred) == 0) {
1787 keep_float_node_alive(pred);
1790 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1792 out_idx = x87_on_stack(state, arch_register_get_index(out));
1794 if (out_idx >= 0 && out_idx != op1_idx) {
1795 /* Matze: out already on stack? how can this happen? */
1796 panic("invalid stack state in x87 simulator");
1799 /* op1 must be killed and placed where out is */
1801 ia32_x87_attr_t *attr;
1802 /* best case, simple remove and rename */
1803 x87_patch_insn(n, op_ia32_Pop);
1804 attr = get_ia32_x87_attr(n);
1805 attr->x87[0] = op1 = get_st_reg(0);
1808 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1810 ia32_x87_attr_t *attr;
1811 /* move op1 to tos, store and pop it */
1813 x87_create_fxch(state, n, op1_idx);
1816 x87_patch_insn(n, op_ia32_Pop);
1817 attr = get_ia32_x87_attr(n);
1818 attr->x87[0] = op1 = get_st_reg(out_idx);
1821 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1823 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1826 /* just a virtual copy */
1827 x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
1828 /* don't remove the node to keep the verifier quiet :),
1829 the emitter won't emit any code for the node */
1832 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1833 exchange(n, get_unop_op(n));
1837 return NO_NODE_ADDED;
1841 * Returns the vf0 result Proj of a Call.
1843 * @para call the Call node
1845 static ir_node *get_call_result_proj(ir_node *call)
1847 /* search the result proj */
1848 foreach_out_edge(call, edge) {
1849 ir_node *proj = get_edge_src_irn(edge);
1850 long pn = get_Proj_proj(proj);
1852 if (pn == pn_ia32_Call_vf0)
1860 * Simulate a ia32_Call.
1862 * @param state the x87 state
1863 * @param n the node that should be simulated (and patched)
1865 * @return NO_NODE_ADDED
1867 static int sim_Call(x87_state *state, ir_node *n)
1869 ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp;
1873 const arch_register_t *reg;
1875 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1877 /* at the begin of a call the x87 state should be empty */
1878 assert(state->depth == 0 && "stack not empty before call");
1880 if (get_method_n_ress(call_tp) <= 0)
1884 * If the called function returns a float, it is returned in st(0).
1885 * This even happens if the return value is NOT used.
1886 * Moreover, only one return result is supported.
1888 res_type = get_method_res_type(call_tp, 0);
1889 mode = get_type_mode(res_type);
1891 if (mode == NULL || !mode_is_float(mode))
1894 resproj = get_call_result_proj(n);
1895 assert(resproj != NULL);
1897 reg = x87_get_irn_register(resproj);
1898 x87_push(state, arch_register_get_index(reg), resproj);
1901 DB((dbg, LEVEL_1, "Stack after: "));
1902 DEBUG_ONLY(x87_dump_stack(state);)
1904 return NO_NODE_ADDED;
1908 * Simulate a be_Return.
1910 * @param state the x87 state
1911 * @param n the node that should be simulated (and patched)
1913 * @return NO_NODE_ADDED
1915 static int sim_Return(x87_state *state, ir_node *n)
1917 int n_res = be_Return_get_n_rets(n);
1918 int i, n_float_res = 0;
1920 /* only floating point return values must reside on stack */
1921 for (i = 0; i < n_res; ++i) {
1922 ir_node *res = get_irn_n(n, n_be_Return_val + i);
1924 if (mode_is_float(get_irn_mode(res)))
1927 assert(x87_get_depth(state) == n_float_res);
1929 /* pop them virtually */
1930 for (i = n_float_res - 1; i >= 0; --i)
1933 return NO_NODE_ADDED;
1936 typedef struct perm_data_t {
1937 const arch_register_t *in;
1938 const arch_register_t *out;
1942 * Simulate a be_Perm.
1944 * @param state the x87 state
1945 * @param irn the node that should be simulated (and patched)
1947 * @return NO_NODE_ADDED
1949 static int sim_Perm(x87_state *state, ir_node *irn)
1952 ir_node *pred = get_irn_n(irn, 0);
1955 /* handle only floating point Perms */
1956 if (! mode_is_float(get_irn_mode(pred)))
1957 return NO_NODE_ADDED;
1959 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1961 /* Perm is a pure virtual instruction on x87.
1962 All inputs must be on the FPU stack and are pairwise
1963 different from each other.
1964 So, all we need to do is to permutate the stack state. */
1965 n = get_irn_arity(irn);
1966 NEW_ARR_A(int, stack_pos, n);
1968 /* collect old stack positions */
1969 for (i = 0; i < n; ++i) {
1970 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1971 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1973 assert(idx >= 0 && "Perm argument not on x87 stack");
1977 /* now do the permutation */
1978 foreach_out_edge(irn, edge) {
1979 ir_node *proj = get_edge_src_irn(edge);
1980 const arch_register_t *out = x87_get_irn_register(proj);
1981 long num = get_Proj_proj(proj);
1983 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1984 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1986 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1988 return NO_NODE_ADDED;
1992 * Kill any dead registers at block start by popping them from the stack.
1994 * @param sim the simulator handle
1995 * @param block the current block
1996 * @param start_state the x87 state at the begin of the block
1998 * @return the x87 state after dead register killed
2000 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
2002 x87_state *state = start_state;
2003 ir_node *first_insn = sched_first(block);
2004 ir_node *keep = NULL;
2005 unsigned live = vfp_live_args_after(sim, block, 0);
2007 int i, depth, num_pop;
2010 depth = x87_get_depth(state);
2011 for (i = depth - 1; i >= 0; --i) {
2012 int reg = x87_get_st_reg(state, i);
2014 if (! is_vfp_live(reg, live))
2015 kill_mask |= (1 << i);
2019 /* create a new state, will be changed */
2020 state = x87_clone_state(sim, state);
2022 DB((dbg, LEVEL_1, "Killing deads:\n"));
2023 DEBUG_ONLY(vfp_dump_live(live);)
2024 DEBUG_ONLY(x87_dump_stack(state);)
2026 if (kill_mask != 0 && live == 0) {
2027 /* special case: kill all registers */
2028 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
2029 if (ia32_cg_config.use_femms) {
2030 /* use FEMMS on AMD processors to clear all */
2031 keep = new_bd_ia32_femms(NULL, block);
2033 /* use EMMS to clear all */
2034 keep = new_bd_ia32_emms(NULL, block);
2036 sched_add_before(first_insn, keep);
2042 /* now kill registers */
2044 /* we can only kill from TOS, so bring them up */
2045 if (! (kill_mask & 1)) {
2046 /* search from behind, because we can to a double-pop */
2047 for (i = depth - 1; i >= 0; --i) {
2048 if (kill_mask & (1 << i)) {
2049 kill_mask &= ~(1 << i);
2056 x87_set_st(state, -1, keep, i);
2057 x87_create_fxch(state, first_insn, i);
2060 if ((kill_mask & 3) == 3) {
2061 /* we can do a double-pop */
2065 /* only a single pop */
2070 kill_mask >>= num_pop;
2071 keep = x87_create_fpop(state, first_insn, num_pop);
2079 * Run a simulation and fix all virtual instructions for a block.
2081 * @param sim the simulator handle
2082 * @param block the current block
2084 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
2087 blk_state *bl_state = x87_get_bl_state(sim, block);
2088 x87_state *state = bl_state->begin;
2089 ir_node *start_block;
2091 assert(state != NULL);
2092 /* already processed? */
2093 if (bl_state->end != NULL)
2096 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2097 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2098 DEBUG_ONLY(x87_dump_stack(state);)
2100 /* at block begin, kill all dead registers */
2101 state = x87_kill_deads(sim, block, state);
2102 /* create a new state, will be changed */
2103 state = x87_clone_state(sim, state);
2105 /* beware, n might change */
2106 for (n = sched_first(block); !sched_is_end(n); n = next) {
2109 ir_op *op = get_irn_op(n);
2112 * get the next node to be simulated here.
2113 * n might be completely removed from the schedule-
2115 next = sched_next(n);
2116 if (op->ops.generic != NULL) {
2117 func = (sim_func)op->ops.generic;
2120 node_inserted = (*func)(state, n);
2123 * sim_func might have added an additional node after n,
2124 * so update next node
2125 * beware: n must not be changed by sim_func
2126 * (i.e. removed from schedule) in this case
2128 if (node_inserted != NO_NODE_ADDED)
2129 next = sched_next(n);
2133 start_block = get_irg_start_block(get_irn_irg(block));
2135 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
2137 /* check if the state must be shuffled */
2138 foreach_block_succ(block, edge) {
2139 ir_node *succ = get_edge_src_irn(edge);
2140 blk_state *succ_state;
2142 if (succ == start_block)
2145 succ_state = x87_get_bl_state(sim, succ);
2147 if (succ_state->begin == NULL) {
2148 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2149 DEBUG_ONLY(x87_dump_stack(state);)
2150 succ_state->begin = state;
2152 waitq_put(sim->worklist, succ);
2154 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2155 /* There is already a begin state for the successor, bad.
2156 Do the necessary permutations.
2157 Note that critical edges are removed, so this is always possible:
2158 If the successor has more than one possible input, then it must
2161 x87_shuffle(sim, block, state, succ, succ_state->begin);
2164 bl_state->end = state;
2168 * Register a simulator function.
2170 * @param op the opcode to simulate
2171 * @param func the simulator function for the opcode
2173 static void register_sim(ir_op *op, sim_func func)
2175 assert(op->ops.generic == NULL);
2176 op->ops.generic = (op_func) func;
2180 * Create a new x87 simulator.
2182 * @param sim a simulator handle, will be initialized
2183 * @param irg the current graph
2185 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
2187 obstack_init(&sim->obst);
2188 sim->blk_states = pmap_create();
2189 sim->n_idx = get_irg_last_idx(irg);
2190 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
2192 DB((dbg, LEVEL_1, "--------------------------------\n"
2193 "x87 Simulator started for %+F\n", irg));
2195 /* set the generic function pointer of instruction we must simulate */
2196 ir_clear_opcodes_generic_func();
2198 register_sim(op_ia32_Call, sim_Call);
2199 register_sim(op_ia32_vfld, sim_fld);
2200 register_sim(op_ia32_vfild, sim_fild);
2201 register_sim(op_ia32_vfld1, sim_fld1);
2202 register_sim(op_ia32_vfldz, sim_fldz);
2203 register_sim(op_ia32_vfadd, sim_fadd);
2204 register_sim(op_ia32_vfsub, sim_fsub);
2205 register_sim(op_ia32_vfmul, sim_fmul);
2206 register_sim(op_ia32_vfdiv, sim_fdiv);
2207 register_sim(op_ia32_vfprem, sim_fprem);
2208 register_sim(op_ia32_vfabs, sim_fabs);
2209 register_sim(op_ia32_vfchs, sim_fchs);
2210 register_sim(op_ia32_vfist, sim_fist);
2211 register_sim(op_ia32_vfisttp, sim_fisttp);
2212 register_sim(op_ia32_vfst, sim_fst);
2213 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2214 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2215 register_sim(op_ia32_vFucomi, sim_Fucom);
2216 register_sim(op_be_Copy, sim_Copy);
2217 register_sim(op_be_Return, sim_Return);
2218 register_sim(op_be_Perm, sim_Perm);
2219 register_sim(op_be_Keep, sim_Keep);
2223 * Destroy a x87 simulator.
2225 * @param sim the simulator handle
2227 static void x87_destroy_simulator(x87_simulator *sim)
2229 pmap_destroy(sim->blk_states);
2230 obstack_free(&sim->obst, NULL);
2231 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2235 * Pre-block walker: calculate the liveness information for the block
2236 * and store it into the sim->live cache.
2238 static void update_liveness_walker(ir_node *block, void *data)
2240 x87_simulator *sim = (x87_simulator*)data;
2241 update_liveness(sim, block);
2245 * Run a simulation and fix all virtual instructions for a graph.
2246 * Replaces all virtual floating point instructions and registers
2249 void ia32_x87_simulate_graph(ir_graph *irg)
2251 /* TODO improve code quality (less executed fxch) by using execfreqs */
2253 ir_node *block, *start_block;
2254 blk_state *bl_state;
2257 /* create the simulator */
2258 x87_init_simulator(&sim, irg);
2260 start_block = get_irg_start_block(irg);
2261 bl_state = x87_get_bl_state(&sim, start_block);
2263 /* start with the empty state */
2264 bl_state->begin = empty;
2267 sim.worklist = new_waitq();
2268 waitq_put(sim.worklist, start_block);
2270 be_assure_live_sets(irg);
2271 sim.lv = be_get_irg_liveness(irg);
2273 /* Calculate the liveness for all nodes. We must precalculate this info,
2274 * because the simulator adds new nodes (possible before Phi nodes) which
2275 * would let a lazy calculation fail.
2276 * On the other hand we reduce the computation amount due to
2277 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2279 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2283 block = (ir_node*)waitq_get(sim.worklist);
2284 x87_simulate_block(&sim, block);
2285 } while (! waitq_empty(sim.worklist));
2288 del_waitq(sim.worklist);
2289 x87_destroy_simulator(&sim);
2292 /* Initializes the x87 simulator. */
2293 void ia32_init_x87(void)
2295 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");