2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define N_FLOAT_REGS (N_ia32_fp_REGS-1) // exclude NOREG
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An entry on the simulated x87 stack.
66 typedef struct st_entry {
67 int reg_idx; /**< the virtual register index of this stack value */
68 ir_node *node; /**< the node that produced this value */
74 typedef struct x87_state {
75 st_entry st[N_FLOAT_REGS]; /**< the register stack */
76 int depth; /**< the current stack depth */
77 x87_simulator *sim; /**< The simulator. */
80 /** An empty state, used for blocks without fp instructions. */
81 static x87_state empty = { { {0, NULL}, }, 0, NULL };
84 * Return values of the instruction simulator functions.
87 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
88 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
89 in the schedule AFTER the current node. */
93 * The type of an instruction simulator function.
95 * @param state the x87 state
96 * @param n the node to be simulated
98 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
100 * NO_NODE_ADDED otherwise
102 typedef int (*sim_func)(x87_state *state, ir_node *n);
105 * A block state: Every block has a x87 state at the beginning and at the end.
107 typedef struct blk_state {
108 x87_state *begin; /**< state at the begin or NULL if not assigned */
109 x87_state *end; /**< state at the end or NULL if not assigned */
112 /** liveness bitset for fp registers. */
113 typedef unsigned char fp_liveness;
118 struct x87_simulator {
119 struct obstack obst; /**< An obstack for fast allocating. */
120 pmap *blk_states; /**< Map blocks to states. */
121 be_lv_t *lv; /**< intrablock liveness. */
122 fp_liveness *live; /**< Liveness information. */
123 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
124 waitq *worklist; /**< Worklist of blocks that must be processed. */
128 * Returns the current stack depth.
130 * @param state the x87 state
132 * @return the x87 stack depth
134 static int x87_get_depth(const x87_state *state)
139 static st_entry *x87_get_entry(x87_state *const state, int const pos)
141 assert(0 <= pos && pos < state->depth);
142 return &state->st[N_FLOAT_REGS - state->depth + pos];
146 * Return the virtual register index at st(pos).
148 * @param state the x87 state
149 * @param pos a stack position
151 * @return the fp register index that produced the value at st(pos)
153 static int x87_get_st_reg(const x87_state *state, int pos)
155 return x87_get_entry((x87_state*)state, pos)->reg_idx;
160 * Dump the stack for debugging.
162 * @param state the x87 state
164 static void x87_dump_stack(const x87_state *state)
166 for (int i = state->depth; i-- != 0;) {
167 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
168 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
170 DB((dbg, LEVEL_2, "<-- TOS\n"));
172 #endif /* DEBUG_libfirm */
175 * Set a virtual register to st(pos).
177 * @param state the x87 state
178 * @param reg_idx the fp register index that should be set
179 * @param node the IR node that produces the value of the fp register
180 * @param pos the stack position where the new value should be entered
182 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
184 st_entry *const entry = x87_get_entry(state, pos);
185 entry->reg_idx = reg_idx;
188 DB((dbg, LEVEL_2, "After SET_REG: "));
189 DEBUG_ONLY(x87_dump_stack(state);)
193 * Swap st(0) with st(pos).
195 * @param state the x87 state
196 * @param pos the stack position to change the tos with
198 static void x87_fxch(x87_state *state, int pos)
200 st_entry *const a = x87_get_entry(state, pos);
201 st_entry *const b = x87_get_entry(state, 0);
202 st_entry const t = *a;
206 DB((dbg, LEVEL_2, "After FXCH: "));
207 DEBUG_ONLY(x87_dump_stack(state);)
211 * Convert a virtual register to the stack index.
213 * @param state the x87 state
214 * @param reg_idx the register fp index
216 * @return the stack position where the register is stacked
217 * or -1 if the virtual register was not found
219 static int x87_on_stack(const x87_state *state, int reg_idx)
221 for (int i = 0; i < state->depth; ++i) {
222 if (x87_get_st_reg(state, i) == reg_idx)
229 * Push a virtual Register onto the stack, double pushes are NOT allowed.
231 * @param state the x87 state
232 * @param reg_idx the register fp index
233 * @param node the node that produces the value of the fp register
235 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
237 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
238 assert(state->depth < N_FLOAT_REGS && "stack overrun");
241 st_entry *const entry = x87_get_entry(state, 0);
242 entry->reg_idx = reg_idx;
245 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
249 * Pop a virtual Register from the stack.
251 * @param state the x87 state
253 static void x87_pop(x87_state *state)
255 assert(state->depth > 0 && "stack underrun");
259 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
263 * Empty the fpu stack
265 * @param state the x87 state
267 static void x87_emms(x87_state *state)
273 * Returns the block state of a block.
275 * @param sim the x87 simulator handle
276 * @param block the current block
278 * @return the block state
280 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
282 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
285 res = OALLOC(&sim->obst, blk_state);
289 pmap_insert(sim->blk_states, block, res);
298 * @param sim the x87 simulator handle
299 * @param src the x87 state that will be cloned
301 * @return a cloned copy of the src state
303 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
305 x87_state *const res = OALLOC(&sim->obst, x87_state);
311 * Returns the first Proj of a mode_T node having a given mode.
313 * @param n the mode_T node
314 * @param m the desired mode of the Proj
315 * @return The first Proj of mode @p m found.
317 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
319 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
321 foreach_out_edge(n, edge) {
322 ir_node *proj = get_edge_src_irn(edge);
323 if (get_irn_mode(proj) == m)
327 panic("Proj not found");
331 * Wrap the arch_* function here so we can check for errors.
333 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
335 const arch_register_t *res = arch_get_irn_register(irn);
337 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
341 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
344 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
346 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_fp]);
350 static inline const arch_register_t *get_st_reg(int index)
352 return &ia32_registers[REG_ST0 + index];
356 * Create a fxch node before another node.
358 * @param state the x87 state
359 * @param n the node after the fxch
360 * @param pos exchange st(pos) with st(0)
362 static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
364 x87_fxch(state, pos);
366 ir_node *const block = get_nodes_block(n);
367 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
368 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
369 attr->reg = get_st_reg(pos);
373 sched_add_before(n, fxch);
374 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fxch), attr->reg->name));
377 /* -------------- x87 perm --------------- */
380 * Calculate the necessary permutations to reach dst_state.
382 * These permutations are done with fxch instructions and placed
383 * at the end of the block.
385 * Note that critical edges are removed here, so we need only
386 * a shuffle if the current block has only one successor.
388 * @param block the current block
389 * @param state the current x87 stack state, might be modified
390 * @param dst_state destination state
394 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
396 int i, n_cycles, k, ri;
397 unsigned cycles[4], all_mask;
398 char cycle_idx[4][8];
400 assert(state->depth == dst_state->depth);
402 /* Some mathematics here:
403 * If we have a cycle of length n that includes the tos,
404 * we need n-1 exchange operations.
405 * We can always add the tos and restore it, so we need
406 * n+1 exchange operations for a cycle not containing the tos.
407 * So, the maximum of needed operations is for a cycle of 7
408 * not including the tos == 8.
409 * This is the same number of ops we would need for using stores,
410 * so exchange is cheaper (we save the loads).
411 * On the other hand, we might need an additional exchange
412 * in the next block to bring one operand on top, so the
413 * number of ops in the first case is identical.
414 * Further, no more than 4 cycles can exists (4 x 2). */
415 all_mask = (1 << (state->depth)) - 1;
417 for (n_cycles = 0; all_mask; ++n_cycles) {
418 int src_idx, dst_idx;
420 /* find the first free slot */
421 for (i = 0; i < state->depth; ++i) {
422 if (all_mask & (1 << i)) {
423 all_mask &= ~(1 << i);
425 /* check if there are differences here */
426 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
432 /* no more cycles found */
437 cycles[n_cycles] = (1 << i);
438 cycle_idx[n_cycles][k++] = i;
439 for (src_idx = i; ; src_idx = dst_idx) {
440 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
442 if ((all_mask & (1 << dst_idx)) == 0)
445 cycle_idx[n_cycles][k++] = dst_idx;
446 cycles[n_cycles] |= (1 << dst_idx);
447 all_mask &= ~(1 << dst_idx);
449 cycle_idx[n_cycles][k] = -1;
453 /* no permutation needed */
457 /* Hmm: permutation needed */
458 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
459 DEBUG_ONLY(x87_dump_stack(state);)
460 DB((dbg, LEVEL_2, " to\n"));
461 DEBUG_ONLY(x87_dump_stack(dst_state);)
465 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
466 for (ri = 0; ri < n_cycles; ++ri) {
467 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
468 for (k = 0; cycle_idx[ri][k] != -1; ++k)
469 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
470 DB((dbg, LEVEL_2, "\n"));
475 * Find the place node must be insert.
476 * We have only one successor block, so the last instruction should
479 ir_node *const before = sched_last(block);
480 assert(is_cfop(before));
482 /* now do the permutations */
483 for (ri = 0; ri < n_cycles; ++ri) {
484 if ((cycles[ri] & 1) == 0) {
485 /* this cycle does not include the tos */
486 x87_create_fxch(state, before, cycle_idx[ri][0]);
488 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
489 x87_create_fxch(state, before, cycle_idx[ri][k]);
491 if ((cycles[ri] & 1) == 0) {
492 /* this cycle does not include the tos */
493 x87_create_fxch(state, before, cycle_idx[ri][0]);
500 * Create a fpush before node n.
502 * @param state the x87 state
503 * @param n the node after the fpush
504 * @param pos push st(pos) on stack
505 * @param val the value to push
507 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
509 x87_push(state, out_reg_idx, val);
511 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
512 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
513 attr->reg = get_st_reg(pos);
516 sched_add_before(n, fpush);
518 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpush), attr->reg->name));
522 * Create a fpop before node n.
523 * This overwrites st(pos) with st(0) and pops st(0).
525 * @param state the x87 state
526 * @param n the node after the fpop
527 * @param pos the index of the entry to remove the register stack
529 * @return the fpop node
531 static ir_node *x87_create_fpop(x87_state *const state, ir_node *const n, int const pos)
534 st_entry *const dst = x87_get_entry(state, pos);
535 st_entry *const src = x87_get_entry(state, 0);
539 ir_node *const block = get_nodes_block(n);
540 ir_node *const fpop = pos == 0 && ia32_cg_config.use_ffreep ?
541 new_bd_ia32_ffreep(NULL, block) :
542 new_bd_ia32_fpop( NULL, block);
543 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpop);
544 attr->reg = get_st_reg(pos);
547 sched_add_before(n, fpop);
548 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->reg->name));
552 /* --------------------------------- liveness ------------------------------------------ */
555 * The liveness transfer function.
556 * Updates a live set over a single step from a given node to its predecessor.
557 * Everything defined at the node is removed from the set, the uses of the node get inserted.
559 * @param irn The node at which liveness should be computed.
560 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
561 * the registers live after irn.
563 * @return The live bitset.
565 static fp_liveness fp_liveness_transfer(ir_node *irn, fp_liveness live)
567 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
569 be_foreach_definition(irn, cls, def, req,
570 const arch_register_t *reg = x87_get_irn_register(def);
571 live &= ~(1 << reg->index);
573 be_foreach_use(irn, cls, in_req_, op, op_req_,
574 const arch_register_t *reg = x87_get_irn_register(op);
575 live |= 1 << reg->index;
581 * Put all live virtual registers at the end of a block into a bitset.
583 * @param sim the simulator handle
584 * @param bl the block
586 * @return The live bitset at the end of this block
588 static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
590 fp_liveness live = 0;
591 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
592 const be_lv_t *lv = sim->lv;
594 be_lv_foreach_cls(lv, block, be_lv_state_end, cls, node) {
595 const arch_register_t *reg = x87_get_irn_register(node);
596 live |= 1 << reg->index;
602 /** get the register mask from an arch_register */
603 #define REGMASK(reg) (1 << (reg->index))
606 * Return a bitset of argument registers which are live at the end of a node.
608 * @param sim the simulator handle
609 * @param pos the node
610 * @param kill kill mask for the output registers
612 * @return The live bitset.
614 static unsigned fp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
616 unsigned idx = get_irn_idx(pos);
618 assert(idx < sim->n_idx);
619 return sim->live[idx] & ~kill;
623 * Calculate the liveness for a whole block and cache it.
625 * @param sim the simulator handle
626 * @param block the block
628 static void update_liveness(x87_simulator *sim, ir_node *block)
630 fp_liveness live = fp_liveness_end_of_block(sim, block);
633 /* now iterate through the block backward and cache the results */
634 sched_foreach_reverse(block, irn) {
635 /* stop at the first Phi: this produces the live-in */
639 idx = get_irn_idx(irn);
640 sim->live[idx] = live;
642 live = fp_liveness_transfer(irn, live);
644 idx = get_irn_idx(block);
645 sim->live[idx] = live;
649 * Returns true if a register is live in a set.
651 * @param reg_idx the fp register index
652 * @param live a live bitset
654 #define is_fp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
658 * Dump liveness info.
660 * @param live the live bitset
662 static void fp_dump_live(fp_liveness live)
666 DB((dbg, LEVEL_2, "Live after: "));
667 for (i = 0; i < 8; ++i) {
668 if (live & (1 << i)) {
669 DB((dbg, LEVEL_2, "vf%d ", i));
672 DB((dbg, LEVEL_2, "\n"));
674 #endif /* DEBUG_libfirm */
676 /* --------------------------------- simulators ---------------------------------------- */
679 * Simulate a virtual binop.
681 * @param state the x87 state
682 * @param n the node that should be simulated (and patched)
684 * @return NO_NODE_ADDED
686 static int sim_binop(x87_state *const state, ir_node *const n)
688 x87_simulator *sim = state->sim;
689 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
690 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
691 const arch_register_t *op1_reg = x87_get_irn_register(op1);
692 const arch_register_t *op2_reg = x87_get_irn_register(op2);
693 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
694 int reg_index_1 = op1_reg->index;
695 int reg_index_2 = op2_reg->index;
696 fp_liveness live = fp_live_args_after(sim, n, REGMASK(out));
700 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, op1_reg->name, op2_reg->name, out->name));
701 DEBUG_ONLY(fp_dump_live(live);)
702 DB((dbg, LEVEL_1, "Stack before: "));
703 DEBUG_ONLY(x87_dump_stack(state);)
705 int op1_idx = x87_on_stack(state, reg_index_1);
706 assert(op1_idx >= 0);
707 op1_live_after = is_fp_live(reg_index_1, live);
712 int const out_reg_idx = out->index;
713 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
714 if (reg_index_2 != REG_FP_FP_NOREG) {
715 /* second operand is a fp register */
716 op2_idx = x87_on_stack(state, reg_index_2);
717 assert(op2_idx >= 0);
718 op2_live_after = is_fp_live(reg_index_2, live);
720 if (op2_live_after) {
721 /* Second operand is live. */
723 if (op1_live_after) {
724 /* Both operands are live: push the first one.
725 * This works even for op1 == op2. */
726 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
727 /* now do fxxx (tos=tos X op) */
732 /* Second live, first operand is dead: Overwrite first. */
733 if (op1_idx != 0 && op2_idx != 0) {
734 /* Bring one operand to tos. */
735 x87_create_fxch(state, n, op1_idx);
741 /* Second operand is dead. */
742 if (op1_live_after) {
743 /* First operand is live, second is dead: Overwrite second. */
744 if (op1_idx != 0 && op2_idx != 0) {
745 /* Bring one operand to tos. */
746 x87_create_fxch(state, n, op2_idx);
751 /* Both operands are dead. */
752 if (op1_idx == op2_idx) {
753 /* Operands are identical: no pop. */
755 x87_create_fxch(state, n, op1_idx);
760 if (op1_idx != 0 && op2_idx != 0) {
761 /* Bring one operand to tos. Heuristically swap the operand not at
762 * st(1) to tos. This way, if any operand was at st(1), the result
763 * will end up in the new st(0) after the implicit pop. If the next
764 * operation uses the result, then no fxch will be necessary. */
766 x87_create_fxch(state, n, op1_idx);
769 x87_create_fxch(state, n, op2_idx);
775 out_idx = op1_idx != 0 ? op1_idx : op2_idx;
779 /* second operand is an address mode */
780 if (op1_live_after) {
781 /* first operand is live: push it here */
782 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
784 /* first operand is dead: bring it to tos */
786 x87_create_fxch(state, n, op1_idx);
789 op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
790 op2_idx = attr->attr.data.ins_permuted ? 0 : -1;
793 assert(op1_idx == 0 || op2_idx == 0);
794 assert(out_idx == op1_idx || out_idx == op2_idx);
796 x87_set_st(state, out_reg_idx, n, out_idx);
800 /* patch the operation */
801 int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
802 attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
803 attr->attr.data.ins_permuted = op1_idx != 0;
804 attr->res_in_reg = out_idx != 0;
808 char const *const l = op1_idx >= 0 ? get_st_reg(op1_idx)->name : "[AM]";
809 char const *const r = op2_idx >= 0 ? get_st_reg(op2_idx)->name : "[AM]";
810 char const *const o = get_st_reg(out_idx)->name;
811 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), l, r, o));
814 return NO_NODE_ADDED;
818 * Simulate a virtual Unop.
820 * @param state the x87 state
821 * @param n the node that should be simulated (and patched)
823 * @return NO_NODE_ADDED
825 static int sim_unop(x87_state *state, ir_node *n)
827 arch_register_t const *const out = x87_get_irn_register(n);
828 unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
829 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
830 DEBUG_ONLY(fp_dump_live(live);)
832 ir_node *const op1 = get_irn_n(n, 0);
833 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
834 int const op1_reg_idx = op1_reg->index;
835 int const op1_idx = x87_on_stack(state, op1_reg_idx);
836 int const out_reg_idx = out->index;
837 if (is_fp_live(op1_reg_idx, live)) {
838 /* push the operand here */
839 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
841 /* operand is dead, bring it to tos */
843 x87_create_fxch(state, n, op1_idx);
847 x87_set_st(state, out_reg_idx, n, 0);
848 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
850 return NO_NODE_ADDED;
854 * Simulate a virtual Load instruction.
856 * @param state the x87 state
857 * @param n the node that should be simulated (and patched)
859 * @return NO_NODE_ADDED
861 static int sim_load(x87_state *state, ir_node *n)
863 assert((int)pn_ia32_fld_res == (int)pn_ia32_fild_res
864 && (int)pn_ia32_fld_res == (int)pn_ia32_fld1_res
865 && (int)pn_ia32_fld_res == (int)pn_ia32_fldz_res);
866 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_fld_res);
868 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
869 x87_push(state, out->index, n);
870 assert(out == x87_irn_get_register(n, pn_ia32_fld_res));
871 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), get_st_reg(0)->name));
873 return NO_NODE_ADDED;
877 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
879 * @param store The store
880 * @param old_val The former value
881 * @param new_val The new value
883 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
885 foreach_out_edge_safe(old_val, edge) {
886 ir_node *user = get_edge_src_irn(edge);
887 /* if the user is scheduled after the store: rewire */
888 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
889 set_irn_n(user, get_edge_src_pos(edge), new_val);
895 * Simulate a virtual Store.
897 * @param state the x87 state
898 * @param n the node that should be simulated (and patched)
900 static int sim_store(x87_state *state, ir_node *n)
902 ir_node *const val = get_irn_n(n, n_ia32_fst_val);
903 arch_register_t const *const op2 = x87_get_irn_register(val);
904 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
907 int insn = NO_NODE_ADDED;
908 int const op2_reg_idx = op2->index;
909 int const op2_idx = x87_on_stack(state, op2_reg_idx);
910 unsigned const live = fp_live_args_after(state->sim, n, 0);
911 int const live_after_node = is_fp_live(op2_reg_idx, live);
912 assert(op2_idx >= 0);
913 if (live_after_node) {
914 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
915 * fist doesn't support 64bit mode, only fistp
917 * - stack not full: push value and fstp
918 * - stack full: fstp value and load again
919 * Note that we cannot test on mode_E, because floats might be 80bit ... */
920 ir_mode *const mode = get_ia32_ls_mode(n);
921 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32U : 64U)) {
922 if (x87_get_depth(state) < N_FLOAT_REGS) {
923 /* ok, we have a free register: push + fstp */
924 x87_create_fpush(state, n, op2_idx, REG_FP_FP_NOREG, val);
927 /* stack full here: need fstp + load */
930 ir_node *const block = get_nodes_block(n);
931 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
932 ir_node *const vfld = new_bd_ia32_fld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
934 /* copy all attributes */
935 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
936 if (is_ia32_use_frame(n))
937 set_ia32_use_frame(vfld);
938 set_ia32_op_type(vfld, ia32_AddrModeS);
939 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
940 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
941 set_ia32_ls_mode(vfld, mode);
943 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_fld_res);
944 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_fld_M);
946 arch_set_irn_register(rproj, op2);
948 /* reroute all former users of the store memory to the load memory */
949 edges_reroute_except(mem, mproj, vfld);
951 sched_add_after(n, vfld);
953 /* rewire all users, scheduled after the store, to the loaded value */
954 collect_and_rewire_users(n, val, rproj);
959 /* we can only store the tos to memory */
961 x87_create_fxch(state, n, op2_idx);
964 /* we can only store the tos to memory */
966 x87_create_fxch(state, n, op2_idx);
974 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
976 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
981 static int sim_fprem(x87_state *const state, ir_node *const n)
985 panic("TODO implement");
989 * Simulate a virtual fisttp.
991 * @param state the x87 state
992 * @param n the node that should be simulated (and patched)
994 * @return NO_NODE_ADDED
996 static int sim_fisttp(x87_state *state, ir_node *n)
998 ir_node *val = get_irn_n(n, n_ia32_fst_val);
999 const arch_register_t *op2 = x87_get_irn_register(val);
1001 int const op2_idx = x87_on_stack(state, op2->index);
1002 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
1003 assert(op2_idx >= 0);
1005 /* Note: although the value is still live here, it is destroyed because
1006 of the pop. The register allocator is aware of that and introduced a copy
1007 if the value must be alive. */
1009 /* we can only store the tos to memory */
1011 x87_create_fxch(state, n, op2_idx);
1015 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), get_st_reg(0)->name));
1017 return NO_NODE_ADDED;
1021 * Simulate a virtual FtstFnstsw.
1023 * @param state the x87 state
1024 * @param n the node that should be simulated (and patched)
1026 * @return NO_NODE_ADDED
1028 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1030 x87_simulator *sim = state->sim;
1031 ir_node *op1_node = get_irn_n(n, n_ia32_FtstFnstsw_left);
1032 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1033 int reg_index_1 = reg1->index;
1034 int op1_idx = x87_on_stack(state, reg_index_1);
1035 unsigned live = fp_live_args_after(sim, n, 0);
1037 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, reg1->name));
1038 DEBUG_ONLY(fp_dump_live(live);)
1039 DB((dbg, LEVEL_1, "Stack before: "));
1040 DEBUG_ONLY(x87_dump_stack(state);)
1041 assert(op1_idx >= 0);
1044 /* bring the value to tos */
1045 x87_create_fxch(state, n, op1_idx);
1048 if (!is_fp_live(reg_index_1, live))
1049 x87_create_fpop(state, sched_next(n), 0);
1051 return NO_NODE_ADDED;
1057 * @param state the x87 state
1058 * @param n the node that should be simulated (and patched)
1060 * @return NO_NODE_ADDED
1062 static int sim_Fucom(x87_state *state, ir_node *n)
1064 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1065 x87_simulator *sim = state->sim;
1066 ir_node *op1_node = get_irn_n(n, n_ia32_FucomFnstsw_left);
1067 ir_node *op2_node = get_irn_n(n, n_ia32_FucomFnstsw_right);
1068 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1069 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1070 int reg_index_1 = op1->index;
1071 int reg_index_2 = op2->index;
1072 unsigned live = fp_live_args_after(sim, n, 0);
1074 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, op1->name, op2->name));
1075 DEBUG_ONLY(fp_dump_live(live);)
1076 DB((dbg, LEVEL_1, "Stack before: "));
1077 DEBUG_ONLY(x87_dump_stack(state);)
1079 int op1_idx = x87_on_stack(state, reg_index_1);
1080 assert(op1_idx >= 0);
1084 /* BEWARE: check for comp a,a cases, they might happen */
1085 if (reg_index_2 != REG_FP_FP_NOREG) {
1086 /* second operand is a fp register */
1087 op2_idx = x87_on_stack(state, reg_index_2);
1088 assert(op2_idx >= 0);
1090 if (is_fp_live(reg_index_2, live)) {
1091 /* second operand is live */
1093 if (is_fp_live(reg_index_1, live)) {
1094 /* both operands are live */
1095 if (op1_idx != 0 && op2_idx != 0) {
1096 /* bring the first one to tos */
1097 x87_create_fxch(state, n, op1_idx);
1098 if (op1_idx == op2_idx)
1101 /* res = tos X op */
1104 /* second live, first operand is dead here, bring it to tos.
1105 This means further, op1_idx != op2_idx. */
1106 assert(op1_idx != op2_idx);
1108 x87_create_fxch(state, n, op1_idx);
1113 /* res = tos X op, pop */
1117 /* second operand is dead */
1118 if (is_fp_live(reg_index_1, live)) {
1119 /* first operand is live: bring second to tos.
1120 This means further, op1_idx != op2_idx. */
1121 assert(op1_idx != op2_idx);
1123 x87_create_fxch(state, n, op2_idx);
1128 /* res = op X tos, pop */
1131 /* both operands are dead here, check first for identity. */
1132 if (op1_idx == op2_idx) {
1133 /* identically, one pop needed */
1135 x87_create_fxch(state, n, op1_idx);
1139 /* res = tos X op, pop */
1142 if (op1_idx != 0 && op2_idx != 0) {
1143 /* Both not at tos: Move one operand to tos. Move the one not at
1144 * pos 1, so we get a chance to use fucompp. */
1146 x87_create_fxch(state, n, op1_idx);
1149 x87_create_fxch(state, n, op2_idx);
1158 /* second operand is an address mode */
1160 x87_create_fxch(state, n, op1_idx);
1161 /* Pop first operand, if it is dead. */
1162 if (!is_fp_live(reg_index_1, live))
1165 op1_idx = attr->attr.data.ins_permuted ? -1 : 0;
1166 op2_idx = attr->attr.data.ins_permuted ? 0 : -1;
1168 assert(op1_idx == 0 || op2_idx == 0);
1170 /* patch the operation */
1171 if (is_ia32_FucomFnstsw(n) && pops == 2
1172 && (op1_idx == 1 || op2_idx == 1)) {
1173 set_irn_op(n, op_ia32_FucomppFnstsw);
1180 int const idx = (op1_idx != 0 ? op1_idx : op2_idx) - 1 /* Due to prior pop. */;
1181 x87_create_fpop(state, sched_next(n), idx);
1185 int const reg_idx = op1_idx != 0 ? op1_idx : op2_idx;
1186 attr->reg = reg_idx >= 0 ? get_st_reg(reg_idx) : NULL;
1187 attr->attr.data.ins_permuted = op1_idx != 0;
1188 attr->pop = pops != 0;
1191 char const *const l = op1_idx >= 0 ? get_st_reg(op1_idx)->name : "[AM]";
1192 char const *const r = op2_idx >= 0 ? get_st_reg(op2_idx)->name : "[AM]";
1193 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n), l, r));
1196 return NO_NODE_ADDED;
1202 * @param state the x87 state
1203 * @param n the node that should be simulated (and patched)
1205 * @return NO_NODE_ADDED
1207 static int sim_Keep(x87_state *state, ir_node *node)
1210 const arch_register_t *op_reg;
1216 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1218 arity = get_irn_arity(node);
1219 for (i = 0; i < arity; ++i) {
1220 op = get_irn_n(node, i);
1221 op_reg = arch_get_irn_register(op);
1222 if (op_reg->reg_class != &ia32_reg_classes[CLASS_ia32_fp])
1225 reg_id = op_reg->index;
1226 live = fp_live_args_after(state->sim, node, 0);
1228 op_stack_idx = x87_on_stack(state, reg_id);
1229 if (op_stack_idx >= 0 && !is_fp_live(reg_id, live))
1230 x87_create_fpop(state, sched_next(node), 0);
1233 DB((dbg, LEVEL_1, "Stack after: "));
1234 DEBUG_ONLY(x87_dump_stack(state);)
1236 return NO_NODE_ADDED;
1240 * Keep the given node alive by adding a be_Keep.
1242 * @param node the node to kept alive
1244 static void keep_float_node_alive(ir_node *node)
1246 ir_node *block = get_nodes_block(node);
1247 ir_node *keep = be_new_Keep(block, 1, &node);
1248 sched_add_after(node, keep);
1252 * Create a copy of a node. Recreate the node if it's a constant.
1254 * @param state the x87 state
1255 * @param n the node to be copied
1257 * @return the copy of n
1259 static ir_node *create_Copy(x87_state *state, ir_node *n)
1261 dbg_info *n_dbg = get_irn_dbg_info(n);
1262 ir_mode *mode = get_irn_mode(n);
1263 ir_node *block = get_nodes_block(n);
1264 ir_node *pred = get_irn_n(n, 0);
1265 ir_node *(*cnstr)(dbg_info *, ir_node *) = NULL;
1267 const arch_register_t *out;
1268 const arch_register_t *op1;
1270 /* Do not copy constants, recreate them. */
1271 switch (get_ia32_irn_opcode(pred)) {
1273 cnstr = new_bd_ia32_fldz;
1276 cnstr = new_bd_ia32_fld1;
1278 case iro_ia32_fldpi:
1279 cnstr = new_bd_ia32_fldpi;
1281 case iro_ia32_fldl2e:
1282 cnstr = new_bd_ia32_fldl2e;
1284 case iro_ia32_fldl2t:
1285 cnstr = new_bd_ia32_fldl2t;
1287 case iro_ia32_fldlg2:
1288 cnstr = new_bd_ia32_fldlg2;
1290 case iro_ia32_fldln2:
1291 cnstr = new_bd_ia32_fldln2;
1297 out = x87_get_irn_register(n);
1298 op1 = x87_get_irn_register(pred);
1300 if (cnstr != NULL) {
1301 /* copy a constant */
1302 res = (*cnstr)(n_dbg, block);
1304 x87_push(state, out->index, res);
1306 int op1_idx = x87_on_stack(state, op1->index);
1308 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1310 x87_push(state, out->index, res);
1312 ia32_x87_attr_t *const attr = get_ia32_x87_attr(res);
1313 attr->reg = get_st_reg(op1_idx);
1315 arch_set_irn_register(res, out);
1321 * Simulate a be_Copy.
1323 * @param state the x87 state
1324 * @param n the node that should be simulated (and patched)
1326 * @return NO_NODE_ADDED
1328 static int sim_Copy(x87_state *state, ir_node *n)
1330 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1331 if (cls != &ia32_reg_classes[CLASS_ia32_fp])
1332 return NO_NODE_ADDED;
1334 ir_node *const pred = be_get_Copy_op(n);
1335 arch_register_t const *const op1 = x87_get_irn_register(pred);
1336 arch_register_t const *const out = x87_get_irn_register(n);
1337 unsigned const live = fp_live_args_after(state->sim, n, REGMASK(out));
1339 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, op1->name, out->name));
1340 DEBUG_ONLY(fp_dump_live(live);)
1342 if (is_fp_live(op1->index, live)) {
1343 /* Operand is still live, a real copy. We need here an fpush that can
1344 hold a a register, so use the fpushCopy or recreate constants */
1345 ir_node *const node = create_Copy(state, n);
1347 /* We have to make sure the old value doesn't go dead (which can happen
1348 * when we recreate constants). As the simulator expected that value in
1349 * the pred blocks. This is unfortunate as removing it would save us 1
1350 * instruction, but we would have to rerun all the simulation to get
1353 ir_node *const next = sched_next(n);
1356 sched_add_before(next, node);
1358 if (get_irn_n_edges(pred) == 0) {
1359 keep_float_node_alive(pred);
1362 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1364 /* Just a virtual copy. */
1365 int const op1_idx = x87_on_stack(state, op1->index);
1366 x87_set_st(state, out->index, n, op1_idx);
1368 return NO_NODE_ADDED;
1372 * Returns the vf0 result Proj of a Call.
1374 * @para call the Call node
1376 static ir_node *get_call_result_proj(ir_node *call)
1378 /* search the result proj */
1379 foreach_out_edge(call, edge) {
1380 ir_node *proj = get_edge_src_irn(edge);
1381 long pn = get_Proj_proj(proj);
1383 if (pn == pn_ia32_Call_st0)
1387 panic("result Proj missing");
1390 static int sim_Asm(x87_state *const state, ir_node *const n)
1394 be_foreach_use(n, &ia32_reg_classes[CLASS_ia32_fp], in_req, value, value_req,
1395 panic("cannot handle %+F with x87 constraints", n);
1398 be_foreach_out(n, i) {
1399 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1400 if (req->cls == &ia32_reg_classes[CLASS_ia32_fp])
1401 panic("cannot handle %+F with x87 constraints", n);
1404 return NO_NODE_ADDED;
1408 * Simulate a ia32_Call.
1410 * @param state the x87 state
1411 * @param n the node that should be simulated (and patched)
1413 * @return NO_NODE_ADDED
1415 static int sim_Call(x87_state *state, ir_node *n)
1417 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1419 /* at the begin of a call the x87 state should be empty */
1420 assert(state->depth == 0 && "stack not empty before call");
1422 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1423 if (get_method_n_ress(call_tp) != 0) {
1424 /* If the called function returns a float, it is returned in st(0).
1425 * This even happens if the return value is NOT used.
1426 * Moreover, only one return result is supported. */
1427 ir_type *const res_type = get_method_res_type(call_tp, 0);
1428 ir_mode *const mode = get_type_mode(res_type);
1429 if (mode && mode_is_float(mode)) {
1430 ir_node *const resproj = get_call_result_proj(n);
1431 arch_register_t const *const reg = x87_get_irn_register(resproj);
1432 x87_push(state, reg->index, resproj);
1435 DB((dbg, LEVEL_1, "Stack after: "));
1436 DEBUG_ONLY(x87_dump_stack(state);)
1438 return NO_NODE_ADDED;
1442 * Simulate a be_Return.
1444 * @param state the x87 state
1445 * @param n the node that should be simulated (and patched)
1447 * @return NO_NODE_ADDED
1449 static int sim_Return(x87_state *state, ir_node *n)
1451 #ifdef DEBUG_libfirm
1452 /* only floating point return values must reside on stack */
1453 int n_float_res = 0;
1454 int const n_res = be_Return_get_n_rets(n);
1455 for (int i = 0; i < n_res; ++i) {
1456 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1457 if (mode_is_float(get_irn_mode(res)))
1460 assert(x87_get_depth(state) == n_float_res);
1463 /* pop them virtually */
1465 return NO_NODE_ADDED;
1469 * Simulate a be_Perm.
1471 * @param state the x87 state
1472 * @param irn the node that should be simulated (and patched)
1474 * @return NO_NODE_ADDED
1476 static int sim_Perm(x87_state *state, ir_node *irn)
1479 ir_node *pred = get_irn_n(irn, 0);
1482 /* handle only floating point Perms */
1483 if (! mode_is_float(get_irn_mode(pred)))
1484 return NO_NODE_ADDED;
1486 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1488 /* Perm is a pure virtual instruction on x87.
1489 All inputs must be on the FPU stack and are pairwise
1490 different from each other.
1491 So, all we need to do is to permutate the stack state. */
1492 n = get_irn_arity(irn);
1493 NEW_ARR_A(int, stack_pos, n);
1495 /* collect old stack positions */
1496 for (i = 0; i < n; ++i) {
1497 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1498 int idx = x87_on_stack(state, inreg->index);
1500 assert(idx >= 0 && "Perm argument not on x87 stack");
1504 /* now do the permutation */
1505 foreach_out_edge(irn, edge) {
1506 ir_node *proj = get_edge_src_irn(edge);
1507 const arch_register_t *out = x87_get_irn_register(proj);
1508 long num = get_Proj_proj(proj);
1510 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1511 x87_set_st(state, out->index, proj, stack_pos[(unsigned)num]);
1513 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1515 return NO_NODE_ADDED;
1519 * Kill any dead registers at block start by popping them from the stack.
1521 * @param sim the simulator handle
1522 * @param block the current block
1523 * @param state the x87 state at the begin of the block
1525 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1527 ir_node *first_insn = sched_first(block);
1528 ir_node *keep = NULL;
1529 unsigned live = fp_live_args_after(sim, block, 0);
1534 depth = x87_get_depth(state);
1535 for (i = depth - 1; i >= 0; --i) {
1536 int reg = x87_get_st_reg(state, i);
1538 if (! is_fp_live(reg, live))
1539 kill_mask |= (1 << i);
1543 DB((dbg, LEVEL_1, "Killing deads:\n"));
1544 DEBUG_ONLY(fp_dump_live(live);)
1545 DEBUG_ONLY(x87_dump_stack(state);)
1547 if (kill_mask != 0 && live == 0) {
1548 /* special case: kill all registers */
1549 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1550 if (ia32_cg_config.use_femms) {
1551 /* use FEMMS on AMD processors to clear all */
1552 keep = new_bd_ia32_femms(NULL, block);
1554 /* use EMMS to clear all */
1555 keep = new_bd_ia32_emms(NULL, block);
1557 sched_add_before(first_insn, keep);
1563 /* now kill registers */
1565 /* we can only kill from TOS, so bring them up */
1566 if (! (kill_mask & 1)) {
1567 /* search from behind, because we can to a double-pop */
1568 for (i = depth - 1; i >= 0; --i) {
1569 if (kill_mask & (1 << i)) {
1570 kill_mask &= ~(1 << i);
1577 x87_set_st(state, -1, keep, i);
1578 x87_create_fxch(state, first_insn, i);
1583 keep = x87_create_fpop(state, first_insn, 0);
1590 * Run a simulation and fix all virtual instructions for a block.
1592 * @param sim the simulator handle
1593 * @param block the current block
1595 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1598 blk_state *bl_state = x87_get_bl_state(sim, block);
1599 x87_state *state = bl_state->begin;
1600 ir_node *start_block;
1602 assert(state != NULL);
1603 /* already processed? */
1604 if (bl_state->end != NULL)
1607 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1608 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1609 DEBUG_ONLY(x87_dump_stack(state);)
1611 /* create a new state, will be changed */
1612 state = x87_clone_state(sim, state);
1613 /* at block begin, kill all dead registers */
1614 x87_kill_deads(sim, block, state);
1616 /* beware, n might change */
1617 for (n = sched_first(block); !sched_is_end(n); n = next) {
1620 ir_op *op = get_irn_op(n);
1623 * get the next node to be simulated here.
1624 * n might be completely removed from the schedule-
1626 next = sched_next(n);
1627 if (op->ops.generic != NULL) {
1628 func = (sim_func)op->ops.generic;
1631 node_inserted = (*func)(state, n);
1634 * sim_func might have added an additional node after n,
1635 * so update next node
1636 * beware: n must not be changed by sim_func
1637 * (i.e. removed from schedule) in this case
1639 if (node_inserted != NO_NODE_ADDED)
1640 next = sched_next(n);
1644 start_block = get_irg_start_block(get_irn_irg(block));
1646 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1648 /* check if the state must be shuffled */
1649 foreach_block_succ(block, edge) {
1650 ir_node *succ = get_edge_src_irn(edge);
1651 blk_state *succ_state;
1653 if (succ == start_block)
1656 succ_state = x87_get_bl_state(sim, succ);
1658 if (succ_state->begin == NULL) {
1659 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
1660 DEBUG_ONLY(x87_dump_stack(state);)
1661 succ_state->begin = state;
1663 waitq_put(sim->worklist, succ);
1665 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
1666 /* There is already a begin state for the successor, bad.
1667 Do the necessary permutations.
1668 Note that critical edges are removed, so this is always possible:
1669 If the successor has more than one possible input, then it must
1672 x87_shuffle(block, state, succ_state->begin);
1675 bl_state->end = state;
1679 * Register a simulator function.
1681 * @param op the opcode to simulate
1682 * @param func the simulator function for the opcode
1684 static void register_sim(ir_op *op, sim_func func)
1686 assert(op->ops.generic == NULL);
1687 op->ops.generic = (op_func) func;
1691 * Create a new x87 simulator.
1693 * @param sim a simulator handle, will be initialized
1694 * @param irg the current graph
1696 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
1698 obstack_init(&sim->obst);
1699 sim->blk_states = pmap_create();
1700 sim->n_idx = get_irg_last_idx(irg);
1701 sim->live = OALLOCN(&sim->obst, fp_liveness, sim->n_idx);
1703 DB((dbg, LEVEL_1, "--------------------------------\n"
1704 "x87 Simulator started for %+F\n", irg));
1706 /* set the generic function pointer of instruction we must simulate */
1707 ir_clear_opcodes_generic_func();
1709 register_sim(op_ia32_Asm, sim_Asm);
1710 register_sim(op_ia32_Call, sim_Call);
1711 register_sim(op_ia32_fld, sim_load);
1712 register_sim(op_ia32_fild, sim_load);
1713 register_sim(op_ia32_fld1, sim_load);
1714 register_sim(op_ia32_fldz, sim_load);
1715 register_sim(op_ia32_fadd, sim_binop);
1716 register_sim(op_ia32_fsub, sim_binop);
1717 register_sim(op_ia32_fmul, sim_binop);
1718 register_sim(op_ia32_fdiv, sim_binop);
1719 register_sim(op_ia32_fprem, sim_fprem);
1720 register_sim(op_ia32_fabs, sim_unop);
1721 register_sim(op_ia32_fchs, sim_unop);
1722 register_sim(op_ia32_fist, sim_store);
1723 register_sim(op_ia32_fisttp, sim_fisttp);
1724 register_sim(op_ia32_fst, sim_store);
1725 register_sim(op_ia32_FtstFnstsw, sim_FtstFnstsw);
1726 register_sim(op_ia32_FucomFnstsw, sim_Fucom);
1727 register_sim(op_ia32_Fucomi, sim_Fucom);
1728 register_sim(op_be_Copy, sim_Copy);
1729 register_sim(op_be_Return, sim_Return);
1730 register_sim(op_be_Perm, sim_Perm);
1731 register_sim(op_be_Keep, sim_Keep);
1735 * Destroy a x87 simulator.
1737 * @param sim the simulator handle
1739 static void x87_destroy_simulator(x87_simulator *sim)
1741 pmap_destroy(sim->blk_states);
1742 obstack_free(&sim->obst, NULL);
1743 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
1747 * Pre-block walker: calculate the liveness information for the block
1748 * and store it into the sim->live cache.
1750 static void update_liveness_walker(ir_node *block, void *data)
1752 x87_simulator *sim = (x87_simulator*)data;
1753 update_liveness(sim, block);
1757 * Run a simulation and fix all virtual instructions for a graph.
1758 * Replaces all virtual floating point instructions and registers
1761 void ia32_x87_simulate_graph(ir_graph *irg)
1763 /* TODO improve code quality (less executed fxch) by using execfreqs */
1765 ir_node *block, *start_block;
1766 blk_state *bl_state;
1769 /* create the simulator */
1770 x87_init_simulator(&sim, irg);
1772 start_block = get_irg_start_block(irg);
1773 bl_state = x87_get_bl_state(&sim, start_block);
1775 /* start with the empty state */
1777 bl_state->begin = ∅
1779 sim.worklist = new_waitq();
1780 waitq_put(sim.worklist, start_block);
1782 be_assure_live_sets(irg);
1783 sim.lv = be_get_irg_liveness(irg);
1785 /* Calculate the liveness for all nodes. We must precalculate this info,
1786 * because the simulator adds new nodes (possible before Phi nodes) which
1787 * would let a lazy calculation fail.
1788 * On the other hand we reduce the computation amount due to
1789 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
1791 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
1795 block = (ir_node*)waitq_get(sim.worklist);
1796 x87_simulate_block(&sim, block);
1797 } while (! waitq_empty(sim.worklist));
1800 del_waitq(sim.worklist);
1801 x87_destroy_simulator(&sim);
1804 /* Initializes the x87 simulator. */
1805 void ia32_init_x87(void)
1807 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");