2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 /** the debug handle */
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 /* Forward declaration. */
59 typedef struct x87_simulator x87_simulator;
62 * An exchange template.
63 * Note that our virtual functions have the same inputs
64 * and attributes as the real ones, so we can simple exchange
66 * Further, x87 supports inverse instructions, so we can handle them.
68 typedef struct exchange_tmpl {
69 ir_op *normal_op; /**< the normal one */
70 ir_op *reverse_op; /**< the reverse one if exists */
71 ir_op *normal_pop_op; /**< the normal one with tos pop */
72 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
76 * An entry on the simulated x87 stack.
78 typedef struct st_entry {
79 int reg_idx; /**< the virtual register index of this stack value */
80 ir_node *node; /**< the node that produced this value */
86 typedef struct x87_state {
87 st_entry st[N_ia32_st_REGS]; /**< the register stack */
88 int depth; /**< the current stack depth */
89 x87_simulator *sim; /**< The simulator. */
92 /** An empty state, used for blocks without fp instructions. */
93 static x87_state empty = { { {0, NULL}, }, 0, NULL };
96 * Return values of the instruction simulator functions.
99 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
100 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
101 in the schedule AFTER the current node. */
105 * The type of an instruction simulator function.
107 * @param state the x87 state
108 * @param n the node to be simulated
110 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
112 * NO_NODE_ADDED otherwise
114 typedef int (*sim_func)(x87_state *state, ir_node *n);
117 * A block state: Every block has a x87 state at the beginning and at the end.
119 typedef struct blk_state {
120 x87_state *begin; /**< state at the begin or NULL if not assigned */
121 x87_state *end; /**< state at the end or NULL if not assigned */
124 /** liveness bitset for vfp registers. */
125 typedef unsigned char vfp_liveness;
130 struct x87_simulator {
131 struct obstack obst; /**< An obstack for fast allocating. */
132 pmap *blk_states; /**< Map blocks to states. */
133 be_lv_t *lv; /**< intrablock liveness. */
134 vfp_liveness *live; /**< Liveness information. */
135 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
136 waitq *worklist; /**< Worklist of blocks that must be processed. */
140 * Returns the current stack depth.
142 * @param state the x87 state
144 * @return the x87 stack depth
146 static int x87_get_depth(const x87_state *state)
151 static st_entry *x87_get_entry(x87_state *const state, int const pos)
153 assert(0 <= pos && pos < state->depth);
154 return &state->st[N_ia32_st_REGS - state->depth + pos];
158 * Return the virtual register index at st(pos).
160 * @param state the x87 state
161 * @param pos a stack position
163 * @return the vfp register index that produced the value at st(pos)
165 static int x87_get_st_reg(const x87_state *state, int pos)
167 return x87_get_entry((x87_state*)state, pos)->reg_idx;
172 * Dump the stack for debugging.
174 * @param state the x87 state
176 static void x87_dump_stack(const x87_state *state)
178 for (int i = state->depth; i-- != 0;) {
179 st_entry const *const entry = x87_get_entry((x87_state*)state, i);
180 DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
182 DB((dbg, LEVEL_2, "<-- TOS\n"));
184 #endif /* DEBUG_libfirm */
187 * Set a virtual register to st(pos).
189 * @param state the x87 state
190 * @param reg_idx the vfp register index that should be set
191 * @param node the IR node that produces the value of the vfp register
192 * @param pos the stack position where the new value should be entered
194 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
196 st_entry *const entry = x87_get_entry(state, pos);
197 entry->reg_idx = reg_idx;
200 DB((dbg, LEVEL_2, "After SET_REG: "));
201 DEBUG_ONLY(x87_dump_stack(state);)
205 * Swap st(0) with st(pos).
207 * @param state the x87 state
208 * @param pos the stack position to change the tos with
210 static void x87_fxch(x87_state *state, int pos)
212 st_entry *const a = x87_get_entry(state, pos);
213 st_entry *const b = x87_get_entry(state, 0);
214 st_entry const t = *a;
218 DB((dbg, LEVEL_2, "After FXCH: "));
219 DEBUG_ONLY(x87_dump_stack(state);)
223 * Convert a virtual register to the stack index.
225 * @param state the x87 state
226 * @param reg_idx the register vfp index
228 * @return the stack position where the register is stacked
229 * or -1 if the virtual register was not found
231 static int x87_on_stack(const x87_state *state, int reg_idx)
233 for (int i = 0; i < state->depth; ++i) {
234 if (x87_get_st_reg(state, i) == reg_idx)
241 * Push a virtual Register onto the stack, double pushes are NOT allowed.
243 * @param state the x87 state
244 * @param reg_idx the register vfp index
245 * @param node the node that produces the value of the vfp register
247 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
249 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
250 assert(state->depth < N_ia32_st_REGS && "stack overrun");
253 st_entry *const entry = x87_get_entry(state, 0);
254 entry->reg_idx = reg_idx;
257 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
261 * Pop a virtual Register from the stack.
263 * @param state the x87 state
265 static void x87_pop(x87_state *state)
267 assert(state->depth > 0 && "stack underrun");
271 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
275 * Empty the fpu stack
277 * @param state the x87 state
279 static void x87_emms(x87_state *state)
285 * Returns the block state of a block.
287 * @param sim the x87 simulator handle
288 * @param block the current block
290 * @return the block state
292 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
294 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
297 res = OALLOC(&sim->obst, blk_state);
301 pmap_insert(sim->blk_states, block, res);
310 * @param sim the x87 simulator handle
311 * @param src the x87 state that will be cloned
313 * @return a cloned copy of the src state
315 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
317 x87_state *const res = OALLOC(&sim->obst, x87_state);
323 * Patch a virtual instruction into a x87 one and return
324 * the node representing the result value.
326 * @param n the IR node to patch
327 * @param op the x87 opcode to patch in
329 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
331 ir_mode *mode = get_irn_mode(n);
336 if (mode == mode_T) {
337 /* patch all Proj's */
338 foreach_out_edge(n, edge) {
339 ir_node *proj = get_edge_src_irn(edge);
341 mode = get_irn_mode(proj);
342 if (mode_is_float(mode)) {
344 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
348 } else if (mode_is_float(mode))
349 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
354 * Returns the first Proj of a mode_T node having a given mode.
356 * @param n the mode_T node
357 * @param m the desired mode of the Proj
358 * @return The first Proj of mode @p m found.
360 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
362 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
364 foreach_out_edge(n, edge) {
365 ir_node *proj = get_edge_src_irn(edge);
366 if (get_irn_mode(proj) == m)
370 panic("Proj not found");
374 * Wrap the arch_* function here so we can check for errors.
376 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
378 const arch_register_t *res = arch_get_irn_register(irn);
380 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
384 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
387 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
389 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
393 static inline const arch_register_t *get_st_reg(int index)
395 return &ia32_registers[REG_ST0 + index];
399 * Create a fxch node before another node.
401 * @param state the x87 state
402 * @param n the node after the fxch
403 * @param pos exchange st(pos) with st(0)
405 static void x87_create_fxch(x87_state *state, ir_node *n, int pos)
407 x87_fxch(state, pos);
409 ir_node *const block = get_nodes_block(n);
410 ir_node *const fxch = new_bd_ia32_fxch(NULL, block);
411 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fxch);
412 attr->x87[0] = get_st_reg(pos);
413 attr->x87[2] = get_st_reg(0);
417 sched_add_before(n, fxch);
418 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
421 /* -------------- x87 perm --------------- */
424 * Calculate the necessary permutations to reach dst_state.
426 * These permutations are done with fxch instructions and placed
427 * at the end of the block.
429 * Note that critical edges are removed here, so we need only
430 * a shuffle if the current block has only one successor.
432 * @param block the current block
433 * @param state the current x87 stack state, might be modified
434 * @param dst_state destination state
438 static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
440 int i, n_cycles, k, ri;
441 unsigned cycles[4], all_mask;
442 char cycle_idx[4][8];
444 assert(state->depth == dst_state->depth);
446 /* Some mathematics here:
447 * If we have a cycle of length n that includes the tos,
448 * we need n-1 exchange operations.
449 * We can always add the tos and restore it, so we need
450 * n+1 exchange operations for a cycle not containing the tos.
451 * So, the maximum of needed operations is for a cycle of 7
452 * not including the tos == 8.
453 * This is the same number of ops we would need for using stores,
454 * so exchange is cheaper (we save the loads).
455 * On the other hand, we might need an additional exchange
456 * in the next block to bring one operand on top, so the
457 * number of ops in the first case is identical.
458 * Further, no more than 4 cycles can exists (4 x 2). */
459 all_mask = (1 << (state->depth)) - 1;
461 for (n_cycles = 0; all_mask; ++n_cycles) {
462 int src_idx, dst_idx;
464 /* find the first free slot */
465 for (i = 0; i < state->depth; ++i) {
466 if (all_mask & (1 << i)) {
467 all_mask &= ~(1 << i);
469 /* check if there are differences here */
470 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
476 /* no more cycles found */
481 cycles[n_cycles] = (1 << i);
482 cycle_idx[n_cycles][k++] = i;
483 for (src_idx = i; ; src_idx = dst_idx) {
484 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
486 if ((all_mask & (1 << dst_idx)) == 0)
489 cycle_idx[n_cycles][k++] = dst_idx;
490 cycles[n_cycles] |= (1 << dst_idx);
491 all_mask &= ~(1 << dst_idx);
493 cycle_idx[n_cycles][k] = -1;
497 /* no permutation needed */
501 /* Hmm: permutation needed */
502 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
503 DEBUG_ONLY(x87_dump_stack(state);)
504 DB((dbg, LEVEL_2, " to\n"));
505 DEBUG_ONLY(x87_dump_stack(dst_state);)
509 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
510 for (ri = 0; ri < n_cycles; ++ri) {
511 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
512 for (k = 0; cycle_idx[ri][k] != -1; ++k)
513 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
514 DB((dbg, LEVEL_2, "\n"));
519 * Find the place node must be insert.
520 * We have only one successor block, so the last instruction should
523 ir_node *const before = sched_last(block);
524 assert(is_cfop(before));
526 /* now do the permutations */
527 for (ri = 0; ri < n_cycles; ++ri) {
528 if ((cycles[ri] & 1) == 0) {
529 /* this cycle does not include the tos */
530 x87_create_fxch(state, before, cycle_idx[ri][0]);
532 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
533 x87_create_fxch(state, before, cycle_idx[ri][k]);
535 if ((cycles[ri] & 1) == 0) {
536 /* this cycle does not include the tos */
537 x87_create_fxch(state, before, cycle_idx[ri][0]);
544 * Create a fpush before node n.
546 * @param state the x87 state
547 * @param n the node after the fpush
548 * @param pos push st(pos) on stack
549 * @param val the value to push
551 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int const out_reg_idx, ir_node *const val)
553 x87_push(state, out_reg_idx, val);
555 ir_node *const fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
556 ia32_x87_attr_t *const attr = get_ia32_x87_attr(fpush);
557 attr->x87[0] = get_st_reg(pos);
558 attr->x87[2] = get_st_reg(0);
561 sched_add_before(n, fpush);
563 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
567 * Create a fpop before node n.
569 * @param state the x87 state
570 * @param n the node after the fpop
571 * @param num pop 1 or 2 values
573 * @return the fpop node
575 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
577 ir_node *fpop = NULL;
578 ia32_x87_attr_t *attr;
583 if (ia32_cg_config.use_ffreep)
584 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
586 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
587 attr = get_ia32_x87_attr(fpop);
588 attr->x87[0] = get_st_reg(0);
589 attr->x87[1] = get_st_reg(0);
590 attr->x87[2] = get_st_reg(0);
593 sched_add_before(n, fpop);
594 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
599 /* --------------------------------- liveness ------------------------------------------ */
602 * The liveness transfer function.
603 * Updates a live set over a single step from a given node to its predecessor.
604 * Everything defined at the node is removed from the set, the uses of the node get inserted.
606 * @param irn The node at which liveness should be computed.
607 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
608 * the registers live after irn.
610 * @return The live bitset.
612 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
615 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
617 if (get_irn_mode(irn) == mode_T) {
618 foreach_out_edge(irn, edge) {
619 ir_node *proj = get_edge_src_irn(edge);
621 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
622 const arch_register_t *reg = x87_get_irn_register(proj);
623 live &= ~(1 << arch_register_get_index(reg));
626 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
627 const arch_register_t *reg = x87_get_irn_register(irn);
628 live &= ~(1 << arch_register_get_index(reg));
631 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
632 ir_node *op = get_irn_n(irn, i);
634 if (mode_is_float(get_irn_mode(op)) &&
635 arch_irn_consider_in_reg_alloc(cls, op)) {
636 const arch_register_t *reg = x87_get_irn_register(op);
637 live |= 1 << arch_register_get_index(reg);
644 * Put all live virtual registers at the end of a block into a bitset.
646 * @param sim the simulator handle
647 * @param bl the block
649 * @return The live bitset at the end of this block
651 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
653 vfp_liveness live = 0;
654 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
655 const be_lv_t *lv = sim->lv;
657 be_lv_foreach(lv, block, be_lv_state_end, node) {
658 const arch_register_t *reg;
659 if (!arch_irn_consider_in_reg_alloc(cls, node))
662 reg = x87_get_irn_register(node);
663 live |= 1 << arch_register_get_index(reg);
669 /** get the register mask from an arch_register */
670 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
673 * Return a bitset of argument registers which are live at the end of a node.
675 * @param sim the simulator handle
676 * @param pos the node
677 * @param kill kill mask for the output registers
679 * @return The live bitset.
681 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
683 unsigned idx = get_irn_idx(pos);
685 assert(idx < sim->n_idx);
686 return sim->live[idx] & ~kill;
690 * Calculate the liveness for a whole block and cache it.
692 * @param sim the simulator handle
693 * @param block the block
695 static void update_liveness(x87_simulator *sim, ir_node *block)
697 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
700 /* now iterate through the block backward and cache the results */
701 sched_foreach_reverse(block, irn) {
702 /* stop at the first Phi: this produces the live-in */
706 idx = get_irn_idx(irn);
707 sim->live[idx] = live;
709 live = vfp_liveness_transfer(irn, live);
711 idx = get_irn_idx(block);
712 sim->live[idx] = live;
716 * Returns true if a register is live in a set.
718 * @param reg_idx the vfp register index
719 * @param live a live bitset
721 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
725 * Dump liveness info.
727 * @param live the live bitset
729 static void vfp_dump_live(vfp_liveness live)
733 DB((dbg, LEVEL_2, "Live after: "));
734 for (i = 0; i < 8; ++i) {
735 if (live & (1 << i)) {
736 DB((dbg, LEVEL_2, "vf%d ", i));
739 DB((dbg, LEVEL_2, "\n"));
741 #endif /* DEBUG_libfirm */
743 /* --------------------------------- simulators ---------------------------------------- */
746 * Simulate a virtual binop.
748 * @param state the x87 state
749 * @param n the node that should be simulated (and patched)
750 * @param tmpl the template containing the 4 possible x87 opcodes
752 * @return NO_NODE_ADDED
754 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
756 int op2_idx = 0, op1_idx;
757 int out_idx, do_pop = 0;
758 ia32_x87_attr_t *attr;
760 ir_node *patched_insn;
762 x87_simulator *sim = state->sim;
763 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
764 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
765 const arch_register_t *op1_reg = x87_get_irn_register(op1);
766 const arch_register_t *op2_reg = x87_get_irn_register(op2);
767 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
768 int reg_index_1 = arch_register_get_index(op1_reg);
769 int reg_index_2 = arch_register_get_index(op2_reg);
770 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
774 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
775 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
776 arch_register_get_name(out)));
777 DEBUG_ONLY(vfp_dump_live(live);)
778 DB((dbg, LEVEL_1, "Stack before: "));
779 DEBUG_ONLY(x87_dump_stack(state);)
781 op1_idx = x87_on_stack(state, reg_index_1);
782 assert(op1_idx >= 0);
783 op1_live_after = is_vfp_live(reg_index_1, live);
785 attr = get_ia32_x87_attr(n);
786 permuted = attr->attr.data.ins_permuted;
788 int const out_reg_idx = arch_register_get_index(out);
789 if (reg_index_2 != REG_VFP_VFP_NOREG) {
792 /* second operand is a vfp register */
793 op2_idx = x87_on_stack(state, reg_index_2);
794 assert(op2_idx >= 0);
795 op2_live_after = is_vfp_live(reg_index_2, live);
797 if (op2_live_after) {
798 /* Second operand is live. */
800 if (op1_live_after) {
801 /* Both operands are live: push the first one.
802 This works even for op1 == op2. */
803 x87_create_fpush(state, n, op1_idx, out_reg_idx, op2);
804 /* now do fxxx (tos=tos X op) */
808 dst = tmpl->normal_op;
810 /* Second live, first operand is dead here, bring it to tos. */
812 x87_create_fxch(state, n, op1_idx);
817 /* now do fxxx (tos=tos X op) */
819 dst = tmpl->normal_op;
822 /* Second operand is dead. */
823 if (op1_live_after) {
824 /* First operand is live: bring second to tos. */
826 x87_create_fxch(state, n, op2_idx);
831 /* now do fxxxr (tos = op X tos) */
833 dst = tmpl->reverse_op;
835 /* Both operands are dead here, pop them from the stack. */
838 /* Both are identically and on tos, no pop needed. */
839 /* here fxxx (tos = tos X tos) */
840 dst = tmpl->normal_op;
843 /* now do fxxxp (op = op X tos, pop) */
844 dst = tmpl->normal_pop_op;
848 } else if (op1_idx == 0) {
849 assert(op1_idx != op2_idx);
850 /* now do fxxxrp (op = tos X op, pop) */
851 dst = tmpl->reverse_pop_op;
855 /* Bring the second on top. */
856 x87_create_fxch(state, n, op2_idx);
857 if (op1_idx == op2_idx) {
858 /* Both are identically and on tos now, no pop needed. */
861 /* use fxxx (tos = tos X tos) */
862 dst = tmpl->normal_op;
865 /* op2 is on tos now */
867 /* use fxxxp (op = op X tos, pop) */
868 dst = tmpl->normal_pop_op;
876 /* second operand is an address mode */
877 if (op1_live_after) {
878 /* first operand is live: push it here */
879 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
882 /* first operand is dead: bring it to tos */
884 x87_create_fxch(state, n, op1_idx);
889 /* use fxxx (tos = tos X mem) */
890 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
894 patched_insn = x87_patch_insn(n, dst);
895 x87_set_st(state, out_reg_idx, patched_insn, out_idx);
900 /* patch the operation */
901 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
902 if (reg_index_2 != REG_VFP_VFP_NOREG) {
903 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
905 attr->x87[2] = out = get_st_reg(out_idx);
907 if (reg_index_2 != REG_VFP_VFP_NOREG) {
908 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
909 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
910 arch_register_get_name(out)));
912 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
913 arch_register_get_name(op1_reg),
914 arch_register_get_name(out)));
917 return NO_NODE_ADDED;
921 * Simulate a virtual Unop.
923 * @param state the x87 state
924 * @param n the node that should be simulated (and patched)
925 * @param op the x87 opcode that will replace n's opcode
927 * @return NO_NODE_ADDED
929 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
931 arch_register_t const *const out = x87_get_irn_register(n);
932 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
933 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
934 DEBUG_ONLY(vfp_dump_live(live);)
936 ir_node *const op1 = get_irn_n(n, 0);
937 arch_register_t const *const op1_reg = x87_get_irn_register(op1);
938 int const op1_reg_idx = arch_register_get_index(op1_reg);
939 int const op1_idx = x87_on_stack(state, op1_reg_idx);
940 int const out_reg_idx = arch_register_get_index(out);
941 if (is_vfp_live(op1_reg_idx, live)) {
942 /* push the operand here */
943 x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
945 /* operand is dead, bring it to tos */
947 x87_create_fxch(state, n, op1_idx);
951 x87_set_st(state, out_reg_idx, x87_patch_insn(n, op), 0);
952 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
953 attr->x87[2] = attr->x87[0] = get_st_reg(0);
954 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), attr->x87[2]->name));
956 return NO_NODE_ADDED;
960 * Simulate a virtual Load instruction.
962 * @param state the x87 state
963 * @param n the node that should be simulated (and patched)
964 * @param op the x87 opcode that will replace n's opcode
966 * @return NO_NODE_ADDED
968 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
970 const arch_register_t *out = x87_irn_get_register(n, res_pos);
971 ia32_x87_attr_t *attr;
973 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
974 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
975 assert(out == x87_irn_get_register(n, res_pos));
976 attr = get_ia32_x87_attr(n);
977 attr->x87[2] = out = get_st_reg(0);
978 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
980 return NO_NODE_ADDED;
984 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
986 * @param store The store
987 * @param old_val The former value
988 * @param new_val The new value
990 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
992 foreach_out_edge_safe(old_val, edge) {
993 ir_node *user = get_edge_src_irn(edge);
994 /* if the user is scheduled after the store: rewire */
995 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
996 set_irn_n(user, get_edge_src_pos(edge), new_val);
1002 * Simulate a virtual Store.
1004 * @param state the x87 state
1005 * @param n the node that should be simulated (and patched)
1006 * @param op the x87 store opcode
1007 * @param op_p the x87 store and pop opcode
1009 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1011 ir_node *const val = get_irn_n(n, n_ia32_vfst_val);
1012 arch_register_t const *const op2 = x87_get_irn_register(val);
1013 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1015 int insn = NO_NODE_ADDED;
1016 int const op2_reg_idx = arch_register_get_index(op2);
1017 int const op2_idx = x87_on_stack(state, op2_reg_idx);
1018 unsigned const live = vfp_live_args_after(state->sim, n, 0);
1019 int const live_after_node = is_vfp_live(op2_reg_idx, live);
1020 assert(op2_idx >= 0);
1021 if (live_after_node) {
1022 /* Problem: fst doesn't support 80bit modes (spills), only fstp does
1023 * fist doesn't support 64bit mode, only fistp
1025 * - stack not full: push value and fstp
1026 * - stack full: fstp value and load again
1027 * Note that we cannot test on mode_E, because floats might be 80bit ... */
1028 ir_mode *const mode = get_ia32_ls_mode(n);
1029 if (get_mode_size_bits(mode) > (mode_is_int(mode) ? 32 : 64)) {
1030 if (x87_get_depth(state) < N_ia32_st_REGS) {
1031 /* ok, we have a free register: push + fstp */
1032 x87_create_fpush(state, n, op2_idx, REG_VFP_VFP_NOREG, val);
1034 x87_patch_insn(n, op_p);
1036 /* stack full here: need fstp + load */
1038 x87_patch_insn(n, op_p);
1040 ir_node *const block = get_nodes_block(n);
1041 ir_node *const mem = get_irn_Proj_for_mode(n, mode_M);
1042 ir_node *const vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), mem, mode);
1044 /* copy all attributes */
1045 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1046 if (is_ia32_use_frame(n))
1047 set_ia32_use_frame(vfld);
1048 set_ia32_op_type(vfld, ia32_AddrModeS);
1049 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1050 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1051 set_ia32_ls_mode(vfld, mode);
1053 ir_node *const rproj = new_r_Proj(vfld, mode, pn_ia32_vfld_res);
1054 ir_node *const mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1056 arch_set_irn_register(rproj, op2);
1058 /* reroute all former users of the store memory to the load memory */
1059 edges_reroute_except(mem, mproj, vfld);
1061 sched_add_after(n, vfld);
1063 /* rewire all users, scheduled after the store, to the loaded value */
1064 collect_and_rewire_users(n, val, rproj);
1069 /* we can only store the tos to memory */
1071 x87_create_fxch(state, n, op2_idx);
1073 /* mode size 64 or smaller -> use normal fst */
1074 x87_patch_insn(n, op);
1077 /* we can only store the tos to memory */
1079 x87_create_fxch(state, n, op2_idx);
1082 x87_patch_insn(n, op_p);
1085 ia32_x87_attr_t *const attr = get_ia32_x87_attr(n);
1086 attr->x87[1] = get_st_reg(0);
1087 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(attr->x87[1])));
1092 #define _GEN_BINOP(op, rev) \
1093 static int sim_##op(x87_state *state, ir_node *n) { \
1094 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1095 return sim_binop(state, n, &tmpl); \
1098 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1099 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1101 #define GEN_LOAD(op) \
1102 static int sim_##op(x87_state *state, ir_node *n) { \
1103 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1106 #define GEN_UNOP(op) \
1107 static int sim_##op(x87_state *state, ir_node *n) { \
1108 return sim_unop(state, n, op_ia32_##op); \
1111 #define GEN_STORE(op) \
1112 static int sim_##op(x87_state *state, ir_node *n) { \
1113 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1135 * Simulate a virtual fisttp.
1137 * @param state the x87 state
1138 * @param n the node that should be simulated (and patched)
1140 * @return NO_NODE_ADDED
1142 static int sim_fisttp(x87_state *state, ir_node *n)
1144 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1145 const arch_register_t *op2 = x87_get_irn_register(val);
1146 ia32_x87_attr_t *attr;
1147 int op2_reg_idx, op2_idx;
1149 op2_reg_idx = arch_register_get_index(op2);
1150 op2_idx = x87_on_stack(state, op2_reg_idx);
1151 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1152 assert(op2_idx >= 0);
1154 /* Note: although the value is still live here, it is destroyed because
1155 of the pop. The register allocator is aware of that and introduced a copy
1156 if the value must be alive. */
1158 /* we can only store the tos to memory */
1160 x87_create_fxch(state, n, op2_idx);
1163 x87_patch_insn(n, op_ia32_fisttp);
1165 attr = get_ia32_x87_attr(n);
1166 attr->x87[1] = op2 = get_st_reg(0);
1167 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1169 return NO_NODE_ADDED;
1173 * Simulate a virtual FtstFnstsw.
1175 * @param state the x87 state
1176 * @param n the node that should be simulated (and patched)
1178 * @return NO_NODE_ADDED
1180 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1182 x87_simulator *sim = state->sim;
1183 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1184 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1185 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1186 int reg_index_1 = arch_register_get_index(reg1);
1187 int op1_idx = x87_on_stack(state, reg_index_1);
1188 unsigned live = vfp_live_args_after(sim, n, 0);
1190 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1191 DEBUG_ONLY(vfp_dump_live(live);)
1192 DB((dbg, LEVEL_1, "Stack before: "));
1193 DEBUG_ONLY(x87_dump_stack(state);)
1194 assert(op1_idx >= 0);
1197 /* bring the value to tos */
1198 x87_create_fxch(state, n, op1_idx);
1202 /* patch the operation */
1203 x87_patch_insn(n, op_ia32_FtstFnstsw);
1204 reg1 = get_st_reg(op1_idx);
1205 attr->x87[0] = reg1;
1206 attr->x87[1] = NULL;
1207 attr->x87[2] = NULL;
1209 if (!is_vfp_live(reg_index_1, live))
1210 x87_create_fpop(state, sched_next(n), 1);
1212 return NO_NODE_ADDED;
1218 * @param state the x87 state
1219 * @param n the node that should be simulated (and patched)
1221 * @return NO_NODE_ADDED
1223 static int sim_Fucom(x87_state *state, ir_node *n)
1227 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1229 x87_simulator *sim = state->sim;
1230 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1231 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1232 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1233 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1234 int reg_index_1 = arch_register_get_index(op1);
1235 int reg_index_2 = arch_register_get_index(op2);
1236 unsigned live = vfp_live_args_after(sim, n, 0);
1237 bool permuted = attr->attr.data.ins_permuted;
1241 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1242 arch_register_get_name(op1), arch_register_get_name(op2)));
1243 DEBUG_ONLY(vfp_dump_live(live);)
1244 DB((dbg, LEVEL_1, "Stack before: "));
1245 DEBUG_ONLY(x87_dump_stack(state);)
1247 op1_idx = x87_on_stack(state, reg_index_1);
1248 assert(op1_idx >= 0);
1250 /* BEWARE: check for comp a,a cases, they might happen */
1251 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1252 /* second operand is a vfp register */
1253 op2_idx = x87_on_stack(state, reg_index_2);
1254 assert(op2_idx >= 0);
1256 if (is_vfp_live(reg_index_2, live)) {
1257 /* second operand is live */
1259 if (is_vfp_live(reg_index_1, live)) {
1260 /* both operands are live */
1263 /* res = tos X op */
1264 } else if (op2_idx == 0) {
1265 /* res = op X tos */
1266 permuted = !permuted;
1269 /* bring the first one to tos */
1270 x87_create_fxch(state, n, op1_idx);
1271 if (op1_idx == op2_idx) {
1273 } else if (op2_idx == 0) {
1277 /* res = tos X op */
1280 /* second live, first operand is dead here, bring it to tos.
1281 This means further, op1_idx != op2_idx. */
1282 assert(op1_idx != op2_idx);
1284 x87_create_fxch(state, n, op1_idx);
1289 /* res = tos X op, pop */
1293 /* second operand is dead */
1294 if (is_vfp_live(reg_index_1, live)) {
1295 /* first operand is live: bring second to tos.
1296 This means further, op1_idx != op2_idx. */
1297 assert(op1_idx != op2_idx);
1299 x87_create_fxch(state, n, op2_idx);
1304 /* res = op X tos, pop */
1306 permuted = !permuted;
1309 /* both operands are dead here, check first for identity. */
1310 if (op1_idx == op2_idx) {
1311 /* identically, one pop needed */
1313 x87_create_fxch(state, n, op1_idx);
1317 /* res = tos X op, pop */
1320 /* different, move them to st and st(1) and pop both.
1321 The tricky part is to get one into st(1).*/
1322 else if (op2_idx == 1) {
1323 /* good, second operand is already in the right place, move the first */
1325 /* bring the first on top */
1326 x87_create_fxch(state, n, op1_idx);
1327 assert(op2_idx != 0);
1330 /* res = tos X op, pop, pop */
1332 } else if (op1_idx == 1) {
1333 /* good, first operand is already in the right place, move the second */
1335 /* bring the first on top */
1336 x87_create_fxch(state, n, op2_idx);
1337 assert(op1_idx != 0);
1340 /* res = op X tos, pop, pop */
1341 permuted = !permuted;
1345 /* if one is already the TOS, we need two fxch */
1347 /* first one is TOS, move to st(1) */
1348 x87_create_fxch(state, n, 1);
1349 assert(op2_idx != 1);
1351 x87_create_fxch(state, n, op2_idx);
1353 /* res = op X tos, pop, pop */
1355 permuted = !permuted;
1357 } else if (op2_idx == 0) {
1358 /* second one is TOS, move to st(1) */
1359 x87_create_fxch(state, n, 1);
1360 assert(op1_idx != 1);
1362 x87_create_fxch(state, n, op1_idx);
1364 /* res = tos X op, pop, pop */
1367 /* none of them is either TOS or st(1), 3 fxch needed */
1368 x87_create_fxch(state, n, op2_idx);
1369 assert(op1_idx != 0);
1370 x87_create_fxch(state, n, 1);
1372 x87_create_fxch(state, n, op1_idx);
1374 /* res = tos X op, pop, pop */
1381 /* second operand is an address mode */
1382 if (is_vfp_live(reg_index_1, live)) {
1383 /* first operand is live: bring it to TOS */
1385 x87_create_fxch(state, n, op1_idx);
1389 /* first operand is dead: bring it to tos */
1391 x87_create_fxch(state, n, op1_idx);
1398 /* patch the operation */
1399 if (is_ia32_vFucomFnstsw(n)) {
1403 case 0: dst = op_ia32_FucomFnstsw; break;
1404 case 1: dst = op_ia32_FucompFnstsw; break;
1405 case 2: dst = op_ia32_FucomppFnstsw; break;
1406 default: panic("invalid popcount");
1409 for (i = 0; i < pops; ++i) {
1412 } else if (is_ia32_vFucomi(n)) {
1414 case 0: dst = op_ia32_Fucomi; break;
1415 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1417 dst = op_ia32_Fucompi;
1419 x87_create_fpop(state, sched_next(n), 1);
1421 default: panic("invalid popcount");
1424 panic("invalid operation %+F", n);
1427 x87_patch_insn(n, dst);
1434 op1 = get_st_reg(op1_idx);
1437 op2 = get_st_reg(op2_idx);
1440 attr->x87[2] = NULL;
1441 attr->attr.data.ins_permuted = permuted;
1444 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1445 arch_register_get_name(op1), arch_register_get_name(op2)));
1447 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1448 arch_register_get_name(op1)));
1451 return NO_NODE_ADDED;
1457 * @param state the x87 state
1458 * @param n the node that should be simulated (and patched)
1460 * @return NO_NODE_ADDED
1462 static int sim_Keep(x87_state *state, ir_node *node)
1465 const arch_register_t *op_reg;
1471 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1473 arity = get_irn_arity(node);
1474 for (i = 0; i < arity; ++i) {
1475 op = get_irn_n(node, i);
1476 op_reg = arch_get_irn_register(op);
1477 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1480 reg_id = arch_register_get_index(op_reg);
1481 live = vfp_live_args_after(state->sim, node, 0);
1483 op_stack_idx = x87_on_stack(state, reg_id);
1484 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1485 x87_create_fpop(state, sched_next(node), 1);
1488 DB((dbg, LEVEL_1, "Stack after: "));
1489 DEBUG_ONLY(x87_dump_stack(state);)
1491 return NO_NODE_ADDED;
1495 * Keep the given node alive by adding a be_Keep.
1497 * @param node the node to kept alive
1499 static void keep_float_node_alive(ir_node *node)
1501 ir_node *block = get_nodes_block(node);
1502 ir_node *keep = be_new_Keep(block, 1, &node);
1503 sched_add_after(node, keep);
1507 * Create a copy of a node. Recreate the node if it's a constant.
1509 * @param state the x87 state
1510 * @param n the node to be copied
1512 * @return the copy of n
1514 static ir_node *create_Copy(x87_state *state, ir_node *n)
1516 dbg_info *n_dbg = get_irn_dbg_info(n);
1517 ir_mode *mode = get_irn_mode(n);
1518 ir_node *block = get_nodes_block(n);
1519 ir_node *pred = get_irn_n(n, 0);
1520 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1522 const arch_register_t *out;
1523 const arch_register_t *op1;
1524 ia32_x87_attr_t *attr;
1526 /* Do not copy constants, recreate them. */
1527 switch (get_ia32_irn_opcode(pred)) {
1529 cnstr = new_bd_ia32_fldz;
1532 cnstr = new_bd_ia32_fld1;
1534 case iro_ia32_fldpi:
1535 cnstr = new_bd_ia32_fldpi;
1537 case iro_ia32_fldl2e:
1538 cnstr = new_bd_ia32_fldl2e;
1540 case iro_ia32_fldl2t:
1541 cnstr = new_bd_ia32_fldl2t;
1543 case iro_ia32_fldlg2:
1544 cnstr = new_bd_ia32_fldlg2;
1546 case iro_ia32_fldln2:
1547 cnstr = new_bd_ia32_fldln2;
1553 out = x87_get_irn_register(n);
1554 op1 = x87_get_irn_register(pred);
1556 if (cnstr != NULL) {
1557 /* copy a constant */
1558 res = (*cnstr)(n_dbg, block, mode);
1560 x87_push(state, arch_register_get_index(out), res);
1562 attr = get_ia32_x87_attr(res);
1563 attr->x87[2] = get_st_reg(0);
1565 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1567 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1569 x87_push(state, arch_register_get_index(out), res);
1571 attr = get_ia32_x87_attr(res);
1572 attr->x87[0] = get_st_reg(op1_idx);
1573 attr->x87[2] = get_st_reg(0);
1575 arch_set_irn_register(res, out);
1581 * Simulate a be_Copy.
1583 * @param state the x87 state
1584 * @param n the node that should be simulated (and patched)
1586 * @return NO_NODE_ADDED
1588 static int sim_Copy(x87_state *state, ir_node *n)
1590 arch_register_class_t const *const cls = arch_get_irn_reg_class(n);
1591 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1592 return NO_NODE_ADDED;
1594 ir_node *const pred = be_get_Copy_op(n);
1595 arch_register_t const *const op1 = x87_get_irn_register(pred);
1596 arch_register_t const *const out = x87_get_irn_register(n);
1597 unsigned const live = vfp_live_args_after(state->sim, n, REGMASK(out));
1599 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1600 arch_register_get_name(op1), arch_register_get_name(out)));
1601 DEBUG_ONLY(vfp_dump_live(live);)
1603 if (is_vfp_live(arch_register_get_index(op1), live)) {
1604 /* Operand is still live, a real copy. We need here an fpush that can
1605 hold a a register, so use the fpushCopy or recreate constants */
1606 ir_node *const node = create_Copy(state, n);
1608 /* We have to make sure the old value doesn't go dead (which can happen
1609 * when we recreate constants). As the simulator expected that value in
1610 * the pred blocks. This is unfortunate as removing it would save us 1
1611 * instruction, but we would have to rerun all the simulation to get
1614 ir_node *const next = sched_next(n);
1617 sched_add_before(next, node);
1619 if (get_irn_n_edges(pred) == 0) {
1620 keep_float_node_alive(pred);
1623 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1625 /* Just a virtual copy. */
1626 int const op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1627 x87_set_st(state, arch_register_get_index(out), n, op1_idx);
1629 return NO_NODE_ADDED;
1633 * Returns the vf0 result Proj of a Call.
1635 * @para call the Call node
1637 static ir_node *get_call_result_proj(ir_node *call)
1639 /* search the result proj */
1640 foreach_out_edge(call, edge) {
1641 ir_node *proj = get_edge_src_irn(edge);
1642 long pn = get_Proj_proj(proj);
1644 if (pn == pn_ia32_Call_vf0)
1648 panic("result Proj missing");
1651 static int sim_Asm(x87_state *const state, ir_node *const n)
1655 for (size_t i = get_irn_arity(n); i-- != 0;) {
1656 arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
1657 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1658 panic("cannot handle %+F with x87 constraints", n);
1661 for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
1662 arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
1663 if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
1664 panic("cannot handle %+F with x87 constraints", n);
1667 return NO_NODE_ADDED;
1671 * Simulate a ia32_Call.
1673 * @param state the x87 state
1674 * @param n the node that should be simulated (and patched)
1676 * @return NO_NODE_ADDED
1678 static int sim_Call(x87_state *state, ir_node *n)
1680 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1682 /* at the begin of a call the x87 state should be empty */
1683 assert(state->depth == 0 && "stack not empty before call");
1685 ir_type *const call_tp = get_ia32_call_attr_const(n)->call_tp;
1686 if (get_method_n_ress(call_tp) != 0) {
1687 /* If the called function returns a float, it is returned in st(0).
1688 * This even happens if the return value is NOT used.
1689 * Moreover, only one return result is supported. */
1690 ir_type *const res_type = get_method_res_type(call_tp, 0);
1691 ir_mode *const mode = get_type_mode(res_type);
1692 if (mode && mode_is_float(mode)) {
1693 ir_node *const resproj = get_call_result_proj(n);
1694 arch_register_t const *const reg = x87_get_irn_register(resproj);
1695 x87_push(state, arch_register_get_index(reg), resproj);
1698 DB((dbg, LEVEL_1, "Stack after: "));
1699 DEBUG_ONLY(x87_dump_stack(state);)
1701 return NO_NODE_ADDED;
1705 * Simulate a be_Return.
1707 * @param state the x87 state
1708 * @param n the node that should be simulated (and patched)
1710 * @return NO_NODE_ADDED
1712 static int sim_Return(x87_state *state, ir_node *n)
1714 #ifdef DEBUG_libfirm
1715 /* only floating point return values must reside on stack */
1716 int n_float_res = 0;
1717 int const n_res = be_Return_get_n_rets(n);
1718 for (int i = 0; i < n_res; ++i) {
1719 ir_node *const res = get_irn_n(n, n_be_Return_val + i);
1720 if (mode_is_float(get_irn_mode(res)))
1723 assert(x87_get_depth(state) == n_float_res);
1726 /* pop them virtually */
1728 return NO_NODE_ADDED;
1732 * Simulate a be_Perm.
1734 * @param state the x87 state
1735 * @param irn the node that should be simulated (and patched)
1737 * @return NO_NODE_ADDED
1739 static int sim_Perm(x87_state *state, ir_node *irn)
1742 ir_node *pred = get_irn_n(irn, 0);
1745 /* handle only floating point Perms */
1746 if (! mode_is_float(get_irn_mode(pred)))
1747 return NO_NODE_ADDED;
1749 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1751 /* Perm is a pure virtual instruction on x87.
1752 All inputs must be on the FPU stack and are pairwise
1753 different from each other.
1754 So, all we need to do is to permutate the stack state. */
1755 n = get_irn_arity(irn);
1756 NEW_ARR_A(int, stack_pos, n);
1758 /* collect old stack positions */
1759 for (i = 0; i < n; ++i) {
1760 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1761 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1763 assert(idx >= 0 && "Perm argument not on x87 stack");
1767 /* now do the permutation */
1768 foreach_out_edge(irn, edge) {
1769 ir_node *proj = get_edge_src_irn(edge);
1770 const arch_register_t *out = x87_get_irn_register(proj);
1771 long num = get_Proj_proj(proj);
1773 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1774 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1776 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1778 return NO_NODE_ADDED;
1782 * Kill any dead registers at block start by popping them from the stack.
1784 * @param sim the simulator handle
1785 * @param block the current block
1786 * @param state the x87 state at the begin of the block
1788 static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
1790 ir_node *first_insn = sched_first(block);
1791 ir_node *keep = NULL;
1792 unsigned live = vfp_live_args_after(sim, block, 0);
1794 int i, depth, num_pop;
1797 depth = x87_get_depth(state);
1798 for (i = depth - 1; i >= 0; --i) {
1799 int reg = x87_get_st_reg(state, i);
1801 if (! is_vfp_live(reg, live))
1802 kill_mask |= (1 << i);
1806 DB((dbg, LEVEL_1, "Killing deads:\n"));
1807 DEBUG_ONLY(vfp_dump_live(live);)
1808 DEBUG_ONLY(x87_dump_stack(state);)
1810 if (kill_mask != 0 && live == 0) {
1811 /* special case: kill all registers */
1812 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
1813 if (ia32_cg_config.use_femms) {
1814 /* use FEMMS on AMD processors to clear all */
1815 keep = new_bd_ia32_femms(NULL, block);
1817 /* use EMMS to clear all */
1818 keep = new_bd_ia32_emms(NULL, block);
1820 sched_add_before(first_insn, keep);
1826 /* now kill registers */
1828 /* we can only kill from TOS, so bring them up */
1829 if (! (kill_mask & 1)) {
1830 /* search from behind, because we can to a double-pop */
1831 for (i = depth - 1; i >= 0; --i) {
1832 if (kill_mask & (1 << i)) {
1833 kill_mask &= ~(1 << i);
1840 x87_set_st(state, -1, keep, i);
1841 x87_create_fxch(state, first_insn, i);
1844 if ((kill_mask & 3) == 3) {
1845 /* we can do a double-pop */
1849 /* only a single pop */
1854 kill_mask >>= num_pop;
1855 keep = x87_create_fpop(state, first_insn, num_pop);
1862 * Run a simulation and fix all virtual instructions for a block.
1864 * @param sim the simulator handle
1865 * @param block the current block
1867 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
1870 blk_state *bl_state = x87_get_bl_state(sim, block);
1871 x87_state *state = bl_state->begin;
1872 ir_node *start_block;
1874 assert(state != NULL);
1875 /* already processed? */
1876 if (bl_state->end != NULL)
1879 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
1880 DB((dbg, LEVEL_2, "State at Block begin:\n "));
1881 DEBUG_ONLY(x87_dump_stack(state);)
1883 /* create a new state, will be changed */
1884 state = x87_clone_state(sim, state);
1885 /* at block begin, kill all dead registers */
1886 x87_kill_deads(sim, block, state);
1888 /* beware, n might change */
1889 for (n = sched_first(block); !sched_is_end(n); n = next) {
1892 ir_op *op = get_irn_op(n);
1895 * get the next node to be simulated here.
1896 * n might be completely removed from the schedule-
1898 next = sched_next(n);
1899 if (op->ops.generic != NULL) {
1900 func = (sim_func)op->ops.generic;
1903 node_inserted = (*func)(state, n);
1906 * sim_func might have added an additional node after n,
1907 * so update next node
1908 * beware: n must not be changed by sim_func
1909 * (i.e. removed from schedule) in this case
1911 if (node_inserted != NO_NODE_ADDED)
1912 next = sched_next(n);
1916 start_block = get_irg_start_block(get_irn_irg(block));
1918 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
1920 /* check if the state must be shuffled */
1921 foreach_block_succ(block, edge) {
1922 ir_node *succ = get_edge_src_irn(edge);
1923 blk_state *succ_state;
1925 if (succ == start_block)
1928 succ_state = x87_get_bl_state(sim, succ);
1930 if (succ_state->begin == NULL) {
1931 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
1932 DEBUG_ONLY(x87_dump_stack(state);)
1933 succ_state->begin = state;
1935 waitq_put(sim->worklist, succ);
1937 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
1938 /* There is already a begin state for the successor, bad.
1939 Do the necessary permutations.
1940 Note that critical edges are removed, so this is always possible:
1941 If the successor has more than one possible input, then it must
1944 x87_shuffle(block, state, succ_state->begin);
1947 bl_state->end = state;
1951 * Register a simulator function.
1953 * @param op the opcode to simulate
1954 * @param func the simulator function for the opcode
1956 static void register_sim(ir_op *op, sim_func func)
1958 assert(op->ops.generic == NULL);
1959 op->ops.generic = (op_func) func;
1963 * Create a new x87 simulator.
1965 * @param sim a simulator handle, will be initialized
1966 * @param irg the current graph
1968 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
1970 obstack_init(&sim->obst);
1971 sim->blk_states = pmap_create();
1972 sim->n_idx = get_irg_last_idx(irg);
1973 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
1975 DB((dbg, LEVEL_1, "--------------------------------\n"
1976 "x87 Simulator started for %+F\n", irg));
1978 /* set the generic function pointer of instruction we must simulate */
1979 ir_clear_opcodes_generic_func();
1981 register_sim(op_ia32_Asm, sim_Asm);
1982 register_sim(op_ia32_Call, sim_Call);
1983 register_sim(op_ia32_vfld, sim_fld);
1984 register_sim(op_ia32_vfild, sim_fild);
1985 register_sim(op_ia32_vfld1, sim_fld1);
1986 register_sim(op_ia32_vfldz, sim_fldz);
1987 register_sim(op_ia32_vfadd, sim_fadd);
1988 register_sim(op_ia32_vfsub, sim_fsub);
1989 register_sim(op_ia32_vfmul, sim_fmul);
1990 register_sim(op_ia32_vfdiv, sim_fdiv);
1991 register_sim(op_ia32_vfprem, sim_fprem);
1992 register_sim(op_ia32_vfabs, sim_fabs);
1993 register_sim(op_ia32_vfchs, sim_fchs);
1994 register_sim(op_ia32_vfist, sim_fist);
1995 register_sim(op_ia32_vfisttp, sim_fisttp);
1996 register_sim(op_ia32_vfst, sim_fst);
1997 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
1998 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
1999 register_sim(op_ia32_vFucomi, sim_Fucom);
2000 register_sim(op_be_Copy, sim_Copy);
2001 register_sim(op_be_Return, sim_Return);
2002 register_sim(op_be_Perm, sim_Perm);
2003 register_sim(op_be_Keep, sim_Keep);
2007 * Destroy a x87 simulator.
2009 * @param sim the simulator handle
2011 static void x87_destroy_simulator(x87_simulator *sim)
2013 pmap_destroy(sim->blk_states);
2014 obstack_free(&sim->obst, NULL);
2015 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2019 * Pre-block walker: calculate the liveness information for the block
2020 * and store it into the sim->live cache.
2022 static void update_liveness_walker(ir_node *block, void *data)
2024 x87_simulator *sim = (x87_simulator*)data;
2025 update_liveness(sim, block);
2029 * Run a simulation and fix all virtual instructions for a graph.
2030 * Replaces all virtual floating point instructions and registers
2033 void ia32_x87_simulate_graph(ir_graph *irg)
2035 /* TODO improve code quality (less executed fxch) by using execfreqs */
2037 ir_node *block, *start_block;
2038 blk_state *bl_state;
2041 /* create the simulator */
2042 x87_init_simulator(&sim, irg);
2044 start_block = get_irg_start_block(irg);
2045 bl_state = x87_get_bl_state(&sim, start_block);
2047 /* start with the empty state */
2049 bl_state->begin = ∅
2051 sim.worklist = new_waitq();
2052 waitq_put(sim.worklist, start_block);
2054 be_assure_live_sets(irg);
2055 sim.lv = be_get_irg_liveness(irg);
2057 /* Calculate the liveness for all nodes. We must precalculate this info,
2058 * because the simulator adds new nodes (possible before Phi nodes) which
2059 * would let a lazy calculation fail.
2060 * On the other hand we reduce the computation amount due to
2061 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2063 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2067 block = (ir_node*)waitq_get(sim.worklist);
2068 x87_simulate_block(&sim, block);
2069 } while (! waitq_empty(sim.worklist));
2072 del_waitq(sim.worklist);
2073 x87_destroy_simulator(&sim);
2076 /* Initializes the x87 simulator. */
2077 void ia32_init_x87(void)
2079 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");