2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
36 #include "iredges_t.h"
47 #include "../belive_t.h"
48 #include "../besched_t.h"
49 #include "../benode_t.h"
50 #include "ia32_new_nodes.h"
51 #include "gen_ia32_new_nodes.h"
52 #include "gen_ia32_regalloc_if.h"
57 /* first and second binop index */
64 /* the store val index */
65 #define STORE_VAL_IDX 2
67 #define MASK_TOS(x) ((x) & (N_x87_REGS - 1))
69 /** the debug handle */
70 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
72 /* Forward declaration. */
73 typedef struct _x87_simulator x87_simulator;
76 * An exchange template.
77 * Note that our virtual functions have the same inputs
78 * and attributes as the real ones, so we can simple exchange
80 * Further, x87 supports inverse instructions, so we can handle them.
82 typedef struct _exchange_tmpl {
83 ir_op *normal_op; /**< the normal one */
84 ir_op *reverse_op; /**< the reverse one if exists */
85 ir_op *normal_pop_op; /**< the normal one with tos pop */
86 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
90 * An entry on the simulated x87 stack.
92 typedef struct _st_entry {
93 int reg_idx; /**< the virtual register index of this stack value */
94 ir_node *node; /**< the node that produced this value */
100 typedef struct _x87_state {
101 st_entry st[N_x87_REGS]; /**< the register stack */
102 int depth; /**< the current stack depth */
103 int tos; /**< position of the tos */
104 x87_simulator *sim; /**< The simulator. */
107 /** An empty state, used for blocks without fp instructions. */
108 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
109 static x87_state *empty = (x87_state *)&_empty;
112 NO_NODE_ADDED = 0, /**< No node was added. */
113 NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */
117 * The type of an instruction simulator function.
119 * @param state the x87 state
120 * @param n the node to be simulated
122 * @return NODE_ADDED if a node was added AFTER n in schedule,
125 typedef int (*sim_func)(x87_state *state, ir_node *n);
128 * A block state: Every block has a x87 state at the beginning and at the end.
130 typedef struct _blk_state {
131 x87_state *begin; /**< state at the begin or NULL if not assigned */
132 x87_state *end; /**< state at the end or NULL if not assigned */
135 #define PTR_TO_BLKSTATE(p) ((blk_state *)(p))
137 /** liveness bitset for vfp registers. */
138 typedef unsigned char vfp_liveness;
143 struct _x87_simulator {
144 struct obstack obst; /**< An obstack for fast allocating. */
145 pmap *blk_states; /**< Map blocks to states. */
146 const arch_env_t *arch_env; /**< The architecture environment. */
147 be_lv_t *lv; /**< intrablock liveness. */
148 vfp_liveness *live; /**< Liveness information. */
149 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
150 waitq *worklist; /**< Worklist of blocks that must be processed. */
154 * Returns the current stack depth.
156 * @param state the x87 state
158 * @return the x87 stack depth
160 static int x87_get_depth(const x87_state *state) {
162 } /* x87_get_depth */
165 * Return the virtual register index at st(pos).
167 * @param state the x87 state
168 * @param pos a stack position
170 * @return the vfp register index that produced the value at st(pos)
172 static int x87_get_st_reg(const x87_state *state, int pos) {
173 assert(pos < state->depth);
174 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
175 } /* x87_get_st_reg */
178 * Return the node at st(pos).
180 * @param state the x87 state
181 * @param pos a stack position
183 * @return the IR node that produced the value at st(pos)
185 static ir_node *x87_get_st_node(const x87_state *state, int pos) {
186 assert(pos < state->depth);
187 return state->st[MASK_TOS(state->tos + pos)].node;
188 } /* x87_get_st_node */
192 * Dump the stack for debugging.
194 * @param state the x87 state
196 static void x87_dump_stack(const x87_state *state) {
199 for (i = state->depth - 1; i >= 0; --i) {
200 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
201 x87_get_st_node(state, i)));
203 DB((dbg, LEVEL_2, "<-- TOS\n"));
204 } /* x87_dump_stack */
205 #endif /* DEBUG_libfirm */
208 * Set a virtual register to st(pos).
210 * @param state the x87 state
211 * @param reg_idx the vfp register index that should be set
212 * @param node the IR node that produces the value of the vfp register
213 * @param pos the stack position where the new value should be entered
215 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
216 assert(0 < state->depth);
217 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
218 state->st[MASK_TOS(state->tos + pos)].node = node;
220 DB((dbg, LEVEL_2, "After SET_REG: "));
221 DEBUG_ONLY(x87_dump_stack(state));
225 * Set the tos virtual register.
227 * @param state the x87 state
228 * @param reg_idx the vfp register index that should be set
229 * @param node the IR node that produces the value of the vfp register
231 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
232 x87_set_st(state, reg_idx, node, 0);
236 * Swap st(0) with st(pos).
238 * @param state the x87 state
239 * @param pos the stack position to change the tos with
241 static void x87_fxch(x87_state *state, int pos) {
243 assert(pos < state->depth);
245 entry = state->st[MASK_TOS(state->tos + pos)];
246 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
247 state->st[MASK_TOS(state->tos)] = entry;
249 DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state));
253 * Convert a virtual register to the stack index.
255 * @param state the x87 state
256 * @param reg_idx the register vfp index
258 * @return the stack position where the register is stacked
259 * or -1 if the virtual register was not found
261 static int x87_on_stack(const x87_state *state, int reg_idx) {
262 int i, tos = state->tos;
264 for (i = 0; i < state->depth; ++i)
265 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
271 * Push a virtual Register onto the stack, double pushed allowed.
273 * @param state the x87 state
274 * @param reg_idx the register vfp index
275 * @param node the node that produces the value of the vfp register
277 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
278 assert(state->depth < N_x87_REGS && "stack overrun");
281 state->tos = MASK_TOS(state->tos - 1);
282 state->st[state->tos].reg_idx = reg_idx;
283 state->st[state->tos].node = node;
285 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state));
289 * Push a virtual Register onto the stack, double pushes are NOT allowed.
291 * @param state the x87 state
292 * @param reg_idx the register vfp index
293 * @param node the node that produces the value of the vfp register
294 * @param dbl_push if != 0 double pushes are allowed
296 static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
297 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
299 x87_push_dbl(state, reg_idx, node);
303 * Pop a virtual Register from the stack.
305 * @param state the x87 state
307 static void x87_pop(x87_state *state) {
308 assert(state->depth > 0 && "stack underrun");
311 state->tos = MASK_TOS(state->tos + 1);
313 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state));
317 * Returns the block state of a block.
319 * @param sim the x87 simulator handle
320 * @param block the current block
322 * @return the block state
324 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
325 pmap_entry *entry = pmap_find(sim->blk_states, block);
328 blk_state *bl_state = obstack_alloc(&sim->obst, sizeof(*bl_state));
329 bl_state->begin = NULL;
330 bl_state->end = NULL;
332 pmap_insert(sim->blk_states, block, bl_state);
336 return PTR_TO_BLKSTATE(entry->value);
337 } /* x87_get_bl_state */
340 * Creates a new x87 state.
342 * @param sim the x87 simulator handle
344 * @return a new x87 state
346 static x87_state *x87_alloc_state(x87_simulator *sim) {
347 x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
351 } /* x87_alloc_state */
356 * @param sim the x87 simulator handle
357 * @param src the x87 state that will be cloned
359 * @return a cloned copy of the src state
361 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
362 x87_state *res = x87_alloc_state(sim);
364 memcpy(res, src, sizeof(*res));
366 } /* x87_clone_state */
369 * Patch a virtual instruction into a x87 one and return
370 * the node representing the result value.
372 * @param n the IR node to patch
373 * @param op the x87 opcode to patch in
375 static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
376 ir_mode *mode = get_irn_mode(n);
381 if (mode == mode_T) {
382 /* patch all Proj's */
383 const ir_edge_t *edge;
385 foreach_out_edge(n, edge) {
386 ir_node *proj = get_edge_src_irn(edge);
388 mode = get_irn_mode(proj);
389 if (mode_is_float(mode)) {
391 set_irn_mode(proj, mode_E);
395 } else if (mode_is_float(mode))
396 set_irn_mode(n, mode_E);
398 } /* x87_patch_insn */
401 * Returns the first Proj of a mode_T node having a given mode.
403 * @param n the mode_T node
404 * @param m the desired mode of the Proj
405 * @return The first Proj of mode @p m found or NULL.
407 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
408 const ir_edge_t *edge;
410 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
412 foreach_out_edge(n, edge) {
413 ir_node *proj = get_edge_src_irn(edge);
414 if (get_irn_mode(proj) == m)
419 } /* get_irn_Proj_for_mode */
422 * Wrap the arch_* function here so we can check for errors.
424 static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
425 const arch_register_t *res;
427 res = arch_get_irn_register(sim->arch_env, irn);
428 assert(res->reg_class->regs == ia32_vfp_regs);
430 } /* x87_get_irn_register */
432 /* -------------- x87 perm --------------- */
435 * Creates a fxch for shuffle.
437 * @param state the x87 state
438 * @param pos parameter for fxch
439 * @param block the block were fxch is inserted
441 * Creates a new fxch node and reroute the user of the old node
444 * @return the fxch node
446 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
448 ia32_x87_attr_t *attr;
450 fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E);
451 attr = get_ia32_x87_attr(fxch);
452 attr->x87[0] = &ia32_st_regs[pos];
453 attr->x87[2] = &ia32_st_regs[0];
457 x87_fxch(state, pos);
459 } /* x87_fxch_shuffle */
462 * Calculate the necessary permutations to reach dst_state.
464 * These permutations are done with fxch instructions and placed
465 * at the end of the block.
467 * Note that critical edges are removed here, so we need only
468 * a shuffle if the current block has only one successor.
470 * @param sim the simulator handle
471 * @param block the current block
472 * @param state the current x87 stack state, might be modified
473 * @param dst_block the destination block
474 * @param dst_state destination state
478 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
479 x87_state *state, ir_node *dst_block,
480 const x87_state *dst_state)
482 int i, n_cycles, k, ri;
483 unsigned cycles[4], all_mask;
484 char cycle_idx[4][8];
485 ir_node *fxch, *before, *after;
489 assert(state->depth == dst_state->depth);
491 /* Some mathematics here:
492 If we have a cycle of length n that includes the tos,
493 we need n-1 exchange operations.
494 We can always add the tos and restore it, so we need
495 n+1 exchange operations for a cycle not containing the tos.
496 So, the maximum of needed operations is for a cycle of 7
497 not including the tos == 8.
498 This is the same number of ops we would need for using stores,
499 so exchange is cheaper (we save the loads).
500 On the other hand, we might need an additional exchange
501 in the next block to bring one operand on top, so the
502 number of ops in the first case is identical.
503 Further, no more than 4 cycles can exists (4 x 2).
505 all_mask = (1 << (state->depth)) - 1;
507 for (n_cycles = 0; all_mask; ++n_cycles) {
508 int src_idx, dst_idx;
510 /* find the first free slot */
511 for (i = 0; i < state->depth; ++i) {
512 if (all_mask & (1 << i)) {
513 all_mask &= ~(1 << i);
515 /* check if there are differences here */
516 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
522 /* no more cycles found */
527 cycles[n_cycles] = (1 << i);
528 cycle_idx[n_cycles][k++] = i;
529 for (src_idx = i; ; src_idx = dst_idx) {
530 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
532 if ((all_mask & (1 << dst_idx)) == 0)
535 cycle_idx[n_cycles][k++] = dst_idx;
536 cycles[n_cycles] |= (1 << dst_idx);
537 all_mask &= ~(1 << dst_idx);
539 cycle_idx[n_cycles][k] = -1;
543 /* no permutation needed */
547 /* Hmm: permutation needed */
548 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
549 DEBUG_ONLY(x87_dump_stack(state));
550 DB((dbg, LEVEL_2, " to\n"));
551 DEBUG_ONLY(x87_dump_stack(dst_state));
555 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
556 for (ri = 0; ri < n_cycles; ++ri) {
557 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
558 for (k = 0; cycle_idx[ri][k] != -1; ++k)
559 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
560 DB((dbg, LEVEL_2, "\n"));
567 * Find the place node must be insert.
568 * We have only one successor block, so the last instruction should
571 before = sched_last(block);
572 assert(is_cfop(before));
574 /* now do the permutations */
575 for (ri = 0; ri < n_cycles; ++ri) {
576 if ((cycles[ri] & 1) == 0) {
577 /* this cycle does not include the tos */
578 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
580 sched_add_after(after, fxch);
582 sched_add_before(before, fxch);
585 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
586 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
588 sched_add_after(after, fxch);
590 sched_add_before(before, fxch);
593 if ((cycles[ri] & 1) == 0) {
594 /* this cycle does not include the tos */
595 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
596 sched_add_after(after, fxch);
603 * Create a fxch node before another node.
605 * @param state the x87 state
606 * @param n the node after the fxch
607 * @param pos exchange st(pos) with st(0)
611 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
614 ia32_x87_attr_t *attr;
615 ir_graph *irg = get_irn_irg(n);
616 ir_node *block = get_nodes_block(n);
618 x87_fxch(state, pos);
620 fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E);
621 attr = get_ia32_x87_attr(fxch);
622 attr->x87[0] = &ia32_st_regs[pos];
623 attr->x87[2] = &ia32_st_regs[0];
627 sched_add_before(n, fxch);
628 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
630 } /* x87_create_fxch */
633 * Create a fpush before node n.
635 * @param state the x87 state
636 * @param n the node after the fpush
637 * @param pos push st(pos) on stack
638 * @param op_idx replace input op_idx of n with the fpush result
640 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
641 ir_node *fpush, *pred = get_irn_n(n, op_idx);
642 ia32_x87_attr_t *attr;
643 const arch_register_t *out = x87_get_irn_register(state->sim, pred);
645 x87_push_dbl(state, arch_register_get_index(out), pred);
647 fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
648 attr = get_ia32_x87_attr(fpush);
649 attr->x87[0] = &ia32_st_regs[pos];
650 attr->x87[2] = &ia32_st_regs[0];
653 sched_add_before(n, fpush);
655 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
656 } /* x87_create_fpush */
659 * Create a fpop before node n.
661 * @param state the x87 state
662 * @param n the node after the fpop
663 * @param num pop 1 or 2 values
665 * @return the fpop node
667 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
670 ia32_x87_attr_t *attr;
674 fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
675 attr = get_ia32_x87_attr(fpop);
676 attr->x87[0] = &ia32_st_regs[0];
677 attr->x87[1] = &ia32_st_regs[0];
678 attr->x87[2] = &ia32_st_regs[0];
681 sched_add_before(n, fpop);
682 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
687 } /* x87_create_fpop */
690 * Creates an fldz before node n
692 * @param state the x87 state
693 * @param n the node after the fldz
695 * @return the fldz node
697 static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
698 ir_graph *irg = get_irn_irg(n);
699 ir_node *block = get_nodes_block(n);
702 fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
704 sched_add_before(n, fldz);
705 DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
708 x87_push(state, regidx, fldz);
713 /* --------------------------------- liveness ------------------------------------------ */
716 * The liveness transfer function.
717 * Updates a live set over a single step from a given node to its predecessor.
718 * Everything defined at the node is removed from the set, the uses of the node get inserted.
720 * @param sim The simulator handle.
721 * @param irn The node at which liveness should be computed.
722 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
723 * the registers live after irn.
725 * @return The live bitset.
727 static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live)
730 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
731 const arch_env_t *arch_env = sim->arch_env;
733 #ifndef SCHEDULE_PROJS
734 if (get_irn_mode(irn) == mode_T) {
735 const ir_edge_t *edge;
737 foreach_out_edge(irn, edge) {
738 ir_node *proj = get_edge_src_irn(edge);
740 if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
741 const arch_register_t *reg = x87_get_irn_register(sim, proj);
742 live &= ~(1 << arch_register_get_index(reg));
748 if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
749 const arch_register_t *reg = x87_get_irn_register(sim, irn);
750 live &= ~(1 << arch_register_get_index(reg));
753 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
754 ir_node *op = get_irn_n(irn, i);
756 if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
757 const arch_register_t *reg = x87_get_irn_register(sim, op);
758 live |= 1 << arch_register_get_index(reg);
762 } /* vfp_liveness_transfer */
765 * Put all live virtual registers at the end of a block into a bitset.
767 * @param sim the simulator handle
768 * @param lv the liveness information
769 * @param bl the block
771 * @return The live bitset at the end of this block
773 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
776 vfp_liveness live = 0;
777 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
778 const arch_env_t *arch_env = sim->arch_env;
779 const be_lv_t *lv = sim->lv;
781 be_lv_foreach(lv, block, be_lv_state_end, i) {
782 const arch_register_t *reg;
783 const ir_node *node = be_lv_get_irn(lv, block, i);
784 if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node))
787 reg = x87_get_irn_register(sim, node);
788 live |= 1 << arch_register_get_index(reg);
792 } /* vfp_liveness_end_of_block */
794 /** get the register mask from an arch_register */
795 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
798 * Return a bitset of argument registers which are live at the end of a node.
800 * @param sim the simulator handle
801 * @param pos the node
802 * @param kill kill mask for the output registers
804 * @return The live bitset.
806 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
808 unsigned idx = get_irn_idx(pos);
810 assert(idx < sim->n_idx);
811 return sim->live[idx] & ~kill;
812 } /* vfp_live_args_after */
815 * Calculate the liveness for a whole block and cache it.
817 * @param sim the simulator handle
818 * @param lv the liveness handle
819 * @param block the block
821 static void update_liveness(x87_simulator *sim, ir_node *block) {
822 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
826 /* now iterate through the block backward and cache the results */
827 sched_foreach_reverse(block, irn) {
828 /* stop at the first Phi: this produces the live-in */
832 idx = get_irn_idx(irn);
833 sim->live[idx] = live;
835 live = vfp_liveness_transfer(sim, irn, live);
837 idx = get_irn_idx(block);
838 sim->live[idx] = live;
839 } /* update_liveness */
842 * Returns true if a register is live in a set.
844 * @param reg_idx the vfp register index
845 * @param live a live bitset
847 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
851 * Dump liveness info.
853 * @param live the live bitset
855 static void vfp_dump_live(vfp_liveness live) {
858 DB((dbg, LEVEL_2, "Live after: "));
859 for (i = 0; i < 8; ++i) {
860 if (live & (1 << i)) {
861 DB((dbg, LEVEL_2, "vf%d ", i));
864 DB((dbg, LEVEL_2, "\n"));
865 } /* vfp_dump_live */
866 #endif /* DEBUG_libfirm */
868 /* --------------------------------- simulators ---------------------------------------- */
870 #define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0)
873 * Simulate a virtual binop.
875 * @param state the x87 state
876 * @param n the node that should be simulated (and patched)
877 * @param tmpl the template containing the 4 possible x87 opcodes
879 * @return NO_NODE_ADDED
881 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
882 int op2_idx = 0, op1_idx;
883 int out_idx, do_pop = 0;
884 ia32_x87_attr_t *attr;
885 ir_node *patched_insn;
887 x87_simulator *sim = state->sim;
888 const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
889 const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2));
890 const arch_register_t *out = x87_get_irn_register(sim, n);
891 int reg_index_1 = arch_register_get_index(op1);
892 int reg_index_2 = arch_register_get_index(op2);
893 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
895 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
896 arch_register_get_name(op1), arch_register_get_name(op2),
897 arch_register_get_name(out)));
898 DEBUG_ONLY(vfp_dump_live(live));
899 DB((dbg, LEVEL_1, "Stack before: "));
900 DEBUG_ONLY(x87_dump_stack(state));
902 op1_idx = x87_on_stack(state, reg_index_1);
903 assert(op1_idx >= 0);
905 if (reg_index_2 != REG_VFP_NOREG) {
906 /* second operand is a vfp register */
907 op2_idx = x87_on_stack(state, reg_index_2);
908 assert(op2_idx >= 0);
910 if (is_vfp_live(arch_register_get_index(op2), live)) {
911 /* Second operand is live. */
913 if (is_vfp_live(arch_register_get_index(op1), live)) {
914 /* Both operands are live: push the first one.
915 This works even for op1 == op2. */
916 x87_create_fpush(state, n, op1_idx, BINOP_IDX_2);
917 /* now do fxxx (tos=tos X op) */
921 dst = tmpl->normal_op;
923 /* Second live, first operand is dead here, bring it to tos. */
925 x87_create_fxch(state, n, op1_idx);
930 /* now do fxxx (tos=tos X op) */
932 dst = tmpl->normal_op;
935 /* Second operand is dead. */
936 if (is_vfp_live(arch_register_get_index(op1), live)) {
937 /* First operand is live: bring second to tos. */
939 x87_create_fxch(state, n, op2_idx);
944 /* now do fxxxr (tos = op X tos) */
946 dst = tmpl->reverse_op;
948 /* Both operands are dead here, pop them from the stack. */
951 /* Both are identically and on tos, no pop needed. */
952 /* here fxxx (tos = tos X tos) */
953 dst = tmpl->normal_op;
956 /* now do fxxxp (op = op X tos, pop) */
957 dst = tmpl->normal_pop_op;
961 } else if (op1_idx == 0) {
962 assert(op1_idx != op2_idx);
963 /* now do fxxxrp (op = tos X op, pop) */
964 dst = tmpl->reverse_pop_op;
968 /* Bring the second on top. */
969 x87_create_fxch(state, n, op2_idx);
970 if (op1_idx == op2_idx) {
971 /* Both are identically and on tos now, no pop needed. */
974 /* use fxxx (tos = tos X tos) */
975 dst = tmpl->normal_op;
978 /* op2 is on tos now */
980 /* use fxxxp (op = op X tos, pop) */
981 dst = tmpl->normal_pop_op;
989 /* second operand is an address mode */
990 if (is_vfp_live(arch_register_get_index(op1), live)) {
991 /* first operand is live: push it here */
992 x87_create_fpush(state, n, op1_idx, BINOP_IDX_1);
994 /* use fxxx (tos = tos X mem) */
995 dst = tmpl->normal_op;
998 /* first operand is dead: bring it to tos */
1000 x87_create_fxch(state, n, op1_idx);
1004 /* use fxxxp (tos = tos X mem) */
1005 dst = tmpl->normal_op;
1010 patched_insn = x87_patch_insn(n, dst);
1011 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1016 /* patch the operation */
1017 attr = get_ia32_x87_attr(n);
1018 attr->x87[0] = op1 = &ia32_st_regs[op1_idx];
1019 if (reg_index_2 != REG_VFP_NOREG) {
1020 attr->x87[1] = op2 = &ia32_st_regs[op2_idx];
1022 attr->x87[2] = out = &ia32_st_regs[out_idx];
1024 if (reg_index_2 != REG_VFP_NOREG) {
1025 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1026 arch_register_get_name(op1), arch_register_get_name(op2),
1027 arch_register_get_name(out)));
1029 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1030 arch_register_get_name(op1),
1031 arch_register_get_name(out)));
1034 return NO_NODE_ADDED;
1038 * Simulate a virtual Unop.
1040 * @param state the x87 state
1041 * @param n the node that should be simulated (and patched)
1042 * @param op the x87 opcode that will replace n's opcode
1044 * @return NO_NODE_ADDED
1046 static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
1047 int op1_idx, out_idx;
1048 x87_simulator *sim = state->sim;
1049 const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
1050 const arch_register_t *out = x87_get_irn_register(sim, n);
1051 ia32_x87_attr_t *attr;
1052 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1054 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1055 DEBUG_ONLY(vfp_dump_live(live));
1057 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1059 if (is_vfp_live(arch_register_get_index(op1), live)) {
1060 /* push the operand here */
1061 x87_create_fpush(state, n, op1_idx, UNOP_IDX);
1065 /* operand is dead, bring it to tos */
1067 x87_create_fxch(state, n, op1_idx);
1072 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1074 attr = get_ia32_x87_attr(n);
1075 attr->x87[0] = op1 = &ia32_st_regs[0];
1076 attr->x87[2] = out = &ia32_st_regs[0];
1077 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1079 return NO_NODE_ADDED;
1083 * Simulate a virtual Load instruction.
1085 * @param state the x87 state
1086 * @param n the node that should be simulated (and patched)
1087 * @param op the x87 opcode that will replace n's opcode
1089 * @return NO_NODE_ADDED
1091 static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
1092 const arch_register_t *out = x87_get_irn_register(state->sim, n);
1093 ia32_x87_attr_t *attr;
1095 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1096 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1097 assert(out == x87_get_irn_register(state->sim, n));
1098 attr = get_ia32_x87_attr(n);
1099 attr->x87[2] = out = &ia32_st_regs[0];
1100 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1102 return NO_NODE_ADDED;
1106 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1108 * @param store The store
1109 * @param old_val The former value
1110 * @param new_val The new value
1112 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) {
1113 const ir_edge_t *edge, *ne;
1115 foreach_out_edge_safe(old_val, edge, ne) {
1116 ir_node *user = get_edge_src_irn(edge);
1118 if (! user || user == store)
1121 /* if the user is scheduled after the store: rewire */
1122 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1124 /* find the input of the user pointing to the old value */
1125 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1126 if (get_irn_n(user, i) == old_val)
1127 set_irn_n(user, i, new_val);
1131 } /* collect_and_rewire_users */
1134 * Simulate a virtual Store.
1136 * @param state the x87 state
1137 * @param n the node that should be simulated (and patched)
1138 * @param op the x87 store opcode
1139 * @param op_p the x87 store and pop opcode
1141 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
1142 x87_simulator *sim = state->sim;
1143 ir_node *val = get_irn_n(n, STORE_VAL_IDX);
1144 const arch_register_t *op2 = x87_get_irn_register(sim, val);
1145 unsigned live = vfp_live_args_after(sim, n, 0);
1146 int insn = NO_NODE_ADDED;
1147 ia32_x87_attr_t *attr;
1148 int op2_reg_idx, op2_idx, depth;
1149 int live_after_node;
1152 op2_reg_idx = arch_register_get_index(op2);
1153 if (op2_reg_idx == REG_VFP_UKNWN) {
1154 /* just take any value from stack */
1155 if(state->depth > 0) {
1157 DEBUG_ONLY(op2 = NULL);
1158 live_after_node = 1;
1160 /* produce a new value which we will consume immediately */
1161 x87_create_fldz(state, n, op2_reg_idx);
1162 live_after_node = 0;
1163 op2_idx = x87_on_stack(state, op2_reg_idx);
1164 assert(op2_idx >= 0);
1167 op2_idx = x87_on_stack(state, op2_reg_idx);
1168 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1169 assert(op2_idx >= 0);
1170 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1173 mode = get_ia32_ls_mode(n);
1174 depth = x87_get_depth(state);
1176 if (live_after_node) {
1178 Problem: fst doesn't support mode_E (spills), only fstp does
1180 - stack not full: push value and fstp
1181 - stack full: fstp value and load again
1183 if (mode == mode_E) {
1184 if (depth < N_x87_REGS) {
1185 /* ok, we have a free register: push + fstp */
1186 x87_create_fpush(state, n, op2_idx, STORE_VAL_IDX);
1188 x87_patch_insn(n, op_p);
1190 ir_node *vfld, *mem, *block, *rproj, *mproj;
1193 /* stack full here: need fstp + load */
1195 x87_patch_insn(n, op_p);
1197 block = get_nodes_block(n);
1198 irg = get_irn_irg(n);
1199 vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
1201 /* copy all attributes */
1202 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1203 if (is_ia32_use_frame(n))
1204 set_ia32_use_frame(vfld);
1205 set_ia32_am_flavour(vfld, get_ia32_am_flavour(n));
1206 set_ia32_op_type(vfld, ia32_am_Source);
1207 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1208 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1209 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1211 rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1212 mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
1213 mem = get_irn_Proj_for_mode(n, mode_M);
1215 assert(mem && "Store memory not found");
1217 arch_set_irn_register(sim->arch_env, rproj, op2);
1219 /* reroute all former users of the store memory to the load memory */
1220 edges_reroute(mem, mproj, irg);
1221 /* set the memory input of the load to the store memory */
1222 set_irn_n(vfld, 2, mem);
1224 sched_add_after(n, vfld);
1225 sched_add_after(vfld, rproj);
1227 /* rewire all users, scheduled after the store, to the loaded value */
1228 collect_and_rewire_users(n, val, rproj);
1233 /* we can only store the tos to memory */
1235 x87_create_fxch(state, n, op2_idx);
1237 /* mode != mode_E -> use normal fst */
1238 x87_patch_insn(n, op);
1241 /* we can only store the tos to memory */
1243 x87_create_fxch(state, n, op2_idx);
1246 x87_patch_insn(n, op_p);
1249 attr = get_ia32_x87_attr(n);
1250 attr->x87[1] = op2 = &ia32_st_regs[0];
1251 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1256 #define _GEN_BINOP(op, rev) \
1257 static int sim_##op(x87_state *state, ir_node *n) { \
1258 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1259 return sim_binop(state, n, &tmpl); \
1262 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1263 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1265 #define GEN_LOAD2(op, nop) \
1266 static int sim_##op(x87_state *state, ir_node *n) { \
1267 return sim_load(state, n, op_ia32_##nop); \
1270 #define GEN_LOAD(op) GEN_LOAD2(op, op)
1272 #define GEN_UNOP(op) \
1273 static int sim_##op(x87_state *state, ir_node *n) { \
1274 return sim_unop(state, n, op_ia32_##op); \
1277 #define GEN_STORE(op) \
1278 static int sim_##op(x87_state *state, ir_node *n) { \
1279 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1304 * Simulate a fCondJmp.
1306 * @param state the x87 state
1307 * @param n the node that should be simulated (and patched)
1309 * @return NO_NODE_ADDED
1311 static int sim_fCondJmp(x87_state *state, ir_node *n) {
1315 ia32_x87_attr_t *attr;
1317 x87_simulator *sim = state->sim;
1318 const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
1319 const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2));
1320 int reg_index_1 = arch_register_get_index(op1);
1321 int reg_index_2 = arch_register_get_index(op2);
1322 unsigned live = vfp_live_args_after(sim, n, 0);
1324 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1325 arch_register_get_name(op1), arch_register_get_name(op2)));
1326 DEBUG_ONLY(vfp_dump_live(live));
1327 DB((dbg, LEVEL_1, "Stack before: "));
1328 DEBUG_ONLY(x87_dump_stack(state));
1330 op1_idx = x87_on_stack(state, reg_index_1);
1331 assert(op1_idx >= 0);
1333 /* BEWARE: check for comp a,a cases, they might happen */
1334 if (reg_index_2 != REG_VFP_NOREG) {
1335 /* second operand is a vfp register */
1336 op2_idx = x87_on_stack(state, reg_index_2);
1337 assert(op2_idx >= 0);
1339 if (is_vfp_live(arch_register_get_index(op2), live)) {
1340 /* second operand is live */
1342 if (is_vfp_live(arch_register_get_index(op1), live)) {
1343 /* both operands are live */
1346 /* res = tos X op */
1347 dst = op_ia32_fcomJmp;
1348 } else if (op2_idx == 0) {
1349 /* res = op X tos */
1350 dst = op_ia32_fcomrJmp;
1352 /* bring the first one to tos */
1353 x87_create_fxch(state, n, op1_idx);
1357 /* res = tos X op */
1358 dst = op_ia32_fcomJmp;
1361 /* second live, first operand is dead here, bring it to tos.
1362 This means further, op1_idx != op2_idx. */
1363 assert(op1_idx != op2_idx);
1365 x87_create_fxch(state, n, op1_idx);
1370 /* res = tos X op, pop */
1371 dst = op_ia32_fcompJmp;
1375 /* second operand is dead */
1376 if (is_vfp_live(arch_register_get_index(op1), live)) {
1377 /* first operand is live: bring second to tos.
1378 This means further, op1_idx != op2_idx. */
1379 assert(op1_idx != op2_idx);
1381 x87_create_fxch(state, n, op2_idx);
1386 /* res = op X tos, pop */
1387 dst = op_ia32_fcomrpJmp;
1390 /* both operands are dead here, check first for identity. */
1391 if (op1_idx == op2_idx) {
1392 /* identically, one pop needed */
1394 x87_create_fxch(state, n, op1_idx);
1398 /* res = tos X op, pop */
1399 dst = op_ia32_fcompJmp;
1402 /* different, move them to st and st(1) and pop both.
1403 The tricky part is to get one into st(1).*/
1404 else if (op2_idx == 1) {
1405 /* good, second operand is already in the right place, move the first */
1407 /* bring the first on top */
1408 x87_create_fxch(state, n, op1_idx);
1409 assert(op2_idx != 0);
1412 /* res = tos X op, pop, pop */
1413 dst = op_ia32_fcomppJmp;
1415 } else if (op1_idx == 1) {
1416 /* good, first operand is already in the right place, move the second */
1418 /* bring the first on top */
1419 x87_create_fxch(state, n, op2_idx);
1420 assert(op1_idx != 0);
1423 dst = op_ia32_fcomrppJmp;
1426 /* if one is already the TOS, we need two fxch */
1428 /* first one is TOS, move to st(1) */
1429 x87_create_fxch(state, n, 1);
1430 assert(op2_idx != 1);
1432 x87_create_fxch(state, n, op2_idx);
1434 /* res = op X tos, pop, pop */
1435 dst = op_ia32_fcomrppJmp;
1437 } else if (op2_idx == 0) {
1438 /* second one is TOS, move to st(1) */
1439 x87_create_fxch(state, n, 1);
1440 assert(op1_idx != 1);
1442 x87_create_fxch(state, n, op1_idx);
1444 /* res = tos X op, pop, pop */
1445 dst = op_ia32_fcomppJmp;
1448 /* none of them is either TOS or st(1), 3 fxch needed */
1449 x87_create_fxch(state, n, op2_idx);
1450 assert(op1_idx != 0);
1451 x87_create_fxch(state, n, 1);
1453 x87_create_fxch(state, n, op1_idx);
1455 /* res = tos X op, pop, pop */
1456 dst = op_ia32_fcomppJmp;
1463 /* second operand is an address mode */
1464 if (is_vfp_live(arch_register_get_index(op1), live)) {
1465 /* first operand is live: bring it to TOS */
1467 x87_create_fxch(state, n, op1_idx);
1470 dst = op_ia32_fcomJmp;
1472 /* first operand is dead: bring it to tos */
1474 x87_create_fxch(state, n, op1_idx);
1477 dst = op_ia32_fcompJmp;
1482 x87_patch_insn(n, dst);
1483 assert(pop_cnt < 3);
1489 /* patch the operation */
1490 attr = get_ia32_x87_attr(n);
1491 op1 = &ia32_st_regs[op1_idx];
1494 op2 = &ia32_st_regs[op2_idx];
1497 attr->x87[2] = NULL;
1500 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1501 arch_register_get_name(op1), arch_register_get_name(op2)));
1503 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1504 arch_register_get_name(op1)));
1506 return NO_NODE_ADDED;
1507 } /* sim_fCondJmp */
1510 int sim_Keep(x87_state *state, ir_node *node)
1513 const arch_register_t *op_reg;
1518 op = get_irn_n(node, 0);
1519 op_reg = arch_get_irn_register(state->sim->arch_env, op);
1520 if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1521 return NO_NODE_ADDED;
1523 reg_id = arch_register_get_index(op_reg);
1524 live = vfp_live_args_after(state->sim, node, 0);
1526 op_stack_idx = x87_on_stack(state, reg_id);
1527 if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
1528 x87_create_fpop(state, sched_next(node), 1);
1532 return NO_NODE_ADDED;
1536 void keep_float_node_alive(x87_state *state, ir_node *node)
1542 const arch_register_class_t *cls;
1544 irg = get_irn_irg(node);
1545 block = get_nodes_block(node);
1546 cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1);
1548 keep = be_new_Keep(cls, irg, block, 1, in);
1550 assert(sched_is_scheduled(node));
1551 sched_add_after(node, keep);
1555 * Create a copy of a node. Recreate the node if it's a constant.
1557 * @param state the x87 state
1558 * @param n the node to be copied
1560 * @return the copy of n
1562 static ir_node *create_Copy(x87_state *state, ir_node *n) {
1563 x87_simulator *sim = state->sim;
1564 ir_graph *irg = get_irn_irg(n);
1565 dbg_info *n_dbg = get_irn_dbg_info(n);
1566 ir_mode *mode = get_irn_mode(n);
1567 ir_node *block = get_nodes_block(n);
1568 ir_node *pred = get_irn_n(n, 0);
1569 ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
1571 const arch_register_t *out;
1572 const arch_register_t *op1;
1573 ia32_x87_attr_t *attr;
1575 /* Do not copy constants, recreate them. */
1576 switch (get_ia32_irn_opcode(pred)) {
1577 case iro_ia32_Unknown_VFP:
1579 cnstr = new_rd_ia32_fldz;
1582 cnstr = new_rd_ia32_fld1;
1584 case iro_ia32_fldpi:
1585 cnstr = new_rd_ia32_fldpi;
1587 case iro_ia32_fldl2e:
1588 cnstr = new_rd_ia32_fldl2e;
1590 case iro_ia32_fldl2t:
1591 cnstr = new_rd_ia32_fldl2t;
1593 case iro_ia32_fldlg2:
1594 cnstr = new_rd_ia32_fldlg2;
1596 case iro_ia32_fldln2:
1597 cnstr = new_rd_ia32_fldln2;
1603 out = x87_get_irn_register(sim, n);
1604 op1 = x87_get_irn_register(sim, pred);
1606 if (cnstr != NULL) {
1607 /* copy a constant */
1608 res = (*cnstr)(n_dbg, irg, block, mode);
1610 x87_push(state, arch_register_get_index(out), res);
1612 attr = get_ia32_x87_attr(res);
1613 attr->x87[2] = &ia32_st_regs[0];
1615 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1617 res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
1619 x87_push(state, arch_register_get_index(out), res);
1621 attr = get_ia32_x87_attr(res);
1622 attr->x87[0] = &ia32_st_regs[op1_idx];
1623 attr->x87[2] = &ia32_st_regs[0];
1625 arch_set_irn_register(sim->arch_env, res, out);
1631 * Simulate a be_Copy.
1633 * @param state the x87 state
1634 * @param n the node that should be simulated (and patched)
1636 * @return NO_NODE_ADDED
1638 static int sim_Copy(x87_state *state, ir_node *n) {
1641 const arch_register_t *out;
1642 const arch_register_t *op1;
1643 ir_node *node, *next;
1644 ia32_x87_attr_t *attr;
1645 int op1_idx, out_idx;
1648 ir_mode *mode = get_irn_mode(n);
1650 if (!mode_is_float(mode))
1654 pred = get_irn_n(n, 0);
1655 out = x87_get_irn_register(sim, n);
1656 op1 = x87_get_irn_register(sim, pred);
1657 live = vfp_live_args_after(sim, n, REGMASK(out));
1659 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1660 arch_register_get_name(op1), arch_register_get_name(out)));
1661 DEBUG_ONLY(vfp_dump_live(live));
1663 /* handle the infamous unknown value */
1664 if (arch_register_get_index(op1) == REG_VFP_UKNWN) {
1665 /* Operand is still live, a real copy. We need here an fpush that can
1666 hold a a register, so use the fpushCopy or recreate constants */
1667 node = create_Copy(state, n);
1669 assert(is_ia32_fldz(node));
1670 next = sched_next(n);
1673 sched_add_before(next, node);
1675 DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
1676 arch_get_irn_register(sim->arch_env, node)->name));
1677 return NO_NODE_ADDED;
1680 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1682 if (is_vfp_live(arch_register_get_index(op1), live)) {
1683 ir_node *pred = get_irn_n(n, 0);
1685 /* Operand is still live, a real copy. We need here an fpush that can
1686 hold a a register, so use the fpushCopy or recreate constants */
1687 node = create_Copy(state, n);
1689 /* We have to make sure the old value doesn't go dead (which can happen
1690 * when we recreate constants). As the simulator expected that value in
1691 * the pred blocks. This is unfortunate as removing it would save us 1
1692 * instruction, but we would have to rerun all the simulation to get
1695 next = sched_next(n);
1698 sched_add_before(next, node);
1700 if(get_irn_n_edges(pred) == 0) {
1701 keep_float_node_alive(state, pred);
1704 DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
1705 arch_get_irn_register(sim->arch_env, node)->name));
1707 out_idx = x87_on_stack(state, arch_register_get_index(out));
1709 if (out_idx >= 0 && out_idx != op1_idx) {
1710 /* Matze: out already on stack? how can this happen? */
1713 /* op1 must be killed and placed where out is */
1715 /* best case, simple remove and rename */
1716 x87_patch_insn(n, op_ia32_Pop);
1717 attr = get_ia32_x87_attr(n);
1718 attr->x87[0] = op1 = &ia32_st_regs[0];
1721 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1723 /* move op1 to tos, store and pop it */
1725 x87_create_fxch(state, n, op1_idx);
1728 x87_patch_insn(n, op_ia32_Pop);
1729 attr = get_ia32_x87_attr(n);
1730 attr->x87[0] = op1 = &ia32_st_regs[out_idx];
1733 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1735 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1737 /* just a virtual copy */
1738 x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
1739 /* don't remove the node to keep the verifier quiet :),
1740 the emitter won't emit any code for the node */
1743 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1744 exchange(n, get_unop_op(n));
1748 return NO_NODE_ADDED;
1752 * Returns the result proj of the call, or NULL if the result is not used
1754 static ir_node *get_call_result_proj(ir_node *call) {
1755 const ir_edge_t *edge;
1756 ir_node *resproj = NULL;
1758 /* search the result proj */
1759 foreach_out_edge(call, edge) {
1760 ir_node *proj = get_edge_src_irn(edge);
1761 long pn = get_Proj_proj(proj);
1763 if (pn == pn_be_Call_first_res) {
1768 if (resproj == NULL) {
1772 /* the result proj is connected to a Keep and maybe other nodes */
1773 foreach_out_edge(resproj, edge) {
1774 ir_node *pred = get_edge_src_irn(edge);
1775 if (!be_is_Keep(pred)) {
1780 /* only be_Keep found, so result is not used */
1782 } /* get_call_result_proj */
1785 * Simulate a be_Call.
1787 * @param state the x87 state
1788 * @param n the node that should be simulated
1789 * @param arch_env the architecture environment
1791 * @return NO_NODE_ADDED
1793 static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
1795 ir_type *call_tp = be_Call_get_type(n);
1799 const arch_register_t *reg;
1802 /* at the begin of a call the x87 state should be empty */
1803 assert(state->depth == 0 && "stack not empty before call");
1805 if (get_method_n_ress(call_tp) <= 0)
1806 return NO_NODE_ADDED;
1809 * If the called function returns a float, it is returned in st(0).
1810 * This even happens if the return value is NOT used.
1811 * Moreover, only one return result is supported.
1813 res_type = get_method_res_type(call_tp, 0);
1814 mode = get_type_mode(res_type);
1816 if (mode == NULL || !mode_is_float(mode))
1817 return NO_NODE_ADDED;
1819 resproj = get_call_result_proj(n);
1820 if (resproj == NULL)
1821 return NO_NODE_ADDED;
1823 reg = x87_get_irn_register(state->sim, resproj);
1824 x87_push(state, arch_register_get_index(reg), resproj);
1826 return NO_NODE_ADDED;
1830 * Simulate a be_Spill.
1832 * @param state the x87 state
1833 * @param n the node that should be simulated (and patched)
1835 * Should not happen, spills are lowered before x87 simulator see them.
1837 static int sim_Spill(x87_state *state, ir_node *n) {
1838 assert(0 && "Spill not lowered");
1839 return sim_fst(state, n);
1843 * Simulate a be_Reload.
1845 * @param state the x87 state
1846 * @param n the node that should be simulated (and patched)
1848 * Should not happen, reloads are lowered before x87 simulator see them.
1850 static int sim_Reload(x87_state *state, ir_node *n) {
1851 assert(0 && "Reload not lowered");
1852 return sim_fld(state, n);
1856 * Simulate a be_Return.
1858 * @param state the x87 state
1859 * @param n the node that should be simulated (and patched)
1861 * @return NO_NODE_ADDED
1863 static int sim_Return(x87_state *state, ir_node *n) {
1864 int n_res = be_Return_get_n_rets(n);
1865 int i, n_float_res = 0;
1867 /* only floating point return values must resist on stack */
1868 for (i = 0; i < n_res; ++i) {
1869 ir_node *res = get_irn_n(n, be_pos_Return_val + i);
1871 if (mode_is_float(get_irn_mode(res)))
1874 assert(x87_get_depth(state) == n_float_res);
1876 /* pop them virtually */
1877 for (i = n_float_res - 1; i >= 0; --i)
1880 return NO_NODE_ADDED;
1883 typedef struct _perm_data_t {
1884 const arch_register_t *in;
1885 const arch_register_t *out;
1889 * Simulate a be_Perm.
1891 * @param state the x87 state
1892 * @param irn the node that should be simulated (and patched)
1894 * @return NO_NODE_ADDED
1896 static int sim_Perm(x87_state *state, ir_node *irn) {
1898 x87_simulator *sim = state->sim;
1899 ir_node *pred = get_irn_n(irn, 0);
1901 const ir_edge_t *edge;
1903 /* handle only floating point Perms */
1904 if (! mode_is_float(get_irn_mode(pred)))
1905 return NO_NODE_ADDED;
1907 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1909 /* Perm is a pure virtual instruction on x87.
1910 All inputs must be on the FPU stack and are pairwise
1911 different from each other.
1912 So, all we need to do is to permutate the stack state. */
1913 n = get_irn_arity(irn);
1914 NEW_ARR_A(int, stack_pos, n);
1916 /* collect old stack positions */
1917 for (i = 0; i < n; ++i) {
1918 const arch_register_t *inreg = x87_get_irn_register(sim, get_irn_n(irn, i));
1919 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1921 assert(idx >= 0 && "Perm argument not on x87 stack");
1925 /* now do the permutation */
1926 foreach_out_edge(irn, edge) {
1927 ir_node *proj = get_edge_src_irn(edge);
1928 const arch_register_t *out = x87_get_irn_register(sim, proj);
1929 long num = get_Proj_proj(proj);
1931 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1932 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1934 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1936 return NO_NODE_ADDED;
1940 * Kill any dead registers at block start by popping them from the stack.
1942 * @param sim the simulator handle
1943 * @param block the current block
1944 * @param start_state the x87 state at the begin of the block
1946 * @return the x87 state after dead register killed
1948 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
1949 x87_state *state = start_state;
1950 ir_node *first_insn = sched_first(block);
1951 ir_node *keep = NULL;
1952 unsigned live = vfp_live_args_after(sim, block, 0);
1954 int i, depth, num_pop;
1957 depth = x87_get_depth(state);
1958 for (i = depth - 1; i >= 0; --i) {
1959 int reg = x87_get_st_reg(state, i);
1961 if (! is_vfp_live(reg, live))
1962 kill_mask |= (1 << i);
1966 /* create a new state, will be changed */
1967 state = x87_clone_state(sim, state);
1969 DB((dbg, LEVEL_1, "Killing deads:\n"));
1970 DEBUG_ONLY(vfp_dump_live(live));
1971 DEBUG_ONLY(x87_dump_stack(state));
1973 /* now kill registers */
1975 /* we can only kill from TOS, so bring them up */
1976 if (! (kill_mask & 1)) {
1977 /* search from behind, because we can to a double-pop */
1978 for (i = depth - 1; i >= 0; --i) {
1979 if (kill_mask & (1 << i)) {
1980 kill_mask &= ~(1 << i);
1987 x87_set_st(state, -1, keep, i);
1988 x87_create_fxch(state, first_insn, i);
1991 if ((kill_mask & 3) == 3) {
1992 /* we can do a double-pop */
1996 /* only a single pop */
2001 kill_mask >>= num_pop;
2002 keep = x87_create_fpop(state, first_insn, num_pop);
2007 } /* x87_kill_deads */
2010 * Run a simulation and fix all virtual instructions for a block.
2012 * @param sim the simulator handle
2013 * @param block the current block
2015 static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
2017 blk_state *bl_state = x87_get_bl_state(sim, block);
2018 x87_state *state = bl_state->begin;
2019 const ir_edge_t *edge;
2020 ir_node *start_block;
2022 assert(state != NULL);
2023 /* already processed? */
2024 if (bl_state->end != NULL)
2027 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2028 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2029 DEBUG_ONLY(x87_dump_stack(state));
2031 /* at block begin, kill all dead registers */
2032 state = x87_kill_deads(sim, block, state);
2034 /* beware, n might change */
2035 for (n = sched_first(block); !sched_is_end(n); n = next) {
2038 ir_op *op = get_irn_op(n);
2040 next = sched_next(n);
2041 if (op->ops.generic == NULL)
2044 func = (sim_func)op->ops.generic;
2046 /* have work to do */
2047 if (state == bl_state->begin) {
2048 /* create a new state, will be changed */
2049 state = x87_clone_state(sim, state);
2053 node_inserted = (*func)(state, n);
2056 sim_func might have added an additional node after n,
2058 beware: n must not be changed by sim_func
2059 (i.e. removed from schedule) in this case
2061 if (node_inserted != NO_NODE_ADDED)
2062 next = sched_next(n);
2065 start_block = get_irg_start_block(get_irn_irg(block));
2067 /* check if the state must be shuffled */
2068 foreach_block_succ(block, edge) {
2069 ir_node *succ = get_edge_src_irn(edge);
2070 blk_state *succ_state;
2072 if (succ == start_block)
2075 succ_state = x87_get_bl_state(sim, succ);
2077 if (succ_state->begin == NULL) {
2078 succ_state->begin = state;
2079 waitq_put(sim->worklist, succ);
2081 /* There is already a begin state for the successor, bad.
2082 Do the necessary permutations.
2083 Note that critical edges are removed, so this is always possible:
2084 If the successor has more than one possible input, then it must
2087 x87_shuffle(sim, block, state, succ, succ_state->begin);
2090 bl_state->end = state;
2092 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state));
2093 } /* x87_simulate_block */
2096 * Create a new x87 simulator.
2098 * @param sim a simulator handle, will be initialized
2099 * @param irg the current graph
2100 * @param arch_env the architecture environment
2102 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
2103 const arch_env_t *arch_env)
2105 obstack_init(&sim->obst);
2106 sim->blk_states = pmap_create();
2107 sim->arch_env = arch_env;
2108 sim->n_idx = get_irg_last_idx(irg);
2109 sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
2111 DB((dbg, LEVEL_1, "--------------------------------\n"
2112 "x87 Simulator started for %+F\n", irg));
2114 /* set the generic function pointer of instruction we must simulate */
2115 clear_irp_opcodes_generic_func();
2117 #define ASSOC(op) (op_ ## op)->ops.generic = (op_func)(sim_##op)
2118 #define ASSOC_IA32(op) (op_ia32_v ## op)->ops.generic = (op_func)(sim_##op)
2119 #define ASSOC_BE(op) (op_be_ ## op)->ops.generic = (op_func)(sim_##op)
2136 ASSOC_IA32(fCondJmp);
2147 } /* x87_init_simulator */
2150 * Destroy a x87 simulator.
2152 * @param sim the simulator handle
2154 static void x87_destroy_simulator(x87_simulator *sim) {
2155 pmap_destroy(sim->blk_states);
2156 obstack_free(&sim->obst, NULL);
2157 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2158 } /* x87_destroy_simulator */
2161 * Pre-block walker: calculate the liveness information for the block
2162 * and store it into the sim->live cache.
2164 static void update_liveness_walker(ir_node *block, void *data) {
2165 x87_simulator *sim = data;
2166 update_liveness(sim, block);
2167 } /* update_liveness_walker */
2170 * Run a simulation and fix all virtual instructions for a graph.
2172 * @param env the architecture environment
2173 * @param irg the current graph
2175 * Needs a block-schedule.
2177 void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
2178 ir_node *block, *start_block;
2179 blk_state *bl_state;
2181 ir_graph *irg = be_get_birg_irg(birg);
2183 /* create the simulator */
2184 x87_init_simulator(&sim, irg, arch_env);
2186 start_block = get_irg_start_block(irg);
2187 bl_state = x87_get_bl_state(&sim, start_block);
2189 /* start with the empty state */
2190 bl_state->begin = empty;
2193 sim.worklist = new_waitq();
2194 waitq_put(sim.worklist, start_block);
2196 be_assure_liveness(birg);
2197 sim.lv = be_get_birg_liveness(birg);
2198 // sim.lv = be_liveness(be_get_birg_irg(birg));
2199 be_liveness_assure_sets(sim.lv);
2201 /* Calculate the liveness for all nodes. We must precalculate this info,
2202 * because the simulator adds new nodes (possible before Phi nodes) which
2203 * would let a lazy calculation fail.
2204 * On the other hand we reduce the computation amount due to
2205 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2207 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2211 block = waitq_get(sim.worklist);
2212 x87_simulate_block(&sim, block);
2213 } while (! waitq_empty(sim.worklist));
2216 del_waitq(sim.worklist);
2217 x87_destroy_simulator(&sim);
2218 } /* x87_simulate_graph */
2220 void ia32_init_x87(void) {
2221 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
2222 } /* ia32_init_x87 */