2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
33 #include "iredges_t.h"
48 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h"
50 #include "gen_ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_architecture.h"
55 #define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1))
57 /** the debug handle */
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 /* Forward declaration. */
61 typedef struct x87_simulator x87_simulator;
64 * An exchange template.
65 * Note that our virtual functions have the same inputs
66 * and attributes as the real ones, so we can simple exchange
68 * Further, x87 supports inverse instructions, so we can handle them.
70 typedef struct exchange_tmpl {
71 ir_op *normal_op; /**< the normal one */
72 ir_op *reverse_op; /**< the reverse one if exists */
73 ir_op *normal_pop_op; /**< the normal one with tos pop */
74 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
78 * An entry on the simulated x87 stack.
80 typedef struct st_entry {
81 int reg_idx; /**< the virtual register index of this stack value */
82 ir_node *node; /**< the node that produced this value */
88 typedef struct x87_state {
89 st_entry st[N_ia32_st_REGS]; /**< the register stack */
90 int depth; /**< the current stack depth */
91 int tos; /**< position of the tos */
92 x87_simulator *sim; /**< The simulator. */
95 /** An empty state, used for blocks without fp instructions. */
96 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
97 static x87_state *empty = (x87_state *)&_empty;
100 * Return values of the instruction simulator functions.
103 NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
104 NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
105 in the schedule AFTER the current node. */
109 * The type of an instruction simulator function.
111 * @param state the x87 state
112 * @param n the node to be simulated
114 * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
116 * NO_NODE_ADDED otherwise
118 typedef int (*sim_func)(x87_state *state, ir_node *n);
121 * A block state: Every block has a x87 state at the beginning and at the end.
123 typedef struct blk_state {
124 x87_state *begin; /**< state at the begin or NULL if not assigned */
125 x87_state *end; /**< state at the end or NULL if not assigned */
128 /** liveness bitset for vfp registers. */
129 typedef unsigned char vfp_liveness;
134 struct x87_simulator {
135 struct obstack obst; /**< An obstack for fast allocating. */
136 pmap *blk_states; /**< Map blocks to states. */
137 be_lv_t *lv; /**< intrablock liveness. */
138 vfp_liveness *live; /**< Liveness information. */
139 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
140 waitq *worklist; /**< Worklist of blocks that must be processed. */
141 ia32_isa_t *isa; /**< the ISA object */
145 * Returns the current stack depth.
147 * @param state the x87 state
149 * @return the x87 stack depth
151 static int x87_get_depth(const x87_state *state)
157 * Return the virtual register index at st(pos).
159 * @param state the x87 state
160 * @param pos a stack position
162 * @return the vfp register index that produced the value at st(pos)
164 static int x87_get_st_reg(const x87_state *state, int pos)
166 assert(pos < state->depth);
167 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
172 * Return the node at st(pos).
174 * @param state the x87 state
175 * @param pos a stack position
177 * @return the IR node that produced the value at st(pos)
179 static ir_node *x87_get_st_node(const x87_state *state, int pos)
181 assert(pos < state->depth);
182 return state->st[MASK_TOS(state->tos + pos)].node;
186 * Dump the stack for debugging.
188 * @param state the x87 state
190 static void x87_dump_stack(const x87_state *state)
194 for (i = state->depth - 1; i >= 0; --i) {
195 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
196 x87_get_st_node(state, i)));
198 DB((dbg, LEVEL_2, "<-- TOS\n"));
200 #endif /* DEBUG_libfirm */
203 * Set a virtual register to st(pos).
205 * @param state the x87 state
206 * @param reg_idx the vfp register index that should be set
207 * @param node the IR node that produces the value of the vfp register
208 * @param pos the stack position where the new value should be entered
210 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
212 assert(0 < state->depth);
213 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
214 state->st[MASK_TOS(state->tos + pos)].node = node;
216 DB((dbg, LEVEL_2, "After SET_REG: "));
217 DEBUG_ONLY(x87_dump_stack(state);)
221 * Set the tos virtual register.
223 * @param state the x87 state
224 * @param reg_idx the vfp register index that should be set
225 * @param node the IR node that produces the value of the vfp register
227 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
229 x87_set_st(state, reg_idx, node, 0);
233 * Swap st(0) with st(pos).
235 * @param state the x87 state
236 * @param pos the stack position to change the tos with
238 static void x87_fxch(x87_state *state, int pos)
241 assert(pos < state->depth);
243 entry = state->st[MASK_TOS(state->tos + pos)];
244 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
245 state->st[MASK_TOS(state->tos)] = entry;
247 DB((dbg, LEVEL_2, "After FXCH: "));
248 DEBUG_ONLY(x87_dump_stack(state);)
252 * Convert a virtual register to the stack index.
254 * @param state the x87 state
255 * @param reg_idx the register vfp index
257 * @return the stack position where the register is stacked
258 * or -1 if the virtual register was not found
260 static int x87_on_stack(const x87_state *state, int reg_idx)
262 int i, tos = state->tos;
264 for (i = 0; i < state->depth; ++i)
265 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
271 * Push a virtual Register onto the stack, double pushed allowed.
273 * @param state the x87 state
274 * @param reg_idx the register vfp index
275 * @param node the node that produces the value of the vfp register
277 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
279 assert(state->depth < N_ia32_st_REGS && "stack overrun");
282 state->tos = MASK_TOS(state->tos - 1);
283 state->st[state->tos].reg_idx = reg_idx;
284 state->st[state->tos].node = node;
286 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
290 * Push a virtual Register onto the stack, double pushes are NOT allowed.
292 * @param state the x87 state
293 * @param reg_idx the register vfp index
294 * @param node the node that produces the value of the vfp register
295 * @param dbl_push if != 0 double pushes are allowed
297 static void x87_push(x87_state *state, int reg_idx, ir_node *node)
299 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
301 x87_push_dbl(state, reg_idx, node);
305 * Pop a virtual Register from the stack.
307 * @param state the x87 state
309 static void x87_pop(x87_state *state)
311 assert(state->depth > 0 && "stack underrun");
314 state->tos = MASK_TOS(state->tos + 1);
316 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
320 * Empty the fpu stack
322 * @param state the x87 state
324 static void x87_emms(x87_state *state)
331 * Returns the block state of a block.
333 * @param sim the x87 simulator handle
334 * @param block the current block
336 * @return the block state
338 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
340 blk_state *res = pmap_get(blk_state, sim->blk_states, block);
343 res = OALLOC(&sim->obst, blk_state);
347 pmap_insert(sim->blk_states, block, res);
354 * Creates a new x87 state.
356 * @param sim the x87 simulator handle
358 * @return a new x87 state
360 static x87_state *x87_alloc_state(x87_simulator *sim)
362 x87_state *res = OALLOC(&sim->obst, x87_state);
371 * @param sim the x87 simulator handle
372 * @param src the x87 state that will be cloned
374 * @return a cloned copy of the src state
376 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
378 x87_state *res = x87_alloc_state(sim);
385 * Patch a virtual instruction into a x87 one and return
386 * the node representing the result value.
388 * @param n the IR node to patch
389 * @param op the x87 opcode to patch in
391 static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
393 ir_mode *mode = get_irn_mode(n);
398 if (mode == mode_T) {
399 /* patch all Proj's */
400 foreach_out_edge(n, edge) {
401 ir_node *proj = get_edge_src_irn(edge);
403 mode = get_irn_mode(proj);
404 if (mode_is_float(mode)) {
406 set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
410 } else if (mode_is_float(mode))
411 set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
416 * Returns the first Proj of a mode_T node having a given mode.
418 * @param n the mode_T node
419 * @param m the desired mode of the Proj
420 * @return The first Proj of mode @p m found or NULL.
422 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
424 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
426 foreach_out_edge(n, edge) {
427 ir_node *proj = get_edge_src_irn(edge);
428 if (get_irn_mode(proj) == m)
436 * Wrap the arch_* function here so we can check for errors.
438 static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
440 const arch_register_t *res = arch_get_irn_register(irn);
442 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
446 static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
449 const arch_register_t *res = arch_get_irn_register_out(irn, pos);
451 assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
455 static inline const arch_register_t *get_st_reg(int index)
457 return &ia32_registers[REG_ST0 + index];
460 /* -------------- x87 perm --------------- */
463 * Creates a fxch for shuffle.
465 * @param state the x87 state
466 * @param pos parameter for fxch
467 * @param block the block were fxch is inserted
469 * Creates a new fxch node and reroute the user of the old node
472 * @return the fxch node
474 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
477 ia32_x87_attr_t *attr;
479 fxch = new_bd_ia32_fxch(NULL, block);
480 attr = get_ia32_x87_attr(fxch);
481 attr->x87[0] = get_st_reg(pos);
482 attr->x87[2] = get_st_reg(0);
486 x87_fxch(state, pos);
491 * Calculate the necessary permutations to reach dst_state.
493 * These permutations are done with fxch instructions and placed
494 * at the end of the block.
496 * Note that critical edges are removed here, so we need only
497 * a shuffle if the current block has only one successor.
499 * @param sim the simulator handle
500 * @param block the current block
501 * @param state the current x87 stack state, might be modified
502 * @param dst_block the destination block
503 * @param dst_state destination state
507 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
508 x87_state *state, ir_node *dst_block,
509 const x87_state *dst_state)
511 int i, n_cycles, k, ri;
512 unsigned cycles[4], all_mask;
513 char cycle_idx[4][8];
514 ir_node *fxch, *before, *after;
518 assert(state->depth == dst_state->depth);
520 /* Some mathematics here:
521 If we have a cycle of length n that includes the tos,
522 we need n-1 exchange operations.
523 We can always add the tos and restore it, so we need
524 n+1 exchange operations for a cycle not containing the tos.
525 So, the maximum of needed operations is for a cycle of 7
526 not including the tos == 8.
527 This is the same number of ops we would need for using stores,
528 so exchange is cheaper (we save the loads).
529 On the other hand, we might need an additional exchange
530 in the next block to bring one operand on top, so the
531 number of ops in the first case is identical.
532 Further, no more than 4 cycles can exists (4 x 2).
534 all_mask = (1 << (state->depth)) - 1;
536 for (n_cycles = 0; all_mask; ++n_cycles) {
537 int src_idx, dst_idx;
539 /* find the first free slot */
540 for (i = 0; i < state->depth; ++i) {
541 if (all_mask & (1 << i)) {
542 all_mask &= ~(1 << i);
544 /* check if there are differences here */
545 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
551 /* no more cycles found */
556 cycles[n_cycles] = (1 << i);
557 cycle_idx[n_cycles][k++] = i;
558 for (src_idx = i; ; src_idx = dst_idx) {
559 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
561 if ((all_mask & (1 << dst_idx)) == 0)
564 cycle_idx[n_cycles][k++] = dst_idx;
565 cycles[n_cycles] |= (1 << dst_idx);
566 all_mask &= ~(1 << dst_idx);
568 cycle_idx[n_cycles][k] = -1;
572 /* no permutation needed */
576 /* Hmm: permutation needed */
577 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
578 DEBUG_ONLY(x87_dump_stack(state);)
579 DB((dbg, LEVEL_2, " to\n"));
580 DEBUG_ONLY(x87_dump_stack(dst_state);)
584 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
585 for (ri = 0; ri < n_cycles; ++ri) {
586 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
587 for (k = 0; cycle_idx[ri][k] != -1; ++k)
588 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
589 DB((dbg, LEVEL_2, "\n"));
596 * Find the place node must be insert.
597 * We have only one successor block, so the last instruction should
600 before = sched_last(block);
601 assert(is_cfop(before));
603 /* now do the permutations */
604 for (ri = 0; ri < n_cycles; ++ri) {
605 if ((cycles[ri] & 1) == 0) {
606 /* this cycle does not include the tos */
607 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
609 sched_add_after(after, fxch);
611 sched_add_before(before, fxch);
614 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
615 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
617 sched_add_after(after, fxch);
619 sched_add_before(before, fxch);
622 if ((cycles[ri] & 1) == 0) {
623 /* this cycle does not include the tos */
624 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
625 sched_add_after(after, fxch);
632 * Create a fxch node before another node.
634 * @param state the x87 state
635 * @param n the node after the fxch
636 * @param pos exchange st(pos) with st(0)
640 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
643 ia32_x87_attr_t *attr;
644 ir_node *block = get_nodes_block(n);
646 x87_fxch(state, pos);
648 fxch = new_bd_ia32_fxch(NULL, block);
649 attr = get_ia32_x87_attr(fxch);
650 attr->x87[0] = get_st_reg(pos);
651 attr->x87[2] = get_st_reg(0);
655 sched_add_before(n, fxch);
656 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
661 * Create a fpush before node n.
663 * @param state the x87 state
664 * @param n the node after the fpush
665 * @param pos push st(pos) on stack
666 * @param op_idx replace input op_idx of n with the fpush result
668 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
670 ir_node *fpush, *pred = get_irn_n(n, op_idx);
671 ia32_x87_attr_t *attr;
672 const arch_register_t *out = x87_get_irn_register(pred);
674 x87_push_dbl(state, arch_register_get_index(out), pred);
676 fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
677 attr = get_ia32_x87_attr(fpush);
678 attr->x87[0] = get_st_reg(pos);
679 attr->x87[2] = get_st_reg(0);
682 sched_add_before(n, fpush);
684 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
688 * Create a fpop before node n.
690 * @param state the x87 state
691 * @param n the node after the fpop
692 * @param num pop 1 or 2 values
694 * @return the fpop node
696 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
698 ir_node *fpop = NULL;
699 ia32_x87_attr_t *attr;
704 if (ia32_cg_config.use_ffreep)
705 fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
707 fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
708 attr = get_ia32_x87_attr(fpop);
709 attr->x87[0] = get_st_reg(0);
710 attr->x87[1] = get_st_reg(0);
711 attr->x87[2] = get_st_reg(0);
714 sched_add_before(n, fpop);
715 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
720 /* --------------------------------- liveness ------------------------------------------ */
723 * The liveness transfer function.
724 * Updates a live set over a single step from a given node to its predecessor.
725 * Everything defined at the node is removed from the set, the uses of the node get inserted.
727 * @param irn The node at which liveness should be computed.
728 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
729 * the registers live after irn.
731 * @return The live bitset.
733 static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
736 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
738 if (get_irn_mode(irn) == mode_T) {
739 foreach_out_edge(irn, edge) {
740 ir_node *proj = get_edge_src_irn(edge);
742 if (arch_irn_consider_in_reg_alloc(cls, proj)) {
743 const arch_register_t *reg = x87_get_irn_register(proj);
744 live &= ~(1 << arch_register_get_index(reg));
747 } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
748 const arch_register_t *reg = x87_get_irn_register(irn);
749 live &= ~(1 << arch_register_get_index(reg));
752 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
753 ir_node *op = get_irn_n(irn, i);
755 if (mode_is_float(get_irn_mode(op)) &&
756 arch_irn_consider_in_reg_alloc(cls, op)) {
757 const arch_register_t *reg = x87_get_irn_register(op);
758 live |= 1 << arch_register_get_index(reg);
765 * Put all live virtual registers at the end of a block into a bitset.
767 * @param sim the simulator handle
768 * @param lv the liveness information
769 * @param bl the block
771 * @return The live bitset at the end of this block
773 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
776 vfp_liveness live = 0;
777 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
778 const be_lv_t *lv = sim->lv;
780 be_lv_foreach(lv, block, be_lv_state_end, i) {
781 const arch_register_t *reg;
782 const ir_node *node = be_lv_get_irn(lv, block, i);
783 if (!arch_irn_consider_in_reg_alloc(cls, node))
786 reg = x87_get_irn_register(node);
787 live |= 1 << arch_register_get_index(reg);
793 /** get the register mask from an arch_register */
794 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
797 * Return a bitset of argument registers which are live at the end of a node.
799 * @param sim the simulator handle
800 * @param pos the node
801 * @param kill kill mask for the output registers
803 * @return The live bitset.
805 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
807 unsigned idx = get_irn_idx(pos);
809 assert(idx < sim->n_idx);
810 return sim->live[idx] & ~kill;
814 * Calculate the liveness for a whole block and cache it.
816 * @param sim the simulator handle
817 * @param lv the liveness handle
818 * @param block the block
820 static void update_liveness(x87_simulator *sim, ir_node *block)
822 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
826 /* now iterate through the block backward and cache the results */
827 sched_foreach_reverse(block, irn) {
828 /* stop at the first Phi: this produces the live-in */
832 idx = get_irn_idx(irn);
833 sim->live[idx] = live;
835 live = vfp_liveness_transfer(irn, live);
837 idx = get_irn_idx(block);
838 sim->live[idx] = live;
842 * Returns true if a register is live in a set.
844 * @param reg_idx the vfp register index
845 * @param live a live bitset
847 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
851 * Dump liveness info.
853 * @param live the live bitset
855 static void vfp_dump_live(vfp_liveness live)
859 DB((dbg, LEVEL_2, "Live after: "));
860 for (i = 0; i < 8; ++i) {
861 if (live & (1 << i)) {
862 DB((dbg, LEVEL_2, "vf%d ", i));
865 DB((dbg, LEVEL_2, "\n"));
867 #endif /* DEBUG_libfirm */
869 /* --------------------------------- simulators ---------------------------------------- */
872 * Simulate a virtual binop.
874 * @param state the x87 state
875 * @param n the node that should be simulated (and patched)
876 * @param tmpl the template containing the 4 possible x87 opcodes
878 * @return NO_NODE_ADDED
880 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
882 int op2_idx = 0, op1_idx;
883 int out_idx, do_pop = 0;
884 ia32_x87_attr_t *attr;
886 ir_node *patched_insn;
888 x87_simulator *sim = state->sim;
889 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
890 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
891 const arch_register_t *op1_reg = x87_get_irn_register(op1);
892 const arch_register_t *op2_reg = x87_get_irn_register(op2);
893 const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
894 int reg_index_1 = arch_register_get_index(op1_reg);
895 int reg_index_2 = arch_register_get_index(op2_reg);
896 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
900 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
901 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
902 arch_register_get_name(out)));
903 DEBUG_ONLY(vfp_dump_live(live);)
904 DB((dbg, LEVEL_1, "Stack before: "));
905 DEBUG_ONLY(x87_dump_stack(state);)
907 op1_idx = x87_on_stack(state, reg_index_1);
908 assert(op1_idx >= 0);
909 op1_live_after = is_vfp_live(reg_index_1, live);
911 attr = get_ia32_x87_attr(n);
912 permuted = attr->attr.data.ins_permuted;
914 if (reg_index_2 != REG_VFP_VFP_NOREG) {
917 /* second operand is a vfp register */
918 op2_idx = x87_on_stack(state, reg_index_2);
919 assert(op2_idx >= 0);
920 op2_live_after = is_vfp_live(reg_index_2, live);
922 if (op2_live_after) {
923 /* Second operand is live. */
925 if (op1_live_after) {
926 /* Both operands are live: push the first one.
927 This works even for op1 == op2. */
928 x87_create_fpush(state, n, op1_idx, n_ia32_binary_right);
929 /* now do fxxx (tos=tos X op) */
933 dst = tmpl->normal_op;
935 /* Second live, first operand is dead here, bring it to tos. */
937 x87_create_fxch(state, n, op1_idx);
942 /* now do fxxx (tos=tos X op) */
944 dst = tmpl->normal_op;
947 /* Second operand is dead. */
948 if (op1_live_after) {
949 /* First operand is live: bring second to tos. */
951 x87_create_fxch(state, n, op2_idx);
956 /* now do fxxxr (tos = op X tos) */
958 dst = tmpl->reverse_op;
960 /* Both operands are dead here, pop them from the stack. */
963 /* Both are identically and on tos, no pop needed. */
964 /* here fxxx (tos = tos X tos) */
965 dst = tmpl->normal_op;
968 /* now do fxxxp (op = op X tos, pop) */
969 dst = tmpl->normal_pop_op;
973 } else if (op1_idx == 0) {
974 assert(op1_idx != op2_idx);
975 /* now do fxxxrp (op = tos X op, pop) */
976 dst = tmpl->reverse_pop_op;
980 /* Bring the second on top. */
981 x87_create_fxch(state, n, op2_idx);
982 if (op1_idx == op2_idx) {
983 /* Both are identically and on tos now, no pop needed. */
986 /* use fxxx (tos = tos X tos) */
987 dst = tmpl->normal_op;
990 /* op2 is on tos now */
992 /* use fxxxp (op = op X tos, pop) */
993 dst = tmpl->normal_pop_op;
1001 /* second operand is an address mode */
1002 if (op1_live_after) {
1003 /* first operand is live: push it here */
1004 x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
1007 /* first operand is dead: bring it to tos */
1009 x87_create_fxch(state, n, op1_idx);
1014 /* use fxxx (tos = tos X mem) */
1015 dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
1019 patched_insn = x87_patch_insn(n, dst);
1020 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1025 /* patch the operation */
1026 attr->x87[0] = op1_reg = get_st_reg(op1_idx);
1027 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1028 attr->x87[1] = op2_reg = get_st_reg(op2_idx);
1030 attr->x87[2] = out = get_st_reg(out_idx);
1032 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1033 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1034 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
1035 arch_register_get_name(out)));
1037 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1038 arch_register_get_name(op1_reg),
1039 arch_register_get_name(out)));
1042 return NO_NODE_ADDED;
1046 * Simulate a virtual Unop.
1048 * @param state the x87 state
1049 * @param n the node that should be simulated (and patched)
1050 * @param op the x87 opcode that will replace n's opcode
1052 * @return NO_NODE_ADDED
1054 static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
1057 x87_simulator *sim = state->sim;
1058 const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
1059 const arch_register_t *out = x87_get_irn_register(n);
1060 ia32_x87_attr_t *attr;
1061 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1063 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1064 DEBUG_ONLY(vfp_dump_live(live);)
1066 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1068 if (is_vfp_live(arch_register_get_index(op1), live)) {
1069 /* push the operand here */
1070 x87_create_fpush(state, n, op1_idx, 0);
1074 /* operand is dead, bring it to tos */
1076 x87_create_fxch(state, n, op1_idx);
1081 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1082 attr = get_ia32_x87_attr(n);
1083 attr->x87[0] = op1 = get_st_reg(0);
1084 attr->x87[2] = out = get_st_reg(0);
1085 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1087 return NO_NODE_ADDED;
1091 * Simulate a virtual Load instruction.
1093 * @param state the x87 state
1094 * @param n the node that should be simulated (and patched)
1095 * @param op the x87 opcode that will replace n's opcode
1097 * @return NO_NODE_ADDED
1099 static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
1101 const arch_register_t *out = x87_irn_get_register(n, res_pos);
1102 ia32_x87_attr_t *attr;
1104 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1105 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1106 assert(out == x87_irn_get_register(n, res_pos));
1107 attr = get_ia32_x87_attr(n);
1108 attr->x87[2] = out = get_st_reg(0);
1109 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1111 return NO_NODE_ADDED;
1115 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1117 * @param store The store
1118 * @param old_val The former value
1119 * @param new_val The new value
1121 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
1123 foreach_out_edge_safe(old_val, edge) {
1124 ir_node *user = get_edge_src_irn(edge);
1126 if (! user || user == store)
1129 /* if the user is scheduled after the store: rewire */
1130 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1132 /* find the input of the user pointing to the old value */
1133 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1134 if (get_irn_n(user, i) == old_val)
1135 set_irn_n(user, i, new_val);
1142 * Simulate a virtual Store.
1144 * @param state the x87 state
1145 * @param n the node that should be simulated (and patched)
1146 * @param op the x87 store opcode
1147 * @param op_p the x87 store and pop opcode
1149 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
1151 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1152 const arch_register_t *op2 = x87_get_irn_register(val);
1153 unsigned live = vfp_live_args_after(state->sim, n, 0);
1154 int insn = NO_NODE_ADDED;
1155 ia32_x87_attr_t *attr;
1156 int op2_reg_idx, op2_idx, depth;
1157 int live_after_node;
1160 op2_reg_idx = arch_register_get_index(op2);
1161 op2_idx = x87_on_stack(state, op2_reg_idx);
1162 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1163 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1164 assert(op2_idx >= 0);
1166 mode = get_ia32_ls_mode(n);
1167 depth = x87_get_depth(state);
1169 if (live_after_node) {
1171 Problem: fst doesn't support 96bit modes (spills), only fstp does
1172 fist doesn't support 64bit mode, only fistp
1174 - stack not full: push value and fstp
1175 - stack full: fstp value and load again
1176 Note that we cannot test on mode_E, because floats might be 96bit ...
1178 if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
1179 if (depth < N_ia32_st_REGS) {
1180 /* ok, we have a free register: push + fstp */
1181 x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
1183 x87_patch_insn(n, op_p);
1185 ir_node *vfld, *mem, *block, *rproj, *mproj;
1186 ir_graph *irg = get_irn_irg(n);
1187 ir_node *nomem = get_irg_no_mem(irg);
1189 /* stack full here: need fstp + load */
1191 x87_patch_insn(n, op_p);
1193 block = get_nodes_block(n);
1194 vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n));
1196 /* copy all attributes */
1197 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1198 if (is_ia32_use_frame(n))
1199 set_ia32_use_frame(vfld);
1200 set_ia32_op_type(vfld, ia32_AddrModeS);
1201 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1202 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1203 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1205 rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1206 mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
1207 mem = get_irn_Proj_for_mode(n, mode_M);
1209 assert(mem && "Store memory not found");
1211 arch_set_irn_register(rproj, op2);
1213 /* reroute all former users of the store memory to the load memory */
1214 edges_reroute(mem, mproj);
1215 /* set the memory input of the load to the store memory */
1216 set_irn_n(vfld, n_ia32_vfld_mem, mem);
1218 sched_add_after(n, vfld);
1219 sched_add_after(vfld, rproj);
1221 /* rewire all users, scheduled after the store, to the loaded value */
1222 collect_and_rewire_users(n, val, rproj);
1227 /* we can only store the tos to memory */
1229 x87_create_fxch(state, n, op2_idx);
1231 /* mode size 64 or smaller -> use normal fst */
1232 x87_patch_insn(n, op);
1235 /* we can only store the tos to memory */
1237 x87_create_fxch(state, n, op2_idx);
1240 x87_patch_insn(n, op_p);
1243 attr = get_ia32_x87_attr(n);
1244 attr->x87[1] = op2 = get_st_reg(0);
1245 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1250 #define _GEN_BINOP(op, rev) \
1251 static int sim_##op(x87_state *state, ir_node *n) { \
1252 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1253 return sim_binop(state, n, &tmpl); \
1256 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1257 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1259 #define GEN_LOAD(op) \
1260 static int sim_##op(x87_state *state, ir_node *n) { \
1261 return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
1264 #define GEN_UNOP(op) \
1265 static int sim_##op(x87_state *state, ir_node *n) { \
1266 return sim_unop(state, n, op_ia32_##op); \
1269 #define GEN_STORE(op) \
1270 static int sim_##op(x87_state *state, ir_node *n) { \
1271 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1293 * Simulate a virtual fisttp.
1295 * @param state the x87 state
1296 * @param n the node that should be simulated (and patched)
1298 * @return NO_NODE_ADDED
1300 static int sim_fisttp(x87_state *state, ir_node *n)
1302 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1303 const arch_register_t *op2 = x87_get_irn_register(val);
1304 ia32_x87_attr_t *attr;
1305 int op2_reg_idx, op2_idx;
1307 op2_reg_idx = arch_register_get_index(op2);
1308 op2_idx = x87_on_stack(state, op2_reg_idx);
1309 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1310 assert(op2_idx >= 0);
1312 /* Note: although the value is still live here, it is destroyed because
1313 of the pop. The register allocator is aware of that and introduced a copy
1314 if the value must be alive. */
1316 /* we can only store the tos to memory */
1318 x87_create_fxch(state, n, op2_idx);
1321 x87_patch_insn(n, op_ia32_fisttp);
1323 attr = get_ia32_x87_attr(n);
1324 attr->x87[1] = op2 = get_st_reg(0);
1325 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1327 return NO_NODE_ADDED;
1331 * Simulate a virtual FtstFnstsw.
1333 * @param state the x87 state
1334 * @param n the node that should be simulated (and patched)
1336 * @return NO_NODE_ADDED
1338 static int sim_FtstFnstsw(x87_state *state, ir_node *n)
1340 x87_simulator *sim = state->sim;
1341 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1342 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1343 const arch_register_t *reg1 = x87_get_irn_register(op1_node);
1344 int reg_index_1 = arch_register_get_index(reg1);
1345 int op1_idx = x87_on_stack(state, reg_index_1);
1346 unsigned live = vfp_live_args_after(sim, n, 0);
1348 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1349 DEBUG_ONLY(vfp_dump_live(live);)
1350 DB((dbg, LEVEL_1, "Stack before: "));
1351 DEBUG_ONLY(x87_dump_stack(state);)
1352 assert(op1_idx >= 0);
1355 /* bring the value to tos */
1356 x87_create_fxch(state, n, op1_idx);
1360 /* patch the operation */
1361 x87_patch_insn(n, op_ia32_FtstFnstsw);
1362 reg1 = get_st_reg(op1_idx);
1363 attr->x87[0] = reg1;
1364 attr->x87[1] = NULL;
1365 attr->x87[2] = NULL;
1367 if (!is_vfp_live(reg_index_1, live))
1368 x87_create_fpop(state, sched_next(n), 1);
1370 return NO_NODE_ADDED;
1376 * @param state the x87 state
1377 * @param n the node that should be simulated (and patched)
1379 * @return NO_NODE_ADDED
1381 static int sim_Fucom(x87_state *state, ir_node *n)
1385 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1387 x87_simulator *sim = state->sim;
1388 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1389 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1390 const arch_register_t *op1 = x87_get_irn_register(op1_node);
1391 const arch_register_t *op2 = x87_get_irn_register(op2_node);
1392 int reg_index_1 = arch_register_get_index(op1);
1393 int reg_index_2 = arch_register_get_index(op2);
1394 unsigned live = vfp_live_args_after(sim, n, 0);
1395 bool permuted = attr->attr.data.ins_permuted;
1399 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1400 arch_register_get_name(op1), arch_register_get_name(op2)));
1401 DEBUG_ONLY(vfp_dump_live(live);)
1402 DB((dbg, LEVEL_1, "Stack before: "));
1403 DEBUG_ONLY(x87_dump_stack(state);)
1405 op1_idx = x87_on_stack(state, reg_index_1);
1406 assert(op1_idx >= 0);
1408 /* BEWARE: check for comp a,a cases, they might happen */
1409 if (reg_index_2 != REG_VFP_VFP_NOREG) {
1410 /* second operand is a vfp register */
1411 op2_idx = x87_on_stack(state, reg_index_2);
1412 assert(op2_idx >= 0);
1414 if (is_vfp_live(reg_index_2, live)) {
1415 /* second operand is live */
1417 if (is_vfp_live(reg_index_1, live)) {
1418 /* both operands are live */
1421 /* res = tos X op */
1422 } else if (op2_idx == 0) {
1423 /* res = op X tos */
1424 permuted = !permuted;
1427 /* bring the first one to tos */
1428 x87_create_fxch(state, n, op1_idx);
1429 if (op1_idx == op2_idx) {
1431 } else if (op2_idx == 0) {
1435 /* res = tos X op */
1438 /* second live, first operand is dead here, bring it to tos.
1439 This means further, op1_idx != op2_idx. */
1440 assert(op1_idx != op2_idx);
1442 x87_create_fxch(state, n, op1_idx);
1447 /* res = tos X op, pop */
1451 /* second operand is dead */
1452 if (is_vfp_live(reg_index_1, live)) {
1453 /* first operand is live: bring second to tos.
1454 This means further, op1_idx != op2_idx. */
1455 assert(op1_idx != op2_idx);
1457 x87_create_fxch(state, n, op2_idx);
1462 /* res = op X tos, pop */
1464 permuted = !permuted;
1467 /* both operands are dead here, check first for identity. */
1468 if (op1_idx == op2_idx) {
1469 /* identically, one pop needed */
1471 x87_create_fxch(state, n, op1_idx);
1475 /* res = tos X op, pop */
1478 /* different, move them to st and st(1) and pop both.
1479 The tricky part is to get one into st(1).*/
1480 else if (op2_idx == 1) {
1481 /* good, second operand is already in the right place, move the first */
1483 /* bring the first on top */
1484 x87_create_fxch(state, n, op1_idx);
1485 assert(op2_idx != 0);
1488 /* res = tos X op, pop, pop */
1490 } else if (op1_idx == 1) {
1491 /* good, first operand is already in the right place, move the second */
1493 /* bring the first on top */
1494 x87_create_fxch(state, n, op2_idx);
1495 assert(op1_idx != 0);
1498 /* res = op X tos, pop, pop */
1499 permuted = !permuted;
1503 /* if one is already the TOS, we need two fxch */
1505 /* first one is TOS, move to st(1) */
1506 x87_create_fxch(state, n, 1);
1507 assert(op2_idx != 1);
1509 x87_create_fxch(state, n, op2_idx);
1511 /* res = op X tos, pop, pop */
1513 permuted = !permuted;
1515 } else if (op2_idx == 0) {
1516 /* second one is TOS, move to st(1) */
1517 x87_create_fxch(state, n, 1);
1518 assert(op1_idx != 1);
1520 x87_create_fxch(state, n, op1_idx);
1522 /* res = tos X op, pop, pop */
1525 /* none of them is either TOS or st(1), 3 fxch needed */
1526 x87_create_fxch(state, n, op2_idx);
1527 assert(op1_idx != 0);
1528 x87_create_fxch(state, n, 1);
1530 x87_create_fxch(state, n, op1_idx);
1532 /* res = tos X op, pop, pop */
1539 /* second operand is an address mode */
1540 if (is_vfp_live(reg_index_1, live)) {
1541 /* first operand is live: bring it to TOS */
1543 x87_create_fxch(state, n, op1_idx);
1547 /* first operand is dead: bring it to tos */
1549 x87_create_fxch(state, n, op1_idx);
1556 /* patch the operation */
1557 if (is_ia32_vFucomFnstsw(n)) {
1561 case 0: dst = op_ia32_FucomFnstsw; break;
1562 case 1: dst = op_ia32_FucompFnstsw; break;
1563 case 2: dst = op_ia32_FucomppFnstsw; break;
1564 default: panic("invalid popcount in sim_Fucom");
1567 for (i = 0; i < pops; ++i) {
1570 } else if (is_ia32_vFucomi(n)) {
1572 case 0: dst = op_ia32_Fucomi; break;
1573 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1575 dst = op_ia32_Fucompi;
1577 x87_create_fpop(state, sched_next(n), 1);
1579 default: panic("invalid popcount in sim_Fucom");
1582 panic("invalid operation %+F in sim_FucomFnstsw", n);
1585 x87_patch_insn(n, dst);
1592 op1 = get_st_reg(op1_idx);
1595 op2 = get_st_reg(op2_idx);
1598 attr->x87[2] = NULL;
1599 attr->attr.data.ins_permuted = permuted;
1602 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1603 arch_register_get_name(op1), arch_register_get_name(op2)));
1605 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1606 arch_register_get_name(op1)));
1609 return NO_NODE_ADDED;
1615 * @param state the x87 state
1616 * @param n the node that should be simulated (and patched)
1618 * @return NO_NODE_ADDED
1620 static int sim_Keep(x87_state *state, ir_node *node)
1623 const arch_register_t *op_reg;
1629 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1631 arity = get_irn_arity(node);
1632 for (i = 0; i < arity; ++i) {
1633 op = get_irn_n(node, i);
1634 op_reg = arch_get_irn_register(op);
1635 if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1638 reg_id = arch_register_get_index(op_reg);
1639 live = vfp_live_args_after(state->sim, node, 0);
1641 op_stack_idx = x87_on_stack(state, reg_id);
1642 if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
1643 x87_create_fpop(state, sched_next(node), 1);
1646 DB((dbg, LEVEL_1, "Stack after: "));
1647 DEBUG_ONLY(x87_dump_stack(state);)
1649 return NO_NODE_ADDED;
1653 * Keep the given node alive by adding a be_Keep.
1655 * @param node the node to kept alive
1657 static void keep_float_node_alive(ir_node *node)
1659 ir_node *block = get_nodes_block(node);
1660 ir_node *keep = be_new_Keep(block, 1, &node);
1662 assert(sched_is_scheduled(node));
1663 sched_add_after(node, keep);
1667 * Create a copy of a node. Recreate the node if it's a constant.
1669 * @param state the x87 state
1670 * @param n the node to be copied
1672 * @return the copy of n
1674 static ir_node *create_Copy(x87_state *state, ir_node *n)
1676 dbg_info *n_dbg = get_irn_dbg_info(n);
1677 ir_mode *mode = get_irn_mode(n);
1678 ir_node *block = get_nodes_block(n);
1679 ir_node *pred = get_irn_n(n, 0);
1680 ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
1682 const arch_register_t *out;
1683 const arch_register_t *op1;
1684 ia32_x87_attr_t *attr;
1686 /* Do not copy constants, recreate them. */
1687 switch (get_ia32_irn_opcode(pred)) {
1689 cnstr = new_bd_ia32_fldz;
1692 cnstr = new_bd_ia32_fld1;
1694 case iro_ia32_fldpi:
1695 cnstr = new_bd_ia32_fldpi;
1697 case iro_ia32_fldl2e:
1698 cnstr = new_bd_ia32_fldl2e;
1700 case iro_ia32_fldl2t:
1701 cnstr = new_bd_ia32_fldl2t;
1703 case iro_ia32_fldlg2:
1704 cnstr = new_bd_ia32_fldlg2;
1706 case iro_ia32_fldln2:
1707 cnstr = new_bd_ia32_fldln2;
1713 out = x87_get_irn_register(n);
1714 op1 = x87_get_irn_register(pred);
1716 if (cnstr != NULL) {
1717 /* copy a constant */
1718 res = (*cnstr)(n_dbg, block, mode);
1720 x87_push(state, arch_register_get_index(out), res);
1722 attr = get_ia32_x87_attr(res);
1723 attr->x87[2] = get_st_reg(0);
1725 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1727 res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
1729 x87_push(state, arch_register_get_index(out), res);
1731 attr = get_ia32_x87_attr(res);
1732 attr->x87[0] = get_st_reg(op1_idx);
1733 attr->x87[2] = get_st_reg(0);
1735 arch_set_irn_register(res, out);
1741 * Simulate a be_Copy.
1743 * @param state the x87 state
1744 * @param n the node that should be simulated (and patched)
1746 * @return NO_NODE_ADDED
1748 static int sim_Copy(x87_state *state, ir_node *n)
1751 const arch_register_t *out;
1752 const arch_register_t *op1;
1753 const arch_register_class_t *cls;
1754 ir_node *node, *next;
1755 int op1_idx, out_idx;
1758 cls = arch_get_irn_reg_class(n);
1759 if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
1762 pred = get_irn_n(n, 0);
1763 out = x87_get_irn_register(n);
1764 op1 = x87_get_irn_register(pred);
1765 live = vfp_live_args_after(state->sim, n, REGMASK(out));
1767 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1768 arch_register_get_name(op1), arch_register_get_name(out)));
1769 DEBUG_ONLY(vfp_dump_live(live);)
1771 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1773 if (is_vfp_live(arch_register_get_index(op1), live)) {
1774 /* Operand is still live, a real copy. We need here an fpush that can
1775 hold a a register, so use the fpushCopy or recreate constants */
1776 node = create_Copy(state, n);
1778 /* We have to make sure the old value doesn't go dead (which can happen
1779 * when we recreate constants). As the simulator expected that value in
1780 * the pred blocks. This is unfortunate as removing it would save us 1
1781 * instruction, but we would have to rerun all the simulation to get
1784 next = sched_next(n);
1787 sched_add_before(next, node);
1789 if (get_irn_n_edges(pred) == 0) {
1790 keep_float_node_alive(pred);
1793 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1795 out_idx = x87_on_stack(state, arch_register_get_index(out));
1797 if (out_idx >= 0 && out_idx != op1_idx) {
1798 /* Matze: out already on stack? how can this happen? */
1799 panic("invalid stack state in x87 simulator");
1802 /* op1 must be killed and placed where out is */
1804 ia32_x87_attr_t *attr;
1805 /* best case, simple remove and rename */
1806 x87_patch_insn(n, op_ia32_Pop);
1807 attr = get_ia32_x87_attr(n);
1808 attr->x87[0] = op1 = get_st_reg(0);
1811 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1813 ia32_x87_attr_t *attr;
1814 /* move op1 to tos, store and pop it */
1816 x87_create_fxch(state, n, op1_idx);
1819 x87_patch_insn(n, op_ia32_Pop);
1820 attr = get_ia32_x87_attr(n);
1821 attr->x87[0] = op1 = get_st_reg(out_idx);
1824 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1826 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1829 /* just a virtual copy */
1830 x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
1831 /* don't remove the node to keep the verifier quiet :),
1832 the emitter won't emit any code for the node */
1835 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1836 exchange(n, get_unop_op(n));
1840 return NO_NODE_ADDED;
1844 * Returns the vf0 result Proj of a Call.
1846 * @para call the Call node
1848 static ir_node *get_call_result_proj(ir_node *call)
1850 /* search the result proj */
1851 foreach_out_edge(call, edge) {
1852 ir_node *proj = get_edge_src_irn(edge);
1853 long pn = get_Proj_proj(proj);
1855 if (pn == pn_ia32_Call_vf0)
1863 * Simulate a ia32_Call.
1865 * @param state the x87 state
1866 * @param n the node that should be simulated (and patched)
1868 * @return NO_NODE_ADDED
1870 static int sim_Call(x87_state *state, ir_node *n)
1872 ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp;
1876 const arch_register_t *reg;
1878 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1880 /* at the begin of a call the x87 state should be empty */
1881 assert(state->depth == 0 && "stack not empty before call");
1883 if (get_method_n_ress(call_tp) <= 0)
1887 * If the called function returns a float, it is returned in st(0).
1888 * This even happens if the return value is NOT used.
1889 * Moreover, only one return result is supported.
1891 res_type = get_method_res_type(call_tp, 0);
1892 mode = get_type_mode(res_type);
1894 if (mode == NULL || !mode_is_float(mode))
1897 resproj = get_call_result_proj(n);
1898 assert(resproj != NULL);
1900 reg = x87_get_irn_register(resproj);
1901 x87_push(state, arch_register_get_index(reg), resproj);
1904 DB((dbg, LEVEL_1, "Stack after: "));
1905 DEBUG_ONLY(x87_dump_stack(state);)
1907 return NO_NODE_ADDED;
1911 * Simulate a be_Return.
1913 * @param state the x87 state
1914 * @param n the node that should be simulated (and patched)
1916 * @return NO_NODE_ADDED
1918 static int sim_Return(x87_state *state, ir_node *n)
1920 int n_res = be_Return_get_n_rets(n);
1921 int i, n_float_res = 0;
1923 /* only floating point return values must reside on stack */
1924 for (i = 0; i < n_res; ++i) {
1925 ir_node *res = get_irn_n(n, n_be_Return_val + i);
1927 if (mode_is_float(get_irn_mode(res)))
1930 assert(x87_get_depth(state) == n_float_res);
1932 /* pop them virtually */
1933 for (i = n_float_res - 1; i >= 0; --i)
1936 return NO_NODE_ADDED;
1939 typedef struct perm_data_t {
1940 const arch_register_t *in;
1941 const arch_register_t *out;
1945 * Simulate a be_Perm.
1947 * @param state the x87 state
1948 * @param irn the node that should be simulated (and patched)
1950 * @return NO_NODE_ADDED
1952 static int sim_Perm(x87_state *state, ir_node *irn)
1955 ir_node *pred = get_irn_n(irn, 0);
1958 /* handle only floating point Perms */
1959 if (! mode_is_float(get_irn_mode(pred)))
1960 return NO_NODE_ADDED;
1962 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
1964 /* Perm is a pure virtual instruction on x87.
1965 All inputs must be on the FPU stack and are pairwise
1966 different from each other.
1967 So, all we need to do is to permutate the stack state. */
1968 n = get_irn_arity(irn);
1969 NEW_ARR_A(int, stack_pos, n);
1971 /* collect old stack positions */
1972 for (i = 0; i < n; ++i) {
1973 const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
1974 int idx = x87_on_stack(state, arch_register_get_index(inreg));
1976 assert(idx >= 0 && "Perm argument not on x87 stack");
1980 /* now do the permutation */
1981 foreach_out_edge(irn, edge) {
1982 ir_node *proj = get_edge_src_irn(edge);
1983 const arch_register_t *out = x87_get_irn_register(proj);
1984 long num = get_Proj_proj(proj);
1986 assert(0 <= num && num < n && "More Proj's than Perm inputs");
1987 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
1989 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
1991 return NO_NODE_ADDED;
1995 * Kill any dead registers at block start by popping them from the stack.
1997 * @param sim the simulator handle
1998 * @param block the current block
1999 * @param start_state the x87 state at the begin of the block
2001 * @return the x87 state after dead register killed
2003 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
2005 x87_state *state = start_state;
2006 ir_node *first_insn = sched_first(block);
2007 ir_node *keep = NULL;
2008 unsigned live = vfp_live_args_after(sim, block, 0);
2010 int i, depth, num_pop;
2013 depth = x87_get_depth(state);
2014 for (i = depth - 1; i >= 0; --i) {
2015 int reg = x87_get_st_reg(state, i);
2017 if (! is_vfp_live(reg, live))
2018 kill_mask |= (1 << i);
2022 /* create a new state, will be changed */
2023 state = x87_clone_state(sim, state);
2025 DB((dbg, LEVEL_1, "Killing deads:\n"));
2026 DEBUG_ONLY(vfp_dump_live(live);)
2027 DEBUG_ONLY(x87_dump_stack(state);)
2029 if (kill_mask != 0 && live == 0) {
2030 /* special case: kill all registers */
2031 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
2032 if (ia32_cg_config.use_femms) {
2033 /* use FEMMS on AMD processors to clear all */
2034 keep = new_bd_ia32_femms(NULL, block);
2036 /* use EMMS to clear all */
2037 keep = new_bd_ia32_emms(NULL, block);
2039 sched_add_before(first_insn, keep);
2045 /* now kill registers */
2047 /* we can only kill from TOS, so bring them up */
2048 if (! (kill_mask & 1)) {
2049 /* search from behind, because we can to a double-pop */
2050 for (i = depth - 1; i >= 0; --i) {
2051 if (kill_mask & (1 << i)) {
2052 kill_mask &= ~(1 << i);
2059 x87_set_st(state, -1, keep, i);
2060 x87_create_fxch(state, first_insn, i);
2063 if ((kill_mask & 3) == 3) {
2064 /* we can do a double-pop */
2068 /* only a single pop */
2073 kill_mask >>= num_pop;
2074 keep = x87_create_fpop(state, first_insn, num_pop);
2082 * Run a simulation and fix all virtual instructions for a block.
2084 * @param sim the simulator handle
2085 * @param block the current block
2087 static void x87_simulate_block(x87_simulator *sim, ir_node *block)
2090 blk_state *bl_state = x87_get_bl_state(sim, block);
2091 x87_state *state = bl_state->begin;
2092 ir_node *start_block;
2094 assert(state != NULL);
2095 /* already processed? */
2096 if (bl_state->end != NULL)
2099 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2100 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2101 DEBUG_ONLY(x87_dump_stack(state);)
2103 /* at block begin, kill all dead registers */
2104 state = x87_kill_deads(sim, block, state);
2105 /* create a new state, will be changed */
2106 state = x87_clone_state(sim, state);
2108 /* beware, n might change */
2109 for (n = sched_first(block); !sched_is_end(n); n = next) {
2112 ir_op *op = get_irn_op(n);
2115 * get the next node to be simulated here.
2116 * n might be completely removed from the schedule-
2118 next = sched_next(n);
2119 if (op->ops.generic != NULL) {
2120 func = (sim_func)op->ops.generic;
2123 node_inserted = (*func)(state, n);
2126 * sim_func might have added an additional node after n,
2127 * so update next node
2128 * beware: n must not be changed by sim_func
2129 * (i.e. removed from schedule) in this case
2131 if (node_inserted != NO_NODE_ADDED)
2132 next = sched_next(n);
2136 start_block = get_irg_start_block(get_irn_irg(block));
2138 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
2140 /* check if the state must be shuffled */
2141 foreach_block_succ(block, edge) {
2142 ir_node *succ = get_edge_src_irn(edge);
2143 blk_state *succ_state;
2145 if (succ == start_block)
2148 succ_state = x87_get_bl_state(sim, succ);
2150 if (succ_state->begin == NULL) {
2151 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2152 DEBUG_ONLY(x87_dump_stack(state);)
2153 succ_state->begin = state;
2155 waitq_put(sim->worklist, succ);
2157 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2158 /* There is already a begin state for the successor, bad.
2159 Do the necessary permutations.
2160 Note that critical edges are removed, so this is always possible:
2161 If the successor has more than one possible input, then it must
2164 x87_shuffle(sim, block, state, succ, succ_state->begin);
2167 bl_state->end = state;
2171 * Register a simulator function.
2173 * @param op the opcode to simulate
2174 * @param func the simulator function for the opcode
2176 static void register_sim(ir_op *op, sim_func func)
2178 assert(op->ops.generic == NULL);
2179 op->ops.generic = (op_func) func;
2183 * Create a new x87 simulator.
2185 * @param sim a simulator handle, will be initialized
2186 * @param irg the current graph
2188 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
2190 obstack_init(&sim->obst);
2191 sim->blk_states = pmap_create();
2192 sim->n_idx = get_irg_last_idx(irg);
2193 sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
2195 DB((dbg, LEVEL_1, "--------------------------------\n"
2196 "x87 Simulator started for %+F\n", irg));
2198 /* set the generic function pointer of instruction we must simulate */
2199 ir_clear_opcodes_generic_func();
2201 register_sim(op_ia32_Call, sim_Call);
2202 register_sim(op_ia32_vfld, sim_fld);
2203 register_sim(op_ia32_vfild, sim_fild);
2204 register_sim(op_ia32_vfld1, sim_fld1);
2205 register_sim(op_ia32_vfldz, sim_fldz);
2206 register_sim(op_ia32_vfadd, sim_fadd);
2207 register_sim(op_ia32_vfsub, sim_fsub);
2208 register_sim(op_ia32_vfmul, sim_fmul);
2209 register_sim(op_ia32_vfdiv, sim_fdiv);
2210 register_sim(op_ia32_vfprem, sim_fprem);
2211 register_sim(op_ia32_vfabs, sim_fabs);
2212 register_sim(op_ia32_vfchs, sim_fchs);
2213 register_sim(op_ia32_vfist, sim_fist);
2214 register_sim(op_ia32_vfisttp, sim_fisttp);
2215 register_sim(op_ia32_vfst, sim_fst);
2216 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2217 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2218 register_sim(op_ia32_vFucomi, sim_Fucom);
2219 register_sim(op_be_Copy, sim_Copy);
2220 register_sim(op_be_Return, sim_Return);
2221 register_sim(op_be_Perm, sim_Perm);
2222 register_sim(op_be_Keep, sim_Keep);
2226 * Destroy a x87 simulator.
2228 * @param sim the simulator handle
2230 static void x87_destroy_simulator(x87_simulator *sim)
2232 pmap_destroy(sim->blk_states);
2233 obstack_free(&sim->obst, NULL);
2234 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2238 * Pre-block walker: calculate the liveness information for the block
2239 * and store it into the sim->live cache.
2241 static void update_liveness_walker(ir_node *block, void *data)
2243 x87_simulator *sim = (x87_simulator*)data;
2244 update_liveness(sim, block);
2248 * Run a simulation and fix all virtual instructions for a graph.
2249 * Replaces all virtual floating point instructions and registers
2252 void ia32_x87_simulate_graph(ir_graph *irg)
2254 /* TODO improve code quality (less executed fxch) by using execfreqs */
2256 ir_node *block, *start_block;
2257 blk_state *bl_state;
2260 /* create the simulator */
2261 x87_init_simulator(&sim, irg);
2263 start_block = get_irg_start_block(irg);
2264 bl_state = x87_get_bl_state(&sim, start_block);
2266 /* start with the empty state */
2267 bl_state->begin = empty;
2270 sim.worklist = new_waitq();
2271 waitq_put(sim.worklist, start_block);
2273 be_assure_live_sets(irg);
2274 sim.lv = be_get_irg_liveness(irg);
2276 /* Calculate the liveness for all nodes. We must precalculate this info,
2277 * because the simulator adds new nodes (possible before Phi nodes) which
2278 * would let a lazy calculation fail.
2279 * On the other hand we reduce the computation amount due to
2280 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2282 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2286 block = (ir_node*)waitq_get(sim.worklist);
2287 x87_simulate_block(&sim, block);
2288 } while (! waitq_empty(sim.worklist));
2291 del_waitq(sim.worklist);
2292 x87_destroy_simulator(&sim);
2295 /* Initializes the x87 simulator. */
2296 void ia32_init_x87(void)
2298 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");