2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the x87 support and virtual to stack
23 * register translation for the ia32 backend.
24 * @author Michael Beck
36 #include "iredges_t.h"
47 #include "../belive_t.h"
48 #include "../besched_t.h"
49 #include "../benode_t.h"
50 #include "bearch_ia32_t.h"
51 #include "ia32_new_nodes.h"
52 #include "gen_ia32_new_nodes.h"
53 #include "gen_ia32_regalloc_if.h"
55 #include "ia32_architecture.h"
62 #define MASK_TOS(x) ((x) & (N_x87_REGS - 1))
64 /** the debug handle */
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 /* Forward declaration. */
68 typedef struct _x87_simulator x87_simulator;
71 * An exchange template.
72 * Note that our virtual functions have the same inputs
73 * and attributes as the real ones, so we can simple exchange
75 * Further, x87 supports inverse instructions, so we can handle them.
77 typedef struct _exchange_tmpl {
78 ir_op *normal_op; /**< the normal one */
79 ir_op *reverse_op; /**< the reverse one if exists */
80 ir_op *normal_pop_op; /**< the normal one with tos pop */
81 ir_op *reverse_pop_op; /**< the reverse one with tos pop */
85 * An entry on the simulated x87 stack.
87 typedef struct _st_entry {
88 int reg_idx; /**< the virtual register index of this stack value */
89 ir_node *node; /**< the node that produced this value */
95 typedef struct _x87_state {
96 st_entry st[N_x87_REGS]; /**< the register stack */
97 int depth; /**< the current stack depth */
98 int tos; /**< position of the tos */
99 x87_simulator *sim; /**< The simulator. */
102 /** An empty state, used for blocks without fp instructions. */
103 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
104 static x87_state *empty = (x87_state *)&_empty;
107 NO_NODE_ADDED = 0, /**< No node was added. */
108 NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */
112 * The type of an instruction simulator function.
114 * @param state the x87 state
115 * @param n the node to be simulated
117 * @return NODE_ADDED if a node was added AFTER n in schedule,
120 typedef int (*sim_func)(x87_state *state, ir_node *n);
123 * A block state: Every block has a x87 state at the beginning and at the end.
125 typedef struct _blk_state {
126 x87_state *begin; /**< state at the begin or NULL if not assigned */
127 x87_state *end; /**< state at the end or NULL if not assigned */
130 #define PTR_TO_BLKSTATE(p) ((blk_state *)(p))
132 /** liveness bitset for vfp registers. */
133 typedef unsigned char vfp_liveness;
138 struct _x87_simulator {
139 struct obstack obst; /**< An obstack for fast allocating. */
140 pmap *blk_states; /**< Map blocks to states. */
141 const arch_env_t *arch_env; /**< The architecture environment. */
142 be_lv_t *lv; /**< intrablock liveness. */
143 vfp_liveness *live; /**< Liveness information. */
144 unsigned n_idx; /**< The cached get_irg_last_idx() result. */
145 waitq *worklist; /**< Worklist of blocks that must be processed. */
146 ia32_isa_t *isa; /**< the ISA object */
150 * Returns the current stack depth.
152 * @param state the x87 state
154 * @return the x87 stack depth
156 static int x87_get_depth(const x87_state *state) {
158 } /* x87_get_depth */
161 * Return the virtual register index at st(pos).
163 * @param state the x87 state
164 * @param pos a stack position
166 * @return the vfp register index that produced the value at st(pos)
168 static int x87_get_st_reg(const x87_state *state, int pos) {
169 assert(pos < state->depth);
170 return state->st[MASK_TOS(state->tos + pos)].reg_idx;
171 } /* x87_get_st_reg */
175 * Return the node at st(pos).
177 * @param state the x87 state
178 * @param pos a stack position
180 * @return the IR node that produced the value at st(pos)
182 static ir_node *x87_get_st_node(const x87_state *state, int pos) {
183 assert(pos < state->depth);
184 return state->st[MASK_TOS(state->tos + pos)].node;
185 } /* x87_get_st_node */
188 * Dump the stack for debugging.
190 * @param state the x87 state
192 static void x87_dump_stack(const x87_state *state) {
195 for (i = state->depth - 1; i >= 0; --i) {
196 DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
197 x87_get_st_node(state, i)));
199 DB((dbg, LEVEL_2, "<-- TOS\n"));
200 } /* x87_dump_stack */
201 #endif /* DEBUG_libfirm */
204 * Set a virtual register to st(pos).
206 * @param state the x87 state
207 * @param reg_idx the vfp register index that should be set
208 * @param node the IR node that produces the value of the vfp register
209 * @param pos the stack position where the new value should be entered
211 static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
212 assert(0 < state->depth);
213 state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
214 state->st[MASK_TOS(state->tos + pos)].node = node;
216 DB((dbg, LEVEL_2, "After SET_REG: "));
217 DEBUG_ONLY(x87_dump_stack(state));
221 * Set the tos virtual register.
223 * @param state the x87 state
224 * @param reg_idx the vfp register index that should be set
225 * @param node the IR node that produces the value of the vfp register
227 static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
228 x87_set_st(state, reg_idx, node, 0);
232 * Swap st(0) with st(pos).
234 * @param state the x87 state
235 * @param pos the stack position to change the tos with
237 static void x87_fxch(x87_state *state, int pos) {
239 assert(pos < state->depth);
241 entry = state->st[MASK_TOS(state->tos + pos)];
242 state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
243 state->st[MASK_TOS(state->tos)] = entry;
245 DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state));
249 * Convert a virtual register to the stack index.
251 * @param state the x87 state
252 * @param reg_idx the register vfp index
254 * @return the stack position where the register is stacked
255 * or -1 if the virtual register was not found
257 static int x87_on_stack(const x87_state *state, int reg_idx) {
258 int i, tos = state->tos;
260 for (i = 0; i < state->depth; ++i)
261 if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
267 * Push a virtual Register onto the stack, double pushed allowed.
269 * @param state the x87 state
270 * @param reg_idx the register vfp index
271 * @param node the node that produces the value of the vfp register
273 static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
274 assert(state->depth < N_x87_REGS && "stack overrun");
277 state->tos = MASK_TOS(state->tos - 1);
278 state->st[state->tos].reg_idx = reg_idx;
279 state->st[state->tos].node = node;
281 DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state));
285 * Push a virtual Register onto the stack, double pushes are NOT allowed.
287 * @param state the x87 state
288 * @param reg_idx the register vfp index
289 * @param node the node that produces the value of the vfp register
290 * @param dbl_push if != 0 double pushes are allowed
292 static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
293 assert(x87_on_stack(state, reg_idx) == -1 && "double push");
295 x87_push_dbl(state, reg_idx, node);
299 * Pop a virtual Register from the stack.
301 * @param state the x87 state
303 static void x87_pop(x87_state *state) {
304 assert(state->depth > 0 && "stack underrun");
307 state->tos = MASK_TOS(state->tos + 1);
309 DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state));
313 * Empty the fpu stack
315 * @param state the x87 state
317 static void x87_emms(x87_state *state) {
323 * Returns the block state of a block.
325 * @param sim the x87 simulator handle
326 * @param block the current block
328 * @return the block state
330 static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
331 pmap_entry *entry = pmap_find(sim->blk_states, block);
334 blk_state *bl_state = obstack_alloc(&sim->obst, sizeof(*bl_state));
335 bl_state->begin = NULL;
336 bl_state->end = NULL;
338 pmap_insert(sim->blk_states, block, bl_state);
342 return PTR_TO_BLKSTATE(entry->value);
343 } /* x87_get_bl_state */
346 * Creates a new x87 state.
348 * @param sim the x87 simulator handle
350 * @return a new x87 state
352 static x87_state *x87_alloc_state(x87_simulator *sim) {
353 x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
357 } /* x87_alloc_state */
362 * @param sim the x87 simulator handle
363 * @param src the x87 state that will be cloned
365 * @return a cloned copy of the src state
367 static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
368 x87_state *res = x87_alloc_state(sim);
370 memcpy(res, src, sizeof(*res));
372 } /* x87_clone_state */
375 * Patch a virtual instruction into a x87 one and return
376 * the node representing the result value.
378 * @param n the IR node to patch
379 * @param op the x87 opcode to patch in
381 static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
382 ir_mode *mode = get_irn_mode(n);
387 if (mode == mode_T) {
388 /* patch all Proj's */
389 const ir_edge_t *edge;
391 foreach_out_edge(n, edge) {
392 ir_node *proj = get_edge_src_irn(edge);
394 mode = get_irn_mode(proj);
395 if (mode_is_float(mode)) {
397 set_irn_mode(proj, mode_E);
401 } else if (mode_is_float(mode))
402 set_irn_mode(n, mode_E);
404 } /* x87_patch_insn */
407 * Returns the first Proj of a mode_T node having a given mode.
409 * @param n the mode_T node
410 * @param m the desired mode of the Proj
411 * @return The first Proj of mode @p m found or NULL.
413 static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
414 const ir_edge_t *edge;
416 assert(get_irn_mode(n) == mode_T && "Need mode_T node");
418 foreach_out_edge(n, edge) {
419 ir_node *proj = get_edge_src_irn(edge);
420 if (get_irn_mode(proj) == m)
425 } /* get_irn_Proj_for_mode */
428 * Wrap the arch_* function here so we can check for errors.
430 static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
431 const arch_register_t *res;
433 res = arch_get_irn_register(sim->arch_env, irn);
434 assert(res->reg_class->regs == ia32_vfp_regs);
436 } /* x87_get_irn_register */
438 /* -------------- x87 perm --------------- */
441 * Creates a fxch for shuffle.
443 * @param state the x87 state
444 * @param pos parameter for fxch
445 * @param block the block were fxch is inserted
447 * Creates a new fxch node and reroute the user of the old node
450 * @return the fxch node
452 static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
454 ia32_x87_attr_t *attr;
456 fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block);
457 attr = get_ia32_x87_attr(fxch);
458 attr->x87[0] = &ia32_st_regs[pos];
459 attr->x87[2] = &ia32_st_regs[0];
463 x87_fxch(state, pos);
465 } /* x87_fxch_shuffle */
468 * Calculate the necessary permutations to reach dst_state.
470 * These permutations are done with fxch instructions and placed
471 * at the end of the block.
473 * Note that critical edges are removed here, so we need only
474 * a shuffle if the current block has only one successor.
476 * @param sim the simulator handle
477 * @param block the current block
478 * @param state the current x87 stack state, might be modified
479 * @param dst_block the destination block
480 * @param dst_state destination state
484 static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
485 x87_state *state, ir_node *dst_block,
486 const x87_state *dst_state)
488 int i, n_cycles, k, ri;
489 unsigned cycles[4], all_mask;
490 char cycle_idx[4][8];
491 ir_node *fxch, *before, *after;
495 assert(state->depth == dst_state->depth);
497 /* Some mathematics here:
498 If we have a cycle of length n that includes the tos,
499 we need n-1 exchange operations.
500 We can always add the tos and restore it, so we need
501 n+1 exchange operations for a cycle not containing the tos.
502 So, the maximum of needed operations is for a cycle of 7
503 not including the tos == 8.
504 This is the same number of ops we would need for using stores,
505 so exchange is cheaper (we save the loads).
506 On the other hand, we might need an additional exchange
507 in the next block to bring one operand on top, so the
508 number of ops in the first case is identical.
509 Further, no more than 4 cycles can exists (4 x 2).
511 all_mask = (1 << (state->depth)) - 1;
513 for (n_cycles = 0; all_mask; ++n_cycles) {
514 int src_idx, dst_idx;
516 /* find the first free slot */
517 for (i = 0; i < state->depth; ++i) {
518 if (all_mask & (1 << i)) {
519 all_mask &= ~(1 << i);
521 /* check if there are differences here */
522 if (x87_get_st_reg(state, i) != x87_get_st_reg(dst_state, i))
528 /* no more cycles found */
533 cycles[n_cycles] = (1 << i);
534 cycle_idx[n_cycles][k++] = i;
535 for (src_idx = i; ; src_idx = dst_idx) {
536 dst_idx = x87_on_stack(dst_state, x87_get_st_reg(state, src_idx));
538 if ((all_mask & (1 << dst_idx)) == 0)
541 cycle_idx[n_cycles][k++] = dst_idx;
542 cycles[n_cycles] |= (1 << dst_idx);
543 all_mask &= ~(1 << dst_idx);
545 cycle_idx[n_cycles][k] = -1;
549 /* no permutation needed */
553 /* Hmm: permutation needed */
554 DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
555 DEBUG_ONLY(x87_dump_stack(state));
556 DB((dbg, LEVEL_2, " to\n"));
557 DEBUG_ONLY(x87_dump_stack(dst_state));
561 DB((dbg, LEVEL_2, "Need %d cycles\n", n_cycles));
562 for (ri = 0; ri < n_cycles; ++ri) {
563 DB((dbg, LEVEL_2, " Ring %d:\n ", ri));
564 for (k = 0; cycle_idx[ri][k] != -1; ++k)
565 DB((dbg, LEVEL_2, " st%d ->", cycle_idx[ri][k]));
566 DB((dbg, LEVEL_2, "\n"));
573 * Find the place node must be insert.
574 * We have only one successor block, so the last instruction should
577 before = sched_last(block);
578 assert(is_cfop(before));
580 /* now do the permutations */
581 for (ri = 0; ri < n_cycles; ++ri) {
582 if ((cycles[ri] & 1) == 0) {
583 /* this cycle does not include the tos */
584 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
586 sched_add_after(after, fxch);
588 sched_add_before(before, fxch);
591 for (k = 1; cycle_idx[ri][k] != -1; ++k) {
592 fxch = x87_fxch_shuffle(state, cycle_idx[ri][k], block);
594 sched_add_after(after, fxch);
596 sched_add_before(before, fxch);
599 if ((cycles[ri] & 1) == 0) {
600 /* this cycle does not include the tos */
601 fxch = x87_fxch_shuffle(state, cycle_idx[ri][0], block);
602 sched_add_after(after, fxch);
609 * Create a fxch node before another node.
611 * @param state the x87 state
612 * @param n the node after the fxch
613 * @param pos exchange st(pos) with st(0)
617 static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
620 ia32_x87_attr_t *attr;
621 ir_graph *irg = get_irn_irg(n);
622 ir_node *block = get_nodes_block(n);
624 x87_fxch(state, pos);
626 fxch = new_rd_ia32_fxch(NULL, irg, block);
627 attr = get_ia32_x87_attr(fxch);
628 attr->x87[0] = &ia32_st_regs[pos];
629 attr->x87[2] = &ia32_st_regs[0];
633 sched_add_before(n, fxch);
634 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
636 } /* x87_create_fxch */
639 * Create a fpush before node n.
641 * @param state the x87 state
642 * @param n the node after the fpush
643 * @param pos push st(pos) on stack
644 * @param op_idx replace input op_idx of n with the fpush result
646 static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
647 ir_node *fpush, *pred = get_irn_n(n, op_idx);
648 ia32_x87_attr_t *attr;
649 const arch_register_t *out = x87_get_irn_register(state->sim, pred);
651 x87_push_dbl(state, arch_register_get_index(out), pred);
653 fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n));
654 attr = get_ia32_x87_attr(fpush);
655 attr->x87[0] = &ia32_st_regs[pos];
656 attr->x87[2] = &ia32_st_regs[0];
659 sched_add_before(n, fpush);
661 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
662 } /* x87_create_fpush */
665 * Create a fpop before node n.
667 * @param state the x87 state
668 * @param n the node after the fpop
669 * @param num pop 1 or 2 values
671 * @return the fpop node
673 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
675 ir_node *fpop = NULL;
676 ia32_x87_attr_t *attr;
681 if (ia32_cg_config.use_ffreep)
682 fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n));
684 fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n));
685 attr = get_ia32_x87_attr(fpop);
686 attr->x87[0] = &ia32_st_regs[0];
687 attr->x87[1] = &ia32_st_regs[0];
688 attr->x87[2] = &ia32_st_regs[0];
691 sched_add_before(n, fpop);
692 DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
697 } /* x87_create_fpop */
700 * Creates an fldz before node n
702 * @param state the x87 state
703 * @param n the node after the fldz
705 * @return the fldz node
707 static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
708 ir_graph *irg = get_irn_irg(n);
709 ir_node *block = get_nodes_block(n);
712 fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
714 sched_add_before(n, fldz);
715 DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
718 x87_push(state, regidx, fldz);
723 /* --------------------------------- liveness ------------------------------------------ */
726 * The liveness transfer function.
727 * Updates a live set over a single step from a given node to its predecessor.
728 * Everything defined at the node is removed from the set, the uses of the node get inserted.
730 * @param sim The simulator handle.
731 * @param irn The node at which liveness should be computed.
732 * @param live The bitset of registers live before @p irn. This set gets modified by updating it to
733 * the registers live after irn.
735 * @return The live bitset.
737 static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live)
740 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
741 const arch_env_t *arch_env = sim->arch_env;
743 if (get_irn_mode(irn) == mode_T) {
744 const ir_edge_t *edge;
746 foreach_out_edge(irn, edge) {
747 ir_node *proj = get_edge_src_irn(edge);
749 if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
750 const arch_register_t *reg = x87_get_irn_register(sim, proj);
751 live &= ~(1 << arch_register_get_index(reg));
756 if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
757 const arch_register_t *reg = x87_get_irn_register(sim, irn);
758 live &= ~(1 << arch_register_get_index(reg));
761 for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
762 ir_node *op = get_irn_n(irn, i);
764 if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
765 const arch_register_t *reg = x87_get_irn_register(sim, op);
766 live |= 1 << arch_register_get_index(reg);
770 } /* vfp_liveness_transfer */
773 * Put all live virtual registers at the end of a block into a bitset.
775 * @param sim the simulator handle
776 * @param lv the liveness information
777 * @param bl the block
779 * @return The live bitset at the end of this block
781 static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
784 vfp_liveness live = 0;
785 const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
786 const arch_env_t *arch_env = sim->arch_env;
787 const be_lv_t *lv = sim->lv;
789 be_lv_foreach(lv, block, be_lv_state_end, i) {
790 const arch_register_t *reg;
791 const ir_node *node = be_lv_get_irn(lv, block, i);
792 if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node))
795 reg = x87_get_irn_register(sim, node);
796 live |= 1 << arch_register_get_index(reg);
800 } /* vfp_liveness_end_of_block */
802 /** get the register mask from an arch_register */
803 #define REGMASK(reg) (1 << (arch_register_get_index(reg)))
806 * Return a bitset of argument registers which are live at the end of a node.
808 * @param sim the simulator handle
809 * @param pos the node
810 * @param kill kill mask for the output registers
812 * @return The live bitset.
814 static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsigned kill)
816 unsigned idx = get_irn_idx(pos);
818 assert(idx < sim->n_idx);
819 return sim->live[idx] & ~kill;
820 } /* vfp_live_args_after */
823 * Calculate the liveness for a whole block and cache it.
825 * @param sim the simulator handle
826 * @param lv the liveness handle
827 * @param block the block
829 static void update_liveness(x87_simulator *sim, ir_node *block) {
830 vfp_liveness live = vfp_liveness_end_of_block(sim, block);
834 /* now iterate through the block backward and cache the results */
835 sched_foreach_reverse(block, irn) {
836 /* stop at the first Phi: this produces the live-in */
840 idx = get_irn_idx(irn);
841 sim->live[idx] = live;
843 live = vfp_liveness_transfer(sim, irn, live);
845 idx = get_irn_idx(block);
846 sim->live[idx] = live;
847 } /* update_liveness */
850 * Returns true if a register is live in a set.
852 * @param reg_idx the vfp register index
853 * @param live a live bitset
855 #define is_vfp_live(reg_idx, live) ((live) & (1 << (reg_idx)))
859 * Dump liveness info.
861 * @param live the live bitset
863 static void vfp_dump_live(vfp_liveness live) {
866 DB((dbg, LEVEL_2, "Live after: "));
867 for (i = 0; i < 8; ++i) {
868 if (live & (1 << i)) {
869 DB((dbg, LEVEL_2, "vf%d ", i));
872 DB((dbg, LEVEL_2, "\n"));
873 } /* vfp_dump_live */
874 #endif /* DEBUG_libfirm */
876 /* --------------------------------- simulators ---------------------------------------- */
878 #define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0)
890 * Simulate a virtual binop.
892 * @param state the x87 state
893 * @param n the node that should be simulated (and patched)
894 * @param tmpl the template containing the 4 possible x87 opcodes
896 * @return NO_NODE_ADDED
898 static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
899 int op2_idx = 0, op1_idx;
900 int out_idx, do_pop = 0;
901 ia32_x87_attr_t *attr;
902 ir_node *patched_insn;
904 x87_simulator *sim = state->sim;
905 ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
906 ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
907 const arch_register_t *op1_reg = x87_get_irn_register(sim, op1);
908 const arch_register_t *op2_reg = x87_get_irn_register(sim, op2);
909 const arch_register_t *out = x87_get_irn_register(sim, n);
910 int reg_index_1 = arch_register_get_index(op1_reg);
911 int reg_index_2 = arch_register_get_index(op2_reg);
912 vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
916 DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
917 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
918 arch_register_get_name(out)));
919 DEBUG_ONLY(vfp_dump_live(live));
920 DB((dbg, LEVEL_1, "Stack before: "));
921 DEBUG_ONLY(x87_dump_stack(state));
923 if(reg_index_1 == REG_VFP_UKNWN) {
927 op1_idx = x87_on_stack(state, reg_index_1);
928 assert(op1_idx >= 0);
929 op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live);
932 if (reg_index_2 != REG_VFP_NOREG) {
933 if(reg_index_2 == REG_VFP_UKNWN) {
937 /* second operand is a vfp register */
938 op2_idx = x87_on_stack(state, reg_index_2);
939 assert(op2_idx >= 0);
941 = is_vfp_live(arch_register_get_index(op2_reg), live);
944 if (op2_live_after) {
945 /* Second operand is live. */
947 if (op1_live_after) {
948 /* Both operands are live: push the first one.
949 This works even for op1 == op2. */
950 x87_create_fpush(state, n, op1_idx, n_ia32_binary_right);
951 /* now do fxxx (tos=tos X op) */
955 dst = tmpl->normal_op;
957 /* Second live, first operand is dead here, bring it to tos. */
959 x87_create_fxch(state, n, op1_idx);
964 /* now do fxxx (tos=tos X op) */
966 dst = tmpl->normal_op;
969 /* Second operand is dead. */
970 if (op1_live_after) {
971 /* First operand is live: bring second to tos. */
973 x87_create_fxch(state, n, op2_idx);
978 /* now do fxxxr (tos = op X tos) */
980 dst = tmpl->reverse_op;
982 /* Both operands are dead here, pop them from the stack. */
985 /* Both are identically and on tos, no pop needed. */
986 /* here fxxx (tos = tos X tos) */
987 dst = tmpl->normal_op;
990 /* now do fxxxp (op = op X tos, pop) */
991 dst = tmpl->normal_pop_op;
995 } else if (op1_idx == 0) {
996 assert(op1_idx != op2_idx);
997 /* now do fxxxrp (op = tos X op, pop) */
998 dst = tmpl->reverse_pop_op;
1002 /* Bring the second on top. */
1003 x87_create_fxch(state, n, op2_idx);
1004 if (op1_idx == op2_idx) {
1005 /* Both are identically and on tos now, no pop needed. */
1008 /* use fxxx (tos = tos X tos) */
1009 dst = tmpl->normal_op;
1012 /* op2 is on tos now */
1014 /* use fxxxp (op = op X tos, pop) */
1015 dst = tmpl->normal_pop_op;
1023 /* second operand is an address mode */
1024 if (op1_live_after) {
1025 /* first operand is live: push it here */
1026 x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
1028 /* use fxxx (tos = tos X mem) */
1029 dst = tmpl->normal_op;
1032 /* first operand is dead: bring it to tos */
1034 x87_create_fxch(state, n, op1_idx);
1038 /* use fxxxp (tos = tos X mem) */
1039 dst = tmpl->normal_op;
1044 patched_insn = x87_patch_insn(n, dst);
1045 x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx);
1050 /* patch the operation */
1051 attr = get_ia32_x87_attr(n);
1052 attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
1053 if (reg_index_2 != REG_VFP_NOREG) {
1054 attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
1056 attr->x87[2] = out = &ia32_st_regs[out_idx];
1058 if (reg_index_2 != REG_VFP_NOREG) {
1059 DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
1060 arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
1061 arch_register_get_name(out)));
1063 DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
1064 arch_register_get_name(op1_reg),
1065 arch_register_get_name(out)));
1068 return NO_NODE_ADDED;
1072 * Simulate a virtual Unop.
1074 * @param state the x87 state
1075 * @param n the node that should be simulated (and patched)
1076 * @param op the x87 opcode that will replace n's opcode
1078 * @return NO_NODE_ADDED
1080 static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
1081 int op1_idx, out_idx;
1082 x87_simulator *sim = state->sim;
1083 const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
1084 const arch_register_t *out = x87_get_irn_register(sim, n);
1085 ia32_x87_attr_t *attr;
1086 unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
1088 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
1089 DEBUG_ONLY(vfp_dump_live(live));
1091 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1093 if (is_vfp_live(arch_register_get_index(op1), live)) {
1094 /* push the operand here */
1095 x87_create_fpush(state, n, op1_idx, UNOP_IDX);
1099 /* operand is dead, bring it to tos */
1101 x87_create_fxch(state, n, op1_idx);
1106 x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
1108 attr = get_ia32_x87_attr(n);
1109 attr->x87[0] = op1 = &ia32_st_regs[0];
1110 attr->x87[2] = out = &ia32_st_regs[0];
1111 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
1113 return NO_NODE_ADDED;
1117 * Simulate a virtual Load instruction.
1119 * @param state the x87 state
1120 * @param n the node that should be simulated (and patched)
1121 * @param op the x87 opcode that will replace n's opcode
1123 * @return NO_NODE_ADDED
1125 static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
1126 const arch_register_t *out = x87_get_irn_register(state->sim, n);
1127 ia32_x87_attr_t *attr;
1129 DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
1130 x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
1131 assert(out == x87_get_irn_register(state->sim, n));
1132 attr = get_ia32_x87_attr(n);
1133 attr->x87[2] = out = &ia32_st_regs[0];
1134 DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
1136 return NO_NODE_ADDED;
1140 * Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
1142 * @param store The store
1143 * @param old_val The former value
1144 * @param new_val The new value
1146 static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) {
1147 const ir_edge_t *edge, *ne;
1149 foreach_out_edge_safe(old_val, edge, ne) {
1150 ir_node *user = get_edge_src_irn(edge);
1152 if (! user || user == store)
1155 /* if the user is scheduled after the store: rewire */
1156 if (sched_is_scheduled(user) && sched_comes_after(store, user)) {
1158 /* find the input of the user pointing to the old value */
1159 for (i = get_irn_arity(user) - 1; i >= 0; i--) {
1160 if (get_irn_n(user, i) == old_val)
1161 set_irn_n(user, i, new_val);
1165 } /* collect_and_rewire_users */
1168 * Simulate a virtual Store.
1170 * @param state the x87 state
1171 * @param n the node that should be simulated (and patched)
1172 * @param op the x87 store opcode
1173 * @param op_p the x87 store and pop opcode
1175 static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
1176 x87_simulator *sim = state->sim;
1177 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1178 const arch_register_t *op2 = x87_get_irn_register(sim, val);
1179 unsigned live = vfp_live_args_after(sim, n, 0);
1180 int insn = NO_NODE_ADDED;
1181 ia32_x87_attr_t *attr;
1182 int op2_reg_idx, op2_idx, depth;
1183 int live_after_node;
1186 op2_reg_idx = arch_register_get_index(op2);
1187 if (op2_reg_idx == REG_VFP_UKNWN) {
1188 /* just take any value from stack */
1189 if(state->depth > 0) {
1191 DEBUG_ONLY(op2 = NULL);
1192 live_after_node = 1;
1194 /* produce a new value which we will consume immediately */
1195 x87_create_fldz(state, n, op2_reg_idx);
1196 live_after_node = 0;
1197 op2_idx = x87_on_stack(state, op2_reg_idx);
1198 assert(op2_idx >= 0);
1201 op2_idx = x87_on_stack(state, op2_reg_idx);
1202 live_after_node = is_vfp_live(arch_register_get_index(op2), live);
1203 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1204 assert(op2_idx >= 0);
1207 mode = get_ia32_ls_mode(n);
1208 depth = x87_get_depth(state);
1210 if (live_after_node) {
1212 Problem: fst doesn't support mode_E (spills), only fstp does
1214 - stack not full: push value and fstp
1215 - stack full: fstp value and load again
1216 Note that we cannot test on mode_E, because floats might be 96bit ...
1218 if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) {
1219 if (depth < N_x87_REGS) {
1220 /* ok, we have a free register: push + fstp */
1221 x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
1223 x87_patch_insn(n, op_p);
1225 ir_node *vfld, *mem, *block, *rproj, *mproj;
1228 /* stack full here: need fstp + load */
1230 x87_patch_insn(n, op_p);
1232 block = get_nodes_block(n);
1233 irg = get_irn_irg(n);
1234 vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
1236 /* copy all attributes */
1237 set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
1238 if (is_ia32_use_frame(n))
1239 set_ia32_use_frame(vfld);
1240 set_ia32_op_type(vfld, ia32_am_Source);
1241 add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
1242 set_ia32_am_sc(vfld, get_ia32_am_sc(n));
1243 set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
1245 rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
1246 mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
1247 mem = get_irn_Proj_for_mode(n, mode_M);
1249 assert(mem && "Store memory not found");
1251 arch_set_irn_register(sim->arch_env, rproj, op2);
1253 /* reroute all former users of the store memory to the load memory */
1254 edges_reroute(mem, mproj, irg);
1255 /* set the memory input of the load to the store memory */
1256 set_irn_n(vfld, n_ia32_vfld_mem, mem);
1258 sched_add_after(n, vfld);
1259 sched_add_after(vfld, rproj);
1261 /* rewire all users, scheduled after the store, to the loaded value */
1262 collect_and_rewire_users(n, val, rproj);
1267 /* we can only store the tos to memory */
1269 x87_create_fxch(state, n, op2_idx);
1271 /* mode != mode_E -> use normal fst */
1272 x87_patch_insn(n, op);
1275 /* we can only store the tos to memory */
1277 x87_create_fxch(state, n, op2_idx);
1280 x87_patch_insn(n, op_p);
1283 attr = get_ia32_x87_attr(n);
1284 attr->x87[1] = op2 = &ia32_st_regs[0];
1285 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1290 #define _GEN_BINOP(op, rev) \
1291 static int sim_##op(x87_state *state, ir_node *n) { \
1292 exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
1293 return sim_binop(state, n, &tmpl); \
1296 #define GEN_BINOP(op) _GEN_BINOP(op, op)
1297 #define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
1299 #define GEN_LOAD2(op, nop) \
1300 static int sim_##op(x87_state *state, ir_node *n) { \
1301 return sim_load(state, n, op_ia32_##nop); \
1304 #define GEN_LOAD(op) GEN_LOAD2(op, op)
1306 #define GEN_UNOP(op) \
1307 static int sim_##op(x87_state *state, ir_node *n) { \
1308 return sim_unop(state, n, op_ia32_##op); \
1311 #define GEN_STORE(op) \
1312 static int sim_##op(x87_state *state, ir_node *n) { \
1313 return sim_store(state, n, op_ia32_##op, op_ia32_##op##p); \
1335 * Simulate a virtual fisttp.
1337 * @param state the x87 state
1338 * @param n the node that should be simulated (and patched)
1340 static int sim_fisttp(x87_state *state, ir_node *n) {
1341 x87_simulator *sim = state->sim;
1342 ir_node *val = get_irn_n(n, n_ia32_vfst_val);
1343 const arch_register_t *op2 = x87_get_irn_register(sim, val);
1344 unsigned live = vfp_live_args_after(sim, n, 0);
1345 int insn = NO_NODE_ADDED;
1346 ia32_x87_attr_t *attr;
1347 int op2_reg_idx, op2_idx, depth;
1349 op2_reg_idx = arch_register_get_index(op2);
1350 if (op2_reg_idx == REG_VFP_UKNWN) {
1351 /* just take any value from stack */
1352 if (state->depth > 0) {
1354 DEBUG_ONLY(op2 = NULL);
1356 /* produce a new value which we will consume immediately */
1357 x87_create_fldz(state, n, op2_reg_idx);
1358 op2_idx = x87_on_stack(state, op2_reg_idx);
1359 assert(op2_idx >= 0);
1362 op2_idx = x87_on_stack(state, op2_reg_idx);
1363 DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
1364 assert(op2_idx >= 0);
1367 depth = x87_get_depth(state);
1369 /* Note: although the value is still live here, it is destroyed because
1370 of the pop. The register allocator is aware of that and introduced a copy
1371 if the value must be alive. */
1373 /* we can only store the tos to memory */
1375 x87_create_fxch(state, n, op2_idx);
1378 x87_patch_insn(n, op_ia32_fisttp);
1380 attr = get_ia32_x87_attr(n);
1381 attr->x87[1] = op2 = &ia32_st_regs[0];
1382 DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
1387 static int sim_FtstFnstsw(x87_state *state, ir_node *n) {
1388 x87_simulator *sim = state->sim;
1389 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1390 ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
1391 const arch_register_t *reg1 = x87_get_irn_register(sim, op1_node);
1392 int reg_index_1 = arch_register_get_index(reg1);
1393 int op1_idx = x87_on_stack(state, reg_index_1);
1394 unsigned live = vfp_live_args_after(sim, n, 0);
1396 DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
1397 DEBUG_ONLY(vfp_dump_live(live));
1398 DB((dbg, LEVEL_1, "Stack before: "));
1399 DEBUG_ONLY(x87_dump_stack(state));
1400 assert(op1_idx >= 0);
1403 /* bring the value to tos */
1404 x87_create_fxch(state, n, op1_idx);
1408 /* patch the operation */
1409 x87_patch_insn(n, op_ia32_FtstFnstsw);
1410 reg1 = &ia32_st_regs[op1_idx];
1411 attr->x87[0] = reg1;
1412 attr->x87[1] = NULL;
1413 attr->x87[2] = NULL;
1415 if(!is_vfp_live(reg_index_1, live)) {
1416 x87_create_fpop(state, sched_next(n), 1);
1420 return NO_NODE_ADDED;
1424 * @param state the x87 state
1425 * @param n the node that should be simulated (and patched)
1427 static int sim_Fucom(x87_state *state, ir_node *n) {
1430 ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
1432 x87_simulator *sim = state->sim;
1433 ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
1434 ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
1435 const arch_register_t *op1 = x87_get_irn_register(sim, op1_node);
1436 const arch_register_t *op2 = x87_get_irn_register(sim, op2_node);
1437 int reg_index_1 = arch_register_get_index(op1);
1438 int reg_index_2 = arch_register_get_index(op2);
1439 unsigned live = vfp_live_args_after(sim, n, 0);
1440 int permuted = attr->attr.data.ins_permuted;
1443 int node_added = NO_NODE_ADDED;
1445 DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
1446 arch_register_get_name(op1), arch_register_get_name(op2)));
1447 DEBUG_ONLY(vfp_dump_live(live));
1448 DB((dbg, LEVEL_1, "Stack before: "));
1449 DEBUG_ONLY(x87_dump_stack(state));
1451 op1_idx = x87_on_stack(state, reg_index_1);
1452 assert(op1_idx >= 0);
1454 /* BEWARE: check for comp a,a cases, they might happen */
1455 if (reg_index_2 != REG_VFP_NOREG) {
1456 /* second operand is a vfp register */
1457 op2_idx = x87_on_stack(state, reg_index_2);
1458 assert(op2_idx >= 0);
1460 if (is_vfp_live(reg_index_2, live)) {
1461 /* second operand is live */
1463 if (is_vfp_live(reg_index_1, live)) {
1464 /* both operands are live */
1467 /* res = tos X op */
1468 } else if (op2_idx == 0) {
1469 /* res = op X tos */
1470 permuted = !permuted;
1473 /* bring the first one to tos */
1474 x87_create_fxch(state, n, op1_idx);
1478 /* res = tos X op */
1481 /* second live, first operand is dead here, bring it to tos.
1482 This means further, op1_idx != op2_idx. */
1483 assert(op1_idx != op2_idx);
1485 x87_create_fxch(state, n, op1_idx);
1490 /* res = tos X op, pop */
1494 /* second operand is dead */
1495 if (is_vfp_live(reg_index_1, live)) {
1496 /* first operand is live: bring second to tos.
1497 This means further, op1_idx != op2_idx. */
1498 assert(op1_idx != op2_idx);
1500 x87_create_fxch(state, n, op2_idx);
1505 /* res = op X tos, pop */
1507 permuted = !permuted;
1510 /* both operands are dead here, check first for identity. */
1511 if (op1_idx == op2_idx) {
1512 /* identically, one pop needed */
1514 x87_create_fxch(state, n, op1_idx);
1518 /* res = tos X op, pop */
1521 /* different, move them to st and st(1) and pop both.
1522 The tricky part is to get one into st(1).*/
1523 else if (op2_idx == 1) {
1524 /* good, second operand is already in the right place, move the first */
1526 /* bring the first on top */
1527 x87_create_fxch(state, n, op1_idx);
1528 assert(op2_idx != 0);
1531 /* res = tos X op, pop, pop */
1533 } else if (op1_idx == 1) {
1534 /* good, first operand is already in the right place, move the second */
1536 /* bring the first on top */
1537 x87_create_fxch(state, n, op2_idx);
1538 assert(op1_idx != 0);
1541 /* res = op X tos, pop, pop */
1542 permuted = !permuted;
1546 /* if one is already the TOS, we need two fxch */
1548 /* first one is TOS, move to st(1) */
1549 x87_create_fxch(state, n, 1);
1550 assert(op2_idx != 1);
1552 x87_create_fxch(state, n, op2_idx);
1554 /* res = op X tos, pop, pop */
1556 permuted = !permuted;
1558 } else if (op2_idx == 0) {
1559 /* second one is TOS, move to st(1) */
1560 x87_create_fxch(state, n, 1);
1561 assert(op1_idx != 1);
1563 x87_create_fxch(state, n, op1_idx);
1565 /* res = tos X op, pop, pop */
1568 /* none of them is either TOS or st(1), 3 fxch needed */
1569 x87_create_fxch(state, n, op2_idx);
1570 assert(op1_idx != 0);
1571 x87_create_fxch(state, n, 1);
1573 x87_create_fxch(state, n, op1_idx);
1575 /* res = tos X op, pop, pop */
1582 /* second operand is an address mode */
1583 if (is_vfp_live(reg_index_1, live)) {
1584 /* first operand is live: bring it to TOS */
1586 x87_create_fxch(state, n, op1_idx);
1590 /* first operand is dead: bring it to tos */
1592 x87_create_fxch(state, n, op1_idx);
1599 /* patch the operation */
1600 if (is_ia32_vFucomFnstsw(n)) {
1604 case 0: dst = op_ia32_FucomFnstsw; break;
1605 case 1: dst = op_ia32_FucompFnstsw; break;
1606 case 2: dst = op_ia32_FucomppFnstsw; break;
1607 default: panic("invalid popcount in sim_Fucom");
1610 for(i = 0; i < pops; ++i) {
1613 } else if(is_ia32_vFucomi(n)) {
1615 case 0: dst = op_ia32_Fucomi; break;
1616 case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
1618 dst = op_ia32_Fucompi;
1620 x87_create_fpop(state, sched_next(n), 1);
1621 node_added = NODE_ADDED;
1623 default: panic("invalid popcount in sim_Fucom");
1626 panic("invalid operation %+F in sim_FucomFnstsw", n);
1629 x87_patch_insn(n, dst);
1636 op1 = &ia32_st_regs[op1_idx];
1639 op2 = &ia32_st_regs[op2_idx];
1642 attr->x87[2] = NULL;
1643 attr->attr.data.ins_permuted = permuted;
1646 DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
1647 arch_register_get_name(op1), arch_register_get_name(op2)));
1649 DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
1650 arch_register_get_name(op1)));
1656 static int sim_Keep(x87_state *state, ir_node *node)
1659 const arch_register_t *op_reg;
1664 int node_added = NO_NODE_ADDED;
1666 DB((dbg, LEVEL_1, ">>> %+F\n", node));
1668 arity = get_irn_arity(node);
1669 for(i = 0; i < arity; ++i) {
1670 op = get_irn_n(node, i);
1671 op_reg = arch_get_irn_register(state->sim->arch_env, op);
1672 if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
1675 reg_id = arch_register_get_index(op_reg);
1676 live = vfp_live_args_after(state->sim, node, 0);
1678 op_stack_idx = x87_on_stack(state, reg_id);
1679 if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
1680 x87_create_fpop(state, sched_next(node), 1);
1681 node_added = NODE_ADDED;
1685 DB((dbg, LEVEL_1, "Stack after: "));
1686 DEBUG_ONLY(x87_dump_stack(state));
1692 void keep_float_node_alive(x87_state *state, ir_node *node)
1698 const arch_register_class_t *cls;
1700 irg = get_irn_irg(node);
1701 block = get_nodes_block(node);
1702 cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1);
1704 keep = be_new_Keep(cls, irg, block, 1, in);
1706 assert(sched_is_scheduled(node));
1707 sched_add_after(node, keep);
1711 * Create a copy of a node. Recreate the node if it's a constant.
1713 * @param state the x87 state
1714 * @param n the node to be copied
1716 * @return the copy of n
1718 static ir_node *create_Copy(x87_state *state, ir_node *n) {
1719 x87_simulator *sim = state->sim;
1720 ir_graph *irg = get_irn_irg(n);
1721 dbg_info *n_dbg = get_irn_dbg_info(n);
1722 ir_mode *mode = get_irn_mode(n);
1723 ir_node *block = get_nodes_block(n);
1724 ir_node *pred = get_irn_n(n, 0);
1725 ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
1727 const arch_register_t *out;
1728 const arch_register_t *op1;
1729 ia32_x87_attr_t *attr;
1731 /* Do not copy constants, recreate them. */
1732 switch (get_ia32_irn_opcode(pred)) {
1733 case iro_ia32_Unknown_VFP:
1735 cnstr = new_rd_ia32_fldz;
1738 cnstr = new_rd_ia32_fld1;
1740 case iro_ia32_fldpi:
1741 cnstr = new_rd_ia32_fldpi;
1743 case iro_ia32_fldl2e:
1744 cnstr = new_rd_ia32_fldl2e;
1746 case iro_ia32_fldl2t:
1747 cnstr = new_rd_ia32_fldl2t;
1749 case iro_ia32_fldlg2:
1750 cnstr = new_rd_ia32_fldlg2;
1752 case iro_ia32_fldln2:
1753 cnstr = new_rd_ia32_fldln2;
1759 out = x87_get_irn_register(sim, n);
1760 op1 = x87_get_irn_register(sim, pred);
1762 if (cnstr != NULL) {
1763 /* copy a constant */
1764 res = (*cnstr)(n_dbg, irg, block, mode);
1766 x87_push(state, arch_register_get_index(out), res);
1768 attr = get_ia32_x87_attr(res);
1769 attr->x87[2] = &ia32_st_regs[0];
1771 int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1773 res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
1775 x87_push(state, arch_register_get_index(out), res);
1777 attr = get_ia32_x87_attr(res);
1778 attr->x87[0] = &ia32_st_regs[op1_idx];
1779 attr->x87[2] = &ia32_st_regs[0];
1781 arch_set_irn_register(sim->arch_env, res, out);
1787 * Simulate a be_Copy.
1789 * @param state the x87 state
1790 * @param n the node that should be simulated (and patched)
1792 * @return NO_NODE_ADDED
1794 static int sim_Copy(x87_state *state, ir_node *n) {
1795 x87_simulator *sim = state->sim;
1797 const arch_register_t *out;
1798 const arch_register_t *op1;
1799 const arch_register_class_t *class;
1800 ir_node *node, *next;
1801 ia32_x87_attr_t *attr;
1802 int op1_idx, out_idx;
1805 class = arch_get_irn_reg_class(sim->arch_env, n, -1);
1806 if (class->regs != ia32_vfp_regs)
1809 pred = get_irn_n(n, 0);
1810 out = x87_get_irn_register(sim, n);
1811 op1 = x87_get_irn_register(sim, pred);
1812 live = vfp_live_args_after(sim, n, REGMASK(out));
1814 DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
1815 arch_register_get_name(op1), arch_register_get_name(out)));
1816 DEBUG_ONLY(vfp_dump_live(live));
1818 /* handle the infamous unknown value */
1819 if (arch_register_get_index(op1) == REG_VFP_UKNWN) {
1820 /* Operand is still live, a real copy. We need here an fpush that can
1821 hold a a register, so use the fpushCopy or recreate constants */
1822 node = create_Copy(state, n);
1824 assert(is_ia32_fldz(node));
1825 next = sched_next(n);
1828 sched_add_before(next, node);
1830 DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
1831 arch_get_irn_register(sim->arch_env, node)->name));
1832 return NO_NODE_ADDED;
1835 op1_idx = x87_on_stack(state, arch_register_get_index(op1));
1837 if (is_vfp_live(arch_register_get_index(op1), live)) {
1838 ir_node *pred = get_irn_n(n, 0);
1840 /* Operand is still live, a real copy. We need here an fpush that can
1841 hold a a register, so use the fpushCopy or recreate constants */
1842 node = create_Copy(state, n);
1844 /* We have to make sure the old value doesn't go dead (which can happen
1845 * when we recreate constants). As the simulator expected that value in
1846 * the pred blocks. This is unfortunate as removing it would save us 1
1847 * instruction, but we would have to rerun all the simulation to get
1850 next = sched_next(n);
1853 sched_add_before(next, node);
1855 if(get_irn_n_edges(pred) == 0) {
1856 keep_float_node_alive(state, pred);
1859 DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
1861 out_idx = x87_on_stack(state, arch_register_get_index(out));
1863 if (out_idx >= 0 && out_idx != op1_idx) {
1864 /* Matze: out already on stack? how can this happen? */
1867 /* op1 must be killed and placed where out is */
1869 /* best case, simple remove and rename */
1870 x87_patch_insn(n, op_ia32_Pop);
1871 attr = get_ia32_x87_attr(n);
1872 attr->x87[0] = op1 = &ia32_st_regs[0];
1875 x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
1877 /* move op1 to tos, store and pop it */
1879 x87_create_fxch(state, n, op1_idx);
1882 x87_patch_insn(n, op_ia32_Pop);
1883 attr = get_ia32_x87_attr(n);
1884 attr->x87[0] = op1 = &ia32_st_regs[out_idx];
1887 x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
1889 DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
1891 /* just a virtual copy */
1892 x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
1893 /* don't remove the node to keep the verifier quiet :),
1894 the emitter won't emit any code for the node */
1897 DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
1898 exchange(n, get_unop_op(n));
1902 return NO_NODE_ADDED;
1906 * Returns the result proj of the call
1908 static ir_node *get_call_result_proj(ir_node *call) {
1909 const ir_edge_t *edge;
1911 /* search the result proj */
1912 foreach_out_edge(call, edge) {
1913 ir_node *proj = get_edge_src_irn(edge);
1914 long pn = get_Proj_proj(proj);
1916 if (pn == pn_be_Call_first_res) {
1922 } /* get_call_result_proj */
1925 * Simulate a be_Call.
1927 * @param state the x87 state
1928 * @param n the node that should be simulated
1930 * @return NO_NODE_ADDED
1932 static int sim_Call(x87_state *state, ir_node *n)
1934 ir_type *call_tp = be_Call_get_type(n);
1938 const arch_register_t *reg;
1940 DB((dbg, LEVEL_1, ">>> %+F\n", n));
1942 /* at the begin of a call the x87 state should be empty */
1943 assert(state->depth == 0 && "stack not empty before call");
1945 if (get_method_n_ress(call_tp) <= 0)
1949 * If the called function returns a float, it is returned in st(0).
1950 * This even happens if the return value is NOT used.
1951 * Moreover, only one return result is supported.
1953 res_type = get_method_res_type(call_tp, 0);
1954 mode = get_type_mode(res_type);
1956 if (mode == NULL || !mode_is_float(mode))
1959 resproj = get_call_result_proj(n);
1960 assert(resproj != NULL);
1962 reg = x87_get_irn_register(state->sim, resproj);
1963 x87_push(state, arch_register_get_index(reg), resproj);
1966 DB((dbg, LEVEL_1, "Stack after: "));
1967 DEBUG_ONLY(x87_dump_stack(state));
1969 return NO_NODE_ADDED;
1973 * Simulate a be_Spill.
1975 * @param state the x87 state
1976 * @param n the node that should be simulated (and patched)
1978 * Should not happen, spills are lowered before x87 simulator see them.
1980 static int sim_Spill(x87_state *state, ir_node *n) {
1981 assert(0 && "Spill not lowered");
1982 return sim_fst(state, n);
1986 * Simulate a be_Reload.
1988 * @param state the x87 state
1989 * @param n the node that should be simulated (and patched)
1991 * Should not happen, reloads are lowered before x87 simulator see them.
1993 static int sim_Reload(x87_state *state, ir_node *n) {
1994 assert(0 && "Reload not lowered");
1995 return sim_fld(state, n);
1999 * Simulate a be_Return.
2001 * @param state the x87 state
2002 * @param n the node that should be simulated (and patched)
2004 * @return NO_NODE_ADDED
2006 static int sim_Return(x87_state *state, ir_node *n) {
2007 int n_res = be_Return_get_n_rets(n);
2008 int i, n_float_res = 0;
2010 /* only floating point return values must resist on stack */
2011 for (i = 0; i < n_res; ++i) {
2012 ir_node *res = get_irn_n(n, be_pos_Return_val + i);
2014 if (mode_is_float(get_irn_mode(res)))
2017 assert(x87_get_depth(state) == n_float_res);
2019 /* pop them virtually */
2020 for (i = n_float_res - 1; i >= 0; --i)
2023 return NO_NODE_ADDED;
2026 typedef struct _perm_data_t {
2027 const arch_register_t *in;
2028 const arch_register_t *out;
2032 * Simulate a be_Perm.
2034 * @param state the x87 state
2035 * @param irn the node that should be simulated (and patched)
2037 * @return NO_NODE_ADDED
2039 static int sim_Perm(x87_state *state, ir_node *irn) {
2041 x87_simulator *sim = state->sim;
2042 ir_node *pred = get_irn_n(irn, 0);
2044 const ir_edge_t *edge;
2046 /* handle only floating point Perms */
2047 if (! mode_is_float(get_irn_mode(pred)))
2048 return NO_NODE_ADDED;
2050 DB((dbg, LEVEL_1, ">>> %+F\n", irn));
2052 /* Perm is a pure virtual instruction on x87.
2053 All inputs must be on the FPU stack and are pairwise
2054 different from each other.
2055 So, all we need to do is to permutate the stack state. */
2056 n = get_irn_arity(irn);
2057 NEW_ARR_A(int, stack_pos, n);
2059 /* collect old stack positions */
2060 for (i = 0; i < n; ++i) {
2061 const arch_register_t *inreg = x87_get_irn_register(sim, get_irn_n(irn, i));
2062 int idx = x87_on_stack(state, arch_register_get_index(inreg));
2064 assert(idx >= 0 && "Perm argument not on x87 stack");
2068 /* now do the permutation */
2069 foreach_out_edge(irn, edge) {
2070 ir_node *proj = get_edge_src_irn(edge);
2071 const arch_register_t *out = x87_get_irn_register(sim, proj);
2072 long num = get_Proj_proj(proj);
2074 assert(0 <= num && num < n && "More Proj's than Perm inputs");
2075 x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
2077 DB((dbg, LEVEL_1, "<<< %+F\n", irn));
2079 return NO_NODE_ADDED;
2082 static int sim_Barrier(x87_state *state, ir_node *node) {
2083 //const arch_env_t *arch_env = state->sim->arch_env;
2086 /* materialize unknown if needed */
2087 arity = get_irn_arity(node);
2088 for(i = 0; i < arity; ++i) {
2089 const arch_register_t *reg;
2092 ia32_x87_attr_t *attr;
2093 ir_node *in = get_irn_n(node, i);
2095 if(!is_ia32_Unknown_VFP(in))
2098 /* TODO: not completely correct... */
2099 reg = &ia32_vfp_regs[REG_VFP_UKNWN];
2102 block = get_nodes_block(node);
2103 zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E);
2104 x87_push(state, arch_register_get_index(reg), zero);
2106 attr = get_ia32_x87_attr(zero);
2107 attr->x87[2] = &ia32_st_regs[0];
2109 sched_add_before(node, zero);
2111 set_irn_n(node, i, zero);
2114 return NO_NODE_ADDED;
2119 * Kill any dead registers at block start by popping them from the stack.
2121 * @param sim the simulator handle
2122 * @param block the current block
2123 * @param start_state the x87 state at the begin of the block
2125 * @return the x87 state after dead register killed
2127 static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
2128 x87_state *state = start_state;
2129 ir_node *first_insn = sched_first(block);
2130 ir_node *keep = NULL;
2131 unsigned live = vfp_live_args_after(sim, block, 0);
2133 int i, depth, num_pop;
2136 depth = x87_get_depth(state);
2137 for (i = depth - 1; i >= 0; --i) {
2138 int reg = x87_get_st_reg(state, i);
2140 if (! is_vfp_live(reg, live))
2141 kill_mask |= (1 << i);
2145 /* create a new state, will be changed */
2146 state = x87_clone_state(sim, state);
2148 DB((dbg, LEVEL_1, "Killing deads:\n"));
2149 DEBUG_ONLY(vfp_dump_live(live));
2150 DEBUG_ONLY(x87_dump_stack(state));
2152 if (kill_mask != 0 && live == 0) {
2153 /* special case: kill all registers */
2154 if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
2155 if (ia32_cg_config.use_femms) {
2156 /* use FEMMS on AMD processors to clear all */
2157 keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block);
2159 /* use EMMS to clear all */
2160 keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block);
2162 sched_add_before(first_insn, keep);
2168 /* now kill registers */
2170 /* we can only kill from TOS, so bring them up */
2171 if (! (kill_mask & 1)) {
2172 /* search from behind, because we can to a double-pop */
2173 for (i = depth - 1; i >= 0; --i) {
2174 if (kill_mask & (1 << i)) {
2175 kill_mask &= ~(1 << i);
2182 x87_set_st(state, -1, keep, i);
2183 x87_create_fxch(state, first_insn, i);
2186 if ((kill_mask & 3) == 3) {
2187 /* we can do a double-pop */
2191 /* only a single pop */
2196 kill_mask >>= num_pop;
2197 keep = x87_create_fpop(state, first_insn, num_pop);
2202 } /* x87_kill_deads */
2205 * If we have PhiEs with unknown operands then we have to make sure that some
2206 * value is actually put onto the stack.
2208 static void fix_unknown_phis(x87_state *state, ir_node *block,
2209 ir_node *pred_block, int pos)
2213 sched_foreach(block, node) {
2215 const arch_register_t *reg;
2216 ia32_x87_attr_t *attr;
2221 op = get_Phi_pred(node, pos);
2222 if(!is_ia32_Unknown_VFP(op))
2225 reg = arch_get_irn_register(state->sim->arch_env, node);
2227 /* create a zero at end of pred block */
2228 zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
2229 x87_push(state, arch_register_get_index(reg), zero);
2231 attr = get_ia32_x87_attr(zero);
2232 attr->x87[2] = &ia32_st_regs[0];
2234 assert(is_ia32_fldz(zero));
2235 sched_add_before(sched_last(pred_block), zero);
2237 set_Phi_pred(node, pos, zero);
2242 * Run a simulation and fix all virtual instructions for a block.
2244 * @param sim the simulator handle
2245 * @param block the current block
2247 static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
2249 blk_state *bl_state = x87_get_bl_state(sim, block);
2250 x87_state *state = bl_state->begin;
2251 const ir_edge_t *edge;
2252 ir_node *start_block;
2254 assert(state != NULL);
2255 /* already processed? */
2256 if (bl_state->end != NULL)
2259 DB((dbg, LEVEL_1, "Simulate %+F\n", block));
2260 DB((dbg, LEVEL_2, "State at Block begin:\n "));
2261 DEBUG_ONLY(x87_dump_stack(state));
2263 /* at block begin, kill all dead registers */
2264 state = x87_kill_deads(sim, block, state);
2265 /* create a new state, will be changed */
2266 state = x87_clone_state(sim, state);
2268 /* beware, n might change */
2269 for (n = sched_first(block); !sched_is_end(n); n = next) {
2272 ir_op *op = get_irn_op(n);
2274 next = sched_next(n);
2275 if (op->ops.generic == NULL)
2278 func = (sim_func)op->ops.generic;
2281 node_inserted = (*func)(state, n);
2284 sim_func might have added an additional node after n,
2286 beware: n must not be changed by sim_func
2287 (i.e. removed from schedule) in this case
2289 if (node_inserted != NO_NODE_ADDED)
2290 next = sched_next(n);
2293 start_block = get_irg_start_block(get_irn_irg(block));
2295 DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state));
2297 /* check if the state must be shuffled */
2298 foreach_block_succ(block, edge) {
2299 ir_node *succ = get_edge_src_irn(edge);
2300 blk_state *succ_state;
2302 if (succ == start_block)
2305 succ_state = x87_get_bl_state(sim, succ);
2307 fix_unknown_phis(state, succ, block, get_edge_src_pos(edge));
2309 if (succ_state->begin == NULL) {
2310 DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
2311 DEBUG_ONLY(x87_dump_stack(state));
2312 succ_state->begin = state;
2314 waitq_put(sim->worklist, succ);
2316 DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
2317 /* There is already a begin state for the successor, bad.
2318 Do the necessary permutations.
2319 Note that critical edges are removed, so this is always possible:
2320 If the successor has more than one possible input, then it must
2323 x87_shuffle(sim, block, state, succ, succ_state->begin);
2326 bl_state->end = state;
2327 } /* x87_simulate_block */
2329 static void register_sim(ir_op *op, sim_func func)
2331 assert(op->ops.generic == NULL);
2332 op->ops.generic = (op_func) func;
2336 * Create a new x87 simulator.
2338 * @param sim a simulator handle, will be initialized
2339 * @param irg the current graph
2340 * @param arch_env the architecture environment
2342 static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
2343 const arch_env_t *arch_env)
2345 obstack_init(&sim->obst);
2346 sim->blk_states = pmap_create();
2347 sim->arch_env = arch_env;
2348 sim->n_idx = get_irg_last_idx(irg);
2349 sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
2350 sim->isa = (ia32_isa_t *)arch_env->isa;
2352 DB((dbg, LEVEL_1, "--------------------------------\n"
2353 "x87 Simulator started for %+F\n", irg));
2355 /* set the generic function pointer of instruction we must simulate */
2356 clear_irp_opcodes_generic_func();
2358 register_sim(op_ia32_vfld, sim_fld);
2359 register_sim(op_ia32_vfild, sim_fild);
2360 register_sim(op_ia32_vfld1, sim_fld1);
2361 register_sim(op_ia32_vfldz, sim_fldz);
2362 register_sim(op_ia32_vfadd, sim_fadd);
2363 register_sim(op_ia32_vfsub, sim_fsub);
2364 register_sim(op_ia32_vfmul, sim_fmul);
2365 register_sim(op_ia32_vfdiv, sim_fdiv);
2366 register_sim(op_ia32_vfprem, sim_fprem);
2367 register_sim(op_ia32_vfabs, sim_fabs);
2368 register_sim(op_ia32_vfchs, sim_fchs);
2369 register_sim(op_ia32_vfist, sim_fist);
2370 register_sim(op_ia32_vfisttp, sim_fisttp);
2371 register_sim(op_ia32_vfst, sim_fst);
2372 register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
2373 register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
2374 register_sim(op_ia32_vFucomi, sim_Fucom);
2375 register_sim(op_be_Copy, sim_Copy);
2376 register_sim(op_be_Call, sim_Call);
2377 register_sim(op_be_Spill, sim_Spill);
2378 register_sim(op_be_Reload, sim_Reload);
2379 register_sim(op_be_Return, sim_Return);
2380 register_sim(op_be_Perm, sim_Perm);
2381 register_sim(op_be_Keep, sim_Keep);
2382 register_sim(op_be_Barrier, sim_Barrier);
2383 } /* x87_init_simulator */
2386 * Destroy a x87 simulator.
2388 * @param sim the simulator handle
2390 static void x87_destroy_simulator(x87_simulator *sim) {
2391 pmap_destroy(sim->blk_states);
2392 obstack_free(&sim->obst, NULL);
2393 DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
2394 } /* x87_destroy_simulator */
2397 * Pre-block walker: calculate the liveness information for the block
2398 * and store it into the sim->live cache.
2400 static void update_liveness_walker(ir_node *block, void *data) {
2401 x87_simulator *sim = data;
2402 update_liveness(sim, block);
2403 } /* update_liveness_walker */
2406 * Run a simulation and fix all virtual instructions for a graph.
2408 * @param env the architecture environment
2409 * @param irg the current graph
2411 * Needs a block-schedule.
2413 void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
2414 ir_node *block, *start_block;
2415 blk_state *bl_state;
2417 ir_graph *irg = be_get_birg_irg(birg);
2419 /* create the simulator */
2420 x87_init_simulator(&sim, irg, arch_env);
2422 start_block = get_irg_start_block(irg);
2423 bl_state = x87_get_bl_state(&sim, start_block);
2425 /* start with the empty state */
2426 bl_state->begin = empty;
2429 sim.worklist = new_waitq();
2430 waitq_put(sim.worklist, start_block);
2432 be_assure_liveness(birg);
2433 sim.lv = be_get_birg_liveness(birg);
2434 // sim.lv = be_liveness(be_get_birg_irg(birg));
2435 be_liveness_assure_sets(sim.lv);
2437 /* Calculate the liveness for all nodes. We must precalculate this info,
2438 * because the simulator adds new nodes (possible before Phi nodes) which
2439 * would let a lazy calculation fail.
2440 * On the other hand we reduce the computation amount due to
2441 * precaching from O(n^2) to O(n) at the expense of O(n) cache memory.
2443 irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim);
2447 block = waitq_get(sim.worklist);
2448 x87_simulate_block(&sim, block);
2449 } while (! waitq_empty(sim.worklist));
2452 del_waitq(sim.worklist);
2453 x87_destroy_simulator(&sim);
2454 } /* x87_simulate_graph */
2456 void ia32_init_x87(void) {
2457 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
2458 } /* ia32_init_x87 */