2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
56 #include "betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_common_transform.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_address_mode.h"
67 #include "ia32_architecture.h"
69 #include "gen_ia32_regalloc_if.h"
71 /* define this to construct SSE constants instead of load them */
72 #undef CONSTRUCT_SSE_CONST
75 #define SFP_SIGN "0x80000000"
76 #define DFP_SIGN "0x8000000000000000"
77 #define SFP_ABS "0x7FFFFFFF"
78 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
79 #define DFP_INTMAX "9223372036854775807"
80 #define ULL_BIAS "18446744073709551616"
82 #define ENT_SFP_SIGN "C_ia32_sfp_sign"
83 #define ENT_DFP_SIGN "C_ia32_dfp_sign"
84 #define ENT_SFP_ABS "C_ia32_sfp_abs"
85 #define ENT_DFP_ABS "C_ia32_dfp_abs"
86 #define ENT_ULL_BIAS "C_ia32_ull_bias"
88 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
89 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
91 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
93 static ir_node *old_initial_fpcw = NULL;
94 static ir_node *initial_fpcw = NULL;
95 int ia32_no_pic_adjust;
97 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
98 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
101 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
102 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
106 ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
109 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
111 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
112 ir_node *base, ir_node *index, ir_node *mem);
114 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
115 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
118 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
120 static ir_node *create_immediate_or_transform(ir_node *node,
121 char immediate_constraint_type);
123 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
124 dbg_info *dbgi, ir_node *block,
125 ir_node *op, ir_node *orig_node);
127 /* its enough to have those once */
128 static ir_node *nomem, *noreg_GP;
130 /** a list to postprocess all calls */
131 static ir_node **call_list;
132 static ir_type **call_types;
134 /** Return non-zero is a node represents the 0 constant. */
135 static bool is_Const_0(ir_node *node)
137 return is_Const(node) && is_Const_null(node);
140 /** Return non-zero is a node represents the 1 constant. */
141 static bool is_Const_1(ir_node *node)
143 return is_Const(node) && is_Const_one(node);
146 /** Return non-zero is a node represents the -1 constant. */
147 static bool is_Const_Minus_1(ir_node *node)
149 return is_Const(node) && is_Const_all_one(node);
153 * returns true if constant can be created with a simple float command
155 static bool is_simple_x87_Const(ir_node *node)
157 ir_tarval *tv = get_Const_tarval(node);
158 if (tarval_is_null(tv) || tarval_is_one(tv))
161 /* TODO: match all the other float constants */
166 * returns true if constant can be created with a simple float command
168 static bool is_simple_sse_Const(ir_node *node)
170 ir_tarval *tv = get_Const_tarval(node);
171 ir_mode *mode = get_tarval_mode(tv);
176 if (tarval_is_null(tv)
177 #ifdef CONSTRUCT_SSE_CONST
182 #ifdef CONSTRUCT_SSE_CONST
183 if (mode == mode_D) {
184 unsigned val = get_tarval_sub_bits(tv, 0) |
185 (get_tarval_sub_bits(tv, 1) << 8) |
186 (get_tarval_sub_bits(tv, 2) << 16) |
187 (get_tarval_sub_bits(tv, 3) << 24);
189 /* lower 32bit are zero, really a 32bit constant */
192 #endif /* CONSTRUCT_SSE_CONST */
193 /* TODO: match all the other float constants */
198 * return NoREG or pic_base in case of PIC.
199 * This is necessary as base address for newly created symbols
201 static ir_node *get_symconst_base(void)
203 ir_graph *irg = current_ir_graph;
205 if (be_get_irg_options(irg)->pic) {
206 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
207 return arch_env->impl->get_pic_base(irg);
214 * Transforms a Const.
216 static ir_node *gen_Const(ir_node *node)
218 ir_node *old_block = get_nodes_block(node);
219 ir_node *block = be_transform_node(old_block);
220 dbg_info *dbgi = get_irn_dbg_info(node);
221 ir_mode *mode = get_irn_mode(node);
223 assert(is_Const(node));
225 if (mode_is_float(mode)) {
230 if (ia32_cg_config.use_sse2) {
231 ir_tarval *tv = get_Const_tarval(node);
232 if (tarval_is_null(tv)) {
233 load = new_bd_ia32_xZero(dbgi, block);
234 set_ia32_ls_mode(load, mode);
236 #ifdef CONSTRUCT_SSE_CONST
237 } else if (tarval_is_one(tv)) {
238 int cnst = mode == mode_F ? 26 : 55;
239 ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
240 ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
241 ir_node *pslld, *psrld;
243 load = new_bd_ia32_xAllOnes(dbgi, block);
244 set_ia32_ls_mode(load, mode);
245 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
246 set_ia32_ls_mode(pslld, mode);
247 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
248 set_ia32_ls_mode(psrld, mode);
250 #endif /* CONSTRUCT_SSE_CONST */
251 } else if (mode == mode_F) {
252 /* we can place any 32bit constant by using a movd gp, sse */
253 unsigned val = get_tarval_sub_bits(tv, 0) |
254 (get_tarval_sub_bits(tv, 1) << 8) |
255 (get_tarval_sub_bits(tv, 2) << 16) |
256 (get_tarval_sub_bits(tv, 3) << 24);
257 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
258 load = new_bd_ia32_xMovd(dbgi, block, cnst);
259 set_ia32_ls_mode(load, mode);
263 #ifdef CONSTRUCT_SSE_CONST
264 if (mode == mode_D) {
265 unsigned val = get_tarval_sub_bits(tv, 0) |
266 (get_tarval_sub_bits(tv, 1) << 8) |
267 (get_tarval_sub_bits(tv, 2) << 16) |
268 (get_tarval_sub_bits(tv, 3) << 24);
270 ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
271 ir_node *cnst, *psllq;
273 /* fine, lower 32bit are zero, produce 32bit value */
274 val = get_tarval_sub_bits(tv, 4) |
275 (get_tarval_sub_bits(tv, 5) << 8) |
276 (get_tarval_sub_bits(tv, 6) << 16) |
277 (get_tarval_sub_bits(tv, 7) << 24);
278 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
279 load = new_bd_ia32_xMovd(dbgi, block, cnst);
280 set_ia32_ls_mode(load, mode);
281 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
282 set_ia32_ls_mode(psllq, mode);
287 #endif /* CONSTRUCT_SSE_CONST */
288 floatent = ia32_create_float_const_entity(node);
290 base = get_symconst_base();
291 load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
293 set_ia32_op_type(load, ia32_AddrModeS);
294 set_ia32_am_sc(load, floatent);
295 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
296 res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
299 if (is_Const_null(node)) {
300 load = new_bd_ia32_vfldz(dbgi, block);
302 set_ia32_ls_mode(load, mode);
303 } else if (is_Const_one(node)) {
304 load = new_bd_ia32_vfld1(dbgi, block);
306 set_ia32_ls_mode(load, mode);
311 floatent = ia32_create_float_const_entity(node);
312 /* create_float_const_ent is smart and sometimes creates
314 ls_mode = get_type_mode(get_entity_type(floatent));
315 base = get_symconst_base();
316 load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
318 set_ia32_op_type(load, ia32_AddrModeS);
319 set_ia32_am_sc(load, floatent);
320 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
321 res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
324 #ifdef CONSTRUCT_SSE_CONST
326 #endif /* CONSTRUCT_SSE_CONST */
327 SET_IA32_ORIG_NODE(load, node);
329 } else { /* non-float mode */
331 ir_tarval *tv = get_Const_tarval(node);
334 tv = tarval_convert_to(tv, mode_Iu);
336 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
338 panic("couldn't convert constant tarval (%+F)", node);
340 val = get_tarval_long(tv);
342 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
343 SET_IA32_ORIG_NODE(cnst, node);
350 * Transforms a SymConst.
352 static ir_node *gen_SymConst(ir_node *node)
354 ir_node *old_block = get_nodes_block(node);
355 ir_node *block = be_transform_node(old_block);
356 dbg_info *dbgi = get_irn_dbg_info(node);
357 ir_mode *mode = get_irn_mode(node);
360 if (mode_is_float(mode)) {
361 if (ia32_cg_config.use_sse2)
362 cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
364 cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
365 set_ia32_am_sc(cnst, get_SymConst_entity(node));
366 set_ia32_use_frame(cnst);
370 if (get_SymConst_kind(node) != symconst_addr_ent) {
371 panic("backend only support symconst_addr_ent (at %+F)", node);
373 entity = get_SymConst_entity(node);
374 if (get_entity_owner(entity) == get_tls_type()) {
375 ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
376 ir_node *lea = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP);
377 set_ia32_am_sc(lea, entity);
380 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
384 SET_IA32_ORIG_NODE(cnst, node);
390 * Create a float type for the given mode and cache it.
392 * @param mode the mode for the float type (might be integer mode for SSE2 types)
393 * @param align alignment
395 static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
401 if (mode == mode_Iu) {
402 static ir_type *int_Iu[16] = {NULL, };
404 if (int_Iu[align] == NULL) {
405 int_Iu[align] = tp = new_type_primitive(mode);
406 /* set the specified alignment */
407 set_type_alignment_bytes(tp, align);
409 return int_Iu[align];
410 } else if (mode == mode_Lu) {
411 static ir_type *int_Lu[16] = {NULL, };
413 if (int_Lu[align] == NULL) {
414 int_Lu[align] = tp = new_type_primitive(mode);
415 /* set the specified alignment */
416 set_type_alignment_bytes(tp, align);
418 return int_Lu[align];
419 } else if (mode == mode_F) {
420 static ir_type *float_F[16] = {NULL, };
422 if (float_F[align] == NULL) {
423 float_F[align] = tp = new_type_primitive(mode);
424 /* set the specified alignment */
425 set_type_alignment_bytes(tp, align);
427 return float_F[align];
428 } else if (mode == mode_D) {
429 static ir_type *float_D[16] = {NULL, };
431 if (float_D[align] == NULL) {
432 float_D[align] = tp = new_type_primitive(mode);
433 /* set the specified alignment */
434 set_type_alignment_bytes(tp, align);
436 return float_D[align];
438 static ir_type *float_E[16] = {NULL, };
440 if (float_E[align] == NULL) {
441 float_E[align] = tp = new_type_primitive(mode);
442 /* set the specified alignment */
443 set_type_alignment_bytes(tp, align);
445 return float_E[align];
450 * Create a float[2] array type for the given atomic type.
452 * @param tp the atomic type
454 static ir_type *ia32_create_float_array(ir_type *tp)
456 ir_mode *mode = get_type_mode(tp);
457 unsigned align = get_type_alignment_bytes(tp);
462 if (mode == mode_F) {
463 static ir_type *float_F[16] = {NULL, };
465 if (float_F[align] != NULL)
466 return float_F[align];
467 arr = float_F[align] = new_type_array(1, tp);
468 } else if (mode == mode_D) {
469 static ir_type *float_D[16] = {NULL, };
471 if (float_D[align] != NULL)
472 return float_D[align];
473 arr = float_D[align] = new_type_array(1, tp);
475 static ir_type *float_E[16] = {NULL, };
477 if (float_E[align] != NULL)
478 return float_E[align];
479 arr = float_E[align] = new_type_array(1, tp);
481 set_type_alignment_bytes(arr, align);
482 set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
483 set_type_state(arr, layout_fixed);
487 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
488 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
490 static const struct {
491 const char *ent_name;
492 const char *cnst_str;
495 } names [ia32_known_const_max] = {
496 { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
497 { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
498 { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
499 { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
500 { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
502 static ir_entity *ent_cache[ia32_known_const_max];
504 const char *ent_name, *cnst_str;
510 ent_name = names[kct].ent_name;
511 if (! ent_cache[kct]) {
512 cnst_str = names[kct].cnst_str;
514 switch (names[kct].mode) {
515 case 0: mode = mode_Iu; break;
516 case 1: mode = mode_Lu; break;
517 default: mode = mode_F; break;
519 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
520 tp = ia32_create_float_type(mode, names[kct].align);
522 if (kct == ia32_ULLBIAS)
523 tp = ia32_create_float_array(tp);
524 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
526 set_entity_ld_ident(ent, get_entity_ident(ent));
527 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
528 set_entity_visibility(ent, ir_visibility_private);
530 if (kct == ia32_ULLBIAS) {
531 ir_initializer_t *initializer = create_initializer_compound(2);
533 set_initializer_compound_value(initializer, 0,
534 create_initializer_tarval(get_mode_null(mode)));
535 set_initializer_compound_value(initializer, 1,
536 create_initializer_tarval(tv));
538 set_entity_initializer(ent, initializer);
540 set_entity_initializer(ent, create_initializer_tarval(tv));
543 /* cache the entry */
544 ent_cache[kct] = ent;
547 return ent_cache[kct];
551 * return true if the node is a Proj(Load) and could be used in source address
552 * mode for another node. Will return only true if the @p other node is not
553 * dependent on the memory of the Load (for binary operations use the other
554 * input here, for unary operations use NULL).
556 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
557 ir_node *other, ir_node *other2, match_flags_t flags)
562 /* float constants are always available */
563 if (is_Const(node)) {
564 ir_mode *mode = get_irn_mode(node);
565 if (mode_is_float(mode)) {
566 if (ia32_cg_config.use_sse2) {
567 if (is_simple_sse_Const(node))
570 if (is_simple_x87_Const(node))
573 if (get_irn_n_edges(node) > 1)
581 load = get_Proj_pred(node);
582 pn = get_Proj_proj(node);
583 if (!is_Load(load) || pn != pn_Load_res)
585 if (get_nodes_block(load) != block)
587 /* we only use address mode if we're the only user of the load */
588 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
590 /* in some edge cases with address mode we might reach the load normally
591 * and through some AM sequence, if it is already materialized then we
592 * can't create an AM node from it */
593 if (be_is_transformed(node))
596 /* don't do AM if other node inputs depend on the load (via mem-proj) */
597 if (other != NULL && ia32_prevents_AM(block, load, other))
600 if (other2 != NULL && ia32_prevents_AM(block, load, other2))
606 typedef struct ia32_address_mode_t ia32_address_mode_t;
607 struct ia32_address_mode_t {
612 ia32_op_type_t op_type;
616 unsigned commutative : 1;
617 unsigned ins_permuted : 1;
620 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
622 /* construct load address */
623 memset(addr, 0, sizeof(addr[0]));
624 ia32_create_address_mode(addr, ptr, ia32_create_am_normal);
626 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
627 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
628 addr->mem = be_transform_node(mem);
631 static void build_address(ia32_address_mode_t *am, ir_node *node,
632 ia32_create_am_flags_t flags)
634 ia32_address_t *addr = &am->addr;
640 /* floating point immediates */
641 if (is_Const(node)) {
642 ir_entity *entity = ia32_create_float_const_entity(node);
643 addr->base = get_symconst_base();
644 addr->index = noreg_GP;
646 addr->symconst_ent = entity;
647 addr->tls_segment = false;
649 am->ls_mode = get_type_mode(get_entity_type(entity));
650 am->pinned = op_pin_state_floats;
654 load = get_Proj_pred(node);
655 ptr = get_Load_ptr(load);
656 mem = get_Load_mem(load);
657 new_mem = be_transform_node(mem);
658 am->pinned = get_irn_pinned(load);
659 am->ls_mode = get_Load_mode(load);
660 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
663 /* construct load address */
664 ia32_create_address_mode(addr, ptr, flags);
666 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
667 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
671 static void set_address(ir_node *node, const ia32_address_t *addr)
673 set_ia32_am_scale(node, addr->scale);
674 set_ia32_am_sc(node, addr->symconst_ent);
675 set_ia32_am_offs_int(node, addr->offset);
676 set_ia32_am_tls_segment(node, addr->tls_segment);
677 if (addr->symconst_sign)
678 set_ia32_am_sc_sign(node);
680 set_ia32_use_frame(node);
681 set_ia32_frame_ent(node, addr->frame_entity);
685 * Apply attributes of a given address mode to a node.
687 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
689 set_address(node, &am->addr);
691 set_ia32_op_type(node, am->op_type);
692 set_ia32_ls_mode(node, am->ls_mode);
693 if (am->pinned == op_pin_state_pinned) {
694 /* beware: some nodes are already pinned and did not allow to change the state */
695 if (get_irn_pinned(node) != op_pin_state_pinned)
696 set_irn_pinned(node, op_pin_state_pinned);
699 set_ia32_commutative(node);
703 * Check, if a given node is a Down-Conv, ie. a integer Conv
704 * from a mode with a mode with more bits to a mode with lesser bits.
705 * Moreover, we return only true if the node has not more than 1 user.
707 * @param node the node
708 * @return non-zero if node is a Down-Conv
710 static int is_downconv(const ir_node *node)
718 /* we only want to skip the conv when we're the only user
719 * (because this test is used in the context of address-mode selection
720 * and we don't want to use address mode for multiple users) */
721 if (get_irn_n_edges(node) > 1)
724 src_mode = get_irn_mode(get_Conv_op(node));
725 dest_mode = get_irn_mode(node);
727 ia32_mode_needs_gp_reg(src_mode) &&
728 ia32_mode_needs_gp_reg(dest_mode) &&
729 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
732 /** Skip all Down-Conv's on a given node and return the resulting node. */
733 ir_node *ia32_skip_downconv(ir_node *node)
735 while (is_downconv(node))
736 node = get_Conv_op(node);
741 static bool is_sameconv(ir_node *node)
749 /* we only want to skip the conv when we're the only user
750 * (because this test is used in the context of address-mode selection
751 * and we don't want to use address mode for multiple users) */
752 if (get_irn_n_edges(node) > 1)
755 src_mode = get_irn_mode(get_Conv_op(node));
756 dest_mode = get_irn_mode(node);
758 ia32_mode_needs_gp_reg(src_mode) &&
759 ia32_mode_needs_gp_reg(dest_mode) &&
760 get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode);
763 /** Skip all signedness convs */
764 static ir_node *ia32_skip_sameconv(ir_node *node)
766 while (is_sameconv(node))
767 node = get_Conv_op(node);
772 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
774 ir_mode *mode = get_irn_mode(node);
779 if (mode_is_signed(mode)) {
784 block = get_nodes_block(node);
785 dbgi = get_irn_dbg_info(node);
787 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
791 * matches operands of a node into ia32 addressing/operand modes. This covers
792 * usage of source address mode, immediates, operations with non 32-bit modes,
794 * The resulting data is filled into the @p am struct. block is the block
795 * of the node whose arguments are matched. op1, op2 are the first and second
796 * input that are matched (op1 may be NULL). other_op is another unrelated
797 * input that is not matched! but which is needed sometimes to check if AM
798 * for op1/op2 is legal.
799 * @p flags describes the supported modes of the operation in detail.
801 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
802 ir_node *op1, ir_node *op2, ir_node *other_op,
805 ia32_address_t *addr = &am->addr;
806 ir_mode *mode = get_irn_mode(op2);
807 int mode_bits = get_mode_size_bits(mode);
808 ir_node *new_op1, *new_op2;
810 unsigned commutative;
811 int use_am_and_immediates;
814 memset(am, 0, sizeof(am[0]));
816 commutative = (flags & match_commutative) != 0;
817 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
818 use_am = (flags & match_am) != 0;
819 use_immediate = (flags & match_immediate) != 0;
820 assert(!use_am_and_immediates || use_immediate);
823 assert(!commutative || op1 != NULL);
824 assert(use_am || !(flags & match_8bit_am));
825 assert(use_am || !(flags & match_16bit_am));
827 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
828 (mode_bits == 16 && !(flags & match_16bit_am))) {
832 /* we can simply skip downconvs for mode neutral nodes: the upper bits
833 * can be random for these operations */
834 if (flags & match_mode_neutral) {
835 op2 = ia32_skip_downconv(op2);
837 op1 = ia32_skip_downconv(op1);
840 op2 = ia32_skip_sameconv(op2);
842 op1 = ia32_skip_sameconv(op1);
846 /* match immediates. firm nodes are normalized: constants are always on the
849 if (!(flags & match_try_am) && use_immediate) {
850 new_op2 = ia32_try_create_Immediate(op2, 0);
853 if (new_op2 == NULL &&
854 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
855 build_address(am, op2, ia32_create_am_normal);
856 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
857 if (mode_is_float(mode)) {
858 new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
862 am->op_type = ia32_AddrModeS;
863 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
865 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
867 build_address(am, op1, ia32_create_am_normal);
869 if (mode_is_float(mode)) {
870 noreg = ia32_new_NoReg_vfp(current_ir_graph);
875 if (new_op2 != NULL) {
878 new_op1 = be_transform_node(op2);
880 am->ins_permuted = true;
882 am->op_type = ia32_AddrModeS;
884 am->op_type = ia32_Normal;
886 if (flags & match_try_am) {
892 mode = get_irn_mode(op2);
893 if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
894 new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
896 new_op2 = create_upconv(op2, NULL);
897 am->ls_mode = mode_Iu;
899 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
901 new_op2 = be_transform_node(op2);
902 am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
905 if (addr->base == NULL)
906 addr->base = noreg_GP;
907 if (addr->index == NULL)
908 addr->index = noreg_GP;
909 if (addr->mem == NULL)
912 am->new_op1 = new_op1;
913 am->new_op2 = new_op2;
914 am->commutative = commutative;
918 * "Fixes" a node that uses address mode by turning it into mode_T
919 * and returning a pn_ia32_res Proj.
921 * @param node the node
922 * @param am its address mode
924 * @return a Proj(pn_ia32_res) if a memory address mode is used,
927 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
932 if (am->mem_proj == NULL)
935 /* we have to create a mode_T so the old MemProj can attach to us */
936 mode = get_irn_mode(node);
937 load = get_Proj_pred(am->mem_proj);
939 be_set_transformed_node(load, node);
941 if (mode != mode_T) {
942 set_irn_mode(node, mode_T);
943 return new_rd_Proj(NULL, node, mode, pn_ia32_res);
950 * Construct a standard binary operation, set AM and immediate if required.
952 * @param node The original node for which the binop is created
953 * @param op1 The first operand
954 * @param op2 The second operand
955 * @param func The node constructor function
956 * @return The constructed ia32 node.
958 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
959 construct_binop_func *func, match_flags_t flags)
962 ir_node *block, *new_block, *new_node;
963 ia32_address_mode_t am;
964 ia32_address_t *addr = &am.addr;
966 block = get_nodes_block(node);
967 match_arguments(&am, block, op1, op2, NULL, flags);
969 dbgi = get_irn_dbg_info(node);
970 new_block = be_transform_node(block);
971 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
972 am.new_op1, am.new_op2);
973 set_am_attributes(new_node, &am);
974 /* we can't use source address mode anymore when using immediates */
975 if (!(flags & match_am_and_immediates) &&
976 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
977 set_ia32_am_support(new_node, ia32_am_none);
978 SET_IA32_ORIG_NODE(new_node, node);
980 new_node = fix_mem_proj(new_node, &am);
986 * Generic names for the inputs of an ia32 binary op.
989 n_ia32_l_binop_left, /**< ia32 left input */
990 n_ia32_l_binop_right, /**< ia32 right input */
991 n_ia32_l_binop_eflags /**< ia32 eflags input */
993 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left)
994 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right)
995 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags)
996 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend)
997 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
998 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags)
1001 * Construct a binary operation which also consumes the eflags.
1003 * @param node The node to transform
1004 * @param func The node constructor function
1005 * @param flags The match flags
1006 * @return The constructor ia32 node
1008 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
1009 match_flags_t flags)
1011 ir_node *src_block = get_nodes_block(node);
1012 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
1013 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
1014 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
1016 ir_node *block, *new_node, *new_eflags;
1017 ia32_address_mode_t am;
1018 ia32_address_t *addr = &am.addr;
1020 match_arguments(&am, src_block, op1, op2, eflags, flags);
1022 dbgi = get_irn_dbg_info(node);
1023 block = be_transform_node(src_block);
1024 new_eflags = be_transform_node(eflags);
1025 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
1026 am.new_op1, am.new_op2, new_eflags);
1027 set_am_attributes(new_node, &am);
1028 /* we can't use source address mode anymore when using immediates */
1029 if (!(flags & match_am_and_immediates) &&
1030 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
1031 set_ia32_am_support(new_node, ia32_am_none);
1032 SET_IA32_ORIG_NODE(new_node, node);
1034 new_node = fix_mem_proj(new_node, &am);
1039 static ir_node *get_fpcw(void)
1041 if (initial_fpcw != NULL)
1042 return initial_fpcw;
1044 initial_fpcw = be_transform_node(old_initial_fpcw);
1045 return initial_fpcw;
1049 * Construct a standard binary operation, set AM and immediate if required.
1051 * @param op1 The first operand
1052 * @param op2 The second operand
1053 * @param func The node constructor function
1054 * @return The constructed ia32 node.
1056 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1057 construct_binop_float_func *func)
1059 ir_mode *mode = get_irn_mode(node);
1061 ir_node *block, *new_block, *new_node;
1062 ia32_address_mode_t am;
1063 ia32_address_t *addr = &am.addr;
1064 ia32_x87_attr_t *attr;
1065 /* All operations are considered commutative, because there are reverse
1067 match_flags_t flags = match_commutative;
1069 /* happens for div nodes... */
1070 if (mode == mode_T) {
1072 mode = get_Div_resmode(node);
1074 panic("can't determine mode");
1077 /* cannot use address mode with long double on x87 */
1078 if (get_mode_size_bits(mode) <= 64)
1081 block = get_nodes_block(node);
1082 match_arguments(&am, block, op1, op2, NULL, flags);
1084 dbgi = get_irn_dbg_info(node);
1085 new_block = be_transform_node(block);
1086 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
1087 am.new_op1, am.new_op2, get_fpcw());
1088 set_am_attributes(new_node, &am);
1090 attr = get_ia32_x87_attr(new_node);
1091 attr->attr.data.ins_permuted = am.ins_permuted;
1093 SET_IA32_ORIG_NODE(new_node, node);
1095 new_node = fix_mem_proj(new_node, &am);
1101 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1103 * @param op1 The first operand
1104 * @param op2 The second operand
1105 * @param func The node constructor function
1106 * @return The constructed ia32 node.
1108 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1109 construct_shift_func *func,
1110 match_flags_t flags)
1113 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
1114 ir_mode *mode = get_irn_mode(node);
1116 assert(! mode_is_float(mode));
1117 assert(flags & match_immediate);
1118 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
1120 if (get_mode_modulo_shift(mode) != 32)
1121 panic("modulo shift!=32 not supported by ia32 backend");
1123 if (flags & match_mode_neutral) {
1124 op1 = ia32_skip_downconv(op1);
1125 new_op1 = be_transform_node(op1);
1126 } else if (get_mode_size_bits(mode) != 32) {
1127 new_op1 = create_upconv(op1, node);
1129 new_op1 = be_transform_node(op1);
1132 /* the shift amount can be any mode that is bigger than 5 bits, since all
1133 * other bits are ignored anyway */
1134 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1135 ir_node *const op = get_Conv_op(op2);
1136 if (mode_is_float(get_irn_mode(op)))
1139 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1141 new_op2 = create_immediate_or_transform(op2, 0);
1143 dbgi = get_irn_dbg_info(node);
1144 block = get_nodes_block(node);
1145 new_block = be_transform_node(block);
1146 new_node = func(dbgi, new_block, new_op1, new_op2);
1147 SET_IA32_ORIG_NODE(new_node, node);
1149 /* lowered shift instruction may have a dependency operand, handle it here */
1150 if (get_irn_arity(node) == 3) {
1151 /* we have a dependency */
1152 ir_node* dep = get_irn_n(node, 2);
1153 if (get_irn_n_edges(dep) > 1) {
1154 /* ... which has at least one user other than 'node' */
1155 ir_node *new_dep = be_transform_node(dep);
1156 add_irn_dep(new_node, new_dep);
1165 * Construct a standard unary operation, set AM and immediate if required.
1167 * @param op The operand
1168 * @param func The node constructor function
1169 * @return The constructed ia32 node.
1171 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1172 match_flags_t flags)
1175 ir_node *block, *new_block, *new_op, *new_node;
1177 assert(flags == 0 || flags == match_mode_neutral);
1178 if (flags & match_mode_neutral) {
1179 op = ia32_skip_downconv(op);
1182 new_op = be_transform_node(op);
1183 dbgi = get_irn_dbg_info(node);
1184 block = get_nodes_block(node);
1185 new_block = be_transform_node(block);
1186 new_node = func(dbgi, new_block, new_op);
1188 SET_IA32_ORIG_NODE(new_node, node);
1193 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1194 ia32_address_t *addr)
1204 base = be_transform_node(base);
1211 idx = be_transform_node(idx);
1214 /* segment overrides are ineffective for Leas :-( so we have to patch
1216 if (addr->tls_segment) {
1217 ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
1218 assert(addr->symconst_ent != NULL);
1219 if (base == noreg_GP)
1222 base = new_bd_ia32_Lea(dbgi, block, tls_base, base);
1223 addr->tls_segment = false;
1226 res = new_bd_ia32_Lea(dbgi, block, base, idx);
1227 set_address(res, addr);
1233 * Returns non-zero if a given address mode has a symbolic or
1234 * numerical offset != 0.
1236 static int am_has_immediates(const ia32_address_t *addr)
1238 return addr->offset != 0 || addr->symconst_ent != NULL
1239 || addr->frame_entity || addr->use_frame;
1242 typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block,
1243 ir_node *high, ir_node *low,
1247 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
1248 * op1 - target to be shifted
1249 * op2 - contains bits to be shifted into target
1251 * Only op3 can be an immediate.
1253 static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block,
1254 ir_node *high, ir_node *low, ir_node *count,
1255 new_shiftd_func func)
1257 ir_node *new_block = be_transform_node(block);
1258 ir_node *new_high = be_transform_node(high);
1259 ir_node *new_low = be_transform_node(low);
1263 /* the shift amount can be any mode that is bigger than 5 bits, since all
1264 * other bits are ignored anyway */
1265 while (is_Conv(count) &&
1266 get_irn_n_edges(count) == 1 &&
1267 mode_is_int(get_irn_mode(count))) {
1268 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
1269 count = get_Conv_op(count);
1271 new_count = create_immediate_or_transform(count, 0);
1273 new_node = func(dbgi, new_block, new_high, new_low, new_count);
1278 * test wether 2 values result in 'x' and '32-x' when interpreted as a shift
1281 static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
1283 if (is_Const(value1) && is_Const(value2)) {
1284 ir_tarval *tv1 = get_Const_tarval(value1);
1285 ir_tarval *tv2 = get_Const_tarval(value2);
1286 if (tarval_is_long(tv1) && tarval_is_long(tv2)) {
1287 long v1 = get_tarval_long(tv1);
1288 long v2 = get_tarval_long(tv2);
1289 return v1 <= v2 && v2 == 32-v1;
1295 static ir_node *match_64bit_shift(ir_node *node)
1297 ir_node *op1 = get_binop_left(node);
1298 ir_node *op2 = get_binop_right(node);
1299 assert(is_Or(node) || is_Add(node));
1307 /* match ShlD operation */
1308 if (is_Shl(op1) && is_Shr(op2)) {
1309 ir_node *shl_right = get_Shl_right(op1);
1310 ir_node *shl_left = get_Shl_left(op1);
1311 ir_node *shr_right = get_Shr_right(op2);
1312 ir_node *shr_left = get_Shr_left(op2);
1313 /* constant ShlD operation */
1314 if (is_complementary_shifts(shl_right, shr_right)) {
1315 dbg_info *dbgi = get_irn_dbg_info(node);
1316 ir_node *block = get_nodes_block(node);
1317 return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right,
1320 /* constant ShrD operation */
1321 if (is_complementary_shifts(shr_right, shl_right)) {
1322 dbg_info *dbgi = get_irn_dbg_info(node);
1323 ir_node *block = get_nodes_block(node);
1324 return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right,
1327 /* lower_dw produces the following for ShlD:
1328 * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */
1329 if (is_Shr(shr_left) && is_Not(shr_right)
1330 && is_Const_1(get_Shr_right(shr_left))
1331 && get_Not_op(shr_right) == shl_right) {
1332 dbg_info *dbgi = get_irn_dbg_info(node);
1333 ir_node *block = get_nodes_block(node);
1334 ir_node *val_h = get_Shr_left(shr_left);
1335 return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right,
1338 /* lower_dw produces the following for ShrD:
1339 * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */
1340 if (is_Shl(shl_left) && is_Not(shl_right)
1341 && is_Const_1(get_Shl_right(shl_left))
1342 && get_Not_op(shl_right) == shr_right) {
1343 dbg_info *dbgi = get_irn_dbg_info(node);
1344 ir_node *block = get_nodes_block(node);
1345 ir_node *val_h = get_Shl_left(shl_left);
1346 return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right,
1355 * Creates an ia32 Add.
1357 * @return the created ia32 Add node
1359 static ir_node *gen_Add(ir_node *node)
1361 ir_mode *mode = get_irn_mode(node);
1362 ir_node *op1 = get_Add_left(node);
1363 ir_node *op2 = get_Add_right(node);
1365 ir_node *block, *new_block, *new_node, *add_immediate_op;
1366 ia32_address_t addr;
1367 ia32_address_mode_t am;
1369 new_node = match_64bit_shift(node);
1370 if (new_node != NULL)
1373 if (mode_is_float(mode)) {
1374 if (ia32_cg_config.use_sse2)
1375 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1376 match_commutative | match_am);
1378 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
1381 ia32_mark_non_am(node);
1383 op2 = ia32_skip_downconv(op2);
1384 op1 = ia32_skip_downconv(op1);
1388 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1389 * 1. Add with immediate -> Lea
1390 * 2. Add with possible source address mode -> Add
1391 * 3. Otherwise -> Lea
1393 memset(&addr, 0, sizeof(addr));
1394 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1395 add_immediate_op = NULL;
1397 dbgi = get_irn_dbg_info(node);
1398 block = get_nodes_block(node);
1399 new_block = be_transform_node(block);
1402 if (addr.base == NULL && addr.index == NULL) {
1403 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1404 addr.symconst_sign, 0, addr.offset);
1405 SET_IA32_ORIG_NODE(new_node, node);
1408 /* add with immediate? */
1409 if (addr.index == NULL) {
1410 add_immediate_op = addr.base;
1411 } else if (addr.base == NULL && addr.scale == 0) {
1412 add_immediate_op = addr.index;
1415 if (add_immediate_op != NULL) {
1416 if (!am_has_immediates(&addr)) {
1417 #ifdef DEBUG_libfirm
1418 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1421 return be_transform_node(add_immediate_op);
1424 new_node = create_lea_from_address(dbgi, new_block, &addr);
1425 SET_IA32_ORIG_NODE(new_node, node);
1429 /* test if we can use source address mode */
1430 match_arguments(&am, block, op1, op2, NULL, match_commutative
1431 | match_mode_neutral | match_am | match_immediate | match_try_am);
1433 /* construct an Add with source address mode */
1434 if (am.op_type == ia32_AddrModeS) {
1435 ia32_address_t *am_addr = &am.addr;
1436 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1437 am_addr->index, am_addr->mem, am.new_op1,
1439 set_am_attributes(new_node, &am);
1440 SET_IA32_ORIG_NODE(new_node, node);
1442 new_node = fix_mem_proj(new_node, &am);
1447 /* otherwise construct a lea */
1448 new_node = create_lea_from_address(dbgi, new_block, &addr);
1449 SET_IA32_ORIG_NODE(new_node, node);
1454 * Creates an ia32 Mul.
1456 * @return the created ia32 Mul node
1458 static ir_node *gen_Mul(ir_node *node)
1460 ir_node *op1 = get_Mul_left(node);
1461 ir_node *op2 = get_Mul_right(node);
1462 ir_mode *mode = get_irn_mode(node);
1464 if (mode_is_float(mode)) {
1465 if (ia32_cg_config.use_sse2)
1466 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1467 match_commutative | match_am);
1469 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
1471 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1472 match_commutative | match_am | match_mode_neutral |
1473 match_immediate | match_am_and_immediates);
1477 * Creates an ia32 Mulh.
1478 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1479 * this result while Mul returns the lower 32 bit.
1481 * @return the created ia32 Mulh node
1483 static ir_node *gen_Mulh(ir_node *node)
1485 dbg_info *dbgi = get_irn_dbg_info(node);
1486 ir_node *op1 = get_Mulh_left(node);
1487 ir_node *op2 = get_Mulh_right(node);
1488 ir_mode *mode = get_irn_mode(node);
1490 ir_node *proj_res_high;
1492 if (get_mode_size_bits(mode) != 32) {
1493 panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
1496 if (mode_is_signed(mode)) {
1497 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1498 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
1500 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1501 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_Mul_res_high);
1503 return proj_res_high;
1507 * Creates an ia32 And.
1509 * @return The created ia32 And node
1511 static ir_node *gen_And(ir_node *node)
1513 ir_node *op1 = get_And_left(node);
1514 ir_node *op2 = get_And_right(node);
1515 assert(! mode_is_float(get_irn_mode(node)));
1517 /* is it a zero extension? */
1518 if (is_Const(op2)) {
1519 ir_tarval *tv = get_Const_tarval(op2);
1520 long v = get_tarval_long(tv);
1522 if (v == 0xFF || v == 0xFFFF) {
1523 dbg_info *dbgi = get_irn_dbg_info(node);
1524 ir_node *block = get_nodes_block(node);
1531 assert(v == 0xFFFF);
1534 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1539 return gen_binop(node, op1, op2, new_bd_ia32_And,
1540 match_commutative | match_mode_neutral | match_am | match_immediate);
1544 * Creates an ia32 Or.
1546 * @return The created ia32 Or node
1548 static ir_node *gen_Or(ir_node *node)
1550 ir_node *op1 = get_Or_left(node);
1551 ir_node *op2 = get_Or_right(node);
1554 res = match_64bit_shift(node);
1558 assert (! mode_is_float(get_irn_mode(node)));
1559 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1560 | match_mode_neutral | match_am | match_immediate);
1566 * Creates an ia32 Eor.
1568 * @return The created ia32 Eor node
1570 static ir_node *gen_Eor(ir_node *node)
1572 ir_node *op1 = get_Eor_left(node);
1573 ir_node *op2 = get_Eor_right(node);
1575 assert(! mode_is_float(get_irn_mode(node)));
1576 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1577 | match_mode_neutral | match_am | match_immediate);
1582 * Creates an ia32 Sub.
1584 * @return The created ia32 Sub node
1586 static ir_node *gen_Sub(ir_node *node)
1588 ir_node *op1 = get_Sub_left(node);
1589 ir_node *op2 = get_Sub_right(node);
1590 ir_mode *mode = get_irn_mode(node);
1592 if (mode_is_float(mode)) {
1593 if (ia32_cg_config.use_sse2)
1594 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1596 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
1599 if (is_Const(op2)) {
1600 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1604 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1605 | match_am | match_immediate);
1608 static ir_node *transform_AM_mem(ir_node *const block,
1609 ir_node *const src_val,
1610 ir_node *const src_mem,
1611 ir_node *const am_mem)
1613 if (is_NoMem(am_mem)) {
1614 return be_transform_node(src_mem);
1615 } else if (is_Proj(src_val) &&
1617 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1618 /* avoid memory loop */
1620 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1621 ir_node *const ptr_pred = get_Proj_pred(src_val);
1622 int const arity = get_Sync_n_preds(src_mem);
1627 NEW_ARR_A(ir_node*, ins, arity + 1);
1629 /* NOTE: This sometimes produces dead-code because the old sync in
1630 * src_mem might not be used anymore, we should detect this case
1631 * and kill the sync... */
1632 for (i = arity - 1; i >= 0; --i) {
1633 ir_node *const pred = get_Sync_pred(src_mem, i);
1635 /* avoid memory loop */
1636 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1639 ins[n++] = be_transform_node(pred);
1642 if (n==1 && ins[0] == am_mem) {
1644 /* creating a new Sync and relying on CSE may fail,
1645 * if am_mem is a ProjM, which does not yet verify. */
1649 return new_r_Sync(block, n, ins);
1653 ins[0] = be_transform_node(src_mem);
1655 return new_r_Sync(block, 2, ins);
1660 * Create a 32bit to 64bit signed extension.
1662 * @param dbgi debug info
1663 * @param block the block where node nodes should be placed
1664 * @param val the value to extend
1665 * @param orig the original node
1667 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1668 ir_node *val, const ir_node *orig)
1673 if (ia32_cg_config.use_short_sex_eax) {
1674 ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
1675 res = new_bd_ia32_Cltd(dbgi, block, val, pval);
1677 ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
1678 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1680 SET_IA32_ORIG_NODE(res, orig);
1685 * Generates an ia32 Div with additional infrastructure for the
1686 * register allocator if needed.
1688 static ir_node *create_Div(ir_node *node)
1690 dbg_info *dbgi = get_irn_dbg_info(node);
1691 ir_node *block = get_nodes_block(node);
1692 ir_node *new_block = be_transform_node(block);
1693 int throws_exception = ir_throws_exception(node);
1700 ir_node *sign_extension;
1701 ia32_address_mode_t am;
1702 ia32_address_t *addr = &am.addr;
1704 /* the upper bits have random contents for smaller modes */
1705 switch (get_irn_opcode(node)) {
1707 op1 = get_Div_left(node);
1708 op2 = get_Div_right(node);
1709 mem = get_Div_mem(node);
1710 mode = get_Div_resmode(node);
1713 op1 = get_Mod_left(node);
1714 op2 = get_Mod_right(node);
1715 mem = get_Mod_mem(node);
1716 mode = get_Mod_resmode(node);
1719 panic("invalid divmod node %+F", node);
1722 match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
1724 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1725 is the memory of the consumed address. We can have only the second op as address
1726 in Div nodes, so check only op2. */
1727 new_mem = transform_AM_mem(block, op2, mem, addr->mem);
1729 if (mode_is_signed(mode)) {
1730 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1731 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1732 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1734 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
1736 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1737 addr->index, new_mem, am.new_op2,
1738 am.new_op1, sign_extension);
1740 ir_set_throws_exception(new_node, throws_exception);
1742 set_irn_pinned(new_node, get_irn_pinned(node));
1744 set_am_attributes(new_node, &am);
1745 SET_IA32_ORIG_NODE(new_node, node);
1747 new_node = fix_mem_proj(new_node, &am);
1753 * Generates an ia32 Mod.
1755 static ir_node *gen_Mod(ir_node *node)
1757 return create_Div(node);
1761 * Generates an ia32 Div.
1763 static ir_node *gen_Div(ir_node *node)
1765 ir_mode *mode = get_Div_resmode(node);
1766 if (mode_is_float(mode)) {
1767 ir_node *op1 = get_Div_left(node);
1768 ir_node *op2 = get_Div_right(node);
1770 if (ia32_cg_config.use_sse2) {
1771 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1773 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
1777 return create_Div(node);
1781 * Creates an ia32 Shl.
1783 * @return The created ia32 Shl node
1785 static ir_node *gen_Shl(ir_node *node)
1787 ir_node *left = get_Shl_left(node);
1788 ir_node *right = get_Shl_right(node);
1790 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1791 match_mode_neutral | match_immediate);
1795 * Creates an ia32 Shr.
1797 * @return The created ia32 Shr node
1799 static ir_node *gen_Shr(ir_node *node)
1801 ir_node *left = get_Shr_left(node);
1802 ir_node *right = get_Shr_right(node);
1804 return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
1810 * Creates an ia32 Sar.
1812 * @return The created ia32 Shrs node
1814 static ir_node *gen_Shrs(ir_node *node)
1816 ir_node *left = get_Shrs_left(node);
1817 ir_node *right = get_Shrs_right(node);
1819 if (is_Const(right)) {
1820 ir_tarval *tv = get_Const_tarval(right);
1821 long val = get_tarval_long(tv);
1823 /* this is a sign extension */
1824 dbg_info *dbgi = get_irn_dbg_info(node);
1825 ir_node *block = be_transform_node(get_nodes_block(node));
1826 ir_node *new_op = be_transform_node(left);
1828 return create_sex_32_64(dbgi, block, new_op, node);
1832 /* 8 or 16 bit sign extension? */
1833 if (is_Const(right) && is_Shl(left)) {
1834 ir_node *shl_left = get_Shl_left(left);
1835 ir_node *shl_right = get_Shl_right(left);
1836 if (is_Const(shl_right)) {
1837 ir_tarval *tv1 = get_Const_tarval(right);
1838 ir_tarval *tv2 = get_Const_tarval(shl_right);
1839 if (tv1 == tv2 && tarval_is_long(tv1)) {
1840 long val = get_tarval_long(tv1);
1841 if (val == 16 || val == 24) {
1842 dbg_info *dbgi = get_irn_dbg_info(node);
1843 ir_node *block = get_nodes_block(node);
1853 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1862 return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
1868 * Creates an ia32 Rol.
1870 * @param op1 The first operator
1871 * @param op2 The second operator
1872 * @return The created ia32 RotL node
1874 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1876 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1882 * Creates an ia32 Ror.
1883 * NOTE: There is no RotR with immediate because this would always be a RotL
1884 * "imm-mode_size_bits" which can be pre-calculated.
1886 * @param op1 The first operator
1887 * @param op2 The second operator
1888 * @return The created ia32 RotR node
1890 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1892 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1898 * Creates an ia32 RotR or RotL (depending on the found pattern).
1900 * @return The created ia32 RotL or RotR node
1902 static ir_node *gen_Rotl(ir_node *node)
1904 ir_node *op1 = get_Rotl_left(node);
1905 ir_node *op2 = get_Rotl_right(node);
1907 if (is_Minus(op2)) {
1908 return gen_Ror(node, op1, get_Minus_op(op2));
1911 return gen_Rol(node, op1, op2);
1917 * Transforms a Minus node.
1919 * @return The created ia32 Minus node
1921 static ir_node *gen_Minus(ir_node *node)
1923 ir_node *op = get_Minus_op(node);
1924 ir_node *block = be_transform_node(get_nodes_block(node));
1925 dbg_info *dbgi = get_irn_dbg_info(node);
1926 ir_mode *mode = get_irn_mode(node);
1931 if (mode_is_float(mode)) {
1932 ir_node *new_op = be_transform_node(op);
1933 if (ia32_cg_config.use_sse2) {
1934 /* TODO: non-optimal... if we have many xXors, then we should
1935 * rather create a load for the const and use that instead of
1936 * several AM nodes... */
1937 ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph);
1939 new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
1940 noreg_GP, nomem, new_op, noreg_xmm);
1942 size = get_mode_size_bits(mode);
1943 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1945 set_ia32_am_sc(new_node, ent);
1946 set_ia32_op_type(new_node, ia32_AddrModeS);
1947 set_ia32_ls_mode(new_node, mode);
1949 new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
1952 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1955 SET_IA32_ORIG_NODE(new_node, node);
1961 * Transforms a Not node.
1963 * @return The created ia32 Not node
1965 static ir_node *gen_Not(ir_node *node)
1967 ir_node *op = get_Not_op(node);
1969 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1970 assert (! mode_is_float(get_irn_mode(node)));
1972 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
1975 static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
1976 bool negate, ir_node *node)
1978 ir_node *new_block = be_transform_node(block);
1979 ir_mode *mode = get_irn_mode(op);
1980 ir_node *new_op = be_transform_node(op);
1985 assert(mode_is_float(mode));
1987 if (ia32_cg_config.use_sse2) {
1988 ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
1989 new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
1990 noreg_GP, nomem, new_op, noreg_fp);
1992 size = get_mode_size_bits(mode);
1993 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1995 set_ia32_am_sc(new_node, ent);
1997 SET_IA32_ORIG_NODE(new_node, node);
1999 set_ia32_op_type(new_node, ia32_AddrModeS);
2000 set_ia32_ls_mode(new_node, mode);
2002 /* TODO, implement -Abs case */
2005 new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
2006 SET_IA32_ORIG_NODE(new_node, node);
2008 new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
2009 SET_IA32_ORIG_NODE(new_node, node);
2017 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
2019 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
2021 dbg_info *dbgi = get_irn_dbg_info(cmp);
2022 ir_node *block = get_nodes_block(cmp);
2023 ir_node *new_block = be_transform_node(block);
2024 ir_node *op1 = be_transform_node(x);
2025 ir_node *op2 = be_transform_node(n);
2027 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
2030 static ia32_condition_code_t relation_to_condition_code(ir_relation relation,
2033 if (mode_is_float(mode)) {
2035 case ir_relation_equal: return ia32_cc_float_equal;
2036 case ir_relation_less: return ia32_cc_float_below;
2037 case ir_relation_less_equal: return ia32_cc_float_below_equal;
2038 case ir_relation_greater: return ia32_cc_float_above;
2039 case ir_relation_greater_equal: return ia32_cc_float_above_equal;
2040 case ir_relation_less_greater: return ia32_cc_not_equal;
2041 case ir_relation_less_equal_greater: return ia32_cc_not_parity;
2042 case ir_relation_unordered: return ia32_cc_parity;
2043 case ir_relation_unordered_equal: return ia32_cc_equal;
2044 case ir_relation_unordered_less: return ia32_cc_float_unordered_below;
2045 case ir_relation_unordered_less_equal:
2046 return ia32_cc_float_unordered_below_equal;
2047 case ir_relation_unordered_greater:
2048 return ia32_cc_float_unordered_above;
2049 case ir_relation_unordered_greater_equal:
2050 return ia32_cc_float_unordered_above_equal;
2051 case ir_relation_unordered_less_greater:
2052 return ia32_cc_float_not_equal;
2053 case ir_relation_false:
2054 case ir_relation_true:
2055 /* should we introduce a jump always/jump never? */
2058 panic("Unexpected float pnc");
2059 } else if (mode_is_signed(mode)) {
2061 case ir_relation_unordered_equal:
2062 case ir_relation_equal: return ia32_cc_equal;
2063 case ir_relation_unordered_less:
2064 case ir_relation_less: return ia32_cc_less;
2065 case ir_relation_unordered_less_equal:
2066 case ir_relation_less_equal: return ia32_cc_less_equal;
2067 case ir_relation_unordered_greater:
2068 case ir_relation_greater: return ia32_cc_greater;
2069 case ir_relation_unordered_greater_equal:
2070 case ir_relation_greater_equal: return ia32_cc_greater_equal;
2071 case ir_relation_unordered_less_greater:
2072 case ir_relation_less_greater: return ia32_cc_not_equal;
2073 case ir_relation_less_equal_greater:
2074 case ir_relation_unordered:
2075 case ir_relation_false:
2076 case ir_relation_true:
2077 /* introduce jump always/jump never? */
2080 panic("Unexpected pnc");
2083 case ir_relation_unordered_equal:
2084 case ir_relation_equal: return ia32_cc_equal;
2085 case ir_relation_unordered_less:
2086 case ir_relation_less: return ia32_cc_below;
2087 case ir_relation_unordered_less_equal:
2088 case ir_relation_less_equal: return ia32_cc_below_equal;
2089 case ir_relation_unordered_greater:
2090 case ir_relation_greater: return ia32_cc_above;
2091 case ir_relation_unordered_greater_equal:
2092 case ir_relation_greater_equal: return ia32_cc_above_equal;
2093 case ir_relation_unordered_less_greater:
2094 case ir_relation_less_greater: return ia32_cc_not_equal;
2095 case ir_relation_less_equal_greater:
2096 case ir_relation_unordered:
2097 case ir_relation_false:
2098 case ir_relation_true:
2099 /* introduce jump always/jump never? */
2102 panic("Unexpected pnc");
2106 static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out)
2108 /* must have a Cmp as input */
2109 ir_relation relation = get_Cmp_relation(cmp);
2110 ir_relation possible;
2111 ir_node *l = get_Cmp_left(cmp);
2112 ir_node *r = get_Cmp_right(cmp);
2113 ir_mode *mode = get_irn_mode(l);
2116 /* check for bit-test */
2117 if (ia32_cg_config.use_bt && (relation == ir_relation_equal
2118 || (mode_is_signed(mode) && relation == ir_relation_less_greater)
2119 || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))
2121 ir_node *la = get_And_left(l);
2122 ir_node *ra = get_And_right(l);
2129 ir_node *c = get_Shl_left(la);
2130 if (is_Const_1(c) && is_Const_0(r)) {
2131 /* (1 << n) & ra) */
2132 ir_node *n = get_Shl_right(la);
2133 flags = gen_bt(cmp, ra, n);
2134 /* the bit is copied into the CF flag */
2135 if (relation & ir_relation_equal)
2136 *cc_out = ia32_cc_above_equal; /* test for CF=0 */
2138 *cc_out = ia32_cc_below; /* test for CF=1 */
2144 /* the middle-end tries to eliminate impossible relations, so a ptr != 0
2145 * test becomes ptr > 0. But for x86 an equal comparison is preferable to
2146 * a >0 (we can sometimes eliminate the cmp in favor of flags produced by
2147 * a predecessor node). So add the < bit */
2148 possible = ir_get_possible_cmp_relations(l, r);
2149 if (((relation & ir_relation_less) && !(possible & ir_relation_greater))
2150 || ((relation & ir_relation_greater) && !(possible & ir_relation_less)))
2151 relation |= ir_relation_less_greater;
2153 /* just do a normal transformation of the Cmp */
2154 *cc_out = relation_to_condition_code(relation, mode);
2155 flags = be_transform_node(cmp);
2160 * Transform a node returning a "flag" result.
2162 * @param node the node to transform
2163 * @param cc_out the compare mode to use
2165 static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out)
2167 assert(is_Cmp(node));
2168 return get_flags_node_cmp(node, cc_out);
2172 * Transforms a Load.
2174 * @return the created ia32 Load node
2176 static ir_node *gen_Load(ir_node *node)
2178 ir_node *old_block = get_nodes_block(node);
2179 ir_node *block = be_transform_node(old_block);
2180 ir_node *ptr = get_Load_ptr(node);
2181 ir_node *mem = get_Load_mem(node);
2182 ir_node *new_mem = be_transform_node(mem);
2183 dbg_info *dbgi = get_irn_dbg_info(node);
2184 ir_mode *mode = get_Load_mode(node);
2185 int throws_exception = ir_throws_exception(node);
2189 ia32_address_t addr;
2191 /* construct load address */
2192 memset(&addr, 0, sizeof(addr));
2193 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2200 base = be_transform_node(base);
2206 idx = be_transform_node(idx);
2209 if (mode_is_float(mode)) {
2210 if (ia32_cg_config.use_sse2) {
2211 new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
2214 new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem,
2218 assert(mode != mode_b);
2220 /* create a conv node with address mode for smaller modes */
2221 if (get_mode_size_bits(mode) < 32) {
2222 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx,
2223 new_mem, noreg_GP, mode);
2225 new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem);
2228 ir_set_throws_exception(new_node, throws_exception);
2230 set_irn_pinned(new_node, get_irn_pinned(node));
2231 set_ia32_op_type(new_node, ia32_AddrModeS);
2232 set_ia32_ls_mode(new_node, mode);
2233 set_address(new_node, &addr);
2235 if (get_irn_pinned(node) == op_pin_state_floats) {
2236 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
2237 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
2238 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
2239 arch_add_irn_flags(new_node, arch_irn_flags_rematerializable);
2242 SET_IA32_ORIG_NODE(new_node, node);
2247 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2248 ir_node *ptr, ir_node *other)
2255 /* we only use address mode if we're the only user of the load */
2256 if (get_irn_n_edges(node) > 1)
2259 load = get_Proj_pred(node);
2262 if (get_nodes_block(load) != block)
2265 /* store should have the same pointer as the load */
2266 if (get_Load_ptr(load) != ptr)
2269 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2270 if (other != NULL &&
2271 get_nodes_block(other) == block &&
2272 heights_reachable_in_block(ia32_heights, other, load)) {
2276 if (ia32_prevents_AM(block, load, mem))
2278 /* Store should be attached to the load via mem */
2279 assert(heights_reachable_in_block(ia32_heights, mem, load));
2284 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2285 ir_node *mem, ir_node *ptr, ir_mode *mode,
2286 construct_binop_dest_func *func,
2287 construct_binop_dest_func *func8bit,
2288 match_flags_t flags)
2290 ir_node *src_block = get_nodes_block(node);
2298 ia32_address_mode_t am;
2299 ia32_address_t *addr = &am.addr;
2300 memset(&am, 0, sizeof(am));
2302 assert(flags & match_immediate); /* there is no destam node without... */
2303 commutative = (flags & match_commutative) != 0;
2305 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
2306 build_address(&am, op1, ia32_create_am_double_use);
2307 new_op = create_immediate_or_transform(op2, 0);
2308 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2309 build_address(&am, op2, ia32_create_am_double_use);
2310 new_op = create_immediate_or_transform(op1, 0);
2315 if (addr->base == NULL)
2316 addr->base = noreg_GP;
2317 if (addr->index == NULL)
2318 addr->index = noreg_GP;
2319 if (addr->mem == NULL)
2322 dbgi = get_irn_dbg_info(node);
2323 block = be_transform_node(src_block);
2324 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2326 if (get_mode_size_bits(mode) == 8) {
2327 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2329 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2331 set_address(new_node, addr);
2332 set_ia32_op_type(new_node, ia32_AddrModeD);
2333 set_ia32_ls_mode(new_node, mode);
2334 SET_IA32_ORIG_NODE(new_node, node);
2336 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2337 mem_proj = be_transform_node(am.mem_proj);
2338 be_set_transformed_node(am.mem_proj, new_node);
2339 be_set_transformed_node(mem_proj, new_node);
2344 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2345 ir_node *ptr, ir_mode *mode,
2346 construct_unop_dest_func *func)
2348 ir_node *src_block = get_nodes_block(node);
2354 ia32_address_mode_t am;
2355 ia32_address_t *addr = &am.addr;
2357 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2360 memset(&am, 0, sizeof(am));
2361 build_address(&am, op, ia32_create_am_double_use);
2363 dbgi = get_irn_dbg_info(node);
2364 block = be_transform_node(src_block);
2365 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2366 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2367 set_address(new_node, addr);
2368 set_ia32_op_type(new_node, ia32_AddrModeD);
2369 set_ia32_ls_mode(new_node, mode);
2370 SET_IA32_ORIG_NODE(new_node, node);
2372 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2373 mem_proj = be_transform_node(am.mem_proj);
2374 be_set_transformed_node(am.mem_proj, new_node);
2375 be_set_transformed_node(mem_proj, new_node);
2380 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2382 ir_mode *mode = get_irn_mode(node);
2383 ir_node *mux_true = get_Mux_true(node);
2384 ir_node *mux_false = get_Mux_false(node);
2392 ia32_condition_code_t cc;
2393 ia32_address_t addr;
2395 if (get_mode_size_bits(mode) != 8)
2398 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2400 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2406 cond = get_Mux_sel(node);
2407 flags = get_flags_node(cond, &cc);
2408 /* we can't handle the float special cases with SetM */
2409 if (cc & ia32_cc_additional_float_cases)
2412 cc = ia32_negate_condition_code(cc);
2414 build_address_ptr(&addr, ptr, mem);
2416 dbgi = get_irn_dbg_info(node);
2417 block = get_nodes_block(node);
2418 new_block = be_transform_node(block);
2419 new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
2420 addr.index, addr.mem, flags, cc);
2421 set_address(new_node, &addr);
2422 set_ia32_op_type(new_node, ia32_AddrModeD);
2423 set_ia32_ls_mode(new_node, mode);
2424 SET_IA32_ORIG_NODE(new_node, node);
2429 static ir_node *try_create_dest_am(ir_node *node)
2431 ir_node *val = get_Store_value(node);
2432 ir_node *mem = get_Store_mem(node);
2433 ir_node *ptr = get_Store_ptr(node);
2434 ir_mode *mode = get_irn_mode(val);
2435 unsigned bits = get_mode_size_bits(mode);
2440 /* handle only GP modes for now... */
2441 if (!ia32_mode_needs_gp_reg(mode))
2445 /* store must be the only user of the val node */
2446 if (get_irn_n_edges(val) > 1)
2448 /* skip pointless convs */
2450 ir_node *conv_op = get_Conv_op(val);
2451 ir_mode *pred_mode = get_irn_mode(conv_op);
2452 if (!ia32_mode_needs_gp_reg(pred_mode))
2454 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2462 /* value must be in the same block */
2463 if (get_nodes_block(node) != get_nodes_block(val))
2466 switch (get_irn_opcode(val)) {
2468 op1 = get_Add_left(val);
2469 op2 = get_Add_right(val);
2470 if (ia32_cg_config.use_incdec) {
2471 if (is_Const_1(op2)) {
2472 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2474 } else if (is_Const_Minus_1(op2)) {
2475 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2479 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2480 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2481 match_commutative | match_immediate);
2484 op1 = get_Sub_left(val);
2485 op2 = get_Sub_right(val);
2486 if (is_Const(op2)) {
2487 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2489 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2490 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2494 op1 = get_And_left(val);
2495 op2 = get_And_right(val);
2496 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2497 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2498 match_commutative | match_immediate);
2501 op1 = get_Or_left(val);
2502 op2 = get_Or_right(val);
2503 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2504 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2505 match_commutative | match_immediate);
2508 op1 = get_Eor_left(val);
2509 op2 = get_Eor_right(val);
2510 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2511 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2512 match_commutative | match_immediate);
2515 op1 = get_Shl_left(val);
2516 op2 = get_Shl_right(val);
2517 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2518 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2522 op1 = get_Shr_left(val);
2523 op2 = get_Shr_right(val);
2524 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2525 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2529 op1 = get_Shrs_left(val);
2530 op2 = get_Shrs_right(val);
2531 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2532 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2536 op1 = get_Rotl_left(val);
2537 op2 = get_Rotl_right(val);
2538 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2539 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2542 /* TODO: match ROR patterns... */
2544 new_node = try_create_SetMem(val, ptr, mem);
2548 op1 = get_Minus_op(val);
2549 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2552 /* should be lowered already */
2553 assert(mode != mode_b);
2554 op1 = get_Not_op(val);
2555 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2561 if (new_node != NULL) {
2562 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2563 get_irn_pinned(node) == op_pin_state_pinned) {
2564 set_irn_pinned(new_node, op_pin_state_pinned);
2571 static bool possible_int_mode_for_fp(ir_mode *mode)
2575 if (!mode_is_signed(mode))
2577 size = get_mode_size_bits(mode);
2578 if (size != 16 && size != 32)
2583 static int is_float_to_int_conv(const ir_node *node)
2585 ir_mode *mode = get_irn_mode(node);
2589 if (!possible_int_mode_for_fp(mode))
2594 conv_op = get_Conv_op(node);
2595 conv_mode = get_irn_mode(conv_op);
2597 if (!mode_is_float(conv_mode))
2604 * Transform a Store(floatConst) into a sequence of
2607 * @return the created ia32 Store node
2609 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2611 ir_mode *mode = get_irn_mode(cns);
2612 unsigned size = get_mode_size_bytes(mode);
2613 ir_tarval *tv = get_Const_tarval(cns);
2614 ir_node *block = get_nodes_block(node);
2615 ir_node *new_block = be_transform_node(block);
2616 ir_node *ptr = get_Store_ptr(node);
2617 ir_node *mem = get_Store_mem(node);
2618 dbg_info *dbgi = get_irn_dbg_info(node);
2621 int throws_exception = ir_throws_exception(node);
2623 ia32_address_t addr;
2625 build_address_ptr(&addr, ptr, mem);
2632 val= get_tarval_sub_bits(tv, ofs) |
2633 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2634 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2635 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2638 } else if (size >= 2) {
2639 val= get_tarval_sub_bits(tv, ofs) |
2640 (get_tarval_sub_bits(tv, ofs + 1) << 8);
2644 panic("invalid size of Store float to mem (%+F)", node);
2646 ir_node *imm = ia32_create_Immediate(NULL, 0, val);
2648 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2649 addr.index, addr.mem, imm);
2650 ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M);
2652 ir_set_throws_exception(new_node, throws_exception);
2653 set_irn_pinned(new_node, get_irn_pinned(node));
2654 set_ia32_op_type(new_node, ia32_AddrModeD);
2655 set_ia32_ls_mode(new_node, mode);
2656 set_address(new_node, &addr);
2657 SET_IA32_ORIG_NODE(new_node, node);
2664 addr.offset += delta;
2665 } while (size != 0);
2668 return new_rd_Sync(dbgi, new_block, i, ins);
2670 return get_Proj_pred(ins[0]);
2675 * Generate a vfist or vfisttp instruction.
2677 static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base,
2678 ir_node *index, ir_node *mem, ir_node *val)
2680 if (ia32_cg_config.use_fisttp) {
2681 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2682 if other users exists */
2683 ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
2684 ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res);
2685 be_new_Keep(block, 1, &value);
2689 ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
2692 ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
2698 * Transforms a general (no special case) Store.
2700 * @return the created ia32 Store node
2702 static ir_node *gen_general_Store(ir_node *node)
2704 ir_node *val = get_Store_value(node);
2705 ir_mode *mode = get_irn_mode(val);
2706 ir_node *block = get_nodes_block(node);
2707 ir_node *new_block = be_transform_node(block);
2708 ir_node *ptr = get_Store_ptr(node);
2709 ir_node *mem = get_Store_mem(node);
2710 dbg_info *dbgi = get_irn_dbg_info(node);
2711 int throws_exception = ir_throws_exception(node);
2714 ia32_address_t addr;
2716 /* check for destination address mode */
2717 new_node = try_create_dest_am(node);
2718 if (new_node != NULL)
2721 /* construct store address */
2722 memset(&addr, 0, sizeof(addr));
2723 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2725 if (addr.base == NULL) {
2726 addr.base = noreg_GP;
2728 addr.base = be_transform_node(addr.base);
2731 if (addr.index == NULL) {
2732 addr.index = noreg_GP;
2734 addr.index = be_transform_node(addr.index);
2736 addr.mem = be_transform_node(mem);
2738 if (mode_is_float(mode)) {
2739 /* Convs (and strict-Convs) before stores are unnecessary if the mode
2741 while (is_Conv(val) && mode == get_irn_mode(val)) {
2742 ir_node *op = get_Conv_op(val);
2743 if (!mode_is_float(get_irn_mode(op)))
2747 new_val = be_transform_node(val);
2748 if (ia32_cg_config.use_sse2) {
2749 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2750 addr.index, addr.mem, new_val);
2752 new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
2753 addr.index, addr.mem, new_val, mode);
2755 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2756 val = get_Conv_op(val);
2758 /* TODO: is this optimisation still necessary at all (middleend)? */
2759 /* We can skip ALL float->float up-Convs (and strict-up-Convs) before
2761 while (is_Conv(val)) {
2762 ir_node *op = get_Conv_op(val);
2763 if (!mode_is_float(get_irn_mode(op)))
2765 if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
2769 new_val = be_transform_node(val);
2770 new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
2772 new_val = create_immediate_or_transform(val, 0);
2773 assert(mode != mode_b);
2775 if (get_mode_size_bits(mode) == 8) {
2776 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2777 addr.index, addr.mem, new_val);
2779 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2780 addr.index, addr.mem, new_val);
2783 ir_set_throws_exception(new_node, throws_exception);
2785 set_irn_pinned(new_node, get_irn_pinned(node));
2786 set_ia32_op_type(new_node, ia32_AddrModeD);
2787 set_ia32_ls_mode(new_node, mode);
2789 set_address(new_node, &addr);
2790 SET_IA32_ORIG_NODE(new_node, node);
2796 * Transforms a Store.
2798 * @return the created ia32 Store node
2800 static ir_node *gen_Store(ir_node *node)
2802 ir_node *val = get_Store_value(node);
2803 ir_mode *mode = get_irn_mode(val);
2805 if (mode_is_float(mode) && is_Const(val)) {
2806 /* We can transform every floating const store
2807 into a sequence of integer stores.
2808 If the constant is already in a register,
2809 it would be better to use it, but we don't
2810 have this information here. */
2811 return gen_float_const_Store(node, val);
2813 return gen_general_Store(node);
2817 * Transforms a Switch.
2819 * @return the created ia32 SwitchJmp node
2821 static ir_node *create_Switch(ir_node *node)
2823 dbg_info *dbgi = get_irn_dbg_info(node);
2824 ir_node *block = be_transform_node(get_nodes_block(node));
2825 ir_node *sel = get_Cond_selector(node);
2826 ir_node *new_sel = be_transform_node(sel);
2827 long default_pn = get_Cond_default_proj(node);
2831 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2833 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
2834 set_entity_visibility(entity, ir_visibility_private);
2835 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
2837 /* TODO: we could perform some more matching here to also use the base
2838 * register of the address mode */
2840 = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, default_pn);
2841 set_ia32_am_scale(new_node, 2);
2842 set_ia32_am_sc(new_node, entity);
2843 set_ia32_op_type(new_node, ia32_AddrModeS);
2844 set_ia32_ls_mode(new_node, mode_Iu);
2845 SET_IA32_ORIG_NODE(new_node, node);
2846 // FIXME This seems wrong. GCC uses PIC for switch on OS X.
2847 get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true;
2853 * Transform a Cond node.
2855 static ir_node *gen_Cond(ir_node *node)
2857 ir_node *block = get_nodes_block(node);
2858 ir_node *new_block = be_transform_node(block);
2859 dbg_info *dbgi = get_irn_dbg_info(node);
2860 ir_node *sel = get_Cond_selector(node);
2861 ir_mode *sel_mode = get_irn_mode(sel);
2862 ir_node *flags = NULL;
2864 ia32_condition_code_t cc;
2866 if (sel_mode != mode_b) {
2867 return create_Switch(node);
2870 /* we get flags from a Cmp */
2871 flags = get_flags_node(sel, &cc);
2873 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc);
2874 SET_IA32_ORIG_NODE(new_node, node);
2880 * Transform a be_Copy.
2882 static ir_node *gen_be_Copy(ir_node *node)
2884 ir_node *new_node = be_duplicate_node(node);
2885 ir_mode *mode = get_irn_mode(new_node);
2887 if (ia32_mode_needs_gp_reg(mode)) {
2888 set_irn_mode(new_node, mode_Iu);
2894 static ir_node *create_Fucom(ir_node *node)
2896 dbg_info *dbgi = get_irn_dbg_info(node);
2897 ir_node *block = get_nodes_block(node);
2898 ir_node *new_block = be_transform_node(block);
2899 ir_node *left = get_Cmp_left(node);
2900 ir_node *new_left = be_transform_node(left);
2901 ir_node *right = get_Cmp_right(node);
2905 if (ia32_cg_config.use_fucomi) {
2906 new_right = be_transform_node(right);
2907 new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
2909 set_ia32_commutative(new_node);
2910 SET_IA32_ORIG_NODE(new_node, node);
2912 if (ia32_cg_config.use_ftst && is_Const_0(right)) {
2913 new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
2915 new_right = be_transform_node(right);
2916 new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2919 set_ia32_commutative(new_node);
2921 SET_IA32_ORIG_NODE(new_node, node);
2923 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2924 SET_IA32_ORIG_NODE(new_node, node);
2930 static ir_node *create_Ucomi(ir_node *node)
2932 dbg_info *dbgi = get_irn_dbg_info(node);
2933 ir_node *src_block = get_nodes_block(node);
2934 ir_node *new_block = be_transform_node(src_block);
2935 ir_node *left = get_Cmp_left(node);
2936 ir_node *right = get_Cmp_right(node);
2938 ia32_address_mode_t am;
2939 ia32_address_t *addr = &am.addr;
2941 match_arguments(&am, src_block, left, right, NULL,
2942 match_commutative | match_am);
2944 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2945 addr->mem, am.new_op1, am.new_op2,
2947 set_am_attributes(new_node, &am);
2949 SET_IA32_ORIG_NODE(new_node, node);
2951 new_node = fix_mem_proj(new_node, &am);
2957 * returns true if it is assured, that the upper bits of a node are "clean"
2958 * which means for a 16 or 8 bit value, that the upper bits in the register
2959 * are 0 for unsigned and a copy of the last significant bit for signed
2962 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
2964 assert(ia32_mode_needs_gp_reg(mode));
2965 if (get_mode_size_bits(mode) >= 32)
2968 if (is_Proj(transformed_node))
2969 return upper_bits_clean(get_Proj_pred(transformed_node), mode);
2971 switch (get_ia32_irn_opcode(transformed_node)) {
2972 case iro_ia32_Conv_I2I:
2973 case iro_ia32_Conv_I2I8Bit: {
2974 ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
2975 if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
2977 if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
2984 if (mode_is_signed(mode)) {
2985 return false; /* TODO handle signed modes */
2987 ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
2988 if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
2989 const ia32_immediate_attr_t *attr
2990 = get_ia32_immediate_attr_const(right);
2991 if (attr->symconst == 0 &&
2992 (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
2996 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
3000 /* TODO too conservative if shift amount is constant */
3001 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
3004 if (!mode_is_signed(mode)) {
3006 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
3007 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
3009 /* TODO if one is known to be zero extended, then || is sufficient */
3014 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
3015 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
3017 case iro_ia32_Const:
3018 case iro_ia32_Immediate: {
3019 const ia32_immediate_attr_t *attr =
3020 get_ia32_immediate_attr_const(transformed_node);
3021 if (mode_is_signed(mode)) {
3022 long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
3023 return shifted == 0 || shifted == -1;
3025 unsigned long shifted = (unsigned long)attr->offset;
3026 shifted >>= get_mode_size_bits(mode)-1;
3028 return shifted == 0;
3038 * Generate code for a Cmp.
3040 static ir_node *gen_Cmp(ir_node *node)
3042 dbg_info *dbgi = get_irn_dbg_info(node);
3043 ir_node *block = get_nodes_block(node);
3044 ir_node *new_block = be_transform_node(block);
3045 ir_node *left = get_Cmp_left(node);
3046 ir_node *right = get_Cmp_right(node);
3047 ir_mode *cmp_mode = get_irn_mode(left);
3049 ia32_address_mode_t am;
3050 ia32_address_t *addr = &am.addr;
3052 if (mode_is_float(cmp_mode)) {
3053 if (ia32_cg_config.use_sse2) {
3054 return create_Ucomi(node);
3056 return create_Fucom(node);
3060 assert(ia32_mode_needs_gp_reg(cmp_mode));
3062 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
3063 if (is_Const_0(right) &&
3065 get_irn_n_edges(left) == 1) {
3066 /* Test(and_left, and_right) */
3067 ir_node *and_left = get_And_left(left);
3068 ir_node *and_right = get_And_right(left);
3070 /* matze: code here used mode instead of cmd_mode, I think it is always
3071 * the same as cmp_mode, but I leave this here to see if this is really
3074 assert(get_irn_mode(and_left) == cmp_mode);
3076 match_arguments(&am, block, and_left, and_right, NULL,
3078 match_am | match_8bit_am | match_16bit_am |
3079 match_am_and_immediates | match_immediate);
3081 /* use 32bit compare mode if possible since the opcode is smaller */
3082 if (upper_bits_clean(am.new_op1, cmp_mode) &&
3083 upper_bits_clean(am.new_op2, cmp_mode)) {
3084 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
3087 if (get_mode_size_bits(cmp_mode) == 8) {
3088 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
3089 addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
3091 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
3092 addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
3095 /* Cmp(left, right) */
3096 match_arguments(&am, block, left, right, NULL,
3097 match_commutative | match_am | match_8bit_am |
3098 match_16bit_am | match_am_and_immediates |
3100 /* use 32bit compare mode if possible since the opcode is smaller */
3101 if (upper_bits_clean(am.new_op1, cmp_mode) &&
3102 upper_bits_clean(am.new_op2, cmp_mode)) {
3103 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
3106 if (get_mode_size_bits(cmp_mode) == 8) {
3107 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
3108 addr->index, addr->mem, am.new_op1,
3109 am.new_op2, am.ins_permuted);
3111 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
3112 addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
3115 set_am_attributes(new_node, &am);
3116 set_ia32_ls_mode(new_node, cmp_mode);
3118 SET_IA32_ORIG_NODE(new_node, node);
3120 new_node = fix_mem_proj(new_node, &am);
3125 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
3126 ia32_condition_code_t cc)
3128 dbg_info *dbgi = get_irn_dbg_info(node);
3129 ir_node *block = get_nodes_block(node);
3130 ir_node *new_block = be_transform_node(block);
3131 ir_node *val_true = get_Mux_true(node);
3132 ir_node *val_false = get_Mux_false(node);
3134 ia32_address_mode_t am;
3135 ia32_address_t *addr;
3137 assert(ia32_cg_config.use_cmov);
3138 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
3142 match_arguments(&am, block, val_false, val_true, flags,
3143 match_commutative | match_am | match_16bit_am | match_mode_neutral);
3145 if (am.ins_permuted)
3146 cc = ia32_negate_condition_code(cc);
3148 new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
3149 addr->mem, am.new_op1, am.new_op2, new_flags,
3151 set_am_attributes(new_node, &am);
3153 SET_IA32_ORIG_NODE(new_node, node);
3155 new_node = fix_mem_proj(new_node, &am);
3161 * Creates a ia32 Setcc instruction.
3163 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
3164 ir_node *flags, ia32_condition_code_t cc,
3167 ir_mode *mode = get_irn_mode(orig_node);
3170 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc);
3171 SET_IA32_ORIG_NODE(new_node, orig_node);
3173 /* we might need to conv the result up */
3174 if (get_mode_size_bits(mode) > 8) {
3175 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
3176 nomem, new_node, mode_Bu);
3177 SET_IA32_ORIG_NODE(new_node, orig_node);
3184 * Create instruction for an unsigned Difference or Zero.
3186 static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
3188 ir_mode *mode = get_irn_mode(psi);
3198 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
3199 match_mode_neutral | match_am | match_immediate | match_two_users);
3201 block = get_nodes_block(new_node);
3203 if (is_Proj(new_node)) {
3204 sub = get_Proj_pred(new_node);
3207 set_irn_mode(sub, mode_T);
3208 new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res);
3210 assert(is_ia32_Sub(sub));
3211 eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
3213 dbgi = get_irn_dbg_info(psi);
3214 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
3215 notn = new_bd_ia32_Not(dbgi, block, sbb);
3217 new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
3218 set_ia32_commutative(new_node);
3223 * Create an const array of two float consts.
3225 * @param c0 the first constant
3226 * @param c1 the second constant
3227 * @param new_mode IN/OUT for the mode of the constants, if NULL
3228 * smallest possible mode will be used
3230 static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode)
3233 ir_mode *mode = *new_mode;
3235 ir_initializer_t *initializer;
3236 ir_tarval *tv0 = get_Const_tarval(c0);
3237 ir_tarval *tv1 = get_Const_tarval(c1);
3240 /* detect the best mode for the constants */
3241 mode = get_tarval_mode(tv0);
3243 if (mode != mode_F) {
3244 if (tarval_ieee754_can_conv_lossless(tv0, mode_F) &&
3245 tarval_ieee754_can_conv_lossless(tv1, mode_F)) {
3247 tv0 = tarval_convert_to(tv0, mode);
3248 tv1 = tarval_convert_to(tv1, mode);
3249 } else if (mode != mode_D) {
3250 if (tarval_ieee754_can_conv_lossless(tv0, mode_D) &&
3251 tarval_ieee754_can_conv_lossless(tv1, mode_D)) {
3253 tv0 = tarval_convert_to(tv0, mode);
3254 tv1 = tarval_convert_to(tv1, mode);
3261 tp = ia32_create_float_type(mode, 4);
3262 tp = ia32_create_float_array(tp);
3264 ent = new_entity(get_glob_type(), id_unique("C%u"), tp);
3266 set_entity_ld_ident(ent, get_entity_ident(ent));
3267 set_entity_visibility(ent, ir_visibility_private);
3268 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
3270 initializer = create_initializer_compound(2);
3272 set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0));
3273 set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1));
3275 set_entity_initializer(ent, initializer);
3282 * Possible transformations for creating a Setcc.
3284 enum setcc_transform_insn {
3297 typedef struct setcc_transform {
3299 ia32_condition_code_t cc;
3301 enum setcc_transform_insn transform;
3305 } setcc_transform_t;
3308 * Setcc can only handle 0 and 1 result.
3309 * Find a transformation that creates 0 and 1 from
3312 static void find_const_transform(ia32_condition_code_t cc,
3313 ir_tarval *t, ir_tarval *f,
3314 setcc_transform_t *res)
3320 if (tarval_is_null(t)) {
3324 cc = ia32_negate_condition_code(cc);
3325 } else if (tarval_cmp(t, f) == ir_relation_less) {
3326 // now, t is the bigger one
3330 cc = ia32_negate_condition_code(cc);
3334 if (! tarval_is_null(f)) {
3335 ir_tarval *t_sub = tarval_sub(t, f, NULL);
3338 res->steps[step].transform = SETCC_TR_ADD;
3340 if (t == tarval_bad)
3341 panic("constant subtract failed");
3342 if (! tarval_is_long(f))
3343 panic("tarval is not long");
3345 res->steps[step].val = get_tarval_long(f);
3347 f = tarval_sub(f, f, NULL);
3348 assert(tarval_is_null(f));
3351 if (tarval_is_one(t)) {
3352 res->steps[step].transform = SETCC_TR_SET;
3353 res->num_steps = ++step;
3357 if (tarval_is_minus_one(t)) {
3358 res->steps[step].transform = SETCC_TR_NEG;
3360 res->steps[step].transform = SETCC_TR_SET;
3361 res->num_steps = ++step;
3364 if (tarval_is_long(t)) {
3365 long v = get_tarval_long(t);
3367 res->steps[step].val = 0;
3370 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3372 res->steps[step].transform = SETCC_TR_LEAxx;
3373 res->steps[step].scale = 3; /* (a << 3) + a */
3376 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3378 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3379 res->steps[step].scale = 3; /* (a << 3) */
3382 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3384 res->steps[step].transform = SETCC_TR_LEAxx;
3385 res->steps[step].scale = 2; /* (a << 2) + a */
3388 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3390 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3391 res->steps[step].scale = 2; /* (a << 2) */
3394 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3396 res->steps[step].transform = SETCC_TR_LEAxx;
3397 res->steps[step].scale = 1; /* (a << 1) + a */
3400 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3402 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3403 res->steps[step].scale = 1; /* (a << 1) */
3406 res->num_steps = step;
3409 if (! tarval_is_single_bit(t)) {
3410 res->steps[step].transform = SETCC_TR_AND;
3411 res->steps[step].val = v;
3413 res->steps[step].transform = SETCC_TR_NEG;
3415 int val = get_tarval_lowest_bit(t);
3418 res->steps[step].transform = SETCC_TR_SHL;
3419 res->steps[step].scale = val;
3423 res->steps[step].transform = SETCC_TR_SET;
3424 res->num_steps = ++step;
3427 panic("tarval is not long");
3431 * Transforms a Mux node into some code sequence.
3433 * @return The transformed node.
3435 static ir_node *gen_Mux(ir_node *node)
3437 dbg_info *dbgi = get_irn_dbg_info(node);
3438 ir_node *block = get_nodes_block(node);
3439 ir_node *new_block = be_transform_node(block);
3440 ir_node *mux_true = get_Mux_true(node);
3441 ir_node *mux_false = get_Mux_false(node);
3442 ir_node *sel = get_Mux_sel(node);
3443 ir_mode *mode = get_irn_mode(node);
3447 ia32_condition_code_t cc;
3449 assert(get_irn_mode(sel) == mode_b);
3451 is_abs = ir_mux_is_abs(sel, mux_false, mux_true);
3453 if (ia32_mode_needs_gp_reg(mode)) {
3454 ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n",
3457 ir_node *op = ir_get_abs_op(sel, mux_false, mux_true);
3458 return create_float_abs(dbgi, block, op, is_abs < 0, node);
3462 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
3463 if (mode_is_float(mode)) {
3464 ir_node *cmp_left = get_Cmp_left(sel);
3465 ir_node *cmp_right = get_Cmp_right(sel);
3466 ir_relation relation = get_Cmp_relation(sel);
3468 if (ia32_cg_config.use_sse2) {
3469 if (relation == ir_relation_less || relation == ir_relation_less_equal) {
3470 if (cmp_left == mux_true && cmp_right == mux_false) {
3471 /* Mux(a <= b, a, b) => MIN */
3472 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3473 match_commutative | match_am | match_two_users);
3474 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3475 /* Mux(a <= b, b, a) => MAX */
3476 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3477 match_commutative | match_am | match_two_users);
3479 } else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) {
3480 if (cmp_left == mux_true && cmp_right == mux_false) {
3481 /* Mux(a >= b, a, b) => MAX */
3482 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3483 match_commutative | match_am | match_two_users);
3484 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3485 /* Mux(a >= b, b, a) => MIN */
3486 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3487 match_commutative | match_am | match_two_users);
3492 if (is_Const(mux_true) && is_Const(mux_false)) {
3493 ia32_address_mode_t am;
3498 flags = get_flags_node(sel, &cc);
3499 new_node = create_set_32bit(dbgi, new_block, flags, cc, node);
3501 if (ia32_cg_config.use_sse2) {
3502 /* cannot load from different mode on SSE */
3505 /* x87 can load any mode */
3509 am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
3511 switch (get_mode_size_bytes(new_mode)) {
3521 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3522 set_ia32_am_scale(new_node, 2);
3527 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3528 set_ia32_am_scale(new_node, 1);
3531 /* arg, shift 16 NOT supported */
3533 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3536 panic("Unsupported constant size");
3539 am.ls_mode = new_mode;
3540 am.addr.base = get_symconst_base();
3541 am.addr.index = new_node;
3542 am.addr.mem = nomem;
3544 am.addr.scale = scale;
3545 am.addr.use_frame = 0;
3546 am.addr.tls_segment = false;
3547 am.addr.frame_entity = NULL;
3548 am.addr.symconst_sign = 0;
3549 am.mem_proj = am.addr.mem;
3550 am.op_type = ia32_AddrModeS;
3553 am.pinned = op_pin_state_floats;
3555 am.ins_permuted = false;
3557 if (ia32_cg_config.use_sse2)
3558 load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3560 load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3561 set_am_attributes(load, &am);
3563 return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
3565 panic("cannot transform floating point Mux");
3568 assert(ia32_mode_needs_gp_reg(mode));
3571 ir_node *cmp_left = get_Cmp_left(sel);
3572 ir_node *cmp_right = get_Cmp_right(sel);
3573 ir_relation relation = get_Cmp_relation(sel);
3574 ir_node *val_true = mux_true;
3575 ir_node *val_false = mux_false;
3577 if (is_Const(val_true) && is_Const_null(val_true)) {
3578 ir_node *tmp = val_false;
3579 val_false = val_true;
3581 relation = get_negated_relation(relation);
3583 if (is_Const_0(val_false) && is_Sub(val_true)) {
3584 if ((relation & ir_relation_greater)
3585 && get_Sub_left(val_true) == cmp_left
3586 && get_Sub_right(val_true) == cmp_right) {
3587 return create_doz(node, cmp_left, cmp_right);
3589 if ((relation & ir_relation_less)
3590 && get_Sub_left(val_true) == cmp_right
3591 && get_Sub_right(val_true) == cmp_left) {
3592 return create_doz(node, cmp_right, cmp_left);
3597 flags = get_flags_node(sel, &cc);
3599 if (is_Const(mux_true) && is_Const(mux_false)) {
3600 /* both are const, good */
3601 ir_tarval *tv_true = get_Const_tarval(mux_true);
3602 ir_tarval *tv_false = get_Const_tarval(mux_false);
3603 setcc_transform_t res;
3606 find_const_transform(cc, tv_true, tv_false, &res);
3608 for (step = (int)res.num_steps - 1; step >= 0; --step) {
3611 switch (res.steps[step].transform) {
3613 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP);
3614 add_ia32_am_offs_int(new_node, res.steps[step].val);
3616 case SETCC_TR_ADDxx:
3617 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3620 new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node);
3621 set_ia32_am_scale(new_node, res.steps[step].scale);
3622 set_ia32_am_offs_int(new_node, res.steps[step].val);
3624 case SETCC_TR_LEAxx:
3625 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3626 set_ia32_am_scale(new_node, res.steps[step].scale);
3627 set_ia32_am_offs_int(new_node, res.steps[step].val);
3630 imm = ia32_immediate_from_long(res.steps[step].scale);
3631 new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
3634 new_node = new_bd_ia32_Neg(dbgi, new_block, new_node);
3637 new_node = new_bd_ia32_Not(dbgi, new_block, new_node);
3640 imm = ia32_immediate_from_long(res.steps[step].val);
3641 new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
3644 new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
3647 new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
3650 panic("unknown setcc transform");
3654 new_node = create_CMov(node, sel, flags, cc);
3661 * Create a conversion from x87 state register to general purpose.
3663 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3665 ir_node *block = be_transform_node(get_nodes_block(node));
3666 ir_node *op = get_Conv_op(node);
3667 ir_node *new_op = be_transform_node(op);
3668 ir_graph *irg = current_ir_graph;
3669 dbg_info *dbgi = get_irn_dbg_info(node);
3670 ir_mode *mode = get_irn_mode(node);
3671 ir_node *frame = get_irg_frame(irg);
3672 ir_node *fist, *load, *mem;
3674 fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op);
3675 set_irn_pinned(fist, op_pin_state_floats);
3676 set_ia32_use_frame(fist);
3677 set_ia32_op_type(fist, ia32_AddrModeD);
3679 assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
3680 mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
3682 assert(get_mode_size_bits(mode) <= 32);
3683 /* exception we can only store signed 32 bit integers, so for unsigned
3684 we store a 64bit (signed) integer and load the lower bits */
3685 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3686 set_ia32_ls_mode(fist, mode_Ls);
3688 set_ia32_ls_mode(fist, mode_Is);
3690 SET_IA32_ORIG_NODE(fist, node);
3693 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem);
3695 set_irn_pinned(load, op_pin_state_floats);
3696 set_ia32_use_frame(load);
3697 set_ia32_op_type(load, ia32_AddrModeS);
3698 set_ia32_ls_mode(load, mode_Is);
3699 if (get_ia32_ls_mode(fist) == mode_Ls) {
3700 ia32_attr_t *attr = get_ia32_attr(load);
3701 attr->data.need_64bit_stackent = 1;
3703 ia32_attr_t *attr = get_ia32_attr(load);
3704 attr->data.need_32bit_stackent = 1;
3706 SET_IA32_ORIG_NODE(load, node);
3708 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
3712 * Creates a x87 strict Conv by placing a Store and a Load
3714 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3716 ir_node *block = get_nodes_block(node);
3717 ir_graph *irg = get_Block_irg(block);
3718 dbg_info *dbgi = get_irn_dbg_info(node);
3719 ir_node *frame = get_irg_frame(irg);
3721 ir_node *store, *load;
3724 store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
3725 set_ia32_use_frame(store);
3726 set_ia32_op_type(store, ia32_AddrModeD);
3727 SET_IA32_ORIG_NODE(store, node);
3729 store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
3731 load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
3732 set_ia32_use_frame(load);
3733 set_ia32_op_type(load, ia32_AddrModeS);
3734 SET_IA32_ORIG_NODE(load, node);
3736 new_node = new_r_Proj(load, mode_E, pn_ia32_vfld_res);
3740 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3741 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3743 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3745 func = get_mode_size_bits(mode) == 8 ?
3746 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3747 return func(dbgi, block, base, index, mem, val, mode);
3751 * Create a conversion from general purpose to x87 register
3753 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3755 ir_node *src_block = get_nodes_block(node);
3756 ir_node *block = be_transform_node(src_block);
3757 ir_graph *irg = get_Block_irg(block);
3758 dbg_info *dbgi = get_irn_dbg_info(node);
3759 ir_node *op = get_Conv_op(node);
3760 ir_node *new_op = NULL;
3762 ir_mode *store_mode;
3768 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3769 if (possible_int_mode_for_fp(src_mode)) {
3770 ia32_address_mode_t am;
3772 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
3773 if (am.op_type == ia32_AddrModeS) {
3774 ia32_address_t *addr = &am.addr;
3776 fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
3777 new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
3779 set_am_attributes(fild, &am);
3780 SET_IA32_ORIG_NODE(fild, node);
3782 fix_mem_proj(fild, &am);
3787 if (new_op == NULL) {
3788 new_op = be_transform_node(op);
3791 mode = get_irn_mode(op);
3793 /* first convert to 32 bit signed if necessary */
3794 if (get_mode_size_bits(src_mode) < 32) {
3795 if (!upper_bits_clean(new_op, src_mode)) {
3796 new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
3797 SET_IA32_ORIG_NODE(new_op, node);
3802 assert(get_mode_size_bits(mode) == 32);
3805 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op);
3807 set_ia32_use_frame(store);
3808 set_ia32_op_type(store, ia32_AddrModeD);
3809 set_ia32_ls_mode(store, mode_Iu);
3811 store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
3813 /* exception for 32bit unsigned, do a 64bit spill+load */
3814 if (!mode_is_signed(mode)) {
3817 ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
3819 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3820 noreg_GP, nomem, zero_const);
3821 ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M);
3823 set_ia32_use_frame(zero_store);
3824 set_ia32_op_type(zero_store, ia32_AddrModeD);
3825 add_ia32_am_offs_int(zero_store, 4);
3826 set_ia32_ls_mode(zero_store, mode_Iu);
3828 in[0] = zero_store_mem;
3831 store_mem = new_rd_Sync(dbgi, block, 2, in);
3832 store_mode = mode_Ls;
3834 store_mode = mode_Is;
3838 fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
3840 set_ia32_use_frame(fild);
3841 set_ia32_op_type(fild, ia32_AddrModeS);
3842 set_ia32_ls_mode(fild, store_mode);
3844 new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
3850 * Create a conversion from one integer mode into another one
3852 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3853 dbg_info *dbgi, ir_node *block, ir_node *op,
3856 ir_node *new_block = be_transform_node(block);
3858 ir_mode *smaller_mode;
3859 ia32_address_mode_t am;
3860 ia32_address_t *addr = &am.addr;
3863 if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
3864 smaller_mode = src_mode;
3866 smaller_mode = tgt_mode;
3869 #ifdef DEBUG_libfirm
3871 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3876 match_arguments(&am, block, NULL, op, NULL,
3877 match_am | match_8bit_am | match_16bit_am);
3879 if (upper_bits_clean(am.new_op2, smaller_mode)) {
3880 /* unnecessary conv. in theory it shouldn't have been AM */
3881 assert(is_ia32_NoReg_GP(addr->base));
3882 assert(is_ia32_NoReg_GP(addr->index));
3883 assert(is_NoMem(addr->mem));
3884 assert(am.addr.offset == 0);
3885 assert(am.addr.symconst_ent == NULL);
3889 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3890 addr->mem, am.new_op2, smaller_mode);
3891 set_am_attributes(new_node, &am);
3892 /* match_arguments assume that out-mode = in-mode, this isn't true here
3894 set_ia32_ls_mode(new_node, smaller_mode);
3895 SET_IA32_ORIG_NODE(new_node, node);
3896 new_node = fix_mem_proj(new_node, &am);
3901 * Transforms a Conv node.
3903 * @return The created ia32 Conv node
3905 static ir_node *gen_Conv(ir_node *node)
3907 ir_node *block = get_nodes_block(node);
3908 ir_node *new_block = be_transform_node(block);
3909 ir_node *op = get_Conv_op(node);
3910 ir_node *new_op = NULL;
3911 dbg_info *dbgi = get_irn_dbg_info(node);
3912 ir_mode *src_mode = get_irn_mode(op);
3913 ir_mode *tgt_mode = get_irn_mode(node);
3914 int src_bits = get_mode_size_bits(src_mode);
3915 int tgt_bits = get_mode_size_bits(tgt_mode);
3916 ir_node *res = NULL;
3918 assert(!mode_is_int(src_mode) || src_bits <= 32);
3919 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3921 /* modeB -> X should already be lowered by the lower_mode_b pass */
3922 if (src_mode == mode_b) {
3923 panic("ConvB not lowered %+F", node);
3926 if (src_mode == tgt_mode) {
3927 if (get_Conv_strict(node)) {
3928 if (ia32_cg_config.use_sse2) {
3929 /* when we are in SSE mode, we can kill all strict no-op conversion */
3930 return be_transform_node(op);
3933 /* this should be optimized already, but who knows... */
3934 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);)
3935 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3936 return be_transform_node(op);
3940 if (mode_is_float(src_mode)) {
3941 new_op = be_transform_node(op);
3942 /* we convert from float ... */
3943 if (mode_is_float(tgt_mode)) {
3945 if (ia32_cg_config.use_sse2) {
3946 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3947 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP,
3949 set_ia32_ls_mode(res, tgt_mode);
3951 if (get_Conv_strict(node)) {
3952 /* if fp_no_float_fold is not set then we assume that we
3953 * don't have any float operations in a non
3954 * mode_float_arithmetic mode and can skip strict upconvs */
3955 if (src_bits < tgt_bits) {
3956 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3959 res = gen_x87_strict_conv(tgt_mode, new_op);
3960 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3964 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3969 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3970 if (ia32_cg_config.use_sse2) {
3971 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP,
3973 set_ia32_ls_mode(res, src_mode);
3975 return gen_x87_fp_to_gp(node);
3979 /* we convert from int ... */
3980 if (mode_is_float(tgt_mode)) {
3982 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3983 if (ia32_cg_config.use_sse2) {
3984 new_op = be_transform_node(op);
3985 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP,
3987 set_ia32_ls_mode(res, tgt_mode);
3989 unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3990 unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode);
3991 res = gen_x87_gp_to_fp(node, src_mode);
3993 /* we need a strict-Conv, if the int mode has more bits than the
3995 if (float_mantissa < int_mantissa) {
3996 res = gen_x87_strict_conv(tgt_mode, res);
3997 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
4001 } else if (tgt_mode == mode_b) {
4002 /* mode_b lowering already took care that we only have 0/1 values */
4003 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
4004 src_mode, tgt_mode));
4005 return be_transform_node(op);
4008 if (src_bits == tgt_bits) {
4009 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
4010 src_mode, tgt_mode));
4011 return be_transform_node(op);
4014 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
4022 static ir_node *create_immediate_or_transform(ir_node *node,
4023 char immediate_constraint_type)
4025 ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
4026 if (new_node == NULL) {
4027 new_node = be_transform_node(node);
4033 * Transforms a FrameAddr into an ia32 Add.
4035 static ir_node *gen_be_FrameAddr(ir_node *node)
4037 ir_node *block = be_transform_node(get_nodes_block(node));
4038 ir_node *op = be_get_FrameAddr_frame(node);
4039 ir_node *new_op = be_transform_node(op);
4040 dbg_info *dbgi = get_irn_dbg_info(node);
4043 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP);
4044 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
4045 set_ia32_use_frame(new_node);
4047 SET_IA32_ORIG_NODE(new_node, node);
4053 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
4055 static ir_node *gen_be_Return(ir_node *node)
4057 ir_graph *irg = current_ir_graph;
4058 ir_node *ret_val = get_irn_n(node, n_be_Return_val);
4059 ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
4060 ir_node *new_ret_val = be_transform_node(ret_val);
4061 ir_node *new_ret_mem = be_transform_node(ret_mem);
4062 ir_entity *ent = get_irg_entity(irg);
4063 ir_type *tp = get_entity_type(ent);
4064 dbg_info *dbgi = get_irn_dbg_info(node);
4065 ir_node *block = be_transform_node(get_nodes_block(node));
4079 assert(ret_val != NULL);
4080 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
4081 return be_duplicate_node(node);
4084 res_type = get_method_res_type(tp, 0);
4086 if (! is_Primitive_type(res_type)) {
4087 return be_duplicate_node(node);
4090 mode = get_type_mode(res_type);
4091 if (! mode_is_float(mode)) {
4092 return be_duplicate_node(node);
4095 assert(get_method_n_ress(tp) == 1);
4097 frame = get_irg_frame(irg);
4099 /* store xmm0 onto stack */
4100 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
4101 new_ret_mem, new_ret_val);
4102 set_ia32_ls_mode(sse_store, mode);
4103 set_ia32_op_type(sse_store, ia32_AddrModeD);
4104 set_ia32_use_frame(sse_store);
4105 store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
4107 /* load into x87 register */
4108 fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode);
4109 set_ia32_op_type(fld, ia32_AddrModeS);
4110 set_ia32_use_frame(fld);
4112 mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
4113 fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
4115 /* create a new return */
4116 arity = get_irn_arity(node);
4117 in = ALLOCAN(ir_node*, arity);
4118 pop = be_Return_get_pop(node);
4119 for (i = 0; i < arity; ++i) {
4120 ir_node *op = get_irn_n(node, i);
4121 if (op == ret_val) {
4123 } else if (op == ret_mem) {
4126 in[i] = be_transform_node(op);
4129 new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
4130 copy_node_attr(irg, node, new_node);
4136 * Transform a be_AddSP into an ia32_SubSP.
4138 static ir_node *gen_be_AddSP(ir_node *node)
4140 ir_node *sz = get_irn_n(node, n_be_AddSP_size);
4141 ir_node *sp = get_irn_n(node, n_be_AddSP_old_sp);
4143 ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP,
4144 match_am | match_immediate);
4145 assert(is_ia32_SubSP(new_node));
4146 arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack,
4147 &ia32_registers[REG_ESP]);
4152 * Transform a be_SubSP into an ia32_AddSP
4154 static ir_node *gen_be_SubSP(ir_node *node)
4156 ir_node *sz = get_irn_n(node, n_be_SubSP_size);
4157 ir_node *sp = get_irn_n(node, n_be_SubSP_old_sp);
4159 ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP,
4160 match_am | match_immediate);
4161 assert(is_ia32_AddSP(new_node));
4162 arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack,
4163 &ia32_registers[REG_ESP]);
4168 * Change some phi modes
4170 static ir_node *gen_Phi(ir_node *node)
4172 const arch_register_req_t *req;
4173 ir_node *block = be_transform_node(get_nodes_block(node));
4174 ir_graph *irg = current_ir_graph;
4175 dbg_info *dbgi = get_irn_dbg_info(node);
4176 ir_mode *mode = get_irn_mode(node);
4179 if (ia32_mode_needs_gp_reg(mode)) {
4180 /* we shouldn't have any 64bit stuff around anymore */
4181 assert(get_mode_size_bits(mode) <= 32);
4182 /* all integer operations are on 32bit registers now */
4184 req = ia32_reg_classes[CLASS_ia32_gp].class_req;
4185 } else if (mode_is_float(mode)) {
4186 if (ia32_cg_config.use_sse2) {
4188 req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
4191 req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
4194 req = arch_no_register_req;
4197 /* phi nodes allow loops, so we use the old arguments for now
4198 * and fix this later */
4199 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
4200 get_irn_in(node) + 1);
4201 copy_node_attr(irg, node, phi);
4202 be_duplicate_deps(node, phi);
4204 arch_set_irn_register_req_out(phi, 0, req);
4206 be_enqueue_preds(node);
4211 static ir_node *gen_Jmp(ir_node *node)
4213 ir_node *block = get_nodes_block(node);
4214 ir_node *new_block = be_transform_node(block);
4215 dbg_info *dbgi = get_irn_dbg_info(node);
4218 new_node = new_bd_ia32_Jmp(dbgi, new_block);
4219 SET_IA32_ORIG_NODE(new_node, node);
4227 static ir_node *gen_IJmp(ir_node *node)
4229 ir_node *block = get_nodes_block(node);
4230 ir_node *new_block = be_transform_node(block);
4231 dbg_info *dbgi = get_irn_dbg_info(node);
4232 ir_node *op = get_IJmp_target(node);
4234 ia32_address_mode_t am;
4235 ia32_address_t *addr = &am.addr;
4237 assert(get_irn_mode(op) == mode_P);
4239 match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
4241 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
4242 addr->mem, am.new_op2);
4243 set_am_attributes(new_node, &am);
4244 SET_IA32_ORIG_NODE(new_node, node);
4246 new_node = fix_mem_proj(new_node, &am);
4251 static ir_node *gen_ia32_l_Add(ir_node *node)
4253 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4254 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4255 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
4256 match_commutative | match_am | match_immediate |
4257 match_mode_neutral);
4259 if (is_Proj(lowered)) {
4260 lowered = get_Proj_pred(lowered);
4262 assert(is_ia32_Add(lowered));
4263 set_irn_mode(lowered, mode_T);
4269 static ir_node *gen_ia32_l_Adc(ir_node *node)
4271 return gen_binop_flags(node, new_bd_ia32_Adc,
4272 match_commutative | match_am | match_immediate |
4273 match_mode_neutral);
4277 * Transforms a l_MulS into a "real" MulS node.
4279 * @return the created ia32 Mul node
4281 static ir_node *gen_ia32_l_Mul(ir_node *node)
4283 ir_node *left = get_binop_left(node);
4284 ir_node *right = get_binop_right(node);
4286 return gen_binop(node, left, right, new_bd_ia32_Mul,
4287 match_commutative | match_am | match_mode_neutral);
4291 * Transforms a l_IMulS into a "real" IMul1OPS node.
4293 * @return the created ia32 IMul1OP node
4295 static ir_node *gen_ia32_l_IMul(ir_node *node)
4297 ir_node *left = get_binop_left(node);
4298 ir_node *right = get_binop_right(node);
4300 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
4301 match_commutative | match_am | match_mode_neutral);
4304 static ir_node *gen_ia32_l_Sub(ir_node *node)
4306 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4307 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4308 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
4309 match_am | match_immediate | match_mode_neutral);
4311 if (is_Proj(lowered)) {
4312 lowered = get_Proj_pred(lowered);
4314 assert(is_ia32_Sub(lowered));
4315 set_irn_mode(lowered, mode_T);
4321 static ir_node *gen_ia32_l_Sbb(ir_node *node)
4323 return gen_binop_flags(node, new_bd_ia32_Sbb,
4324 match_am | match_immediate | match_mode_neutral);
4327 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
4329 ir_node *src_block = get_nodes_block(node);
4330 ir_node *block = be_transform_node(src_block);
4331 ir_graph *irg = current_ir_graph;
4332 dbg_info *dbgi = get_irn_dbg_info(node);
4333 ir_node *frame = get_irg_frame(irg);
4334 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4335 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4336 ir_node *new_val_low = be_transform_node(val_low);
4337 ir_node *new_val_high = be_transform_node(val_high);
4339 ir_node *sync, *fild, *res;
4341 ir_node *store_high;
4345 if (ia32_cg_config.use_sse2) {
4346 panic("ia32_l_LLtoFloat not implemented for SSE2");
4350 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4352 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4354 SET_IA32_ORIG_NODE(store_low, node);
4355 SET_IA32_ORIG_NODE(store_high, node);
4357 mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M);
4358 mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M);
4360 set_ia32_use_frame(store_low);
4361 set_ia32_use_frame(store_high);
4362 set_ia32_op_type(store_low, ia32_AddrModeD);
4363 set_ia32_op_type(store_high, ia32_AddrModeD);
4364 set_ia32_ls_mode(store_low, mode_Iu);
4365 set_ia32_ls_mode(store_high, mode_Is);
4366 add_ia32_am_offs_int(store_high, 4);
4370 sync = new_rd_Sync(dbgi, block, 2, in);
4373 fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
4375 set_ia32_use_frame(fild);
4376 set_ia32_op_type(fild, ia32_AddrModeS);
4377 set_ia32_ls_mode(fild, mode_Ls);
4379 SET_IA32_ORIG_NODE(fild, node);
4381 res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
4383 if (! mode_is_signed(get_irn_mode(val_high))) {
4384 ia32_address_mode_t am;
4386 ir_node *count = ia32_create_Immediate(NULL, 0, 31);
4389 am.addr.base = get_symconst_base();
4390 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
4391 am.addr.mem = nomem;
4394 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
4395 am.addr.tls_segment = false;
4396 am.addr.use_frame = 0;
4397 am.addr.frame_entity = NULL;
4398 am.addr.symconst_sign = 0;
4399 am.ls_mode = mode_F;
4400 am.mem_proj = nomem;
4401 am.op_type = ia32_AddrModeS;
4403 am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
4404 am.pinned = op_pin_state_floats;
4406 am.ins_permuted = false;
4408 fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
4409 am.new_op1, am.new_op2, get_fpcw());
4410 set_am_attributes(fadd, &am);
4412 set_irn_mode(fadd, mode_T);
4413 res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
4418 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
4420 ir_node *src_block = get_nodes_block(node);
4421 ir_node *block = be_transform_node(src_block);
4422 ir_graph *irg = get_Block_irg(block);
4423 dbg_info *dbgi = get_irn_dbg_info(node);
4424 ir_node *frame = get_irg_frame(irg);
4425 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4426 ir_node *new_val = be_transform_node(val);
4429 fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val);
4430 SET_IA32_ORIG_NODE(fist, node);
4431 set_ia32_use_frame(fist);
4432 set_ia32_op_type(fist, ia32_AddrModeD);
4433 set_ia32_ls_mode(fist, mode_Ls);
4435 assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
4436 return new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
4439 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
4441 ir_node *block = be_transform_node(get_nodes_block(node));
4442 ir_graph *irg = get_Block_irg(block);
4443 ir_node *pred = get_Proj_pred(node);
4444 ir_node *new_pred = be_transform_node(pred);
4445 ir_node *frame = get_irg_frame(irg);
4446 dbg_info *dbgi = get_irn_dbg_info(node);
4447 long pn = get_Proj_proj(node);
4452 load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred);
4453 SET_IA32_ORIG_NODE(load, node);
4454 set_ia32_use_frame(load);
4455 set_ia32_op_type(load, ia32_AddrModeS);
4456 set_ia32_ls_mode(load, mode_Iu);
4457 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4458 * 32 bit from it with this particular load */
4459 attr = get_ia32_attr(load);
4460 attr->data.need_64bit_stackent = 1;
4462 if (pn == pn_ia32_l_FloattoLL_res_high) {
4463 add_ia32_am_offs_int(load, 4);
4465 assert(pn == pn_ia32_l_FloattoLL_res_low);
4468 proj = new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4474 * Transform the Projs of an AddSP.
4476 static ir_node *gen_Proj_be_AddSP(ir_node *node)
4478 ir_node *pred = get_Proj_pred(node);
4479 ir_node *new_pred = be_transform_node(pred);
4480 dbg_info *dbgi = get_irn_dbg_info(node);
4481 long proj = get_Proj_proj(node);
4483 if (proj == pn_be_AddSP_sp) {
4484 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4485 pn_ia32_SubSP_stack);
4486 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4488 } else if (proj == pn_be_AddSP_res) {
4489 return new_rd_Proj(dbgi, new_pred, mode_Iu,
4490 pn_ia32_SubSP_addr);
4491 } else if (proj == pn_be_AddSP_M) {
4492 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_SubSP_M);
4495 panic("No idea how to transform proj->AddSP");
4499 * Transform the Projs of a SubSP.
4501 static ir_node *gen_Proj_be_SubSP(ir_node *node)
4503 ir_node *pred = get_Proj_pred(node);
4504 ir_node *new_pred = be_transform_node(pred);
4505 dbg_info *dbgi = get_irn_dbg_info(node);
4506 long proj = get_Proj_proj(node);
4508 if (proj == pn_be_SubSP_sp) {
4509 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4510 pn_ia32_AddSP_stack);
4511 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4513 } else if (proj == pn_be_SubSP_M) {
4514 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M);
4517 panic("No idea how to transform proj->SubSP");
4521 * Transform and renumber the Projs from a Load.
4523 static ir_node *gen_Proj_Load(ir_node *node)
4526 ir_node *pred = get_Proj_pred(node);
4527 dbg_info *dbgi = get_irn_dbg_info(node);
4528 long proj = get_Proj_proj(node);
4530 /* loads might be part of source address mode matches, so we don't
4531 * transform the ProjMs yet (with the exception of loads whose result is
4534 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4537 /* this is needed, because sometimes we have loops that are only
4538 reachable through the ProjM */
4539 be_enqueue_preds(node);
4540 /* do it in 2 steps, to silence firm verifier */
4541 res = new_rd_Proj(dbgi, pred, mode_M, pn_Load_M);
4542 set_Proj_proj(res, pn_ia32_mem);
4546 /* renumber the proj */
4547 new_pred = be_transform_node(pred);
4548 if (is_ia32_Load(new_pred)) {
4549 switch ((pn_Load)proj) {
4551 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
4553 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
4554 case pn_Load_X_except:
4555 /* This Load might raise an exception. Mark it. */
4556 set_ia32_exc_label(new_pred, 1);
4557 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except);
4558 case pn_Load_X_regular:
4559 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
4561 } else if (is_ia32_Conv_I2I(new_pred) ||
4562 is_ia32_Conv_I2I8Bit(new_pred)) {
4563 set_irn_mode(new_pred, mode_T);
4564 switch ((pn_Load)proj) {
4566 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
4568 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
4569 case pn_Load_X_except:
4570 /* This Load might raise an exception. Mark it. */
4571 set_ia32_exc_label(new_pred, 1);
4572 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except);
4573 case pn_Load_X_regular:
4574 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular);
4576 } else if (is_ia32_xLoad(new_pred)) {
4577 switch ((pn_Load)proj) {
4579 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
4581 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
4582 case pn_Load_X_except:
4583 /* This Load might raise an exception. Mark it. */
4584 set_ia32_exc_label(new_pred, 1);
4585 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except);
4586 case pn_Load_X_regular:
4587 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
4589 } else if (is_ia32_vfld(new_pred)) {
4590 switch ((pn_Load)proj) {
4592 return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
4594 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
4595 case pn_Load_X_except:
4596 /* This Load might raise an exception. Mark it. */
4597 set_ia32_exc_label(new_pred, 1);
4598 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except);
4599 case pn_Load_X_regular:
4600 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular);
4603 /* can happen for ProJMs when source address mode happened for the
4606 /* however it should not be the result proj, as that would mean the
4607 load had multiple users and should not have been used for
4609 if (proj != pn_Load_M) {
4610 panic("internal error: transformed node not a Load");
4612 return new_rd_Proj(dbgi, new_pred, mode_M, 1);
4615 panic("No idea how to transform Proj(Load) %+F", node);
4618 static ir_node *gen_Proj_Store(ir_node *node)
4620 ir_node *pred = get_Proj_pred(node);
4621 ir_node *new_pred = be_transform_node(pred);
4622 dbg_info *dbgi = get_irn_dbg_info(node);
4623 long pn = get_Proj_proj(node);
4625 if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
4626 switch ((pn_Store)pn) {
4628 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
4629 case pn_Store_X_except:
4630 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except);
4631 case pn_Store_X_regular:
4632 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
4634 } else if (is_ia32_vfist(new_pred)) {
4635 switch ((pn_Store)pn) {
4637 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M);
4638 case pn_Store_X_except:
4639 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except);
4640 case pn_Store_X_regular:
4641 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular);
4643 } else if (is_ia32_vfisttp(new_pred)) {
4644 switch ((pn_Store)pn) {
4646 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M);
4647 case pn_Store_X_except:
4648 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except);
4649 case pn_Store_X_regular:
4650 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular);
4652 } else if (is_ia32_vfst(new_pred)) {
4653 switch ((pn_Store)pn) {
4655 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M);
4656 case pn_Store_X_except:
4657 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except);
4658 case pn_Store_X_regular:
4659 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular);
4661 } else if (is_ia32_xStore(new_pred)) {
4662 switch ((pn_Store)pn) {
4664 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M);
4665 case pn_Store_X_except:
4666 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except);
4667 case pn_Store_X_regular:
4668 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular);
4670 } else if (is_Sync(new_pred)) {
4671 /* hack for the case that gen_float_const_Store produced a Sync */
4672 if (pn == pn_Store_M) {
4675 panic("exception control flow for gen_float_const_Store not implemented yet");
4676 } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) {
4677 /* destination address mode */
4678 if (pn == pn_Store_M) {
4681 panic("exception control flow for destination AM not implemented yet");
4684 panic("No idea how to transform Proj(Store) %+F", node);
4688 * Transform and renumber the Projs from a Div or Mod instruction.
4690 static ir_node *gen_Proj_Div(ir_node *node)
4692 ir_node *pred = get_Proj_pred(node);
4693 ir_node *new_pred = be_transform_node(pred);
4694 dbg_info *dbgi = get_irn_dbg_info(node);
4695 long proj = get_Proj_proj(node);
4697 assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
4698 assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res);
4700 switch ((pn_Div)proj) {
4702 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4703 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4704 } else if (is_ia32_xDiv(new_pred)) {
4705 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
4706 } else if (is_ia32_vfdiv(new_pred)) {
4707 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
4709 panic("Div transformed to unexpected thing %+F", new_pred);
4712 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4713 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
4714 } else if (is_ia32_xDiv(new_pred)) {
4715 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
4716 } else if (is_ia32_vfdiv(new_pred)) {
4717 return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4719 panic("Div transformed to unexpected thing %+F", new_pred);
4721 case pn_Div_X_except:
4722 set_ia32_exc_label(new_pred, 1);
4723 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
4724 case pn_Div_X_regular:
4725 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
4728 panic("No idea how to transform proj->Div");
4732 * Transform and renumber the Projs from a Div or Mod instruction.
4734 static ir_node *gen_Proj_Mod(ir_node *node)
4736 ir_node *pred = get_Proj_pred(node);
4737 ir_node *new_pred = be_transform_node(pred);
4738 dbg_info *dbgi = get_irn_dbg_info(node);
4739 long proj = get_Proj_proj(node);
4741 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4742 assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
4743 assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res);
4745 switch ((pn_Mod)proj) {
4747 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4749 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4750 case pn_Mod_X_except:
4751 set_ia32_exc_label(new_pred, 1);
4752 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
4753 case pn_Mod_X_regular:
4754 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
4756 panic("No idea how to transform proj->Mod");
4760 * Transform and renumber the Projs from a CopyB.
4762 static ir_node *gen_Proj_CopyB(ir_node *node)
4764 ir_node *pred = get_Proj_pred(node);
4765 ir_node *new_pred = be_transform_node(pred);
4766 dbg_info *dbgi = get_irn_dbg_info(node);
4767 long proj = get_Proj_proj(node);
4769 switch ((pn_CopyB)proj) {
4771 if (is_ia32_CopyB_i(new_pred)) {
4772 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
4773 } else if (is_ia32_CopyB(new_pred)) {
4774 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
4777 case pn_CopyB_X_regular:
4778 if (is_ia32_CopyB_i(new_pred)) {
4779 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular);
4780 } else if (is_ia32_CopyB(new_pred)) {
4781 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular);
4784 case pn_CopyB_X_except:
4785 if (is_ia32_CopyB_i(new_pred)) {
4786 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except);
4787 } else if (is_ia32_CopyB(new_pred)) {
4788 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except);
4793 panic("No idea how to transform proj->CopyB");
4796 static ir_node *gen_be_Call(ir_node *node)
4798 dbg_info *const dbgi = get_irn_dbg_info(node);
4799 ir_node *const src_block = get_nodes_block(node);
4800 ir_node *const block = be_transform_node(src_block);
4801 ir_node *const src_mem = get_irn_n(node, n_be_Call_mem);
4802 ir_node *const src_sp = get_irn_n(node, n_be_Call_sp);
4803 ir_node *const sp = be_transform_node(src_sp);
4804 ir_node *const src_ptr = get_irn_n(node, n_be_Call_ptr);
4805 ia32_address_mode_t am;
4806 ia32_address_t *const addr = &am.addr;
4811 ir_node * eax = noreg_GP;
4812 ir_node * ecx = noreg_GP;
4813 ir_node * edx = noreg_GP;
4814 unsigned const pop = be_Call_get_pop(node);
4815 ir_type *const call_tp = be_Call_get_type(node);
4816 int old_no_pic_adjust;
4817 int throws_exception = ir_throws_exception(node);
4819 /* Run the x87 simulator if the call returns a float value */
4820 if (get_method_n_ress(call_tp) > 0) {
4821 ir_type *const res_type = get_method_res_type(call_tp, 0);
4822 ir_mode *const res_mode = get_type_mode(res_type);
4824 if (res_mode != NULL && mode_is_float(res_mode)) {
4825 ir_graph *irg = current_ir_graph;
4826 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4827 irg_data->do_x87_sim = 1;
4831 /* We do not want be_Call direct calls */
4832 assert(be_Call_get_entity(node) == NULL);
4834 /* special case for PIC trampoline calls */
4835 old_no_pic_adjust = ia32_no_pic_adjust;
4836 ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic;
4838 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4839 match_am | match_immediate);
4841 ia32_no_pic_adjust = old_no_pic_adjust;
4843 i = get_irn_arity(node) - 1;
4844 fpcw = be_transform_node(get_irn_n(node, i--));
4845 for (; i >= n_be_Call_first_arg; --i) {
4846 arch_register_req_t const *const req
4847 = arch_get_irn_register_req_in(node, i);
4848 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4850 assert(req->type == arch_register_req_type_limited);
4851 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4853 switch (*req->limited) {
4854 case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
4855 case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
4856 case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
4857 default: panic("Invalid GP register for register parameter");
4861 mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
4862 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4863 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4864 ir_set_throws_exception(call, throws_exception);
4865 set_am_attributes(call, &am);
4866 call = fix_mem_proj(call, &am);
4868 if (get_irn_pinned(node) == op_pin_state_pinned)
4869 set_irn_pinned(call, op_pin_state_pinned);
4871 SET_IA32_ORIG_NODE(call, node);
4873 if (ia32_cg_config.use_sse2) {
4874 /* remember this call for post-processing */
4875 ARR_APP1(ir_node *, call_list, call);
4876 ARR_APP1(ir_type *, call_types, be_Call_get_type(node));
4883 * Transform Builtin trap
4885 static ir_node *gen_trap(ir_node *node)
4887 dbg_info *dbgi = get_irn_dbg_info(node);
4888 ir_node *block = be_transform_node(get_nodes_block(node));
4889 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4891 return new_bd_ia32_UD2(dbgi, block, mem);
4895 * Transform Builtin debugbreak
4897 static ir_node *gen_debugbreak(ir_node *node)
4899 dbg_info *dbgi = get_irn_dbg_info(node);
4900 ir_node *block = be_transform_node(get_nodes_block(node));
4901 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4903 return new_bd_ia32_Breakpoint(dbgi, block, mem);
4907 * Transform Builtin return_address
4909 static ir_node *gen_return_address(ir_node *node)
4911 ir_node *param = get_Builtin_param(node, 0);
4912 ir_node *frame = get_Builtin_param(node, 1);
4913 dbg_info *dbgi = get_irn_dbg_info(node);
4914 ir_tarval *tv = get_Const_tarval(param);
4915 ir_graph *irg = get_irn_irg(node);
4916 unsigned long value = get_tarval_long(tv);
4918 ir_node *block = be_transform_node(get_nodes_block(node));
4919 ir_node *ptr = be_transform_node(frame);
4923 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4924 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4925 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4928 /* load the return address from this frame */
4929 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4931 set_irn_pinned(load, get_irn_pinned(node));
4932 set_ia32_op_type(load, ia32_AddrModeS);
4933 set_ia32_ls_mode(load, mode_Iu);
4935 set_ia32_am_offs_int(load, 0);
4936 set_ia32_use_frame(load);
4937 set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
4939 if (get_irn_pinned(node) == op_pin_state_floats) {
4940 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
4941 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
4942 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4943 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
4946 SET_IA32_ORIG_NODE(load, node);
4947 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4951 * Transform Builtin frame_address
4953 static ir_node *gen_frame_address(ir_node *node)
4955 ir_node *param = get_Builtin_param(node, 0);
4956 ir_node *frame = get_Builtin_param(node, 1);
4957 dbg_info *dbgi = get_irn_dbg_info(node);
4958 ir_tarval *tv = get_Const_tarval(param);
4959 ir_graph *irg = get_irn_irg(node);
4960 unsigned long value = get_tarval_long(tv);
4962 ir_node *block = be_transform_node(get_nodes_block(node));
4963 ir_node *ptr = be_transform_node(frame);
4968 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4969 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4970 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4973 /* load the frame address from this frame */
4974 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4976 set_irn_pinned(load, get_irn_pinned(node));
4977 set_ia32_op_type(load, ia32_AddrModeS);
4978 set_ia32_ls_mode(load, mode_Iu);
4980 ent = ia32_get_frame_address_entity(irg);
4982 set_ia32_am_offs_int(load, 0);
4983 set_ia32_use_frame(load);
4984 set_ia32_frame_ent(load, ent);
4986 /* will fail anyway, but gcc does this: */
4987 set_ia32_am_offs_int(load, 0);
4990 if (get_irn_pinned(node) == op_pin_state_floats) {
4991 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
4992 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
4993 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4994 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
4997 SET_IA32_ORIG_NODE(load, node);
4998 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
5002 * Transform Builtin frame_address
5004 static ir_node *gen_prefetch(ir_node *node)
5007 ir_node *ptr, *block, *mem, *base, *idx;
5008 ir_node *param, *new_node;
5011 ia32_address_t addr;
5013 if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
5014 /* no prefetch at all, route memory */
5015 return be_transform_node(get_Builtin_mem(node));
5018 param = get_Builtin_param(node, 1);
5019 tv = get_Const_tarval(param);
5020 rw = get_tarval_long(tv);
5022 /* construct load address */
5023 memset(&addr, 0, sizeof(addr));
5024 ptr = get_Builtin_param(node, 0);
5025 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
5032 base = be_transform_node(base);
5038 idx = be_transform_node(idx);
5041 dbgi = get_irn_dbg_info(node);
5042 block = be_transform_node(get_nodes_block(node));
5043 mem = be_transform_node(get_Builtin_mem(node));
5045 if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
5046 /* we have 3DNow!, this was already checked above */
5047 new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem);
5048 } else if (ia32_cg_config.use_sse_prefetch) {
5049 /* note: rw == 1 is IGNORED in that case */
5050 param = get_Builtin_param(node, 2);
5051 tv = get_Const_tarval(param);
5052 locality = get_tarval_long(tv);
5054 /* SSE style prefetch */
5057 new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem);
5060 new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem);
5063 new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem);
5066 new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem);
5070 assert(ia32_cg_config.use_3dnow_prefetch);
5071 /* 3DNow! style prefetch */
5072 new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem);
5075 set_irn_pinned(new_node, get_irn_pinned(node));
5076 set_ia32_op_type(new_node, ia32_AddrModeS);
5077 set_ia32_ls_mode(new_node, mode_Bu);
5078 set_address(new_node, &addr);
5080 SET_IA32_ORIG_NODE(new_node, node);
5082 return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M);
5086 * Transform bsf like node
5088 static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func)
5090 ir_node *param = get_Builtin_param(node, 0);
5091 dbg_info *dbgi = get_irn_dbg_info(node);
5093 ir_node *block = get_nodes_block(node);
5094 ir_node *new_block = be_transform_node(block);
5096 ia32_address_mode_t am;
5097 ia32_address_t *addr = &am.addr;
5100 match_arguments(&am, block, NULL, param, NULL, match_am);
5102 cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5103 set_am_attributes(cnt, &am);
5104 set_ia32_ls_mode(cnt, get_irn_mode(param));
5106 SET_IA32_ORIG_NODE(cnt, node);
5107 return fix_mem_proj(cnt, &am);
5111 * Transform builtin ffs.
5113 static ir_node *gen_ffs(ir_node *node)
5115 ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf);
5116 ir_node *real = skip_Proj(bsf);
5117 dbg_info *dbgi = get_irn_dbg_info(real);
5118 ir_node *block = get_nodes_block(real);
5119 ir_node *flag, *set, *conv, *neg, *orn, *add;
5122 if (get_irn_mode(real) != mode_T) {
5123 set_irn_mode(real, mode_T);
5124 bsf = new_r_Proj(real, mode_Iu, pn_ia32_res);
5127 flag = new_r_Proj(real, mode_b, pn_ia32_flags);
5130 set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal);
5131 SET_IA32_ORIG_NODE(set, node);
5134 conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
5135 SET_IA32_ORIG_NODE(conv, node);
5138 neg = new_bd_ia32_Neg(dbgi, block, conv);
5141 orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
5142 set_ia32_commutative(orn);
5145 add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP);
5146 add_ia32_am_offs_int(add, 1);
5151 * Transform builtin clz.
5153 static ir_node *gen_clz(ir_node *node)
5155 ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr);
5156 ir_node *real = skip_Proj(bsr);
5157 dbg_info *dbgi = get_irn_dbg_info(real);
5158 ir_node *block = get_nodes_block(real);
5159 ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
5161 return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
5165 * Transform builtin ctz.
5167 static ir_node *gen_ctz(ir_node *node)
5169 return gen_unop_AM(node, new_bd_ia32_Bsf);
5173 * Transform builtin parity.
5175 static ir_node *gen_parity(ir_node *node)
5177 dbg_info *dbgi = get_irn_dbg_info(node);
5178 ir_node *block = get_nodes_block(node);
5179 ir_node *new_block = be_transform_node(block);
5180 ir_node *param = get_Builtin_param(node, 0);
5181 ir_node *new_param = be_transform_node(param);
5184 /* the x86 parity bit is stupid: it only looks at the lowest byte,
5185 * so we have to do complicated xoring first.
5186 * (we should also better lower this before the backend so we still have a
5187 * chance for CSE, constant folding and other goodies for some of these
5190 ir_node *count = ia32_create_Immediate(NULL, 0, 16);
5191 ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
5192 ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
5194 ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor);
5197 set_ia32_commutative(xor);
5199 set_irn_mode(xor2, mode_T);
5200 flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
5203 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity);
5204 SET_IA32_ORIG_NODE(new_node, node);
5207 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
5208 nomem, new_node, mode_Bu);
5209 SET_IA32_ORIG_NODE(new_node, node);
5214 * Transform builtin popcount
5216 static ir_node *gen_popcount(ir_node *node)
5218 ir_node *param = get_Builtin_param(node, 0);
5219 dbg_info *dbgi = get_irn_dbg_info(node);
5221 ir_node *block = get_nodes_block(node);
5222 ir_node *new_block = be_transform_node(block);
5225 ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13;
5227 /* check for SSE4.2 or SSE4a and use the popcnt instruction */
5228 if (ia32_cg_config.use_popcnt) {
5229 ia32_address_mode_t am;
5230 ia32_address_t *addr = &am.addr;
5233 match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am);
5235 cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5236 set_am_attributes(cnt, &am);
5237 set_ia32_ls_mode(cnt, get_irn_mode(param));
5239 SET_IA32_ORIG_NODE(cnt, node);
5240 return fix_mem_proj(cnt, &am);
5243 new_param = be_transform_node(param);
5245 /* do the standard popcount algo */
5246 /* TODO: This is stupid, we should transform this before the backend,
5247 * to get CSE, localopts, etc. for the operations
5248 * TODO: This is also not the optimal algorithm (it is just the starting
5249 * example in hackers delight, they optimize it more on the following page)
5250 * But I'm too lazy to fix this now, as the code should get lowered before
5251 * the backend anyway.
5254 /* m1 = x & 0x55555555 */
5255 imm = ia32_create_Immediate(NULL, 0, 0x55555555);
5256 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
5259 simm = ia32_create_Immediate(NULL, 0, 1);
5260 s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
5262 /* m2 = s1 & 0x55555555 */
5263 m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
5266 m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
5268 /* m4 = m3 & 0x33333333 */
5269 imm = ia32_create_Immediate(NULL, 0, 0x33333333);
5270 m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
5273 simm = ia32_create_Immediate(NULL, 0, 2);
5274 s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
5276 /* m5 = s2 & 0x33333333 */
5277 m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
5280 m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
5282 /* m7 = m6 & 0x0F0F0F0F */
5283 imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
5284 m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
5287 simm = ia32_create_Immediate(NULL, 0, 4);
5288 s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
5290 /* m8 = s3 & 0x0F0F0F0F */
5291 m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
5294 m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
5296 /* m10 = m9 & 0x00FF00FF */
5297 imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
5298 m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
5301 simm = ia32_create_Immediate(NULL, 0, 8);
5302 s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
5304 /* m11 = s4 & 0x00FF00FF */
5305 m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
5307 /* m12 = m10 + m11 */
5308 m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
5310 /* m13 = m12 & 0x0000FFFF */
5311 imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
5312 m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
5314 /* s5 = m12 >> 16 */
5315 simm = ia32_create_Immediate(NULL, 0, 16);
5316 s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
5318 /* res = m13 + s5 */
5319 return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
5323 * Transform builtin byte swap.
5325 static ir_node *gen_bswap(ir_node *node)
5327 ir_node *param = be_transform_node(get_Builtin_param(node, 0));
5328 dbg_info *dbgi = get_irn_dbg_info(node);
5330 ir_node *block = get_nodes_block(node);
5331 ir_node *new_block = be_transform_node(block);
5332 ir_mode *mode = get_irn_mode(param);
5333 unsigned size = get_mode_size_bits(mode);
5334 ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4;
5338 if (ia32_cg_config.use_i486) {
5339 /* swap available */
5340 return new_bd_ia32_Bswap(dbgi, new_block, param);
5342 s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5343 s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5345 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00));
5346 m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1);
5348 s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5350 m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000));
5351 m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3);
5353 s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5354 return new_bd_ia32_Lea(dbgi, new_block, m4, s4);
5357 /* swap16 always available */
5358 return new_bd_ia32_Bswap16(dbgi, new_block, param);
5361 panic("Invalid bswap size (%d)", size);
5366 * Transform builtin outport.
5368 static ir_node *gen_outport(ir_node *node)
5370 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5371 ir_node *oldv = get_Builtin_param(node, 1);
5372 ir_mode *mode = get_irn_mode(oldv);
5373 ir_node *value = be_transform_node(oldv);
5374 ir_node *block = be_transform_node(get_nodes_block(node));
5375 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5376 dbg_info *dbgi = get_irn_dbg_info(node);
5378 ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem);
5379 set_ia32_ls_mode(res, mode);
5384 * Transform builtin inport.
5386 static ir_node *gen_inport(ir_node *node)
5388 ir_type *tp = get_Builtin_type(node);
5389 ir_type *rstp = get_method_res_type(tp, 0);
5390 ir_mode *mode = get_type_mode(rstp);
5391 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5392 ir_node *block = be_transform_node(get_nodes_block(node));
5393 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5394 dbg_info *dbgi = get_irn_dbg_info(node);
5396 ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem);
5397 set_ia32_ls_mode(res, mode);
5399 /* check for missing Result Proj */
5404 * Transform a builtin inner trampoline
5406 static ir_node *gen_inner_trampoline(ir_node *node)
5408 ir_node *ptr = get_Builtin_param(node, 0);
5409 ir_node *callee = get_Builtin_param(node, 1);
5410 ir_node *env = be_transform_node(get_Builtin_param(node, 2));
5411 ir_node *mem = get_Builtin_mem(node);
5412 ir_node *block = get_nodes_block(node);
5413 ir_node *new_block = be_transform_node(block);
5417 ir_node *trampoline;
5419 dbg_info *dbgi = get_irn_dbg_info(node);
5420 ia32_address_t addr;
5422 /* construct store address */
5423 memset(&addr, 0, sizeof(addr));
5424 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
5426 if (addr.base == NULL) {
5427 addr.base = noreg_GP;
5429 addr.base = be_transform_node(addr.base);
5432 if (addr.index == NULL) {
5433 addr.index = noreg_GP;
5435 addr.index = be_transform_node(addr.index);
5437 addr.mem = be_transform_node(mem);
5439 /* mov ecx, <env> */
5440 val = ia32_create_Immediate(NULL, 0, 0xB9);
5441 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5442 addr.index, addr.mem, val);
5443 set_irn_pinned(store, get_irn_pinned(node));
5444 set_ia32_op_type(store, ia32_AddrModeD);
5445 set_ia32_ls_mode(store, mode_Bu);
5446 set_address(store, &addr);
5450 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5451 addr.index, addr.mem, env);
5452 set_irn_pinned(store, get_irn_pinned(node));
5453 set_ia32_op_type(store, ia32_AddrModeD);
5454 set_ia32_ls_mode(store, mode_Iu);
5455 set_address(store, &addr);
5459 /* jmp rel <callee> */
5460 val = ia32_create_Immediate(NULL, 0, 0xE9);
5461 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5462 addr.index, addr.mem, val);
5463 set_irn_pinned(store, get_irn_pinned(node));
5464 set_ia32_op_type(store, ia32_AddrModeD);
5465 set_ia32_ls_mode(store, mode_Bu);
5466 set_address(store, &addr);
5470 trampoline = be_transform_node(ptr);
5472 /* the callee is typically an immediate */
5473 if (is_SymConst(callee)) {
5474 rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
5476 rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP);
5477 add_ia32_am_offs_int(rel, -10);
5479 rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
5481 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5482 addr.index, addr.mem, rel);
5483 set_irn_pinned(store, get_irn_pinned(node));
5484 set_ia32_op_type(store, ia32_AddrModeD);
5485 set_ia32_ls_mode(store, mode_Iu);
5486 set_address(store, &addr);
5491 return new_r_Tuple(new_block, 2, in);
5495 * Transform Builtin node.
5497 static ir_node *gen_Builtin(ir_node *node)
5499 ir_builtin_kind kind = get_Builtin_kind(node);
5503 return gen_trap(node);
5504 case ir_bk_debugbreak:
5505 return gen_debugbreak(node);
5506 case ir_bk_return_address:
5507 return gen_return_address(node);
5508 case ir_bk_frame_address:
5509 return gen_frame_address(node);
5510 case ir_bk_prefetch:
5511 return gen_prefetch(node);
5513 return gen_ffs(node);
5515 return gen_clz(node);
5517 return gen_ctz(node);
5519 return gen_parity(node);
5520 case ir_bk_popcount:
5521 return gen_popcount(node);
5523 return gen_bswap(node);
5525 return gen_outport(node);
5527 return gen_inport(node);
5528 case ir_bk_inner_trampoline:
5529 return gen_inner_trampoline(node);
5531 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5535 * Transform Proj(Builtin) node.
5537 static ir_node *gen_Proj_Builtin(ir_node *proj)
5539 ir_node *node = get_Proj_pred(proj);
5540 ir_node *new_node = be_transform_node(node);
5541 ir_builtin_kind kind = get_Builtin_kind(node);
5544 case ir_bk_return_address:
5545 case ir_bk_frame_address:
5550 case ir_bk_popcount:
5552 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
5555 case ir_bk_debugbreak:
5556 case ir_bk_prefetch:
5558 assert(get_Proj_proj(proj) == pn_Builtin_M);
5561 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5562 return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res);
5564 assert(get_Proj_proj(proj) == pn_Builtin_M);
5565 return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M);
5567 case ir_bk_inner_trampoline:
5568 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5569 return get_Tuple_pred(new_node, 1);
5571 assert(get_Proj_proj(proj) == pn_Builtin_M);
5572 return get_Tuple_pred(new_node, 0);
5575 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5578 static ir_node *gen_be_IncSP(ir_node *node)
5580 ir_node *res = be_duplicate_node(node);
5581 arch_add_irn_flags(res, arch_irn_flags_modify_flags);
5587 * Transform the Projs from a be_Call.
5589 static ir_node *gen_Proj_be_Call(ir_node *node)
5591 ir_node *call = get_Proj_pred(node);
5592 ir_node *new_call = be_transform_node(call);
5593 dbg_info *dbgi = get_irn_dbg_info(node);
5594 long proj = get_Proj_proj(node);
5595 ir_mode *mode = get_irn_mode(node);
5598 if (proj == pn_be_Call_M) {
5599 return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
5601 /* transform call modes */
5602 if (mode_is_data(mode)) {
5603 const arch_register_class_t *cls = arch_get_irn_reg_class(node);
5607 /* Map from be_Call to ia32_Call proj number */
5608 if (proj == pn_be_Call_sp) {
5609 proj = pn_ia32_Call_stack;
5610 } else if (proj == pn_be_Call_M) {
5611 proj = pn_ia32_Call_M;
5612 } else if (proj == pn_be_Call_X_except) {
5613 proj = pn_ia32_Call_X_except;
5614 } else if (proj == pn_be_Call_X_regular) {
5615 proj = pn_ia32_Call_X_regular;
5617 arch_register_req_t const *const req = arch_get_irn_register_req(node);
5618 int const n_outs = arch_get_irn_n_outs(new_call);
5621 assert(proj >= pn_be_Call_first_res);
5622 assert(req->type & arch_register_req_type_limited);
5624 for (i = 0; i < n_outs; ++i) {
5625 arch_register_req_t const *const new_req
5626 = arch_get_irn_register_req_out(new_call, i);
5628 if (!(new_req->type & arch_register_req_type_limited) ||
5629 new_req->cls != req->cls ||
5630 *new_req->limited != *req->limited)
5639 res = new_rd_Proj(dbgi, new_call, mode, proj);
5641 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
5643 case pn_ia32_Call_stack:
5644 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
5647 case pn_ia32_Call_fpcw:
5648 arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
5656 * Transform the Projs from a Cmp.
5658 static ir_node *gen_Proj_Cmp(ir_node *node)
5660 /* this probably means not all mode_b nodes were lowered... */
5661 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
5665 static ir_node *gen_Proj_ASM(ir_node *node)
5667 ir_mode *mode = get_irn_mode(node);
5668 ir_node *pred = get_Proj_pred(node);
5669 ir_node *new_pred = be_transform_node(pred);
5670 long pos = get_Proj_proj(node);
5672 if (mode == mode_M) {
5673 pos = arch_get_irn_n_outs(new_pred)-1;
5674 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
5676 } else if (mode_is_float(mode)) {
5679 panic("unexpected proj mode at ASM");
5682 return new_r_Proj(new_pred, mode, pos);
5686 * Transform and potentially renumber Proj nodes.
5688 static ir_node *gen_Proj(ir_node *node)
5690 ir_node *pred = get_Proj_pred(node);
5693 switch (get_irn_opcode(pred)) {
5695 return gen_Proj_Load(node);
5697 return gen_Proj_Store(node);
5699 return gen_Proj_ASM(node);
5701 return gen_Proj_Builtin(node);
5703 return gen_Proj_Div(node);
5705 return gen_Proj_Mod(node);
5707 return gen_Proj_CopyB(node);
5709 return gen_Proj_be_SubSP(node);
5711 return gen_Proj_be_AddSP(node);
5713 return gen_Proj_be_Call(node);
5715 return gen_Proj_Cmp(node);
5717 proj = get_Proj_proj(node);
5719 case pn_Start_X_initial_exec: {
5720 ir_node *block = get_nodes_block(pred);
5721 ir_node *new_block = be_transform_node(block);
5722 dbg_info *dbgi = get_irn_dbg_info(node);
5723 /* we exchange the ProjX with a jump */
5724 ir_node *jump = new_rd_Jmp(dbgi, new_block);
5732 if (is_ia32_l_FloattoLL(pred)) {
5733 return gen_Proj_l_FloattoLL(node);
5735 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5739 ir_mode *mode = get_irn_mode(node);
5740 if (ia32_mode_needs_gp_reg(mode)) {
5741 ir_node *new_pred = be_transform_node(pred);
5742 ir_node *new_proj = new_r_Proj(new_pred, mode_Iu,
5743 get_Proj_proj(node));
5744 new_proj->node_nr = node->node_nr;
5749 return be_duplicate_node(node);
5753 * Enters all transform functions into the generic pointer
5755 static void register_transformers(void)
5757 /* first clear the generic function pointer for all ops */
5758 be_start_transform_setup();
5760 be_set_transform_function(op_Add, gen_Add);
5761 be_set_transform_function(op_And, gen_And);
5762 be_set_transform_function(op_ASM, ia32_gen_ASM);
5763 be_set_transform_function(op_be_AddSP, gen_be_AddSP);
5764 be_set_transform_function(op_be_Call, gen_be_Call);
5765 be_set_transform_function(op_be_Copy, gen_be_Copy);
5766 be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr);
5767 be_set_transform_function(op_be_IncSP, gen_be_IncSP);
5768 be_set_transform_function(op_be_Return, gen_be_Return);
5769 be_set_transform_function(op_be_SubSP, gen_be_SubSP);
5770 be_set_transform_function(op_Builtin, gen_Builtin);
5771 be_set_transform_function(op_Cmp, gen_Cmp);
5772 be_set_transform_function(op_Cond, gen_Cond);
5773 be_set_transform_function(op_Const, gen_Const);
5774 be_set_transform_function(op_Conv, gen_Conv);
5775 be_set_transform_function(op_CopyB, ia32_gen_CopyB);
5776 be_set_transform_function(op_Div, gen_Div);
5777 be_set_transform_function(op_Eor, gen_Eor);
5778 be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc);
5779 be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add);
5780 be_set_transform_function(op_ia32_Leave, be_duplicate_node);
5781 be_set_transform_function(op_ia32_l_FloattoLL, gen_ia32_l_FloattoLL);
5782 be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
5783 be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
5784 be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
5785 be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
5786 be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
5787 be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
5788 be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
5789 be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
5790 be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
5791 be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
5792 be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
5793 be_set_transform_function(op_ia32_Push, be_duplicate_node);
5794 be_set_transform_function(op_IJmp, gen_IJmp);
5795 be_set_transform_function(op_Jmp, gen_Jmp);
5796 be_set_transform_function(op_Load, gen_Load);
5797 be_set_transform_function(op_Minus, gen_Minus);
5798 be_set_transform_function(op_Mod, gen_Mod);
5799 be_set_transform_function(op_Mul, gen_Mul);
5800 be_set_transform_function(op_Mulh, gen_Mulh);
5801 be_set_transform_function(op_Mux, gen_Mux);
5802 be_set_transform_function(op_Not, gen_Not);
5803 be_set_transform_function(op_Or, gen_Or);
5804 be_set_transform_function(op_Phi, gen_Phi);
5805 be_set_transform_function(op_Proj, gen_Proj);
5806 be_set_transform_function(op_Rotl, gen_Rotl);
5807 be_set_transform_function(op_Shl, gen_Shl);
5808 be_set_transform_function(op_Shr, gen_Shr);
5809 be_set_transform_function(op_Shrs, gen_Shrs);
5810 be_set_transform_function(op_Store, gen_Store);
5811 be_set_transform_function(op_Sub, gen_Sub);
5812 be_set_transform_function(op_SymConst, gen_SymConst);
5813 be_set_transform_function(op_Unknown, ia32_gen_Unknown);
5817 * Pre-transform all unknown and noreg nodes.
5819 static void ia32_pretransform_node(void)
5821 ir_graph *irg = current_ir_graph;
5822 ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
5824 irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
5825 irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
5826 irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
5827 irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
5828 irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
5830 nomem = get_irg_no_mem(irg);
5831 noreg_GP = ia32_new_NoReg_gp(irg);
5835 * Post-process all calls if we are in SSE mode.
5836 * The ABI requires that the results are in st0, copy them
5837 * to a xmm register.
5839 static void postprocess_fp_call_results(void)
5843 for (i = 0, n = ARR_LEN(call_list); i < n; ++i) {
5844 ir_node *call = call_list[i];
5845 ir_type *mtp = call_types[i];
5848 for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
5849 ir_type *res_tp = get_method_res_type(mtp, j);
5850 ir_node *res, *new_res;
5851 const ir_edge_t *edge, *next;
5854 if (! is_atomic_type(res_tp)) {
5855 /* no floating point return */
5858 res_mode = get_type_mode(res_tp);
5859 if (! mode_is_float(res_mode)) {
5860 /* no floating point return */
5864 res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
5867 /* now patch the users */
5868 foreach_out_edge_safe(res, edge, next) {
5869 ir_node *succ = get_edge_src_irn(edge);
5872 if (be_is_Keep(succ))
5875 if (is_ia32_xStore(succ)) {
5876 /* an xStore can be patched into an vfst */
5877 dbg_info *db = get_irn_dbg_info(succ);
5878 ir_node *block = get_nodes_block(succ);
5879 ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
5880 ir_node *idx = get_irn_n(succ, n_ia32_xStore_index);
5881 ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
5882 ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
5883 ir_mode *mode = get_ia32_ls_mode(succ);
5885 ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode);
5886 //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M);
5887 set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
5888 if (is_ia32_use_frame(succ))
5889 set_ia32_use_frame(st);
5890 set_ia32_frame_ent(st, get_ia32_frame_ent(succ));
5891 set_irn_pinned(st, get_irn_pinned(succ));
5892 set_ia32_op_type(st, ia32_AddrModeD);
5894 assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M);
5895 assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular);
5896 assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except);
5903 if (new_res == NULL) {
5904 dbg_info *db = get_irn_dbg_info(call);
5905 ir_node *block = get_nodes_block(call);
5906 ir_node *frame = get_irg_frame(current_ir_graph);
5907 ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
5908 ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
5909 ir_node *vfst, *xld, *new_mem;
5912 /* store st(0) on stack */
5913 vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem,
5915 set_ia32_op_type(vfst, ia32_AddrModeD);
5916 set_ia32_use_frame(vfst);
5918 vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M);
5920 /* load into SSE register */
5921 xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
5923 set_ia32_op_type(xld, ia32_AddrModeS);
5924 set_ia32_use_frame(xld);
5926 new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res);
5927 new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
5929 if (old_mem != NULL) {
5930 edges_reroute(old_mem, new_mem);
5934 set_irn_n(succ, get_edge_src_pos(edge), new_res);
5940 /* do the transformation */
5941 void ia32_transform_graph(ir_graph *irg)
5945 register_transformers();
5946 initial_fpcw = NULL;
5947 ia32_no_pic_adjust = 0;
5949 old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]);
5951 be_timer_push(T_HEIGHTS);
5952 ia32_heights = heights_new(irg);
5953 be_timer_pop(T_HEIGHTS);
5954 ia32_calculate_non_address_mode_nodes(irg);
5956 /* the transform phase is not safe for CSE (yet) because several nodes get
5957 * attributes set after their creation */
5958 cse_last = get_opt_cse();
5961 call_list = NEW_ARR_F(ir_node *, 0);
5962 call_types = NEW_ARR_F(ir_type *, 0);
5963 be_transform_graph(irg, ia32_pretransform_node);
5965 if (ia32_cg_config.use_sse2)
5966 postprocess_fp_call_results();
5967 DEL_ARR_F(call_types);
5968 DEL_ARR_F(call_list);
5970 set_opt_cse(cse_last);
5972 ia32_free_non_address_mode_nodes();
5973 heights_free(ia32_heights);
5974 ia32_heights = NULL;
5977 void ia32_init_transform(void)
5979 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");