2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 if (USE_SSE2(env_cg)) {
556 set_ia32_ls_mode(new_node, mode);
559 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
565 * Construct a standard binary operation, set AM and immediate if required.
567 * @param op1 The first operand
568 * @param op2 The second operand
569 * @param func The node constructor function
570 * @return The constructed ia32 node.
572 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
573 construct_binop_float_func *func)
575 ir_node *block = be_transform_node(get_nodes_block(node));
576 ir_node *new_op1 = be_transform_node(op1);
577 ir_node *new_op2 = be_transform_node(op2);
578 ir_node *new_node = NULL;
579 dbg_info *dbgi = get_irn_dbg_info(node);
580 ir_graph *irg = current_ir_graph;
581 ir_mode *mode = get_irn_mode(node);
582 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
583 ir_node *nomem = new_NoMem();
584 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
585 &ia32_fp_cw_regs[REG_FPCW]);
587 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
589 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
590 if (is_op_commutative(get_irn_op(node))) {
591 set_ia32_commutative(new_node);
593 if (USE_SSE2(env_cg)) {
594 set_ia32_ls_mode(new_node, mode);
597 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
603 * Construct a shift/rotate binary operation, sets AM and immediate if required.
605 * @param op1 The first operand
606 * @param op2 The second operand
607 * @param func The node constructor function
608 * @return The constructed ia32 node.
610 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
611 construct_binop_func *func)
613 ir_node *block = be_transform_node(get_nodes_block(node));
614 ir_node *new_op1 = be_transform_node(op1);
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = current_ir_graph;
619 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
620 ir_node *nomem = new_NoMem();
622 assert(! mode_is_float(get_irn_mode(node))
623 && "Shift/Rotate with float not supported");
625 new_op2 = create_immediate_or_transform(op2, 'N');
627 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
630 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
632 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
634 set_ia32_emit_cl(new_op);
641 * Construct a standard unary operation, set AM and immediate if required.
643 * @param op The operand
644 * @param func The node constructor function
645 * @return The constructed ia32 node.
647 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
649 ir_node *block = be_transform_node(get_nodes_block(node));
650 ir_node *new_op = be_transform_node(op);
651 ir_node *new_node = NULL;
652 ir_graph *irg = current_ir_graph;
653 dbg_info *dbgi = get_irn_dbg_info(node);
654 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
655 ir_node *nomem = new_NoMem();
657 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
658 DB((dbg, LEVEL_1, "INT unop ..."));
659 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
667 * Creates an ia32 Add.
669 * @return the created ia32 Add node
671 static ir_node *gen_Add(ir_node *node) {
672 ir_node *block = be_transform_node(get_nodes_block(node));
673 ir_node *op1 = get_Add_left(node);
674 ir_node *new_op1 = be_transform_node(op1);
675 ir_node *op2 = get_Add_right(node);
676 ir_node *new_op2 = be_transform_node(op2);
677 ir_node *new_op = NULL;
678 ir_graph *irg = current_ir_graph;
679 dbg_info *dbgi = get_irn_dbg_info(node);
680 ir_mode *mode = get_irn_mode(node);
681 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
682 ir_node *nomem = new_NoMem();
683 ir_node *expr_op, *imm_op;
685 /* Check if immediate optimization is on and */
686 /* if it's an operation with immediate. */
687 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
688 expr_op = get_expr_op(new_op1, new_op2);
690 assert((expr_op || imm_op) && "invalid operands");
692 if (mode_is_float(mode)) {
694 if (USE_SSE2(env_cg))
695 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
697 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
702 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
703 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
705 /* No expr_op means, that we have two const - one symconst and */
706 /* one tarval or another symconst - because this case is not */
707 /* covered by constant folding */
708 /* We need to check for: */
709 /* 1) symconst + const -> becomes a LEA */
710 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
711 /* linker doesn't support two symconsts */
713 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
714 /* this is the 2nd case */
715 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
716 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
717 set_ia32_am_flavour(new_op, ia32_am_B);
718 set_ia32_op_type(new_op, ia32_AddrModeS);
720 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
721 } else if (tp1 == ia32_ImmSymConst) {
722 tarval *tv = get_ia32_Immop_tarval(new_op2);
723 long offs = get_tarval_long(tv);
725 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
726 add_irn_dep(new_op, get_irg_frame(irg));
727 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
730 add_ia32_am_offs_int(new_op, offs);
731 set_ia32_am_flavour(new_op, ia32_am_OB);
732 set_ia32_op_type(new_op, ia32_AddrModeS);
733 } else if (tp2 == ia32_ImmSymConst) {
734 tarval *tv = get_ia32_Immop_tarval(new_op1);
735 long offs = get_tarval_long(tv);
737 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
738 add_irn_dep(new_op, get_irg_frame(irg));
739 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 add_ia32_am_offs_int(new_op, offs);
742 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
743 set_ia32_am_flavour(new_op, ia32_am_OB);
744 set_ia32_op_type(new_op, ia32_AddrModeS);
746 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
747 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
748 tarval *restv = tarval_add(tv1, tv2);
750 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
752 new_op = new_rd_ia32_Const(dbgi, irg, block);
753 set_ia32_Const_tarval(new_op, restv);
754 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
757 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
760 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
761 tarval_classification_t class_tv, class_negtv;
762 tarval *tv = get_ia32_Immop_tarval(imm_op);
764 /* optimize tarvals */
765 class_tv = classify_tarval(tv);
766 class_negtv = classify_tarval(tarval_neg(tv));
768 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
769 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
770 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
771 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
773 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
774 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
775 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
782 /* This is a normal add */
783 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
786 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
787 set_ia32_commutative(new_op);
789 fold_immediate(new_op, 2, 3);
791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
797 * Creates an ia32 Mul.
799 * @return the created ia32 Mul node
801 static ir_node *gen_Mul(ir_node *node) {
802 ir_node *op1 = get_Mul_left(node);
803 ir_node *op2 = get_Mul_right(node);
804 ir_mode *mode = get_irn_mode(node);
806 if (mode_is_float(mode)) {
808 if (USE_SSE2(env_cg))
809 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
811 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
815 for the lower 32bit of the result it doesn't matter whether we use
816 signed or unsigned multiplication so we use IMul as it has fewer
819 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
823 * Creates an ia32 Mulh.
824 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
825 * this result while Mul returns the lower 32 bit.
827 * @return the created ia32 Mulh node
829 static ir_node *gen_Mulh(ir_node *node) {
830 ir_node *block = be_transform_node(get_nodes_block(node));
831 ir_node *op1 = get_irn_n(node, 0);
832 ir_node *new_op1 = be_transform_node(op1);
833 ir_node *op2 = get_irn_n(node, 1);
834 ir_node *new_op2 = be_transform_node(op2);
835 ir_graph *irg = current_ir_graph;
836 dbg_info *dbgi = get_irn_dbg_info(node);
837 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
838 ir_mode *mode = get_irn_mode(node);
839 ir_node *proj_EAX, *proj_EDX, *res;
842 assert(!mode_is_float(mode) && "Mulh with float not supported");
843 if (mode_is_signed(mode)) {
844 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
846 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
849 set_ia32_commutative(res);
850 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
852 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
853 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
857 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
865 * Creates an ia32 And.
867 * @return The created ia32 And node
869 static ir_node *gen_And(ir_node *node) {
870 ir_node *op1 = get_And_left(node);
871 ir_node *op2 = get_And_right(node);
873 assert (! mode_is_float(get_irn_mode(node)));
874 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
880 * Creates an ia32 Or.
882 * @return The created ia32 Or node
884 static ir_node *gen_Or(ir_node *node) {
885 ir_node *op1 = get_Or_left(node);
886 ir_node *op2 = get_Or_right(node);
888 assert (! mode_is_float(get_irn_mode(node)));
889 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
895 * Creates an ia32 Eor.
897 * @return The created ia32 Eor node
899 static ir_node *gen_Eor(ir_node *node) {
900 ir_node *op1 = get_Eor_left(node);
901 ir_node *op2 = get_Eor_right(node);
903 assert(! mode_is_float(get_irn_mode(node)));
904 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
910 * Creates an ia32 Max.
912 * @return the created ia32 Max node
914 static ir_node *gen_Max(ir_node *node) {
915 ir_node *block = be_transform_node(get_nodes_block(node));
916 ir_node *op1 = get_irn_n(node, 0);
917 ir_node *new_op1 = be_transform_node(op1);
918 ir_node *op2 = get_irn_n(node, 1);
919 ir_node *new_op2 = be_transform_node(op2);
920 ir_graph *irg = current_ir_graph;
921 ir_mode *mode = get_irn_mode(node);
922 dbg_info *dbgi = get_irn_dbg_info(node);
923 ir_mode *op_mode = get_irn_mode(op1);
926 assert(get_mode_size_bits(mode) == 32);
928 if (mode_is_float(mode)) {
930 if (USE_SSE2(env_cg)) {
931 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
933 panic("Can't create Max node");
936 long pnc = pn_Cmp_Gt;
937 if (! mode_is_signed(op_mode)) {
938 pnc |= ia32_pn_Cmp_Unsigned;
940 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
941 new_op1, new_op2, pnc);
943 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
949 * Creates an ia32 Min.
951 * @return the created ia32 Min node
953 static ir_node *gen_Min(ir_node *node) {
954 ir_node *block = be_transform_node(get_nodes_block(node));
955 ir_node *op1 = get_irn_n(node, 0);
956 ir_node *new_op1 = be_transform_node(op1);
957 ir_node *op2 = get_irn_n(node, 1);
958 ir_node *new_op2 = be_transform_node(op2);
959 ir_graph *irg = current_ir_graph;
960 ir_mode *mode = get_irn_mode(node);
961 dbg_info *dbgi = get_irn_dbg_info(node);
962 ir_mode *op_mode = get_irn_mode(op1);
965 assert(get_mode_size_bits(mode) == 32);
967 if (mode_is_float(mode)) {
969 if (USE_SSE2(env_cg)) {
970 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
972 panic("can't create Min node");
975 long pnc = pn_Cmp_Lt;
976 if (! mode_is_signed(op_mode)) {
977 pnc |= ia32_pn_Cmp_Unsigned;
979 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
980 new_op1, new_op2, pnc);
982 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
989 * Creates an ia32 Sub.
991 * @return The created ia32 Sub node
993 static ir_node *gen_Sub(ir_node *node) {
994 ir_node *block = be_transform_node(get_nodes_block(node));
995 ir_node *op1 = get_Sub_left(node);
996 ir_node *new_op1 = be_transform_node(op1);
997 ir_node *op2 = get_Sub_right(node);
998 ir_node *new_op2 = be_transform_node(op2);
999 ir_node *new_op = NULL;
1000 ir_graph *irg = current_ir_graph;
1001 dbg_info *dbgi = get_irn_dbg_info(node);
1002 ir_mode *mode = get_irn_mode(node);
1003 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1004 ir_node *nomem = new_NoMem();
1005 ir_node *expr_op, *imm_op;
1007 /* Check if immediate optimization is on and */
1008 /* if it's an operation with immediate. */
1009 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1010 expr_op = get_expr_op(new_op1, new_op2);
1012 assert((expr_op || imm_op) && "invalid operands");
1014 if (mode_is_float(mode)) {
1016 if (USE_SSE2(env_cg))
1017 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1019 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1024 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1025 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1027 /* No expr_op means, that we have two const - one symconst and */
1028 /* one tarval or another symconst - because this case is not */
1029 /* covered by constant folding */
1030 /* We need to check for: */
1031 /* 1) symconst - const -> becomes a LEA */
1032 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1033 /* linker doesn't support two symconsts */
1034 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1035 /* this is the 2nd case */
1036 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1037 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1038 set_ia32_am_sc_sign(new_op);
1039 set_ia32_am_flavour(new_op, ia32_am_B);
1041 DBG_OPT_LEA3(op1, op2, node, new_op);
1042 } else if (tp1 == ia32_ImmSymConst) {
1043 tarval *tv = get_ia32_Immop_tarval(new_op2);
1044 long offs = get_tarval_long(tv);
1046 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1047 add_irn_dep(new_op, get_irg_frame(irg));
1048 DBG_OPT_LEA3(op1, op2, node, new_op);
1050 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1051 add_ia32_am_offs_int(new_op, -offs);
1052 set_ia32_am_flavour(new_op, ia32_am_OB);
1053 set_ia32_op_type(new_op, ia32_AddrModeS);
1054 } else if (tp2 == ia32_ImmSymConst) {
1055 tarval *tv = get_ia32_Immop_tarval(new_op1);
1056 long offs = get_tarval_long(tv);
1058 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1059 add_irn_dep(new_op, get_irg_frame(irg));
1060 DBG_OPT_LEA3(op1, op2, node, new_op);
1062 add_ia32_am_offs_int(new_op, offs);
1063 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1064 set_ia32_am_sc_sign(new_op);
1065 set_ia32_am_flavour(new_op, ia32_am_OB);
1066 set_ia32_op_type(new_op, ia32_AddrModeS);
1068 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1069 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1070 tarval *restv = tarval_sub(tv1, tv2);
1072 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1074 new_op = new_rd_ia32_Const(dbgi, irg, block);
1075 set_ia32_Const_tarval(new_op, restv);
1076 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1079 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1081 } else if (imm_op) {
1082 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1083 tarval_classification_t class_tv, class_negtv;
1084 tarval *tv = get_ia32_Immop_tarval(imm_op);
1086 /* optimize tarvals */
1087 class_tv = classify_tarval(tv);
1088 class_negtv = classify_tarval(tarval_neg(tv));
1090 if (class_tv == TV_CLASSIFY_ONE) {
1091 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1092 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1093 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1095 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1096 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1097 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1098 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1104 /* This is a normal sub */
1105 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1107 /* set AM support */
1108 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1110 fold_immediate(new_op, 2, 3);
1112 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1120 * Generates an ia32 DivMod with additional infrastructure for the
1121 * register allocator if needed.
1123 * @param dividend -no comment- :)
1124 * @param divisor -no comment- :)
1125 * @param dm_flav flavour_Div/Mod/DivMod
1126 * @return The created ia32 DivMod node
1128 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1129 ir_node *divisor, ia32_op_flavour_t dm_flav)
1131 ir_node *block = be_transform_node(get_nodes_block(node));
1132 ir_node *new_dividend = be_transform_node(dividend);
1133 ir_node *new_divisor = be_transform_node(divisor);
1134 ir_graph *irg = current_ir_graph;
1135 dbg_info *dbgi = get_irn_dbg_info(node);
1136 ir_mode *mode = get_irn_mode(node);
1137 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1138 ir_node *res, *proj_div, *proj_mod;
1139 ir_node *sign_extension;
1140 ir_node *in_keep[2];
1141 ir_node *mem, *new_mem;
1142 ir_node *projs[pn_DivMod_max];
1145 ia32_collect_Projs(node, projs, pn_DivMod_max);
1147 proj_div = proj_mod = NULL;
1151 mem = get_Div_mem(node);
1152 mode = get_Div_resmode(node);
1153 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1154 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1157 mem = get_Mod_mem(node);
1158 mode = get_Mod_resmode(node);
1159 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1160 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1162 case flavour_DivMod:
1163 mem = get_DivMod_mem(node);
1164 mode = get_DivMod_resmode(node);
1165 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1166 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1167 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1170 panic("invalid divmod flavour!");
1172 new_mem = be_transform_node(mem);
1174 if (mode_is_signed(mode)) {
1175 /* in signed mode, we need to sign extend the dividend */
1176 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1178 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1179 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1181 add_irn_dep(sign_extension, get_irg_frame(irg));
1184 if (mode_is_signed(mode)) {
1185 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1186 sign_extension, new_divisor, new_mem, dm_flav);
1188 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1189 sign_extension, new_divisor, new_mem, dm_flav);
1192 set_ia32_exc_label(res, has_exc);
1193 set_irn_pinned(res, get_irn_pinned(node));
1195 /* Matze: code can't handle this at the moment... */
1197 /* set AM support */
1198 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1201 /* check, which Proj-Keep, we need to add */
1203 if (proj_div == NULL) {
1204 /* We have only mod result: add div res Proj-Keep */
1205 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1208 if (proj_mod == NULL) {
1209 /* We have only div result: add mod res Proj-Keep */
1210 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1214 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1216 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1223 * Wrapper for generate_DivMod. Sets flavour_Mod.
1226 static ir_node *gen_Mod(ir_node *node) {
1227 return generate_DivMod(node, get_Mod_left(node),
1228 get_Mod_right(node), flavour_Mod);
1232 * Wrapper for generate_DivMod. Sets flavour_Div.
1235 static ir_node *gen_Div(ir_node *node) {
1236 return generate_DivMod(node, get_Div_left(node),
1237 get_Div_right(node), flavour_Div);
1241 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1243 static ir_node *gen_DivMod(ir_node *node) {
1244 return generate_DivMod(node, get_DivMod_left(node),
1245 get_DivMod_right(node), flavour_DivMod);
1251 * Creates an ia32 floating Div.
1253 * @return The created ia32 xDiv node
1255 static ir_node *gen_Quot(ir_node *node) {
1256 ir_node *block = be_transform_node(get_nodes_block(node));
1257 ir_node *op1 = get_Quot_left(node);
1258 ir_node *new_op1 = be_transform_node(op1);
1259 ir_node *op2 = get_Quot_right(node);
1260 ir_node *new_op2 = be_transform_node(op2);
1261 ir_graph *irg = current_ir_graph;
1262 dbg_info *dbgi = get_irn_dbg_info(node);
1263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1264 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1268 if (USE_SSE2(env_cg)) {
1269 ir_mode *mode = get_irn_mode(op1);
1270 if (is_ia32_xConst(new_op2)) {
1271 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1272 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1273 copy_ia32_Immop_attr(new_op, new_op2);
1275 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1276 // Matze: disabled for now, spillslot coalescer fails
1277 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1279 set_ia32_ls_mode(new_op, mode);
1281 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1282 &ia32_fp_cw_regs[REG_FPCW]);
1283 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1284 new_op2, nomem, fpcw);
1285 // Matze: disabled for now (spillslot coalescer fails)
1286 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1288 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1294 * Creates an ia32 Shl.
1296 * @return The created ia32 Shl node
1298 static ir_node *gen_Shl(ir_node *node) {
1299 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1306 * Creates an ia32 Shr.
1308 * @return The created ia32 Shr node
1310 static ir_node *gen_Shr(ir_node *node) {
1311 return gen_shift_binop(node, get_Shr_left(node),
1312 get_Shr_right(node), new_rd_ia32_Shr);
1318 * Creates an ia32 Sar.
1320 * @return The created ia32 Shrs node
1322 static ir_node *gen_Shrs(ir_node *node) {
1323 ir_node *left = get_Shrs_left(node);
1324 ir_node *right = get_Shrs_right(node);
1325 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1326 tarval *tv = get_Const_tarval(right);
1327 long val = get_tarval_long(tv);
1329 /* this is a sign extension */
1330 ir_graph *irg = current_ir_graph;
1331 dbg_info *dbgi = get_irn_dbg_info(node);
1332 ir_node *block = be_transform_node(get_nodes_block(node));
1334 ir_node *new_op = be_transform_node(op);
1336 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1340 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1346 * Creates an ia32 RotL.
1348 * @param op1 The first operator
1349 * @param op2 The second operator
1350 * @return The created ia32 RotL node
1352 static ir_node *gen_RotL(ir_node *node,
1353 ir_node *op1, ir_node *op2) {
1354 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1360 * Creates an ia32 RotR.
1361 * NOTE: There is no RotR with immediate because this would always be a RotL
1362 * "imm-mode_size_bits" which can be pre-calculated.
1364 * @param op1 The first operator
1365 * @param op2 The second operator
1366 * @return The created ia32 RotR node
1368 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1370 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1376 * Creates an ia32 RotR or RotL (depending on the found pattern).
1378 * @return The created ia32 RotL or RotR node
1380 static ir_node *gen_Rot(ir_node *node) {
1381 ir_node *rotate = NULL;
1382 ir_node *op1 = get_Rot_left(node);
1383 ir_node *op2 = get_Rot_right(node);
1385 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1386 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1387 that means we can create a RotR instead of an Add and a RotL */
1389 if (get_irn_op(op2) == op_Add) {
1391 ir_node *left = get_Add_left(add);
1392 ir_node *right = get_Add_right(add);
1393 if (is_Const(right)) {
1394 tarval *tv = get_Const_tarval(right);
1395 ir_mode *mode = get_irn_mode(node);
1396 long bits = get_mode_size_bits(mode);
1398 if (get_irn_op(left) == op_Minus &&
1399 tarval_is_long(tv) &&
1400 get_tarval_long(tv) == bits)
1402 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1403 rotate = gen_RotR(node, op1, get_Minus_op(left));
1408 if (rotate == NULL) {
1409 rotate = gen_RotL(node, op1, op2);
1418 * Transforms a Minus node.
1420 * @param op The Minus operand
1421 * @return The created ia32 Minus node
1423 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1424 ir_node *block = be_transform_node(get_nodes_block(node));
1425 ir_graph *irg = current_ir_graph;
1426 dbg_info *dbgi = get_irn_dbg_info(node);
1427 ir_mode *mode = get_irn_mode(node);
1432 if (mode_is_float(mode)) {
1433 ir_node *new_op = be_transform_node(op);
1435 if (USE_SSE2(env_cg)) {
1436 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1437 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1438 ir_node *nomem = new_rd_NoMem(irg);
1440 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1442 size = get_mode_size_bits(mode);
1443 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1445 set_ia32_am_sc(res, ent);
1446 set_ia32_op_type(res, ia32_AddrModeS);
1447 set_ia32_ls_mode(res, mode);
1449 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1452 res = gen_unop(node, op, new_rd_ia32_Neg);
1455 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1461 * Transforms a Minus node.
1463 * @return The created ia32 Minus node
1465 static ir_node *gen_Minus(ir_node *node) {
1466 return gen_Minus_ex(node, get_Minus_op(node));
1471 * Transforms a Not node.
1473 * @return The created ia32 Not node
1475 static ir_node *gen_Not(ir_node *node) {
1476 ir_node *op = get_Not_op(node);
1478 assert (! mode_is_float(get_irn_mode(node)));
1479 return gen_unop(node, op, new_rd_ia32_Not);
1485 * Transforms an Abs node.
1487 * @return The created ia32 Abs node
1489 static ir_node *gen_Abs(ir_node *node) {
1490 ir_node *block = be_transform_node(get_nodes_block(node));
1491 ir_node *op = get_Abs_op(node);
1492 ir_node *new_op = be_transform_node(op);
1493 ir_graph *irg = current_ir_graph;
1494 dbg_info *dbgi = get_irn_dbg_info(node);
1495 ir_mode *mode = get_irn_mode(node);
1496 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1497 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1498 ir_node *nomem = new_NoMem();
1503 if (mode_is_float(mode)) {
1505 if (USE_SSE2(env_cg)) {
1506 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1508 size = get_mode_size_bits(mode);
1509 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1511 set_ia32_am_sc(res, ent);
1513 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1515 set_ia32_op_type(res, ia32_AddrModeS);
1516 set_ia32_ls_mode(res, mode);
1519 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1520 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1524 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1525 SET_IA32_ORIG_NODE(sign_extension,
1526 ia32_get_old_node_name(env_cg, node));
1528 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1529 sign_extension, nomem);
1530 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1532 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1533 sign_extension, nomem);
1534 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1543 * Transforms a Load.
1545 * @return the created ia32 Load node
1547 static ir_node *gen_Load(ir_node *node) {
1548 ir_node *block = be_transform_node(get_nodes_block(node));
1549 ir_node *ptr = get_Load_ptr(node);
1550 ir_node *new_ptr = be_transform_node(ptr);
1551 ir_node *mem = get_Load_mem(node);
1552 ir_node *new_mem = be_transform_node(mem);
1553 ir_graph *irg = current_ir_graph;
1554 dbg_info *dbgi = get_irn_dbg_info(node);
1555 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1556 ir_mode *mode = get_Load_mode(node);
1558 ir_node *lptr = new_ptr;
1561 ir_node *projs[pn_Load_max];
1562 ia32_am_flavour_t am_flav = ia32_am_B;
1564 ia32_collect_Projs(node, projs, pn_Load_max);
1566 /* address might be a constant (symconst or absolute address) */
1567 if (is_ia32_Const(new_ptr)) {
1572 if (mode_is_float(mode)) {
1574 if (USE_SSE2(env_cg)) {
1575 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1576 res_mode = mode_xmm;
1578 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1579 res_mode = mode_vfp;
1582 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1587 check for special case: the loaded value might not be used
1589 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1590 /* add a result proj and a Keep to produce a pseudo use */
1591 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1593 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1596 /* base is a constant address */
1598 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1599 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1600 am_flav = ia32_am_N;
1602 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1603 long offs = get_tarval_long(tv);
1605 add_ia32_am_offs_int(new_op, offs);
1606 am_flav = ia32_am_O;
1610 set_irn_pinned(new_op, get_irn_pinned(node));
1611 set_ia32_op_type(new_op, ia32_AddrModeS);
1612 set_ia32_am_flavour(new_op, am_flav);
1613 set_ia32_ls_mode(new_op, mode);
1615 /* make sure we are scheduled behind the initial IncSP/Barrier
1616 * to avoid spills being placed before it
1618 if (block == get_irg_start_block(irg)) {
1619 add_irn_dep(new_op, get_irg_frame(irg));
1622 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1623 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1631 * Transforms a Store.
1633 * @return the created ia32 Store node
1635 static ir_node *gen_Store(ir_node *node) {
1636 ir_node *block = be_transform_node(get_nodes_block(node));
1637 ir_node *ptr = get_Store_ptr(node);
1638 ir_node *new_ptr = be_transform_node(ptr);
1639 ir_node *val = get_Store_value(node);
1641 ir_node *mem = get_Store_mem(node);
1642 ir_node *new_mem = be_transform_node(mem);
1643 ir_graph *irg = current_ir_graph;
1644 dbg_info *dbgi = get_irn_dbg_info(node);
1645 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1646 ir_node *sptr = new_ptr;
1647 ir_mode *mode = get_irn_mode(val);
1650 ia32_am_flavour_t am_flav = ia32_am_B;
1652 /* address might be a constant (symconst or absolute address) */
1653 if (is_ia32_Const(new_ptr)) {
1658 if (mode_is_float(mode)) {
1661 new_val = be_transform_node(val);
1662 if (USE_SSE2(env_cg)) {
1663 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1666 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1670 new_val = create_immediate_or_transform(val, 0);
1672 if (get_mode_size_bits(mode) == 8) {
1673 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1676 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1681 /* base is an constant address */
1683 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1684 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1685 am_flav = ia32_am_N;
1687 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1688 long offs = get_tarval_long(tv);
1690 add_ia32_am_offs_int(new_op, offs);
1691 am_flav = ia32_am_O;
1695 set_irn_pinned(new_op, get_irn_pinned(node));
1696 set_ia32_op_type(new_op, ia32_AddrModeD);
1697 set_ia32_am_flavour(new_op, am_flav);
1698 set_ia32_ls_mode(new_op, mode);
1700 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1701 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1706 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1708 ir_node *cmp_a = get_Cmp_left(node);
1710 ir_node *cmp_b = get_Cmp_right(node);
1720 if(!is_Const(cmp_b))
1723 tv = get_Const_tarval(cmp_b);
1724 if(!tarval_is_null(tv))
1728 if(is_And(cmp_a) && (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg)) {
1729 and_left = get_And_left(cmp_a);
1730 and_right = get_And_right(cmp_a);
1732 new_cmp_a = be_transform_node(and_left);
1733 new_cmp_b = create_immediate_or_transform(and_right, 0);
1735 new_cmp_a = be_transform_node(cmp_a);
1736 new_cmp_b = be_transform_node(cmp_a);
1739 dbgi = get_irn_dbg_info(node);
1740 noreg = ia32_new_NoReg_gp(env_cg);
1741 nomem = new_NoMem();
1743 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1744 new_cmp_a, new_cmp_b, nomem, pnc);
1745 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1746 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1751 static ir_node *create_Switch(ir_node *node)
1753 ir_graph *irg = current_ir_graph;
1754 dbg_info *dbgi = get_irn_dbg_info(node);
1755 ir_node *block = be_transform_node(get_nodes_block(node));
1756 ir_node *sel = get_Cond_selector(node);
1757 ir_node *new_sel = be_transform_node(sel);
1759 int switch_min = INT_MAX;
1760 const ir_edge_t *edge;
1762 /* determine the smallest switch case value */
1763 foreach_out_edge(node, edge) {
1764 ir_node *proj = get_edge_src_irn(edge);
1765 int pn = get_Proj_proj(proj);
1770 if (switch_min != 0) {
1771 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1773 /* if smallest switch case is not 0 we need an additional sub */
1774 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1775 add_ia32_am_offs_int(new_sel, -switch_min);
1776 set_ia32_am_flavour(new_sel, ia32_am_OB);
1777 set_ia32_op_type(new_sel, ia32_AddrModeS);
1779 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1782 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1783 set_ia32_pncode(res, get_Cond_defaultProj(node));
1785 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1791 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1793 * @return The transformed node.
1795 static ir_node *gen_Cond(ir_node *node) {
1796 ir_node *block = be_transform_node(get_nodes_block(node));
1797 ir_graph *irg = current_ir_graph;
1798 dbg_info *dbgi = get_irn_dbg_info(node);
1799 ir_node *sel = get_Cond_selector(node);
1800 ir_mode *sel_mode = get_irn_mode(sel);
1801 ir_node *res = NULL;
1802 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1809 ir_node *nomem = new_NoMem();
1812 if (sel_mode != mode_b) {
1813 return create_Switch(node);
1816 cmp = get_Proj_pred(sel);
1817 cmp_a = get_Cmp_left(cmp);
1818 cmp_b = get_Cmp_right(cmp);
1819 cmp_mode = get_irn_mode(cmp_a);
1820 pnc = get_Proj_proj(sel);
1821 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1822 pnc |= ia32_pn_Cmp_Unsigned;
1825 if(mode_needs_gp_reg(cmp_mode)) {
1826 res = try_create_TestJmp(block, cmp, pnc);
1831 new_cmp_a = be_transform_node(cmp_a);
1832 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1834 if (mode_is_float(cmp_mode)) {
1836 if (USE_SSE2(env_cg)) {
1837 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1839 set_ia32_commutative(res);
1840 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1841 set_ia32_ls_mode(res, cmp_mode);
1844 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1845 set_ia32_commutative(res);
1846 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1847 pn_ia32_vfCondJmp_temp_reg_eax);
1848 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1852 assert(get_mode_size_bits(cmp_mode) == 32);
1853 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1854 new_cmp_a, new_cmp_b, nomem, pnc);
1855 set_ia32_commutative(res);
1856 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1859 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1867 * Transforms a CopyB node.
1869 * @return The transformed node.
1871 static ir_node *gen_CopyB(ir_node *node) {
1872 ir_node *block = be_transform_node(get_nodes_block(node));
1873 ir_node *src = get_CopyB_src(node);
1874 ir_node *new_src = be_transform_node(src);
1875 ir_node *dst = get_CopyB_dst(node);
1876 ir_node *new_dst = be_transform_node(dst);
1877 ir_node *mem = get_CopyB_mem(node);
1878 ir_node *new_mem = be_transform_node(mem);
1879 ir_node *res = NULL;
1880 ir_graph *irg = current_ir_graph;
1881 dbg_info *dbgi = get_irn_dbg_info(node);
1882 int size = get_type_size_bytes(get_CopyB_type(node));
1883 ir_mode *dst_mode = get_irn_mode(dst);
1884 ir_mode *src_mode = get_irn_mode(src);
1888 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1889 /* then we need the size explicitly in ECX. */
1890 if (size >= 32 * 4) {
1891 rem = size & 0x3; /* size % 4 */
1894 res = new_rd_ia32_Const(dbgi, irg, block);
1895 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1896 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1898 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1899 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1901 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1902 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1903 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1904 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1905 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1908 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1909 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1911 /* ok: now attach Proj's because movsd will destroy esi and edi */
1912 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1913 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1914 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1917 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1923 ir_node *gen_be_Copy(ir_node *node)
1925 ir_node *result = be_duplicate_node(node);
1926 ir_mode *mode = get_irn_mode(result);
1928 if (mode_needs_gp_reg(mode)) {
1929 set_irn_mode(result, mode_Iu);
1938 * Transforms a Mux node into CMov.
1940 * @return The transformed node.
1942 static ir_node *gen_Mux(ir_node *node) {
1943 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1944 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1946 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1952 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1953 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1954 ir_node *psi_default);
1957 * Transforms a Psi node into CMov.
1959 * @return The transformed node.
1961 static ir_node *gen_Psi(ir_node *node) {
1962 ir_node *block = be_transform_node(get_nodes_block(node));
1963 ir_node *psi_true = get_Psi_val(node, 0);
1964 ir_node *psi_default = get_Psi_default(node);
1965 ia32_code_gen_t *cg = env_cg;
1966 ir_graph *irg = current_ir_graph;
1967 dbg_info *dbgi = get_irn_dbg_info(node);
1968 ir_node *cond = get_Psi_cond(node, 0);
1969 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1970 ir_node *nomem = new_NoMem();
1972 ir_node *cmp, *cmp_a, *cmp_b;
1973 ir_node *new_cmp_a, *new_cmp_b;
1977 assert(get_Psi_n_conds(node) == 1);
1978 assert(get_irn_mode(cond) == mode_b);
1980 if(is_And(cond) || is_Or(cond)) {
1981 ir_node *new_cond = be_transform_node(cond);
1982 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
1983 arch_set_irn_register(env_cg->arch_env, zero,
1984 &ia32_gp_regs[REG_GP_NOREG]);
1986 /* we have to compare the result against zero */
1987 new_cmp_a = new_cond;
1992 cmp = get_Proj_pred(cond);
1993 cmp_a = get_Cmp_left(cmp);
1994 cmp_b = get_Cmp_right(cmp);
1995 cmp_mode = get_irn_mode(cmp_a);
1996 pnc = get_Proj_proj(cond);
1998 new_cmp_a = be_transform_node(cmp_a);
1999 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2001 if (!mode_is_signed(cmp_mode)) {
2002 pnc |= ia32_pn_Cmp_Unsigned;
2006 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2007 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2008 new_cmp_a, new_cmp_b, nomem, pnc);
2009 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2010 pnc = get_negated_pnc(pnc, cmp_mode);
2011 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2012 new_cmp_a, new_cmp_b, nomem, pnc);
2014 ir_node *new_psi_true = be_transform_node(psi_true);
2015 ir_node *new_psi_default = be_transform_node(psi_default);
2016 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2017 new_psi_true, new_psi_default, pnc);
2019 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2025 * Following conversion rules apply:
2029 * 1) n bit -> m bit n > m (downscale)
2031 * 2) n bit -> m bit n == m (sign change)
2033 * 3) n bit -> m bit n < m (upscale)
2034 * a) source is signed: movsx
2035 * b) source is unsigned: and with lower bits sets
2039 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2043 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2047 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2048 * x87 is mode_E internally, conversions happen only at load and store
2049 * in non-strict semantic
2053 * Create a conversion from x87 state register to general purpose.
2055 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2056 ir_node *block = be_transform_node(get_nodes_block(node));
2057 ir_node *op = get_Conv_op(node);
2058 ir_node *new_op = be_transform_node(op);
2059 ia32_code_gen_t *cg = env_cg;
2060 ir_graph *irg = current_ir_graph;
2061 dbg_info *dbgi = get_irn_dbg_info(node);
2062 ir_node *noreg = ia32_new_NoReg_gp(cg);
2063 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2064 ir_node *fist, *load;
2067 fist = new_rd_ia32_vfist(dbgi, irg, block,
2068 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2070 set_irn_pinned(fist, op_pin_state_floats);
2071 set_ia32_use_frame(fist);
2072 set_ia32_op_type(fist, ia32_AddrModeD);
2073 set_ia32_am_flavour(fist, ia32_am_B);
2074 set_ia32_ls_mode(fist, mode_Iu);
2075 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2078 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2080 set_irn_pinned(load, op_pin_state_floats);
2081 set_ia32_use_frame(load);
2082 set_ia32_op_type(load, ia32_AddrModeS);
2083 set_ia32_am_flavour(load, ia32_am_B);
2084 set_ia32_ls_mode(load, mode_Iu);
2085 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2087 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2091 * Create a conversion from general purpose to x87 register
2093 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2094 ir_node *block = be_transform_node(get_nodes_block(node));
2095 ir_node *op = get_Conv_op(node);
2096 ir_node *new_op = be_transform_node(op);
2097 ir_graph *irg = current_ir_graph;
2098 dbg_info *dbgi = get_irn_dbg_info(node);
2099 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2100 ir_node *nomem = new_NoMem();
2101 ir_node *fild, *store;
2104 /* first convert to 32 bit if necessary */
2105 src_bits = get_mode_size_bits(src_mode);
2106 if (src_bits == 8) {
2107 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2108 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2109 set_ia32_ls_mode(new_op, src_mode);
2110 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2111 } else if (src_bits < 32) {
2112 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2113 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2114 set_ia32_ls_mode(new_op, src_mode);
2115 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2119 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2121 set_ia32_use_frame(store);
2122 set_ia32_op_type(store, ia32_AddrModeD);
2123 set_ia32_am_flavour(store, ia32_am_OB);
2124 set_ia32_ls_mode(store, mode_Iu);
2127 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2129 set_ia32_use_frame(fild);
2130 set_ia32_op_type(fild, ia32_AddrModeS);
2131 set_ia32_am_flavour(fild, ia32_am_OB);
2132 set_ia32_ls_mode(fild, mode_Iu);
2134 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2137 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2140 ir_node *block = get_nodes_block(node);
2141 ir_graph *irg = current_ir_graph;
2142 dbg_info *dbgi = get_irn_dbg_info(node);
2143 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2144 ir_node *nomem = new_NoMem();
2145 int src_bits = get_mode_size_bits(src_mode);
2146 int tgt_bits = get_mode_size_bits(tgt_mode);
2147 ir_node *frame = get_irg_frame(irg);
2148 ir_mode *smaller_mode;
2149 ir_node *store, *load;
2152 if(src_bits <= tgt_bits)
2153 smaller_mode = src_mode;
2155 smaller_mode = tgt_mode;
2157 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2159 set_ia32_use_frame(store);
2160 set_ia32_op_type(store, ia32_AddrModeD);
2161 set_ia32_am_flavour(store, ia32_am_OB);
2163 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2165 set_ia32_use_frame(load);
2166 set_ia32_op_type(load, ia32_AddrModeS);
2167 set_ia32_am_flavour(load, ia32_am_OB);
2169 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2174 * Transforms a Conv node.
2176 * @return The created ia32 Conv node
2178 static ir_node *gen_Conv(ir_node *node) {
2179 ir_node *block = be_transform_node(get_nodes_block(node));
2180 ir_node *op = get_Conv_op(node);
2181 ir_node *new_op = be_transform_node(op);
2182 ir_graph *irg = current_ir_graph;
2183 dbg_info *dbgi = get_irn_dbg_info(node);
2184 ir_mode *src_mode = get_irn_mode(op);
2185 ir_mode *tgt_mode = get_irn_mode(node);
2186 int src_bits = get_mode_size_bits(src_mode);
2187 int tgt_bits = get_mode_size_bits(tgt_mode);
2188 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2189 ir_node *nomem = new_rd_NoMem(irg);
2192 if (src_mode == tgt_mode) {
2193 if (get_Conv_strict(node)) {
2194 if (USE_SSE2(env_cg)) {
2195 /* when we are in SSE mode, we can kill all strict no-op conversion */
2199 /* this should be optimized already, but who knows... */
2200 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2201 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2206 if (mode_is_float(src_mode)) {
2207 /* we convert from float ... */
2208 if (mode_is_float(tgt_mode)) {
2209 if(src_mode == mode_E && tgt_mode == mode_D
2210 && !get_Conv_strict(node)) {
2211 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2216 if (USE_SSE2(env_cg)) {
2217 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2218 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2219 set_ia32_ls_mode(res, tgt_mode);
2221 // Matze: TODO what about strict convs?
2222 if(get_Conv_strict(node)) {
2223 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2224 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2227 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2232 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2233 if (USE_SSE2(env_cg)) {
2234 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2235 set_ia32_ls_mode(res, src_mode);
2237 return gen_x87_fp_to_gp(node);
2241 /* we convert from int ... */
2242 if (mode_is_float(tgt_mode)) {
2245 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2246 if (USE_SSE2(env_cg)) {
2247 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2248 set_ia32_ls_mode(res, tgt_mode);
2249 if(src_bits == 32) {
2250 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2253 return gen_x87_gp_to_fp(node, src_mode);
2257 ir_mode *smaller_mode;
2260 if (src_bits == tgt_bits) {
2261 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2265 if (src_bits < tgt_bits) {
2266 smaller_mode = src_mode;
2267 smaller_bits = src_bits;
2269 smaller_mode = tgt_mode;
2270 smaller_bits = tgt_bits;
2273 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2274 if (smaller_bits == 8) {
2275 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2276 set_ia32_ls_mode(res, smaller_mode);
2278 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2279 set_ia32_ls_mode(res, smaller_mode);
2281 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2291 int check_immediate_constraint(long val, char immediate_constraint_type)
2293 switch (immediate_constraint_type) {
2297 return val >= 0 && val <= 32;
2299 return val >= 0 && val <= 63;
2301 return val >= -128 && val <= 127;
2303 return val == 0xff || val == 0xffff;
2305 return val >= 0 && val <= 3;
2307 return val >= 0 && val <= 255;
2309 return val >= 0 && val <= 127;
2313 panic("Invalid immediate constraint found");
2318 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2321 tarval *offset = NULL;
2322 int offset_sign = 0;
2324 ir_entity *symconst_ent = NULL;
2325 int symconst_sign = 0;
2327 ir_node *cnst = NULL;
2328 ir_node *symconst = NULL;
2334 mode = get_irn_mode(node);
2335 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2336 !mode_is_reference(mode)) {
2340 if(is_Minus(node)) {
2342 node = get_Minus_op(node);
2345 if(is_Const(node)) {
2348 offset_sign = minus;
2349 } else if(is_SymConst(node)) {
2352 symconst_sign = minus;
2353 } else if(is_Add(node)) {
2354 ir_node *left = get_Add_left(node);
2355 ir_node *right = get_Add_right(node);
2356 if(is_Const(left) && is_SymConst(right)) {
2359 symconst_sign = minus;
2360 offset_sign = minus;
2361 } else if(is_SymConst(left) && is_Const(right)) {
2364 symconst_sign = minus;
2365 offset_sign = minus;
2367 } else if(is_Sub(node)) {
2368 ir_node *left = get_Sub_left(node);
2369 ir_node *right = get_Sub_right(node);
2370 if(is_Const(left) && is_SymConst(right)) {
2373 symconst_sign = !minus;
2374 offset_sign = minus;
2375 } else if(is_SymConst(left) && is_Const(right)) {
2378 symconst_sign = minus;
2379 offset_sign = !minus;
2386 offset = get_Const_tarval(cnst);
2387 if(tarval_is_long(offset)) {
2388 val = get_tarval_long(offset);
2389 } else if(tarval_is_null(offset)) {
2392 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2397 if(!check_immediate_constraint(val, immediate_constraint_type))
2400 if(symconst != NULL) {
2401 if(immediate_constraint_type != 0) {
2402 /* we need full 32bits for symconsts */
2406 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2408 symconst_ent = get_SymConst_entity(symconst);
2410 if(cnst == NULL && symconst == NULL)
2413 if(offset_sign && offset != NULL) {
2414 offset = tarval_neg(offset);
2417 irg = current_ir_graph;
2418 dbgi = get_irn_dbg_info(node);
2419 block = get_irg_start_block(irg);
2420 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2422 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2424 /* make sure we don't schedule stuff before the barrier */
2425 add_irn_dep(res, get_irg_frame(irg));
2431 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2433 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2434 if (new_node == NULL) {
2435 new_node = be_transform_node(node);
2440 typedef struct constraint_t constraint_t;
2441 struct constraint_t {
2444 const arch_register_req_t **out_reqs;
2446 const arch_register_req_t *req;
2447 unsigned immediate_possible;
2448 char immediate_type;
2451 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2453 int immediate_possible = 0;
2454 char immediate_type = 0;
2455 unsigned limited = 0;
2456 const arch_register_class_t *cls = NULL;
2458 struct obstack *obst;
2459 arch_register_req_t *req;
2460 unsigned *limited_ptr;
2464 /* TODO: replace all the asserts with nice error messages */
2466 printf("Constraint: %s\n", c);
2476 assert(cls == NULL ||
2477 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2478 cls = &ia32_reg_classes[CLASS_ia32_gp];
2479 limited |= 1 << REG_EAX;
2482 assert(cls == NULL ||
2483 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2484 cls = &ia32_reg_classes[CLASS_ia32_gp];
2485 limited |= 1 << REG_EBX;
2488 assert(cls == NULL ||
2489 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2490 cls = &ia32_reg_classes[CLASS_ia32_gp];
2491 limited |= 1 << REG_ECX;
2494 assert(cls == NULL ||
2495 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2496 cls = &ia32_reg_classes[CLASS_ia32_gp];
2497 limited |= 1 << REG_EDX;
2500 assert(cls == NULL ||
2501 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2502 cls = &ia32_reg_classes[CLASS_ia32_gp];
2503 limited |= 1 << REG_EDI;
2506 assert(cls == NULL ||
2507 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2508 cls = &ia32_reg_classes[CLASS_ia32_gp];
2509 limited |= 1 << REG_ESI;
2512 case 'q': /* q means lower part of the regs only, this makes no
2513 * difference to Q for us (we only assigne whole registers) */
2514 assert(cls == NULL ||
2515 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2516 cls = &ia32_reg_classes[CLASS_ia32_gp];
2517 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2521 assert(cls == NULL ||
2522 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2523 cls = &ia32_reg_classes[CLASS_ia32_gp];
2524 limited |= 1 << REG_EAX | 1 << REG_EDX;
2527 assert(cls == NULL ||
2528 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2529 cls = &ia32_reg_classes[CLASS_ia32_gp];
2530 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2531 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2538 assert(cls == NULL);
2539 cls = &ia32_reg_classes[CLASS_ia32_gp];
2545 /* TODO: mark values so the x87 simulator knows about t and u */
2546 assert(cls == NULL);
2547 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2552 assert(cls == NULL);
2553 /* TODO: check that sse2 is supported */
2554 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2564 assert(!immediate_possible);
2565 immediate_possible = 1;
2566 immediate_type = *c;
2570 assert(!immediate_possible);
2571 immediate_possible = 1;
2575 assert(!immediate_possible && cls == NULL);
2576 immediate_possible = 1;
2577 cls = &ia32_reg_classes[CLASS_ia32_gp];
2590 assert(constraint->is_in && "can only specify same constraint "
2593 sscanf(c, "%d%n", &same_as, &p);
2600 case 'E': /* no float consts yet */
2601 case 'F': /* no float consts yet */
2602 case 's': /* makes no sense on x86 */
2603 case 'X': /* we can't support that in firm */
2607 case '<': /* no autodecrement on x86 */
2608 case '>': /* no autoincrement on x86 */
2609 case 'C': /* sse constant not supported yet */
2610 case 'G': /* 80387 constant not supported yet */
2611 case 'y': /* we don't support mmx registers yet */
2612 case 'Z': /* not available in 32 bit mode */
2613 case 'e': /* not available in 32 bit mode */
2614 assert(0 && "asm constraint not supported");
2617 assert(0 && "unknown asm constraint found");
2624 const arch_register_req_t *other_constr;
2626 assert(cls == NULL && "same as and register constraint not supported");
2627 assert(!immediate_possible && "same as and immediate constraint not "
2629 assert(same_as < constraint->n_outs && "wrong constraint number in "
2630 "same_as constraint");
2632 other_constr = constraint->out_reqs[same_as];
2634 req = obstack_alloc(obst, sizeof(req[0]));
2635 req->cls = other_constr->cls;
2636 req->type = arch_register_req_type_should_be_same;
2637 req->limited = NULL;
2638 req->other_same = pos;
2639 req->other_different = -1;
2641 /* switch constraints. This is because in firm we have same_as
2642 * constraints on the output constraints while in the gcc asm syntax
2643 * they are specified on the input constraints */
2644 constraint->req = other_constr;
2645 constraint->out_reqs[same_as] = req;
2646 constraint->immediate_possible = 0;
2650 if(immediate_possible && cls == NULL) {
2651 cls = &ia32_reg_classes[CLASS_ia32_gp];
2653 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2654 assert(cls != NULL);
2656 if(immediate_possible) {
2657 assert(constraint->is_in
2658 && "imeediates make no sense for output constraints");
2660 /* todo: check types (no float input on 'r' constrainted in and such... */
2662 irg = current_ir_graph;
2663 obst = get_irg_obstack(irg);
2666 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2667 limited_ptr = (unsigned*) (req+1);
2669 req = obstack_alloc(obst, sizeof(req[0]));
2671 memset(req, 0, sizeof(req[0]));
2674 req->type = arch_register_req_type_limited;
2675 *limited_ptr = limited;
2676 req->limited = limited_ptr;
2678 req->type = arch_register_req_type_normal;
2682 constraint->req = req;
2683 constraint->immediate_possible = immediate_possible;
2684 constraint->immediate_type = immediate_type;
2688 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2695 panic("Clobbers not supported yet");
2698 ir_node *gen_ASM(ir_node *node)
2701 ir_graph *irg = current_ir_graph;
2702 ir_node *block = be_transform_node(get_nodes_block(node));
2703 dbg_info *dbgi = get_irn_dbg_info(node);
2710 ia32_asm_attr_t *attr;
2711 const arch_register_req_t **out_reqs;
2712 const arch_register_req_t **in_reqs;
2713 struct obstack *obst;
2714 constraint_t parsed_constraint;
2716 /* assembler could contain float statements */
2719 /* transform inputs */
2720 arity = get_irn_arity(node);
2721 in = alloca(arity * sizeof(in[0]));
2722 memset(in, 0, arity * sizeof(in[0]));
2724 n_outs = get_ASM_n_output_constraints(node);
2725 n_clobbers = get_ASM_n_clobbers(node);
2726 out_arity = n_outs + n_clobbers;
2728 /* construct register constraints */
2729 obst = get_irg_obstack(irg);
2730 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2731 parsed_constraint.out_reqs = out_reqs;
2732 parsed_constraint.n_outs = n_outs;
2733 parsed_constraint.is_in = 0;
2734 for(i = 0; i < out_arity; ++i) {
2738 const ir_asm_constraint *constraint;
2739 constraint = & get_ASM_output_constraints(node) [i];
2740 c = get_id_str(constraint->constraint);
2741 parse_asm_constraint(i, &parsed_constraint, c);
2743 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2744 c = get_id_str(glob_id);
2745 parse_clobber(node, i, &parsed_constraint, c);
2747 out_reqs[i] = parsed_constraint.req;
2750 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2751 parsed_constraint.is_in = 1;
2752 for(i = 0; i < arity; ++i) {
2753 const ir_asm_constraint *constraint;
2757 constraint = & get_ASM_input_constraints(node) [i];
2758 constr_id = constraint->constraint;
2759 c = get_id_str(constr_id);
2760 parse_asm_constraint(i, &parsed_constraint, c);
2761 in_reqs[i] = parsed_constraint.req;
2763 if(parsed_constraint.immediate_possible) {
2764 ir_node *pred = get_irn_n(node, i);
2765 char imm_type = parsed_constraint.immediate_type;
2766 ir_node *immediate = try_create_Immediate(pred, imm_type);
2768 if(immediate != NULL) {
2774 /* transform inputs */
2775 for(i = 0; i < arity; ++i) {
2777 ir_node *transformed;
2782 pred = get_irn_n(node, i);
2783 transformed = be_transform_node(pred);
2784 in[i] = transformed;
2787 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2789 generic_attr = get_irn_generic_attr(res);
2790 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2791 attr->asm_text = get_ASM_text(node);
2792 set_ia32_out_req_all(res, out_reqs);
2793 set_ia32_in_req_all(res, in_reqs);
2795 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2800 /********************************************
2803 * | |__ ___ _ __ ___ __| | ___ ___
2804 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2805 * | |_) | __/ | | | (_) | (_| | __/\__ \
2806 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2808 ********************************************/
2810 static ir_node *gen_be_StackParam(ir_node *node) {
2811 ir_node *block = be_transform_node(get_nodes_block(node));
2812 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2813 ir_node *new_ptr = be_transform_node(ptr);
2814 ir_node *new_op = NULL;
2815 ir_graph *irg = current_ir_graph;
2816 dbg_info *dbgi = get_irn_dbg_info(node);
2817 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2818 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2819 ir_mode *load_mode = get_irn_mode(node);
2820 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2824 if (mode_is_float(load_mode)) {
2826 if (USE_SSE2(env_cg)) {
2827 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2828 pn_res = pn_ia32_xLoad_res;
2829 proj_mode = mode_xmm;
2831 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2832 pn_res = pn_ia32_vfld_res;
2833 proj_mode = mode_vfp;
2836 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2837 proj_mode = mode_Iu;
2838 pn_res = pn_ia32_Load_res;
2841 set_irn_pinned(new_op, op_pin_state_floats);
2842 set_ia32_frame_ent(new_op, ent);
2843 set_ia32_use_frame(new_op);
2845 set_ia32_op_type(new_op, ia32_AddrModeS);
2846 set_ia32_am_flavour(new_op, ia32_am_B);
2847 set_ia32_ls_mode(new_op, load_mode);
2848 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2850 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2852 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2856 * Transforms a FrameAddr into an ia32 Add.
2858 static ir_node *gen_be_FrameAddr(ir_node *node) {
2859 ir_node *block = be_transform_node(get_nodes_block(node));
2860 ir_node *op = be_get_FrameAddr_frame(node);
2861 ir_node *new_op = be_transform_node(op);
2862 ir_graph *irg = current_ir_graph;
2863 dbg_info *dbgi = get_irn_dbg_info(node);
2864 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2867 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2868 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2869 set_ia32_use_frame(res);
2870 set_ia32_am_flavour(res, ia32_am_OB);
2872 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2878 * Transforms a FrameLoad into an ia32 Load.
2880 static ir_node *gen_be_FrameLoad(ir_node *node) {
2881 ir_node *block = be_transform_node(get_nodes_block(node));
2882 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2883 ir_node *new_mem = be_transform_node(mem);
2884 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2885 ir_node *new_ptr = be_transform_node(ptr);
2886 ir_node *new_op = NULL;
2887 ir_graph *irg = current_ir_graph;
2888 dbg_info *dbgi = get_irn_dbg_info(node);
2889 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2890 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2891 ir_mode *mode = get_type_mode(get_entity_type(ent));
2892 ir_node *projs[pn_Load_max];
2894 ia32_collect_Projs(node, projs, pn_Load_max);
2896 if (mode_is_float(mode)) {
2898 if (USE_SSE2(env_cg)) {
2899 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2902 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2906 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2909 set_irn_pinned(new_op, op_pin_state_floats);
2910 set_ia32_frame_ent(new_op, ent);
2911 set_ia32_use_frame(new_op);
2913 set_ia32_op_type(new_op, ia32_AddrModeS);
2914 set_ia32_am_flavour(new_op, ia32_am_B);
2915 set_ia32_ls_mode(new_op, mode);
2916 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2918 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2925 * Transforms a FrameStore into an ia32 Store.
2927 static ir_node *gen_be_FrameStore(ir_node *node) {
2928 ir_node *block = be_transform_node(get_nodes_block(node));
2929 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2930 ir_node *new_mem = be_transform_node(mem);
2931 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2932 ir_node *new_ptr = be_transform_node(ptr);
2933 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2934 ir_node *new_val = be_transform_node(val);
2935 ir_node *new_op = NULL;
2936 ir_graph *irg = current_ir_graph;
2937 dbg_info *dbgi = get_irn_dbg_info(node);
2938 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2939 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2940 ir_mode *mode = get_irn_mode(val);
2942 if (mode_is_float(mode)) {
2944 if (USE_SSE2(env_cg)) {
2945 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2947 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2949 } else if (get_mode_size_bits(mode) == 8) {
2950 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2952 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2955 set_ia32_frame_ent(new_op, ent);
2956 set_ia32_use_frame(new_op);
2958 set_ia32_op_type(new_op, ia32_AddrModeD);
2959 set_ia32_am_flavour(new_op, ia32_am_B);
2960 set_ia32_ls_mode(new_op, mode);
2962 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2968 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2970 static ir_node *gen_be_Return(ir_node *node) {
2971 ir_graph *irg = current_ir_graph;
2972 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2973 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2974 ir_entity *ent = get_irg_entity(irg);
2975 ir_type *tp = get_entity_type(ent);
2980 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2981 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2984 int pn_ret_val, pn_ret_mem, arity, i;
2986 assert(ret_val != NULL);
2987 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2988 return be_duplicate_node(node);
2991 res_type = get_method_res_type(tp, 0);
2993 if (! is_Primitive_type(res_type)) {
2994 return be_duplicate_node(node);
2997 mode = get_type_mode(res_type);
2998 if (! mode_is_float(mode)) {
2999 return be_duplicate_node(node);
3002 assert(get_method_n_ress(tp) == 1);
3004 pn_ret_val = get_Proj_proj(ret_val);
3005 pn_ret_mem = get_Proj_proj(ret_mem);
3007 /* get the Barrier */
3008 barrier = get_Proj_pred(ret_val);
3010 /* get result input of the Barrier */
3011 ret_val = get_irn_n(barrier, pn_ret_val);
3012 new_ret_val = be_transform_node(ret_val);
3014 /* get memory input of the Barrier */
3015 ret_mem = get_irn_n(barrier, pn_ret_mem);
3016 new_ret_mem = be_transform_node(ret_mem);
3018 frame = get_irg_frame(irg);
3020 dbgi = get_irn_dbg_info(barrier);
3021 block = be_transform_node(get_nodes_block(barrier));
3023 noreg = ia32_new_NoReg_gp(env_cg);
3025 /* store xmm0 onto stack */
3026 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3027 set_ia32_ls_mode(sse_store, mode);
3028 set_ia32_op_type(sse_store, ia32_AddrModeD);
3029 set_ia32_use_frame(sse_store);
3030 set_ia32_am_flavour(sse_store, ia32_am_B);
3033 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3034 set_ia32_ls_mode(fld, mode);
3035 set_ia32_op_type(fld, ia32_AddrModeS);
3036 set_ia32_use_frame(fld);
3037 set_ia32_am_flavour(fld, ia32_am_B);
3039 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3040 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3041 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3043 /* create a new barrier */
3044 arity = get_irn_arity(barrier);
3045 in = alloca(arity * sizeof(in[0]));
3046 for (i = 0; i < arity; ++i) {
3049 if (i == pn_ret_val) {
3051 } else if (i == pn_ret_mem) {
3054 ir_node *in = get_irn_n(barrier, i);
3055 new_in = be_transform_node(in);
3060 new_barrier = new_ir_node(dbgi, irg, block,
3061 get_irn_op(barrier), get_irn_mode(barrier),
3063 copy_node_attr(barrier, new_barrier);
3064 be_duplicate_deps(barrier, new_barrier);
3065 be_set_transformed_node(barrier, new_barrier);
3066 mark_irn_visited(barrier);
3068 /* transform normally */
3069 return be_duplicate_node(node);
3073 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3075 static ir_node *gen_be_AddSP(ir_node *node) {
3076 ir_node *block = be_transform_node(get_nodes_block(node));
3077 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3079 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3080 ir_node *new_sp = be_transform_node(sp);
3081 ir_graph *irg = current_ir_graph;
3082 dbg_info *dbgi = get_irn_dbg_info(node);
3083 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3084 ir_node *nomem = new_NoMem();
3087 new_sz = create_immediate_or_transform(sz, 0);
3089 /* ia32 stack grows in reverse direction, make a SubSP */
3090 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3092 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3093 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3099 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3101 static ir_node *gen_be_SubSP(ir_node *node) {
3102 ir_node *block = be_transform_node(get_nodes_block(node));
3103 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3105 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3106 ir_node *new_sp = be_transform_node(sp);
3107 ir_graph *irg = current_ir_graph;
3108 dbg_info *dbgi = get_irn_dbg_info(node);
3109 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3110 ir_node *nomem = new_NoMem();
3113 new_sz = create_immediate_or_transform(sz, 0);
3115 /* ia32 stack grows in reverse direction, make an AddSP */
3116 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3117 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3118 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3124 * This function just sets the register for the Unknown node
3125 * as this is not done during register allocation because Unknown
3126 * is an "ignore" node.
3128 static ir_node *gen_Unknown(ir_node *node) {
3129 ir_mode *mode = get_irn_mode(node);
3131 if (mode_is_float(mode)) {
3132 if (USE_SSE2(env_cg))
3133 return ia32_new_Unknown_xmm(env_cg);
3135 return ia32_new_Unknown_vfp(env_cg);
3136 } else if (mode_needs_gp_reg(mode)) {
3137 return ia32_new_Unknown_gp(env_cg);
3139 assert(0 && "unsupported Unknown-Mode");
3146 * Change some phi modes
3148 static ir_node *gen_Phi(ir_node *node) {
3149 ir_node *block = be_transform_node(get_nodes_block(node));
3150 ir_graph *irg = current_ir_graph;
3151 dbg_info *dbgi = get_irn_dbg_info(node);
3152 ir_mode *mode = get_irn_mode(node);
3155 if(mode_needs_gp_reg(mode)) {
3156 /* we shouldn't have any 64bit stuff around anymore */
3157 assert(get_mode_size_bits(mode) <= 32);
3158 /* all integer operations are on 32bit registers now */
3160 } else if(mode_is_float(mode)) {
3161 if (USE_SSE2(env_cg)) {
3168 /* phi nodes allow loops, so we use the old arguments for now
3169 * and fix this later */
3170 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3171 copy_node_attr(node, phi);
3172 be_duplicate_deps(node, phi);
3174 be_set_transformed_node(node, phi);
3175 be_enqueue_preds(node);
3180 /**********************************************************************
3183 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3184 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3185 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3186 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3188 **********************************************************************/
3190 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3192 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3195 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3196 ir_node *val, ir_node *mem);
3199 * Transforms a lowered Load into a "real" one.
3201 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3202 ir_node *block = be_transform_node(get_nodes_block(node));
3203 ir_node *ptr = get_irn_n(node, 0);
3204 ir_node *new_ptr = be_transform_node(ptr);
3205 ir_node *mem = get_irn_n(node, 1);
3206 ir_node *new_mem = be_transform_node(mem);
3207 ir_graph *irg = current_ir_graph;
3208 dbg_info *dbgi = get_irn_dbg_info(node);
3209 ir_mode *mode = get_ia32_ls_mode(node);
3210 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3214 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3215 lowering we have x87 nodes, so we need to enforce simulation.
3217 if (mode_is_float(mode)) {
3219 if (fp_unit == fp_x87)
3223 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3225 set_ia32_op_type(new_op, ia32_AddrModeS);
3226 set_ia32_am_flavour(new_op, ia32_am_OB);
3227 set_ia32_am_offs_int(new_op, 0);
3228 set_ia32_am_scale(new_op, 1);
3229 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3230 if (is_ia32_am_sc_sign(node))
3231 set_ia32_am_sc_sign(new_op);
3232 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3233 if (is_ia32_use_frame(node)) {
3234 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3235 set_ia32_use_frame(new_op);
3238 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3244 * Transforms a lowered Store into a "real" one.
3246 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3247 ir_node *block = be_transform_node(get_nodes_block(node));
3248 ir_node *ptr = get_irn_n(node, 0);
3249 ir_node *new_ptr = be_transform_node(ptr);
3250 ir_node *val = get_irn_n(node, 1);
3251 ir_node *new_val = be_transform_node(val);
3252 ir_node *mem = get_irn_n(node, 2);
3253 ir_node *new_mem = be_transform_node(mem);
3254 ir_graph *irg = current_ir_graph;
3255 dbg_info *dbgi = get_irn_dbg_info(node);
3256 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3257 ir_mode *mode = get_ia32_ls_mode(node);
3260 ia32_am_flavour_t am_flav = ia32_B;
3263 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3264 lowering we have x87 nodes, so we need to enforce simulation.
3266 if (mode_is_float(mode)) {
3268 if (fp_unit == fp_x87)
3272 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3274 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3276 add_ia32_am_offs_int(new_op, am_offs);
3279 set_ia32_op_type(new_op, ia32_AddrModeD);
3280 set_ia32_am_flavour(new_op, am_flav);
3281 set_ia32_ls_mode(new_op, mode);
3282 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3283 set_ia32_use_frame(new_op);
3285 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3292 * Transforms an ia32_l_XXX into a "real" XXX node
3294 * @param env The transformation environment
3295 * @return the created ia32 XXX node
3297 #define GEN_LOWERED_OP(op) \
3298 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3299 ir_mode *mode = get_irn_mode(node); \
3300 if (mode_is_float(mode)) \
3302 return gen_binop(node, get_binop_left(node), \
3303 get_binop_right(node), new_rd_ia32_##op,0); \
3306 #define GEN_LOWERED_x87_OP(op) \
3307 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3309 FORCE_x87(env_cg); \
3310 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3311 get_binop_right(node), new_rd_ia32_##op); \
3315 #define GEN_LOWERED_UNOP(op) \
3316 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3317 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3320 #define GEN_LOWERED_SHIFT_OP(op) \
3321 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3322 return gen_shift_binop(node, get_binop_left(node), \
3323 get_binop_right(node), new_rd_ia32_##op); \
3326 #define GEN_LOWERED_LOAD(op, fp_unit) \
3327 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3328 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3331 #define GEN_LOWERED_STORE(op, fp_unit) \
3332 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3333 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3340 GEN_LOWERED_OP(IMul)
3342 GEN_LOWERED_x87_OP(vfprem)
3343 GEN_LOWERED_x87_OP(vfmul)
3344 GEN_LOWERED_x87_OP(vfsub)
3346 GEN_LOWERED_UNOP(Neg)
3348 GEN_LOWERED_LOAD(vfild, fp_x87)
3349 GEN_LOWERED_LOAD(Load, fp_none)
3350 /*GEN_LOWERED_STORE(vfist, fp_x87)
3353 GEN_LOWERED_STORE(Store, fp_none)
3355 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3356 ir_node *block = be_transform_node(get_nodes_block(node));
3357 ir_node *left = get_binop_left(node);
3358 ir_node *new_left = be_transform_node(left);
3359 ir_node *right = get_binop_right(node);
3360 ir_node *new_right = be_transform_node(right);
3361 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3362 ir_graph *irg = current_ir_graph;
3363 dbg_info *dbgi = get_irn_dbg_info(node);
3364 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3365 &ia32_fp_cw_regs[REG_FPCW]);
3368 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3369 new_right, new_NoMem(), fpcw);
3370 clear_ia32_commutative(vfdiv);
3371 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3373 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3381 * Transforms a l_MulS into a "real" MulS node.
3383 * @param env The transformation environment
3384 * @return the created ia32 Mul node
3386 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3387 ir_node *block = be_transform_node(get_nodes_block(node));
3388 ir_node *left = get_binop_left(node);
3389 ir_node *new_left = be_transform_node(left);
3390 ir_node *right = get_binop_right(node);
3391 ir_node *new_right = be_transform_node(right);
3392 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3393 ir_graph *irg = current_ir_graph;
3394 dbg_info *dbgi = get_irn_dbg_info(node);
3397 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3398 /* and then skip the result Proj, because all needed Projs are already there. */
3399 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3400 new_right, new_NoMem());
3401 clear_ia32_commutative(muls);
3402 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3404 /* check if EAX and EDX proj exist, add missing one */
3405 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3406 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3407 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3409 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3414 GEN_LOWERED_SHIFT_OP(Shl)
3415 GEN_LOWERED_SHIFT_OP(Shr)
3416 GEN_LOWERED_SHIFT_OP(Sar)
3419 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3420 * op1 - target to be shifted
3421 * op2 - contains bits to be shifted into target
3423 * Only op3 can be an immediate.
3425 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3426 ir_node *op2, ir_node *count)
3428 ir_node *block = be_transform_node(get_nodes_block(node));
3429 ir_node *new_op1 = be_transform_node(op1);
3430 ir_node *new_op2 = be_transform_node(op2);
3431 ir_node *new_count = be_transform_node(count);
3432 ir_node *new_op = NULL;
3433 ir_graph *irg = current_ir_graph;
3434 dbg_info *dbgi = get_irn_dbg_info(node);
3435 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3436 ir_node *nomem = new_NoMem();
3440 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3442 /* Check if immediate optimization is on and */
3443 /* if it's an operation with immediate. */
3444 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3446 /* Limit imm_op within range imm8 */
3448 tv = get_ia32_Immop_tarval(imm_op);
3451 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3452 set_ia32_Immop_tarval(imm_op, tv);
3459 /* integer operations */
3461 /* This is ShiftD with const */
3462 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3464 if (is_ia32_l_ShlD(node))
3465 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3466 new_op1, new_op2, noreg, nomem);
3468 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3469 new_op1, new_op2, noreg, nomem);
3470 copy_ia32_Immop_attr(new_op, imm_op);
3473 /* This is a normal ShiftD */
3474 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3475 if (is_ia32_l_ShlD(node))
3476 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3477 new_op1, new_op2, new_count, nomem);
3479 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3480 new_op1, new_op2, new_count, nomem);
3483 /* set AM support */
3484 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3486 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3488 set_ia32_emit_cl(new_op);
3493 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3494 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3495 get_irn_n(node, 1), get_irn_n(node, 2));
3498 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3499 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3500 get_irn_n(node, 1), get_irn_n(node, 2));
3504 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3506 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3507 ir_node *block = be_transform_node(get_nodes_block(node));
3508 ir_node *val = get_irn_n(node, 1);
3509 ir_node *new_val = be_transform_node(val);
3510 ia32_code_gen_t *cg = env_cg;
3511 ir_node *res = NULL;
3512 ir_graph *irg = current_ir_graph;
3514 ir_node *noreg, *new_ptr, *new_mem;
3521 mem = get_irn_n(node, 2);
3522 new_mem = be_transform_node(mem);
3523 ptr = get_irn_n(node, 0);
3524 new_ptr = be_transform_node(ptr);
3525 noreg = ia32_new_NoReg_gp(cg);
3526 dbgi = get_irn_dbg_info(node);
3528 /* Store x87 -> MEM */
3529 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3530 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3531 set_ia32_use_frame(res);
3532 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3533 set_ia32_am_flavour(res, ia32_B);
3534 set_ia32_op_type(res, ia32_AddrModeD);
3536 /* Load MEM -> SSE */
3537 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3538 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3539 set_ia32_use_frame(res);
3540 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3541 set_ia32_am_flavour(res, ia32_B);
3542 set_ia32_op_type(res, ia32_AddrModeS);
3543 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3549 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3551 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3552 ir_node *block = be_transform_node(get_nodes_block(node));
3553 ir_node *val = get_irn_n(node, 1);
3554 ir_node *new_val = be_transform_node(val);
3555 ia32_code_gen_t *cg = env_cg;
3556 ir_graph *irg = current_ir_graph;
3557 ir_node *res = NULL;
3558 ir_entity *fent = get_ia32_frame_ent(node);
3559 ir_mode *lsmode = get_ia32_ls_mode(node);
3561 ir_node *noreg, *new_ptr, *new_mem;
3565 if (! USE_SSE2(cg)) {
3566 /* SSE unit is not used -> skip this node. */
3570 ptr = get_irn_n(node, 0);
3571 new_ptr = be_transform_node(ptr);
3572 mem = get_irn_n(node, 2);
3573 new_mem = be_transform_node(mem);
3574 noreg = ia32_new_NoReg_gp(cg);
3575 dbgi = get_irn_dbg_info(node);
3577 /* Store SSE -> MEM */
3578 if (is_ia32_xLoad(skip_Proj(new_val))) {
3579 ir_node *ld = skip_Proj(new_val);
3581 /* we can vfld the value directly into the fpu */
3582 fent = get_ia32_frame_ent(ld);
3583 ptr = get_irn_n(ld, 0);
3584 offs = get_ia32_am_offs_int(ld);
3586 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3587 set_ia32_frame_ent(res, fent);
3588 set_ia32_use_frame(res);
3589 set_ia32_ls_mode(res, lsmode);
3590 set_ia32_am_flavour(res, ia32_B);
3591 set_ia32_op_type(res, ia32_AddrModeD);
3595 /* Load MEM -> x87 */
3596 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3597 set_ia32_frame_ent(res, fent);
3598 set_ia32_use_frame(res);
3599 add_ia32_am_offs_int(res, offs);
3600 set_ia32_am_flavour(res, ia32_B);
3601 set_ia32_op_type(res, ia32_AddrModeS);
3602 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3607 /*********************************************************
3610 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3611 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3612 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3613 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3615 *********************************************************/
3618 * the BAD transformer.
3620 static ir_node *bad_transform(ir_node *node) {
3621 panic("No transform function for %+F available.\n", node);
3626 * Transform the Projs of an AddSP.
3628 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3629 ir_node *block = be_transform_node(get_nodes_block(node));
3630 ir_node *pred = get_Proj_pred(node);
3631 ir_node *new_pred = be_transform_node(pred);
3632 ir_graph *irg = current_ir_graph;
3633 dbg_info *dbgi = get_irn_dbg_info(node);
3634 long proj = get_Proj_proj(node);
3636 if (proj == pn_be_AddSP_res) {
3637 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3638 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3640 } else if (proj == pn_be_AddSP_M) {
3641 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3645 return new_rd_Unknown(irg, get_irn_mode(node));
3649 * Transform the Projs of a SubSP.
3651 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3652 ir_node *block = be_transform_node(get_nodes_block(node));
3653 ir_node *pred = get_Proj_pred(node);
3654 ir_node *new_pred = be_transform_node(pred);
3655 ir_graph *irg = current_ir_graph;
3656 dbg_info *dbgi = get_irn_dbg_info(node);
3657 long proj = get_Proj_proj(node);
3659 if (proj == pn_be_SubSP_res) {
3660 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3661 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3663 } else if (proj == pn_be_SubSP_M) {
3664 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3668 return new_rd_Unknown(irg, get_irn_mode(node));
3672 * Transform and renumber the Projs from a Load.
3674 static ir_node *gen_Proj_Load(ir_node *node) {
3675 ir_node *block = be_transform_node(get_nodes_block(node));
3676 ir_node *pred = get_Proj_pred(node);
3677 ir_node *new_pred = be_transform_node(pred);
3678 ir_graph *irg = current_ir_graph;
3679 dbg_info *dbgi = get_irn_dbg_info(node);
3680 long proj = get_Proj_proj(node);
3682 /* renumber the proj */
3683 if (is_ia32_Load(new_pred)) {
3684 if (proj == pn_Load_res) {
3685 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3686 } else if (proj == pn_Load_M) {
3687 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3689 } else if (is_ia32_xLoad(new_pred)) {
3690 if (proj == pn_Load_res) {
3691 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3692 } else if (proj == pn_Load_M) {
3693 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3695 } else if (is_ia32_vfld(new_pred)) {
3696 if (proj == pn_Load_res) {
3697 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3698 } else if (proj == pn_Load_M) {
3699 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3704 return new_rd_Unknown(irg, get_irn_mode(node));
3708 * Transform and renumber the Projs from a DivMod like instruction.
3710 static ir_node *gen_Proj_DivMod(ir_node *node) {
3711 ir_node *block = be_transform_node(get_nodes_block(node));
3712 ir_node *pred = get_Proj_pred(node);
3713 ir_node *new_pred = be_transform_node(pred);
3714 ir_graph *irg = current_ir_graph;
3715 dbg_info *dbgi = get_irn_dbg_info(node);
3716 ir_mode *mode = get_irn_mode(node);
3717 long proj = get_Proj_proj(node);
3719 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3721 switch (get_irn_opcode(pred)) {
3725 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3727 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3735 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3737 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3745 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3746 case pn_DivMod_res_div:
3747 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3748 case pn_DivMod_res_mod:
3749 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3759 return new_rd_Unknown(irg, mode);
3763 * Transform and renumber the Projs from a CopyB.
3765 static ir_node *gen_Proj_CopyB(ir_node *node) {
3766 ir_node *block = be_transform_node(get_nodes_block(node));
3767 ir_node *pred = get_Proj_pred(node);
3768 ir_node *new_pred = be_transform_node(pred);
3769 ir_graph *irg = current_ir_graph;
3770 dbg_info *dbgi = get_irn_dbg_info(node);
3771 ir_mode *mode = get_irn_mode(node);
3772 long proj = get_Proj_proj(node);
3775 case pn_CopyB_M_regular:
3776 if (is_ia32_CopyB_i(new_pred)) {
3777 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3778 } else if (is_ia32_CopyB(new_pred)) {
3779 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3787 return new_rd_Unknown(irg, mode);
3791 * Transform and renumber the Projs from a vfdiv.
3793 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3794 ir_node *block = be_transform_node(get_nodes_block(node));
3795 ir_node *pred = get_Proj_pred(node);
3796 ir_node *new_pred = be_transform_node(pred);
3797 ir_graph *irg = current_ir_graph;
3798 dbg_info *dbgi = get_irn_dbg_info(node);
3799 ir_mode *mode = get_irn_mode(node);
3800 long proj = get_Proj_proj(node);
3803 case pn_ia32_l_vfdiv_M:
3804 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3805 case pn_ia32_l_vfdiv_res:
3806 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3811 return new_rd_Unknown(irg, mode);
3815 * Transform and renumber the Projs from a Quot.
3817 static ir_node *gen_Proj_Quot(ir_node *node) {
3818 ir_node *block = be_transform_node(get_nodes_block(node));
3819 ir_node *pred = get_Proj_pred(node);
3820 ir_node *new_pred = be_transform_node(pred);
3821 ir_graph *irg = current_ir_graph;
3822 dbg_info *dbgi = get_irn_dbg_info(node);
3823 ir_mode *mode = get_irn_mode(node);
3824 long proj = get_Proj_proj(node);
3828 if (is_ia32_xDiv(new_pred)) {
3829 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3830 } else if (is_ia32_vfdiv(new_pred)) {
3831 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3835 if (is_ia32_xDiv(new_pred)) {
3836 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3837 } else if (is_ia32_vfdiv(new_pred)) {
3838 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3846 return new_rd_Unknown(irg, mode);
3850 * Transform the Thread Local Storage Proj.
3852 static ir_node *gen_Proj_tls(ir_node *node) {
3853 ir_node *block = be_transform_node(get_nodes_block(node));
3854 ir_graph *irg = current_ir_graph;
3855 dbg_info *dbgi = NULL;
3856 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3862 * Transform the Projs from a be_Call.
3864 static ir_node *gen_Proj_be_Call(ir_node *node) {
3865 ir_node *block = be_transform_node(get_nodes_block(node));
3866 ir_node *call = get_Proj_pred(node);
3867 ir_node *new_call = be_transform_node(call);
3868 ir_graph *irg = current_ir_graph;
3869 dbg_info *dbgi = get_irn_dbg_info(node);
3870 long proj = get_Proj_proj(node);
3871 ir_mode *mode = get_irn_mode(node);
3873 const arch_register_class_t *cls;
3875 /* The following is kinda tricky: If we're using SSE, then we have to
3876 * move the result value of the call in floating point registers to an
3877 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3878 * after the call, we have to make sure to correctly make the
3879 * MemProj and the result Proj use these 2 nodes
3881 if (proj == pn_be_Call_M_regular) {
3882 // get new node for result, are we doing the sse load/store hack?
3883 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3884 ir_node *call_res_new;
3885 ir_node *call_res_pred = NULL;
3887 if (call_res != NULL) {
3888 call_res_new = be_transform_node(call_res);
3889 call_res_pred = get_Proj_pred(call_res_new);
3892 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3893 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3895 assert(is_ia32_xLoad(call_res_pred));
3896 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3899 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3901 ir_node *frame = get_irg_frame(irg);
3902 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3904 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3906 const arch_register_class_t *cls;
3908 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3909 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3911 /* store st(0) onto stack */
3912 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3914 set_ia32_ls_mode(fstp, mode);
3915 set_ia32_op_type(fstp, ia32_AddrModeD);
3916 set_ia32_use_frame(fstp);
3917 set_ia32_am_flavour(fstp, ia32_am_B);
3919 /* load into SSE register */
3920 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3921 set_ia32_ls_mode(sse_load, mode);
3922 set_ia32_op_type(sse_load, ia32_AddrModeS);
3923 set_ia32_use_frame(sse_load);
3924 set_ia32_am_flavour(sse_load, ia32_am_B);
3926 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3928 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3930 /* get a Proj representing a caller save register */
3931 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3932 assert(is_Proj(p) && "Proj expected.");
3934 /* user of the the proj is the Keep */
3935 p = get_edge_src_irn(get_irn_out_edge_first(p));
3936 assert(be_is_Keep(p) && "Keep expected.");
3938 /* keep the result */
3939 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3940 keepin[0] = sse_load;
3941 be_new_Keep(cls, irg, block, 1, keepin);
3946 /* transform call modes */
3947 if (mode_is_data(mode)) {
3948 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3952 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3956 * Transform the Projs from a Cmp.
3958 static ir_node *gen_Proj_Cmp(ir_node *node)
3960 /* normally Cmps are processed when looking at Cond nodes, but this case
3961 * can happen in complicated Psi conditions */
3963 ir_graph *irg = current_ir_graph;
3964 dbg_info *dbgi = get_irn_dbg_info(node);
3965 ir_node *block = be_transform_node(get_nodes_block(node));
3966 ir_node *cmp = get_Proj_pred(node);
3967 long pnc = get_Proj_proj(node);
3968 ir_node *cmp_left = get_Cmp_left(cmp);
3969 ir_node *cmp_right = get_Cmp_right(cmp);
3970 ir_node *new_cmp_left;
3971 ir_node *new_cmp_right;
3972 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3973 ir_node *nomem = new_rd_NoMem(irg);
3974 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3977 assert(!mode_is_float(cmp_mode));
3979 /* (a != b) -> (a ^ b) */
3980 if(pnc == pn_Cmp_Lg) {
3981 if(is_Const_0(cmp_left)) {
3982 new_op = be_transform_node(cmp_right);
3983 } else if(is_Const_0(cmp_right)) {
3984 new_op = be_transform_node(cmp_left);
3986 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
3992 * (a == b) -> !(a ^ b)
3993 * (a < 0) -> (a & 0x80000000) oder a >> 31
3994 * (a >= 0) -> (a >> 31) ^ 1
3997 if(!mode_is_signed(cmp_mode)) {
3998 pnc |= ia32_pn_Cmp_Unsigned;
4001 new_cmp_left = be_transform_node(cmp_left);
4002 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
4004 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4005 new_cmp_right, nomem, pnc);
4006 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4012 * Transform and potentially renumber Proj nodes.
4014 static ir_node *gen_Proj(ir_node *node) {
4015 ir_graph *irg = current_ir_graph;
4016 dbg_info *dbgi = get_irn_dbg_info(node);
4017 ir_node *pred = get_Proj_pred(node);
4018 long proj = get_Proj_proj(node);
4020 if (is_Store(pred) || be_is_FrameStore(pred)) {
4021 if (proj == pn_Store_M) {
4022 return be_transform_node(pred);
4025 return new_r_Bad(irg);
4027 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4028 return gen_Proj_Load(node);
4029 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4030 return gen_Proj_DivMod(node);
4031 } else if (is_CopyB(pred)) {
4032 return gen_Proj_CopyB(node);
4033 } else if (is_Quot(pred)) {
4034 return gen_Proj_Quot(node);
4035 } else if (is_ia32_l_vfdiv(pred)) {
4036 return gen_Proj_l_vfdiv(node);
4037 } else if (be_is_SubSP(pred)) {
4038 return gen_Proj_be_SubSP(node);
4039 } else if (be_is_AddSP(pred)) {
4040 return gen_Proj_be_AddSP(node);
4041 } else if (be_is_Call(pred)) {
4042 return gen_Proj_be_Call(node);
4043 } else if (is_Cmp(pred)) {
4044 return gen_Proj_Cmp(node);
4045 } else if (get_irn_op(pred) == op_Start) {
4046 if (proj == pn_Start_X_initial_exec) {
4047 ir_node *block = get_nodes_block(pred);
4050 /* we exchange the ProjX with a jump */
4051 block = be_transform_node(block);
4052 jump = new_rd_Jmp(dbgi, irg, block);
4055 if (node == be_get_old_anchor(anchor_tls)) {
4056 return gen_Proj_tls(node);
4059 ir_node *new_pred = be_transform_node(pred);
4060 ir_node *block = be_transform_node(get_nodes_block(node));
4061 ir_mode *mode = get_irn_mode(node);
4062 if (mode_needs_gp_reg(mode)) {
4063 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4064 get_Proj_proj(node));
4065 #ifdef DEBUG_libfirm
4066 new_proj->node_nr = node->node_nr;
4072 return be_duplicate_node(node);
4076 * Enters all transform functions into the generic pointer
4078 static void register_transformers(void) {
4079 ir_op *op_Max, *op_Min, *op_Mulh;
4081 /* first clear the generic function pointer for all ops */
4082 clear_irp_opcodes_generic_func();
4084 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4085 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4122 /* transform ops from intrinsic lowering */
4142 /* GEN(ia32_l_vfist); TODO */
4144 GEN(ia32_l_X87toSSE);
4145 GEN(ia32_l_SSEtoX87);
4150 /* we should never see these nodes */
4165 /* handle generic backend nodes */
4176 /* set the register for all Unknown nodes */
4179 op_Max = get_op_Max();
4182 op_Min = get_op_Min();
4185 op_Mulh = get_op_Mulh();
4194 * Pre-transform all unknown and noreg nodes.
4196 static void ia32_pretransform_node(void *arch_cg) {
4197 ia32_code_gen_t *cg = arch_cg;
4199 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4200 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4201 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4202 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4203 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4204 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4207 /* do the transformation */
4208 void ia32_transform_graph(ia32_code_gen_t *cg) {
4209 register_transformers();
4211 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4214 void ia32_init_transform(void)
4216 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");