2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem, ir_mode *mode);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
84 * Gets the Proj with number pn from irn.
86 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
87 const ir_edge_t *edge;
89 assert(get_irn_mode(irn) == mode_T && "need mode_T");
91 foreach_out_edge(irn, edge) {
92 proj = get_edge_src_irn(edge);
94 if (get_Proj_proj(proj) == pn)
101 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
102 static const char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
103 static const struct {
105 const char *ent_name;
106 const char *cnst_str;
107 } names [ia32_known_const_max] = {
108 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
109 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
110 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
111 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
113 static struct entity *ent_cache[ia32_known_const_max];
115 const char *tp_name, *ent_name, *cnst_str;
122 ent_name = names[kct].ent_name;
123 if (! ent_cache[kct]) {
124 tp_name = names[kct].tp_name;
125 cnst_str = names[kct].cnst_str;
127 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
128 tp = new_type_primitive(new_id_from_str(tp_name), mode);
129 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
131 set_entity_ld_ident(ent, get_entity_ident(ent));
132 set_entity_visibility(ent, visibility_local);
133 set_entity_variability(ent, variability_constant);
134 set_entity_allocation(ent, allocation_static);
136 /* we create a new entity here: It's initialization must resist on the
138 rem = current_ir_graph;
139 current_ir_graph = get_const_code_irg();
140 cnst = new_Const(mode, tv);
141 current_ir_graph = rem;
143 set_atomic_ent_value(ent, cnst);
145 /* cache the entry */
146 ent_cache[kct] = ent;
153 * Prints the old node name on cg obst and returns a pointer to it.
155 const char *get_old_node_name(ia32_transform_env_t *env) {
156 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
158 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
159 obstack_1grow(isa->name_obst, 0);
160 isa->name_obst_size += obstack_object_size(isa->name_obst);
161 return obstack_finish(isa->name_obst);
165 /* determine if one operator is an Imm */
166 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
168 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
169 else return is_ia32_Cnst(op2) ? op2 : NULL;
172 /* determine if one operator is not an Imm */
173 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
174 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
179 * Construct a standard binary operation, set AM and immediate if required.
181 * @param env The transformation environment
182 * @param op1 The first operand
183 * @param op2 The second operand
184 * @param func The node constructor function
185 * @return The constructed ia32 node.
187 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
188 ir_node *new_op = NULL;
189 ir_mode *mode = env->mode;
190 dbg_info *dbg = env->dbg;
191 ir_graph *irg = env->irg;
192 ir_node *block = env->block;
193 firm_dbg_module_t *mod = env->mod;
194 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
195 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
196 ir_node *nomem = new_NoMem();
197 ir_node *expr_op, *imm_op;
199 /* Check if immediate optimization is on and */
200 /* if it's an operation with immediate. */
201 if (! env->cg->opt.immops) {
205 else if (is_op_commutative(get_irn_op(env->irn))) {
206 imm_op = get_immediate_op(op1, op2);
207 expr_op = get_expr_op(op1, op2);
210 imm_op = get_immediate_op(NULL, op2);
211 expr_op = get_expr_op(op1, op2);
214 assert((expr_op || imm_op) && "invalid operands");
217 /* We have two consts here: not yet supported */
221 if (mode_is_float(mode)) {
222 /* floating point operations */
224 DB((mod, LEVEL_1, "FP with immediate ..."));
225 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
226 set_ia32_Immop_attr(new_op, imm_op);
227 set_ia32_am_support(new_op, ia32_am_None);
230 DB((mod, LEVEL_1, "FP binop ..."));
231 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
232 set_ia32_am_support(new_op, ia32_am_Source);
236 /* integer operations */
238 /* This is expr + const */
239 DB((mod, LEVEL_1, "INT with immediate ..."));
240 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
241 set_ia32_Immop_attr(new_op, imm_op);
244 set_ia32_am_support(new_op, ia32_am_Dest);
247 DB((mod, LEVEL_1, "INT binop ..."));
248 /* This is a normal operation */
249 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
252 set_ia32_am_support(new_op, ia32_am_Full);
256 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
258 set_ia32_res_mode(new_op, mode);
260 if (is_op_commutative(get_irn_op(env->irn))) {
261 set_ia32_commutative(new_op);
264 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
270 * Construct a shift/rotate binary operation, sets AM and immediate if required.
272 * @param env The transformation environment
273 * @param op1 The first operand
274 * @param op2 The second operand
275 * @param func The node constructor function
276 * @return The constructed ia32 node.
278 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
279 ir_node *new_op = NULL;
280 ir_mode *mode = env->mode;
281 dbg_info *dbg = env->dbg;
282 ir_graph *irg = env->irg;
283 ir_node *block = env->block;
284 firm_dbg_module_t *mod = env->mod;
285 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
286 ir_node *nomem = new_NoMem();
287 ir_node *expr_op, *imm_op;
290 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
292 /* Check if immediate optimization is on and */
293 /* if it's an operation with immediate. */
294 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
295 expr_op = get_expr_op(op1, op2);
297 assert((expr_op || imm_op) && "invalid operands");
300 /* We have two consts here: not yet supported */
304 /* Limit imm_op within range imm8 */
306 tv = get_ia32_Immop_tarval(imm_op);
309 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
316 /* integer operations */
318 /* This is shift/rot with const */
319 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
321 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
322 set_ia32_Immop_attr(new_op, imm_op);
325 /* This is a normal shift/rot */
326 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
327 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
331 set_ia32_am_support(new_op, ia32_am_Dest);
333 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
335 set_ia32_res_mode(new_op, mode);
337 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
342 * Construct a standard unary operation, set AM and immediate if required.
344 * @param env The transformation environment
345 * @param op The operand
346 * @param func The node constructor function
347 * @return The constructed ia32 node.
349 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
350 ir_node *new_op = NULL;
351 ir_mode *mode = env->mode;
352 dbg_info *dbg = env->dbg;
353 firm_dbg_module_t *mod = env->mod;
354 ir_graph *irg = env->irg;
355 ir_node *block = env->block;
356 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
357 ir_node *nomem = new_NoMem();
359 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
361 if (mode_is_float(mode)) {
362 DB((mod, LEVEL_1, "FP unop ..."));
363 /* floating point operations don't support implicit store */
364 set_ia32_am_support(new_op, ia32_am_None);
367 DB((mod, LEVEL_1, "INT unop ..."));
368 set_ia32_am_support(new_op, ia32_am_Dest);
371 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
373 set_ia32_res_mode(new_op, mode);
375 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
381 * Creates an ia32 Add with immediate.
383 * @param env The transformation environment
384 * @param expr_op The expression operator
385 * @param const_op The constant
386 * @return the created ia32 Add node
388 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
389 ir_node *new_op = NULL;
390 tarval *tv = get_ia32_Immop_tarval(const_op);
391 firm_dbg_module_t *mod = env->mod;
392 dbg_info *dbg = env->dbg;
393 ir_graph *irg = env->irg;
394 ir_node *block = env->block;
395 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
396 ir_node *nomem = new_NoMem();
398 tarval_classification_t class_tv, class_negtv;
400 /* try to optimize to inc/dec */
401 if (env->cg->opt.incdec && tv) {
402 /* optimize tarvals */
403 class_tv = classify_tarval(tv);
404 class_negtv = classify_tarval(tarval_neg(tv));
406 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
407 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
408 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
411 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
412 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
413 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
419 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
420 set_ia32_Immop_attr(new_op, const_op);
427 * Creates an ia32 Add.
429 * @param dbg firm node dbg
430 * @param block the block the new node should belong to
431 * @param op1 first operator
432 * @param op2 second operator
433 * @param mode node mode
434 * @return the created ia32 Add node
436 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
437 ir_node *new_op = NULL;
438 dbg_info *dbg = env->dbg;
439 ir_mode *mode = env->mode;
440 ir_graph *irg = env->irg;
441 ir_node *block = env->block;
442 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
443 ir_node *nomem = new_NoMem();
444 ir_node *expr_op, *imm_op;
446 /* Check if immediate optimization is on and */
447 /* if it's an operation with immediate. */
448 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
449 expr_op = get_expr_op(op1, op2);
451 assert((expr_op || imm_op) && "invalid operands");
453 if (mode_is_float(mode)) {
454 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
459 /* No expr_op means, that we have two const - one symconst and */
460 /* one tarval or another symconst - because this case is not */
461 /* covered by constant folding */
463 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
464 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
465 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
468 set_ia32_am_support(new_op, ia32_am_Source);
469 set_ia32_op_type(new_op, ia32_AddrModeS);
470 set_ia32_am_flavour(new_op, ia32_am_O);
472 /* Lea doesn't need a Proj */
476 /* This is expr + const */
477 new_op = gen_imm_Add(env, expr_op, imm_op);
480 set_ia32_am_support(new_op, ia32_am_Dest);
483 /* This is a normal add */
484 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
487 set_ia32_am_support(new_op, ia32_am_Full);
491 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
493 set_ia32_res_mode(new_op, mode);
495 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
501 * Creates an ia32 Mul.
503 * @param dbg firm node dbg
504 * @param block the block the new node should belong to
505 * @param op1 first operator
506 * @param op2 second operator
507 * @param mode node mode
508 * @return the created ia32 Mul node
510 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
513 if (mode_is_float(env->mode)) {
514 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
517 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
526 * Creates an ia32 Mulh.
527 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
528 * this result while Mul returns the lower 32 bit.
530 * @param env The transformation environment
531 * @param op1 The first operator
532 * @param op2 The second operator
533 * @return the created ia32 Mulh node
535 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
536 ir_node *proj_EAX, *proj_EDX, *mulh;
539 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
540 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
541 mulh = get_Proj_pred(proj_EAX);
542 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
544 /* to be on the save side */
545 set_Proj_proj(proj_EAX, pn_EAX);
547 if (get_ia32_cnst(mulh)) {
548 /* Mulh with const cannot have AM */
549 set_ia32_am_support(mulh, ia32_am_None);
552 /* Mulh cannot have AM for destination */
553 set_ia32_am_support(mulh, ia32_am_Source);
559 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
567 * Creates an ia32 And.
569 * @param env The transformation environment
570 * @param op1 The first operator
571 * @param op2 The second operator
572 * @return The created ia32 And node
574 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
575 if (mode_is_float(env->mode)) {
576 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
579 return gen_binop(env, op1, op2, new_rd_ia32_And);
586 * Creates an ia32 Or.
588 * @param env The transformation environment
589 * @param op1 The first operator
590 * @param op2 The second operator
591 * @return The created ia32 Or node
593 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
594 if (mode_is_float(env->mode)) {
595 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
598 return gen_binop(env, op1, op2, new_rd_ia32_Or);
605 * Creates an ia32 Eor.
607 * @param env The transformation environment
608 * @param op1 The first operator
609 * @param op2 The second operator
610 * @return The created ia32 Eor node
612 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
613 if (mode_is_float(env->mode)) {
614 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
617 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
624 * Creates an ia32 Max.
626 * @param env The transformation environment
627 * @param op1 The first operator
628 * @param op2 The second operator
629 * @return the created ia32 Max node
631 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
634 if (mode_is_float(env->mode)) {
635 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
638 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
639 set_ia32_am_support(new_op, ia32_am_None);
640 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
649 * Creates an ia32 Min.
651 * @param env The transformation environment
652 * @param op1 The first operator
653 * @param op2 The second operator
654 * @return the created ia32 Min node
656 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
659 if (mode_is_float(env->mode)) {
660 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
663 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
664 set_ia32_am_support(new_op, ia32_am_None);
665 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
674 * Creates an ia32 Sub with immediate.
676 * @param env The transformation environment
677 * @param op1 The first operator
678 * @param op2 The second operator
679 * @return The created ia32 Sub node
681 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
682 ir_node *new_op = NULL;
683 tarval *tv = get_ia32_Immop_tarval(const_op);
684 firm_dbg_module_t *mod = env->mod;
685 dbg_info *dbg = env->dbg;
686 ir_graph *irg = env->irg;
687 ir_node *block = env->block;
688 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
689 ir_node *nomem = new_NoMem();
691 tarval_classification_t class_tv, class_negtv;
693 /* try to optimize to inc/dec */
694 if (env->cg->opt.incdec && tv) {
695 /* optimize tarvals */
696 class_tv = classify_tarval(tv);
697 class_negtv = classify_tarval(tarval_neg(tv));
699 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
700 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
701 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
704 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
705 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
706 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
712 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
713 set_ia32_Immop_attr(new_op, const_op);
720 * Creates an ia32 Sub.
722 * @param env The transformation environment
723 * @param op1 The first operator
724 * @param op2 The second operator
725 * @return The created ia32 Sub node
727 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
728 ir_node *new_op = NULL;
729 dbg_info *dbg = env->dbg;
730 ir_mode *mode = env->mode;
731 ir_graph *irg = env->irg;
732 ir_node *block = env->block;
733 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
734 ir_node *nomem = new_NoMem();
735 ir_node *expr_op, *imm_op;
737 /* Check if immediate optimization is on and */
738 /* if it's an operation with immediate. */
739 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
740 expr_op = get_expr_op(op1, op2);
742 assert((expr_op || imm_op) && "invalid operands");
744 if (mode_is_float(mode)) {
745 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
750 /* No expr_op means, that we have two const - one symconst and */
751 /* one tarval or another symconst - because this case is not */
752 /* covered by constant folding */
754 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
755 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
756 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
759 set_ia32_am_support(new_op, ia32_am_Source);
760 set_ia32_op_type(new_op, ia32_AddrModeS);
761 set_ia32_am_flavour(new_op, ia32_am_O);
763 /* Lea doesn't need a Proj */
767 /* This is expr - const */
768 new_op = gen_imm_Sub(env, expr_op, imm_op);
771 set_ia32_am_support(new_op, ia32_am_Dest);
774 /* This is a normal sub */
775 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
778 set_ia32_am_support(new_op, ia32_am_Full);
782 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
784 set_ia32_res_mode(new_op, mode);
786 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
792 * Generates an ia32 DivMod with additional infrastructure for the
793 * register allocator if needed.
795 * @param env The transformation environment
796 * @param dividend -no comment- :)
797 * @param divisor -no comment- :)
798 * @param dm_flav flavour_Div/Mod/DivMod
799 * @return The created ia32 DivMod node
801 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
803 ir_node *edx_node, *cltd;
805 dbg_info *dbg = env->dbg;
806 ir_graph *irg = env->irg;
807 ir_node *block = env->block;
808 ir_mode *mode = env->mode;
809 ir_node *irn = env->irn;
814 mem = get_Div_mem(irn);
815 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
818 mem = get_Mod_mem(irn);
819 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
822 mem = get_DivMod_mem(irn);
823 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
829 if (mode_is_signed(mode)) {
830 /* in signed mode, we need to sign extend the dividend */
831 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
832 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
833 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
836 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
837 set_ia32_Const_type(edx_node, ia32_Const);
838 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
841 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
843 set_ia32_flavour(res, dm_flav);
844 set_ia32_n_res(res, 2);
846 /* Only one proj is used -> We must add a second proj and */
847 /* connect this one to a Keep node to eat up the second */
848 /* destroyed register. */
849 if (get_irn_n_edges(irn) == 1) {
850 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
851 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
853 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
854 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
857 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
863 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
865 set_ia32_res_mode(res, mode_Is);
872 * Wrapper for generate_DivMod. Sets flavour_Mod.
874 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
875 return generate_DivMod(env, op1, op2, flavour_Mod);
881 * Wrapper for generate_DivMod. Sets flavour_Div.
883 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
884 return generate_DivMod(env, op1, op2, flavour_Div);
890 * Wrapper for generate_DivMod. Sets flavour_DivMod.
892 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
893 return generate_DivMod(env, op1, op2, flavour_DivMod);
899 * Creates an ia32 floating Div.
901 * @param env The transformation environment
902 * @param op1 The first operator
903 * @param op2 The second operator
904 * @return The created ia32 fDiv node
906 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
907 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
908 ir_node *nomem = new_rd_NoMem(env->irg);
911 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
912 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
913 set_ia32_am_support(new_op, ia32_am_Source);
915 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
923 * Creates an ia32 Shl.
925 * @param env The transformation environment
926 * @param op1 The first operator
927 * @param op2 The second operator
928 * @return The created ia32 Shl node
930 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
931 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
937 * Creates an ia32 Shr.
939 * @param env The transformation environment
940 * @param op1 The first operator
941 * @param op2 The second operator
942 * @return The created ia32 Shr node
944 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
945 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
951 * Creates an ia32 Shrs.
953 * @param env The transformation environment
954 * @param op1 The first operator
955 * @param op2 The second operator
956 * @return The created ia32 Shrs node
958 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
959 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
965 * Creates an ia32 RotL.
967 * @param env The transformation environment
968 * @param op1 The first operator
969 * @param op2 The second operator
970 * @return The created ia32 RotL node
972 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
973 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
979 * Creates an ia32 RotR.
980 * NOTE: There is no RotR with immediate because this would always be a RotL
981 * "imm-mode_size_bits" which can be pre-calculated.
983 * @param env The transformation environment
984 * @param op1 The first operator
985 * @param op2 The second operator
986 * @return The created ia32 RotR node
988 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
989 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
995 * Creates an ia32 RotR or RotL (depending on the found pattern).
997 * @param env The transformation environment
998 * @param op1 The first operator
999 * @param op2 The second operator
1000 * @return The created ia32 RotL or RotR node
1002 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1003 ir_node *rotate = NULL;
1005 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1006 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1007 that means we can create a RotR instead of an Add and a RotL */
1010 ir_node *pred = get_Proj_pred(op2);
1012 if (is_ia32_Add(pred)) {
1013 ir_node *pred_pred = get_irn_n(pred, 2);
1014 tarval *tv = get_ia32_Immop_tarval(pred);
1015 long bits = get_mode_size_bits(env->mode);
1017 if (is_Proj(pred_pred)) {
1018 pred_pred = get_Proj_pred(pred_pred);
1021 if (is_ia32_Minus(pred_pred) &&
1022 tarval_is_long(tv) &&
1023 get_tarval_long(tv) == bits)
1025 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1026 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1033 rotate = gen_RotL(env, op1, op2);
1042 * Transforms a Minus node.
1044 * @param env The transformation environment
1045 * @param op The operator
1046 * @return The created ia32 Minus node
1048 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1051 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1052 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1053 ir_node *nomem = new_rd_NoMem(env->irg);
1056 if (mode_is_float(env->mode)) {
1057 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1059 size = get_mode_size_bits(env->mode);
1060 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1062 set_ia32_sc(new_op, name);
1064 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1066 set_ia32_res_mode(new_op, env->mode);
1068 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1071 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1080 * Transforms a Not node.
1082 * @param env The transformation environment
1083 * @param op The operator
1084 * @return The created ia32 Not node
1086 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1089 if (mode_is_float(env->mode)) {
1093 new_op = gen_unop(env, op, new_rd_ia32_Not);
1102 * Transforms an Abs node.
1104 * @param env The transformation environment
1105 * @param op The operator
1106 * @return The created ia32 Abs node
1108 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1109 ir_node *res, *p_eax, *p_edx;
1110 dbg_info *dbg = env->dbg;
1111 ir_mode *mode = env->mode;
1112 ir_graph *irg = env->irg;
1113 ir_node *block = env->block;
1114 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1115 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1116 ir_node *nomem = new_NoMem();
1120 if (mode_is_float(mode)) {
1121 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1123 size = get_mode_size_bits(mode);
1124 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1126 set_ia32_sc(res, name);
1128 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1130 set_ia32_res_mode(res, mode);
1132 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1135 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1136 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1137 set_ia32_res_mode(res, mode);
1139 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1140 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1142 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1143 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1144 set_ia32_res_mode(res, mode);
1146 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1148 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1149 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1150 set_ia32_res_mode(res, mode);
1152 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1161 * Transforms a Load.
1163 * @param mod the debug module
1164 * @param block the block the new node should belong to
1165 * @param node the ir Load node
1166 * @param mode node mode
1167 * @return the created ia32 Load node
1169 static ir_node *gen_Load(ia32_transform_env_t *env) {
1170 ir_node *node = env->irn;
1171 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1172 ir_mode *mode = get_Load_mode(node);
1175 if (mode_is_float(mode)) {
1176 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1179 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1182 set_ia32_am_support(new_op, ia32_am_Source);
1183 set_ia32_op_type(new_op, ia32_AddrModeS);
1184 set_ia32_am_flavour(new_op, ia32_B);
1185 set_ia32_ls_mode(new_op, mode);
1187 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1195 * Transforms a Store.
1197 * @param mod the debug module
1198 * @param block the block the new node should belong to
1199 * @param node the ir Store node
1200 * @param mode node mode
1201 * @return the created ia32 Store node
1203 static ir_node *gen_Store(ia32_transform_env_t *env) {
1204 ir_node *node = env->irn;
1205 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1206 ir_node *val = get_Store_value(node);
1207 ir_node *ptr = get_Store_ptr(node);
1208 ir_node *mem = get_Store_mem(node);
1209 ir_mode *mode = get_irn_mode(val);
1210 ir_node *sval = val;
1213 /* in case of storing a const (but not a symconst) -> make it an attribute */
1214 if (is_ia32_Const(val)) {
1218 if (mode_is_float(mode)) {
1219 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1221 else if (get_mode_size_bits(mode) == 8) {
1222 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1225 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1228 /* stored const is an attribute (saves a register) */
1229 if (is_ia32_Const(val)) {
1230 set_ia32_Immop_attr(new_op, val);
1233 set_ia32_am_support(new_op, ia32_am_Dest);
1234 set_ia32_op_type(new_op, ia32_AddrModeD);
1235 set_ia32_am_flavour(new_op, ia32_B);
1236 set_ia32_ls_mode(new_op, get_irn_mode(val));
1238 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1246 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1248 * @param env The transformation environment
1249 * @return The transformed node.
1251 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1252 dbg_info *dbg = env->dbg;
1253 ir_graph *irg = env->irg;
1254 ir_node *block = env->block;
1255 ir_node *node = env->irn;
1256 ir_node *sel = get_Cond_selector(node);
1257 ir_mode *sel_mode = get_irn_mode(sel);
1258 ir_node *res = NULL;
1259 ir_node *pred = NULL;
1260 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1261 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1263 if (is_Proj(sel) && sel_mode == mode_b) {
1264 ir_node *nomem = new_NoMem();
1266 pred = get_Proj_pred(sel);
1268 /* get both compare operators */
1269 cmp_a = get_Cmp_left(pred);
1270 cmp_b = get_Cmp_right(pred);
1272 /* check if we can use a CondJmp with immediate */
1273 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1274 expr = get_expr_op(cmp_a, cmp_b);
1277 if (mode_is_int(get_irn_mode(expr))) {
1278 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1280 ir_node *op1 = expr;
1281 ir_node *op2 = expr;
1282 ir_node *and = skip_Proj(expr);
1285 /* check, if expr is an only once used And operation */
1286 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1287 op1 = get_irn_n(and, 2);
1288 op2 = get_irn_n(and, 3);
1290 cnst = get_ia32_cnst(and);
1292 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1293 set_ia32_pncode(res, get_Proj_proj(sel));
1296 copy_ia32_Immop_attr(res, and);
1299 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1304 if (mode_is_float(get_irn_mode(expr))) {
1305 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1308 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1310 set_ia32_Immop_attr(res, cnst);
1313 if (mode_is_float(get_irn_mode(cmp_a))) {
1314 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1317 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1321 set_ia32_pncode(res, get_Proj_proj(sel));
1322 set_ia32_am_support(res, ia32_am_Source);
1325 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1326 set_ia32_pncode(res, get_Cond_defaultProj(node));
1329 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1336 * Transforms a CopyB node.
1338 * @param env The transformation environment
1339 * @return The transformed node.
1341 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1342 ir_node *res = NULL;
1343 dbg_info *dbg = env->dbg;
1344 ir_graph *irg = env->irg;
1345 ir_mode *mode = env->mode;
1346 ir_node *block = env->block;
1347 ir_node *node = env->irn;
1348 ir_node *src = get_CopyB_src(node);
1349 ir_node *dst = get_CopyB_dst(node);
1350 ir_node *mem = get_CopyB_mem(node);
1351 int size = get_type_size_bytes(get_CopyB_type(node));
1354 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1355 /* then we need the size explicitly in ECX. */
1356 if (size >= 16 * 4) {
1357 rem = size & 0x3; /* size % 4 */
1360 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1361 set_ia32_op_type(res, ia32_Const);
1362 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1364 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1365 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1368 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1369 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1372 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1380 * Transforms a Mux node into CMov.
1382 * @param env The transformation environment
1383 * @return The transformed node.
1385 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1386 ir_node *node = env->irn;
1387 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1388 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1390 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1397 * Following conversion rules apply:
1401 * 1) n bit -> m bit n > m (downscale)
1402 * a) target is signed: movsx
1403 * b) target is unsigned: and with lower bits sets
1404 * 2) n bit -> m bit n == m (sign change)
1406 * 3) n bit -> m bit n < m (upscale)
1407 * a) source is signed: movsx
1408 * b) source is unsigned: and with lower bits sets
1412 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1416 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1417 * if target mode < 32bit: additional INT -> INT conversion (see above)
1421 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1424 //static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1425 // ir_mode *src_mode, ir_mode *tgt_mode)
1427 // int n = get_mode_size_bits(src_mode);
1428 // int m = get_mode_size_bits(tgt_mode);
1429 // dbg_info *dbg = env->dbg;
1430 // ir_graph *irg = env->irg;
1431 // ir_node *block = env->block;
1432 // ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1433 // ir_node *nomem = new_rd_NoMem(irg);
1434 // ir_node *new_op, *proj;
1435 // assert(n > m && "downscale expected");
1436 // if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1437 // /* ASHL Sn, n - m */
1438 // new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1439 // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1440 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1441 // set_ia32_am_support(new_op, ia32_am_Source);
1442 // SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1443 // /* ASHR Sn, n - m */
1444 // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1445 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1448 // new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1449 // set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1455 * Transforms a Conv node.
1457 * @param env The transformation environment
1458 * @param op The operator
1459 * @return The created ia32 Conv node
1461 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1462 dbg_info *dbg = env->dbg;
1463 ir_graph *irg = env->irg;
1464 ir_mode *src_mode = get_irn_mode(op);
1465 ir_mode *tgt_mode = env->mode;
1466 int tgt_bits = get_mode_size_bits(tgt_mode);
1467 ir_node *block = env->block;
1468 ir_node *new_op = NULL;
1469 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1470 ir_node *nomem = new_rd_NoMem(irg);
1471 firm_dbg_module_t *mod = env->mod;
1474 if (src_mode == tgt_mode) {
1475 /* this can happen when changing mode_P to mode_Is */
1476 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1477 edges_reroute(env->irn, op, irg);
1479 else if (mode_is_float(src_mode)) {
1480 /* we convert from float ... */
1481 if (mode_is_float(tgt_mode)) {
1483 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1484 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1488 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1489 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1490 /* if target mode is not int: add an additional downscale convert */
1491 if (tgt_bits < 32) {
1492 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1493 set_ia32_res_mode(new_op, tgt_mode);
1494 set_ia32_am_support(new_op, ia32_am_Source);
1496 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1498 if (tgt_bits == 8) {
1499 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1502 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1508 /* we convert from int ... */
1509 if (mode_is_float(tgt_mode)) {
1511 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1512 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1516 if (get_mode_size_bits(src_mode) == tgt_bits) {
1517 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1518 edges_reroute(env->irn, op, irg);
1521 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1522 if (tgt_bits == 8) {
1523 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1526 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1533 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1534 set_ia32_res_mode(new_op, tgt_mode);
1536 set_ia32_am_support(new_op, ia32_am_Source);
1538 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1546 /********************************************
1549 * | |__ ___ _ __ ___ __| | ___ ___
1550 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1551 * | |_) | __/ | | | (_) | (_| | __/\__ \
1552 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1554 ********************************************/
1556 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1557 ir_node *new_op = NULL;
1558 ir_node *node = env->irn;
1559 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1560 ir_node *mem = new_rd_NoMem(env->irg);
1561 ir_node *ptr = get_irn_n(node, 0);
1562 entity *ent = be_get_frame_entity(node);
1563 ir_mode *mode = env->mode;
1565 if (mode_is_float(mode)) {
1566 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1569 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1572 set_ia32_frame_ent(new_op, ent);
1573 set_ia32_use_frame(new_op);
1575 set_ia32_am_support(new_op, ia32_am_Source);
1576 set_ia32_op_type(new_op, ia32_AddrModeS);
1577 set_ia32_am_flavour(new_op, ia32_B);
1578 set_ia32_ls_mode(new_op, mode);
1580 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1582 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1586 * Transforms a FrameAddr into an ia32 Add.
1588 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1589 ir_node *new_op = NULL;
1590 ir_node *node = env->irn;
1591 ir_node *op = get_irn_n(node, 0);
1592 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1593 ir_node *nomem = new_rd_NoMem(env->irg);
1595 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1596 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1597 set_ia32_am_support(new_op, ia32_am_Full);
1598 set_ia32_use_frame(new_op);
1600 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1602 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1606 * Transforms a FrameLoad into an ia32 Load.
1608 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1609 ir_node *new_op = NULL;
1610 ir_node *node = env->irn;
1611 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1612 ir_node *mem = get_irn_n(node, 0);
1613 ir_node *ptr = get_irn_n(node, 1);
1614 entity *ent = be_get_frame_entity(node);
1615 ir_mode *mode = get_type_mode(get_entity_type(ent));
1617 if (mode_is_float(mode)) {
1618 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1621 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1624 set_ia32_frame_ent(new_op, ent);
1625 set_ia32_use_frame(new_op);
1627 set_ia32_am_support(new_op, ia32_am_Source);
1628 set_ia32_op_type(new_op, ia32_AddrModeS);
1629 set_ia32_am_flavour(new_op, ia32_B);
1630 set_ia32_ls_mode(new_op, mode);
1632 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1639 * Transforms a FrameStore into an ia32 Store.
1641 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1642 ir_node *new_op = NULL;
1643 ir_node *node = env->irn;
1644 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1645 ir_node *mem = get_irn_n(node, 0);
1646 ir_node *ptr = get_irn_n(node, 1);
1647 ir_node *val = get_irn_n(node, 2);
1648 entity *ent = be_get_frame_entity(node);
1649 ir_mode *mode = get_irn_mode(val);
1651 if (mode_is_float(mode)) {
1652 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1654 else if (get_mode_size_bits(mode) == 8) {
1655 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1658 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1661 set_ia32_frame_ent(new_op, ent);
1662 set_ia32_use_frame(new_op);
1664 set_ia32_am_support(new_op, ia32_am_Dest);
1665 set_ia32_op_type(new_op, ia32_AddrModeD);
1666 set_ia32_am_flavour(new_op, ia32_B);
1667 set_ia32_ls_mode(new_op, mode);
1669 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1676 /*********************************************************
1679 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1680 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1681 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1682 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1684 *********************************************************/
1687 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1688 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1690 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1691 ia32_transform_env_t tenv;
1692 ir_node *in1, *in2, *noreg, *nomem, *res;
1693 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1695 /* Return if AM node or not a Sub or fSub */
1696 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1699 noreg = ia32_new_NoReg_gp(cg);
1700 nomem = new_rd_NoMem(cg->irg);
1701 in1 = get_irn_n(irn, 2);
1702 in2 = get_irn_n(irn, 3);
1703 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1704 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1705 out_reg = get_ia32_out_reg(irn, 0);
1707 tenv.block = get_nodes_block(irn);
1708 tenv.dbg = get_irn_dbg_info(irn);
1712 tenv.mode = get_ia32_res_mode(irn);
1715 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1716 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1717 /* generate the neg src2 */
1718 res = gen_Minus(&tenv, in2);
1719 arch_set_irn_register(cg->arch_env, res, in2_reg);
1721 /* add to schedule */
1722 sched_add_before(irn, res);
1724 /* generate the add */
1725 if (mode_is_float(tenv.mode)) {
1726 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1727 set_ia32_am_support(res, ia32_am_Source);
1730 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1731 set_ia32_am_support(res, ia32_am_Full);
1734 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1736 slots = get_ia32_slots(res);
1739 /* add to schedule */
1740 sched_add_before(irn, res);
1742 /* remove the old sub */
1745 /* exchange the add and the sub */
1751 * Transforms a LEA into an Add if possible
1752 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1754 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
1755 ia32_am_flavour_t am_flav;
1757 ir_node *res = NULL;
1758 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
1760 ia32_transform_env_t tenv;
1761 const arch_register_t *out_reg, *base_reg, *index_reg;
1764 if (! is_ia32_Lea(irn))
1767 am_flav = get_ia32_am_flavour(irn);
1769 /* only some LEAs can be transformed to an Add */
1770 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
1773 noreg = ia32_new_NoReg_gp(cg);
1774 nomem = new_rd_NoMem(cg->irg);
1777 base = get_irn_n(irn, 0);
1778 index = get_irn_n(irn,1);
1780 offs = get_ia32_am_offs(irn);
1782 /* offset has a explicit sign -> we need to skip + */
1783 if (offs && offs[0] == '+')
1786 out_reg = arch_get_irn_register(cg->arch_env, irn);
1787 base_reg = arch_get_irn_register(cg->arch_env, base);
1788 index_reg = arch_get_irn_register(cg->arch_env, index);
1790 tenv.block = get_nodes_block(irn);
1791 tenv.dbg = get_irn_dbg_info(irn);
1795 tenv.mode = get_irn_mode(irn);
1798 switch(get_ia32_am_flavour(irn)) {
1800 /* out register must be same as base register */
1801 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1807 /* out register must be same as base register */
1808 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1815 /* out register must be same as index register */
1816 if (! REGS_ARE_EQUAL(out_reg, index_reg))
1823 /* out register must be same as one in register */
1824 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
1828 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
1833 /* in registers a different from out -> no Add possible */
1840 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
1841 arch_set_irn_register(cg->arch_env, res, out_reg);
1842 set_ia32_op_type(res, ia32_Normal);
1845 set_ia32_cnst(res, offs);
1847 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1849 /* add Add to schedule */
1850 sched_add_before(irn, res);
1852 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
1854 /* add result Proj to schedule */
1855 sched_add_before(irn, res);
1857 /* remove the old LEA */
1860 /* exchange the Add and the LEA */
1865 * Transforms the given firm node (and maybe some other related nodes)
1866 * into one or more assembler nodes.
1868 * @param node the firm node
1869 * @param env the debug module
1871 void ia32_transform_node(ir_node *node, void *env) {
1872 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1874 ir_node *asm_node = NULL;
1875 ia32_transform_env_t tenv;
1880 tenv.block = get_nodes_block(node);
1881 tenv.dbg = get_irn_dbg_info(node);
1882 tenv.irg = current_ir_graph;
1884 tenv.mod = cgenv->mod;
1885 tenv.mode = get_irn_mode(node);
1888 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1889 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1890 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1891 #define IGN(a) case iro_##a: break
1892 #define BAD(a) case iro_##a: goto bad
1893 #define OTHER_BIN(a) \
1894 if (get_irn_op(node) == get_op_##a()) { \
1895 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1899 if (be_is_##a(node)) { \
1900 asm_node = gen_##a(&tenv); \
1904 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1906 code = get_irn_opcode(node);
1952 /* constant transformation happens earlier */
1982 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1986 /* exchange nodes if a new one was generated */
1988 exchange(node, asm_node);
1989 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1992 DB((tenv.mod, LEVEL_1, "ignored\n"));