2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
32 #include "bearch_ia32_t.h"
34 #include "ia32_nodes_attr.h"
35 #include "../arch/archop.h" /* we need this for Min and Max nodes */
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
41 #include "gen_ia32_regalloc_if.h"
43 #define SFP_SIGN "0x80000000"
44 #define DFP_SIGN "0x8000000000000000"
45 #define SFP_ABS "0x7FFFFFFF"
46 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
48 #define TP_SFP_SIGN "ia32_sfp_sign"
49 #define TP_DFP_SIGN "ia32_dfp_sign"
50 #define TP_SFP_ABS "ia32_sfp_abs"
51 #define TP_DFP_ABS "ia32_dfp_abs"
53 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
54 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
55 #define ENT_SFP_ABS "IA32_SFP_ABS"
56 #define ENT_DFP_ABS "IA32_DFP_ABS"
58 extern ir_op *get_op_Mulh(void);
60 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
61 ir_node *op1, ir_node *op2, ir_node *mem);
63 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op, ir_node *mem);
67 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
70 /****************************************************************************************************
72 * | | | | / _| | | (_)
73 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
74 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
75 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
76 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
78 ****************************************************************************************************/
81 * Gets the Proj with number pn from irn.
83 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
84 const ir_edge_t *edge;
86 assert(get_irn_mode(irn) == mode_T && "need mode_T");
88 foreach_out_edge(irn, edge) {
89 proj = get_edge_src_irn(edge);
91 if (get_Proj_proj(proj) == pn)
98 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
99 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
100 static const struct {
102 const char *ent_name;
103 const char *cnst_str;
104 } names [ia32_known_const_max] = {
105 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
106 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
107 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
108 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
110 static struct entity *ent_cache[ia32_known_const_max];
112 const char *tp_name, *ent_name, *cnst_str;
119 ent_name = names[kct].ent_name;
120 if (! ent_cache[kct]) {
121 tp_name = names[kct].tp_name;
122 cnst_str = names[kct].cnst_str;
124 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
125 tp = new_type_primitive(new_id_from_str(tp_name), mode);
126 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
128 set_entity_ld_ident(ent, get_entity_ident(ent));
129 set_entity_visibility(ent, visibility_local);
130 set_entity_variability(ent, variability_constant);
131 set_entity_allocation(ent, allocation_static);
133 /* we create a new entity here: It's initialization must resist on the
135 rem = current_ir_graph;
136 current_ir_graph = get_const_code_irg();
137 cnst = new_Const(mode, tv);
138 current_ir_graph = rem;
140 set_atomic_ent_value(ent, cnst);
142 /* cache the entry */
143 ent_cache[kct] = ent;
146 return get_entity_ident(ent_cache[kct]);
151 * Prints the old node name on cg obst and returns a pointer to it.
153 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
154 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
156 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
157 obstack_1grow(isa->name_obst, 0);
158 isa->name_obst_size += obstack_object_size(isa->name_obst);
159 return obstack_finish(isa->name_obst);
163 /* determine if one operator is an Imm */
164 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
166 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
167 else return is_ia32_Cnst(op2) ? op2 : NULL;
170 /* determine if one operator is not an Imm */
171 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
172 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
177 * Construct a standard binary operation, set AM and immediate if required.
179 * @param env The transformation environment
180 * @param op1 The first operand
181 * @param op2 The second operand
182 * @param func The node constructor function
183 * @return The constructed ia32 node.
185 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
186 ir_node *new_op = NULL;
187 ir_mode *mode = env->mode;
188 dbg_info *dbg = env->dbg;
189 ir_graph *irg = env->irg;
190 ir_node *block = env->block;
191 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
192 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
193 ir_node *nomem = new_NoMem();
194 ir_node *expr_op, *imm_op;
195 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
197 /* Check if immediate optimization is on and */
198 /* if it's an operation with immediate. */
199 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
203 else if (is_op_commutative(get_irn_op(env->irn))) {
204 imm_op = get_immediate_op(op1, op2);
205 expr_op = get_expr_op(op1, op2);
208 imm_op = get_immediate_op(NULL, op2);
209 expr_op = get_expr_op(op1, op2);
212 assert((expr_op || imm_op) && "invalid operands");
215 /* We have two consts here: not yet supported */
219 if (mode_is_float(mode)) {
220 /* floating point operations */
222 DB((mod, LEVEL_1, "FP with immediate ..."));
223 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
224 set_ia32_Immop_attr(new_op, imm_op);
225 set_ia32_am_support(new_op, ia32_am_None);
228 DB((mod, LEVEL_1, "FP binop ..."));
229 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
230 set_ia32_am_support(new_op, ia32_am_Source);
234 /* integer operations */
236 /* This is expr + const */
237 DB((mod, LEVEL_1, "INT with immediate ..."));
238 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
239 set_ia32_Immop_attr(new_op, imm_op);
242 set_ia32_am_support(new_op, ia32_am_Dest);
245 DB((mod, LEVEL_1, "INT binop ..."));
246 /* This is a normal operation */
247 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
250 set_ia32_am_support(new_op, ia32_am_Full);
254 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
256 set_ia32_res_mode(new_op, mode);
258 if (is_op_commutative(get_irn_op(env->irn))) {
259 set_ia32_commutative(new_op);
262 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
268 * Construct a shift/rotate binary operation, sets AM and immediate if required.
270 * @param env The transformation environment
271 * @param op1 The first operand
272 * @param op2 The second operand
273 * @param func The node constructor function
274 * @return The constructed ia32 node.
276 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
277 ir_node *new_op = NULL;
278 ir_mode *mode = env->mode;
279 dbg_info *dbg = env->dbg;
280 ir_graph *irg = env->irg;
281 ir_node *block = env->block;
282 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
283 ir_node *nomem = new_NoMem();
284 ir_node *expr_op, *imm_op;
286 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
288 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
290 /* Check if immediate optimization is on and */
291 /* if it's an operation with immediate. */
292 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
293 expr_op = get_expr_op(op1, op2);
295 assert((expr_op || imm_op) && "invalid operands");
298 /* We have two consts here: not yet supported */
302 /* Limit imm_op within range imm8 */
304 tv = get_ia32_Immop_tarval(imm_op);
307 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
314 /* integer operations */
316 /* This is shift/rot with const */
317 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
319 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
320 set_ia32_Immop_attr(new_op, imm_op);
323 /* This is a normal shift/rot */
324 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
325 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
329 set_ia32_am_support(new_op, ia32_am_Dest);
331 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
333 set_ia32_res_mode(new_op, mode);
334 set_ia32_emit_cl(new_op);
336 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
341 * Construct a standard unary operation, set AM and immediate if required.
343 * @param env The transformation environment
344 * @param op The operand
345 * @param func The node constructor function
346 * @return The constructed ia32 node.
348 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
349 ir_node *new_op = NULL;
350 ir_mode *mode = env->mode;
351 dbg_info *dbg = env->dbg;
352 ir_graph *irg = env->irg;
353 ir_node *block = env->block;
354 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
355 ir_node *nomem = new_NoMem();
356 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
358 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
360 if (mode_is_float(mode)) {
361 DB((mod, LEVEL_1, "FP unop ..."));
362 /* floating point operations don't support implicit store */
363 set_ia32_am_support(new_op, ia32_am_None);
366 DB((mod, LEVEL_1, "INT unop ..."));
367 set_ia32_am_support(new_op, ia32_am_Dest);
370 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
372 set_ia32_res_mode(new_op, mode);
374 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
380 * Creates an ia32 Add with immediate.
382 * @param env The transformation environment
383 * @param expr_op The expression operator
384 * @param const_op The constant
385 * @return the created ia32 Add node
387 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
388 ir_node *new_op = NULL;
389 tarval *tv = get_ia32_Immop_tarval(const_op);
390 dbg_info *dbg = env->dbg;
391 ir_graph *irg = env->irg;
392 ir_node *block = env->block;
393 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
394 ir_node *nomem = new_NoMem();
396 tarval_classification_t class_tv, class_negtv;
397 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
399 /* try to optimize to inc/dec */
400 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
401 /* optimize tarvals */
402 class_tv = classify_tarval(tv);
403 class_negtv = classify_tarval(tarval_neg(tv));
405 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
406 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
407 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
410 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
411 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
412 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
418 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
419 set_ia32_Immop_attr(new_op, const_op);
426 * Creates an ia32 Add.
428 * @param env The transformation environment
429 * @return the created ia32 Add node
431 static ir_node *gen_Add(ia32_transform_env_t *env) {
432 ir_node *new_op = NULL;
433 dbg_info *dbg = env->dbg;
434 ir_mode *mode = env->mode;
435 ir_graph *irg = env->irg;
436 ir_node *block = env->block;
437 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
438 ir_node *nomem = new_NoMem();
439 ir_node *expr_op, *imm_op;
440 ir_node *op1 = get_Add_left(env->irn);
441 ir_node *op2 = get_Add_right(env->irn);
443 /* Check if immediate optimization is on and */
444 /* if it's an operation with immediate. */
445 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
446 expr_op = get_expr_op(op1, op2);
448 assert((expr_op || imm_op) && "invalid operands");
450 if (mode_is_float(mode)) {
452 if (USE_SSE2(env->cg))
453 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
455 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
460 /* No expr_op means, that we have two const - one symconst and */
461 /* one tarval or another symconst - because this case is not */
462 /* covered by constant folding */
463 /* We need to check for: */
464 /* 1) symconst + const -> becomes a LEA */
465 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
466 /* linker doesn't support two symconsts */
468 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
469 /* this is the 2nd case */
470 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
471 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
472 set_ia32_am_flavour(new_op, ia32_am_OB);
475 /* this is the 1st case */
476 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
478 if (get_ia32_op_type(op1) == ia32_SymConst) {
479 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
480 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
483 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
484 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
486 set_ia32_am_flavour(new_op, ia32_am_O);
490 set_ia32_am_support(new_op, ia32_am_Source);
491 set_ia32_op_type(new_op, ia32_AddrModeS);
493 /* Lea doesn't need a Proj */
497 /* This is expr + const */
498 new_op = gen_imm_Add(env, expr_op, imm_op);
501 set_ia32_am_support(new_op, ia32_am_Dest);
504 /* This is a normal add */
505 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
508 set_ia32_am_support(new_op, ia32_am_Full);
509 set_ia32_commutative(new_op);
513 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
515 set_ia32_res_mode(new_op, mode);
517 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
523 * Creates an ia32 Mul.
525 * @param env The transformation environment
526 * @return the created ia32 Mul node
528 static ir_node *gen_Mul(ia32_transform_env_t *env) {
529 ir_node *op1 = get_Mul_left(env->irn);
530 ir_node *op2 = get_Mul_right(env->irn);
533 if (mode_is_float(env->mode)) {
535 if (USE_SSE2(env->cg))
536 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
538 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
541 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
550 * Creates an ia32 Mulh.
551 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
552 * this result while Mul returns the lower 32 bit.
554 * @param env The transformation environment
555 * @return the created ia32 Mulh node
557 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
558 ir_node *op1 = get_irn_n(env->irn, 0);
559 ir_node *op2 = get_irn_n(env->irn, 1);
560 ir_node *proj_EAX, *proj_EDX, *mulh;
563 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
564 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
565 mulh = get_Proj_pred(proj_EAX);
566 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
568 /* to be on the save side */
569 set_Proj_proj(proj_EAX, pn_EAX);
571 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
572 /* Mulh with const cannot have AM */
573 set_ia32_am_support(mulh, ia32_am_None);
576 /* Mulh cannot have AM for destination */
577 set_ia32_am_support(mulh, ia32_am_Source);
583 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
591 * Creates an ia32 And.
593 * @param env The transformation environment
594 * @return The created ia32 And node
596 static ir_node *gen_And(ia32_transform_env_t *env) {
597 ir_node *op1 = get_And_left(env->irn);
598 ir_node *op2 = get_And_right(env->irn);
600 assert (! mode_is_float(env->mode));
601 return gen_binop(env, op1, op2, new_rd_ia32_And);
607 * Creates an ia32 Or.
609 * @param env The transformation environment
610 * @return The created ia32 Or node
612 static ir_node *gen_Or(ia32_transform_env_t *env) {
613 ir_node *op1 = get_Or_left(env->irn);
614 ir_node *op2 = get_Or_right(env->irn);
616 assert (! mode_is_float(env->mode));
617 return gen_binop(env, op1, op2, new_rd_ia32_Or);
623 * Creates an ia32 Eor.
625 * @param env The transformation environment
626 * @return The created ia32 Eor node
628 static ir_node *gen_Eor(ia32_transform_env_t *env) {
629 ir_node *op1 = get_Eor_left(env->irn);
630 ir_node *op2 = get_Eor_right(env->irn);
632 assert(! mode_is_float(env->mode));
633 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
639 * Creates an ia32 Max.
641 * @param env The transformation environment
642 * @return the created ia32 Max node
644 static ir_node *gen_Max(ia32_transform_env_t *env) {
645 ir_node *op1 = get_irn_n(env->irn, 0);
646 ir_node *op2 = get_irn_n(env->irn, 1);
649 if (mode_is_float(env->mode)) {
651 if (USE_SSE2(env->cg))
652 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
658 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
659 set_ia32_am_support(new_op, ia32_am_None);
660 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
669 * Creates an ia32 Min.
671 * @param env The transformation environment
672 * @return the created ia32 Min node
674 static ir_node *gen_Min(ia32_transform_env_t *env) {
675 ir_node *op1 = get_irn_n(env->irn, 0);
676 ir_node *op2 = get_irn_n(env->irn, 1);
679 if (mode_is_float(env->mode)) {
681 if (USE_SSE2(env->cg))
682 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
688 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
689 set_ia32_am_support(new_op, ia32_am_None);
690 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
699 * Creates an ia32 Sub with immediate.
701 * @param env The transformation environment
702 * @param expr_op The first operator
703 * @param const_op The constant operator
704 * @return The created ia32 Sub node
706 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
707 ir_node *new_op = NULL;
708 tarval *tv = get_ia32_Immop_tarval(const_op);
709 dbg_info *dbg = env->dbg;
710 ir_graph *irg = env->irg;
711 ir_node *block = env->block;
712 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
713 ir_node *nomem = new_NoMem();
715 tarval_classification_t class_tv, class_negtv;
716 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
718 /* try to optimize to inc/dec */
719 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
720 /* optimize tarvals */
721 class_tv = classify_tarval(tv);
722 class_negtv = classify_tarval(tarval_neg(tv));
724 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
725 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
726 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
729 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
730 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
731 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
737 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
738 set_ia32_Immop_attr(new_op, const_op);
745 * Creates an ia32 Sub.
747 * @param env The transformation environment
748 * @return The created ia32 Sub node
750 static ir_node *gen_Sub(ia32_transform_env_t *env) {
751 ir_node *new_op = NULL;
752 dbg_info *dbg = env->dbg;
753 ir_mode *mode = env->mode;
754 ir_graph *irg = env->irg;
755 ir_node *block = env->block;
756 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
757 ir_node *nomem = new_NoMem();
758 ir_node *op1 = get_Sub_left(env->irn);
759 ir_node *op2 = get_Sub_right(env->irn);
760 ir_node *expr_op, *imm_op;
762 /* Check if immediate optimization is on and */
763 /* if it's an operation with immediate. */
764 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
765 expr_op = get_expr_op(op1, op2);
767 assert((expr_op || imm_op) && "invalid operands");
769 if (mode_is_float(mode)) {
771 if (USE_SSE2(env->cg))
772 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
774 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
779 /* No expr_op means, that we have two const - one symconst and */
780 /* one tarval or another symconst - because this case is not */
781 /* covered by constant folding */
782 /* We need to check for: */
783 /* 1) symconst + const -> becomes a LEA */
784 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
785 /* linker doesn't support two symconsts */
787 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
788 /* this is the 2nd case */
789 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
790 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
791 set_ia32_am_sc_sign(new_op);
792 set_ia32_am_flavour(new_op, ia32_am_OB);
795 /* this is the 1st case */
796 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
798 if (get_ia32_op_type(op1) == ia32_SymConst) {
799 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
800 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
803 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
804 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
805 set_ia32_am_sc_sign(new_op);
807 set_ia32_am_flavour(new_op, ia32_am_O);
811 set_ia32_am_support(new_op, ia32_am_Source);
812 set_ia32_op_type(new_op, ia32_AddrModeS);
814 /* Lea doesn't need a Proj */
818 /* This is expr - const */
819 new_op = gen_imm_Sub(env, expr_op, imm_op);
822 set_ia32_am_support(new_op, ia32_am_Dest);
825 /* This is a normal sub */
826 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
829 set_ia32_am_support(new_op, ia32_am_Full);
833 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
835 set_ia32_res_mode(new_op, mode);
837 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
843 * Generates an ia32 DivMod with additional infrastructure for the
844 * register allocator if needed.
846 * @param env The transformation environment
847 * @param dividend -no comment- :)
848 * @param divisor -no comment- :)
849 * @param dm_flav flavour_Div/Mod/DivMod
850 * @return The created ia32 DivMod node
852 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
854 ir_node *edx_node, *cltd;
856 dbg_info *dbg = env->dbg;
857 ir_graph *irg = env->irg;
858 ir_node *block = env->block;
859 ir_mode *mode = env->mode;
860 ir_node *irn = env->irn;
865 mem = get_Div_mem(irn);
866 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
869 mem = get_Mod_mem(irn);
870 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
873 mem = get_DivMod_mem(irn);
874 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
880 if (mode_is_signed(mode)) {
881 /* in signed mode, we need to sign extend the dividend */
882 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
883 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
884 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
887 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
888 set_ia32_Const_type(edx_node, ia32_Const);
889 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
892 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
894 set_ia32_n_res(res, 2);
896 /* Only one proj is used -> We must add a second proj and */
897 /* connect this one to a Keep node to eat up the second */
898 /* destroyed register. */
899 if (get_irn_n_edges(irn) == 1) {
900 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
901 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
903 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
904 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
907 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
910 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
913 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
915 set_ia32_res_mode(res, mode_Is);
922 * Wrapper for generate_DivMod. Sets flavour_Mod.
924 * @param env The transformation environment
926 static ir_node *gen_Mod(ia32_transform_env_t *env) {
927 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
931 * Wrapper for generate_DivMod. Sets flavour_Div.
933 * @param env The transformation environment
935 static ir_node *gen_Div(ia32_transform_env_t *env) {
936 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
940 * Wrapper for generate_DivMod. Sets flavour_DivMod.
942 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
943 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
949 * Creates an ia32 floating Div.
951 * @param env The transformation environment
952 * @return The created ia32 xDiv node
954 static ir_node *gen_Quot(ia32_transform_env_t *env) {
955 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
957 ir_node *nomem = new_rd_NoMem(env->irg);
958 ir_node *op1 = get_Quot_left(env->irn);
959 ir_node *op2 = get_Quot_right(env->irn);
962 if (USE_SSE2(env->cg)) {
963 if (is_ia32_xConst(op2)) {
964 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
965 set_ia32_am_support(new_op, ia32_am_None);
966 set_ia32_Immop_attr(new_op, op2);
969 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
970 set_ia32_am_support(new_op, ia32_am_Source);
974 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
975 set_ia32_am_support(new_op, ia32_am_Source);
977 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
978 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
986 * Creates an ia32 Shl.
988 * @param env The transformation environment
989 * @return The created ia32 Shl node
991 static ir_node *gen_Shl(ia32_transform_env_t *env) {
992 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
998 * Creates an ia32 Shr.
1000 * @param env The transformation environment
1001 * @return The created ia32 Shr node
1003 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1004 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1010 * Creates an ia32 Shrs.
1012 * @param env The transformation environment
1013 * @return The created ia32 Shrs node
1015 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1016 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1022 * Creates an ia32 RotL.
1024 * @param env The transformation environment
1025 * @param op1 The first operator
1026 * @param op2 The second operator
1027 * @return The created ia32 RotL node
1029 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1030 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1036 * Creates an ia32 RotR.
1037 * NOTE: There is no RotR with immediate because this would always be a RotL
1038 * "imm-mode_size_bits" which can be pre-calculated.
1040 * @param env The transformation environment
1041 * @param op1 The first operator
1042 * @param op2 The second operator
1043 * @return The created ia32 RotR node
1045 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1046 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1052 * Creates an ia32 RotR or RotL (depending on the found pattern).
1054 * @param env The transformation environment
1055 * @return The created ia32 RotL or RotR node
1057 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1058 ir_node *rotate = NULL;
1059 ir_node *op1 = get_Rot_left(env->irn);
1060 ir_node *op2 = get_Rot_right(env->irn);
1062 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1063 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1064 that means we can create a RotR instead of an Add and a RotL */
1067 ir_node *pred = get_Proj_pred(op2);
1069 if (is_ia32_Add(pred)) {
1070 ir_node *pred_pred = get_irn_n(pred, 2);
1071 tarval *tv = get_ia32_Immop_tarval(pred);
1072 long bits = get_mode_size_bits(env->mode);
1074 if (is_Proj(pred_pred)) {
1075 pred_pred = get_Proj_pred(pred_pred);
1078 if (is_ia32_Minus(pred_pred) &&
1079 tarval_is_long(tv) &&
1080 get_tarval_long(tv) == bits)
1082 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1083 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1090 rotate = gen_RotL(env, op1, op2);
1099 * Transforms a Minus node.
1101 * @param env The transformation environment
1102 * @param op The Minus operand
1103 * @return The created ia32 Minus node
1105 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1110 if (mode_is_float(env->mode)) {
1112 if (USE_SSE2(env->cg)) {
1113 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1114 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1115 ir_node *nomem = new_rd_NoMem(env->irg);
1117 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1119 size = get_mode_size_bits(env->mode);
1120 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1122 set_ia32_sc(new_op, name);
1124 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1126 set_ia32_res_mode(new_op, env->mode);
1127 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1129 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1132 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1133 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1137 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1144 * Transforms a Minus node.
1146 * @param env The transformation environment
1147 * @return The created ia32 Minus node
1149 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1150 return gen_Minus_ex(env, get_Minus_op(env->irn));
1155 * Transforms a Not node.
1157 * @param env The transformation environment
1158 * @return The created ia32 Not node
1160 static ir_node *gen_Not(ia32_transform_env_t *env) {
1161 assert (! mode_is_float(env->mode));
1162 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1168 * Transforms an Abs node.
1170 * @param env The transformation environment
1171 * @return The created ia32 Abs node
1173 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1174 ir_node *res, *p_eax, *p_edx;
1175 dbg_info *dbg = env->dbg;
1176 ir_mode *mode = env->mode;
1177 ir_graph *irg = env->irg;
1178 ir_node *block = env->block;
1179 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1180 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1181 ir_node *nomem = new_NoMem();
1182 ir_node *op = get_Abs_op(env->irn);
1186 if (mode_is_float(mode)) {
1188 if (USE_SSE2(env->cg)) {
1189 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1191 size = get_mode_size_bits(mode);
1192 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1194 set_ia32_sc(res, name);
1196 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1198 set_ia32_res_mode(res, mode);
1199 set_ia32_immop_type(res, ia32_ImmSymConst);
1201 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1204 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1205 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1209 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1210 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1211 set_ia32_res_mode(res, mode);
1213 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1214 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1216 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1217 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1218 set_ia32_res_mode(res, mode);
1220 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1222 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1223 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1224 set_ia32_res_mode(res, mode);
1226 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1235 * Transforms a Load.
1237 * @param env The transformation environment
1238 * @return the created ia32 Load node
1240 static ir_node *gen_Load(ia32_transform_env_t *env) {
1241 ir_node *node = env->irn;
1242 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1243 ir_node *ptr = get_Load_ptr(node);
1244 ir_node *lptr = ptr;
1245 ir_mode *mode = get_Load_mode(node);
1248 ia32_am_flavour_t am_flav = ia32_B;
1250 /* address might be a constant (symconst or absolute address) */
1251 if (is_ia32_Const(ptr)) {
1256 if (mode_is_float(mode)) {
1258 if (USE_SSE2(env->cg))
1259 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1261 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1264 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1267 /* base is an constant address */
1269 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1270 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1273 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1279 set_ia32_am_support(new_op, ia32_am_Source);
1280 set_ia32_op_type(new_op, ia32_AddrModeS);
1281 set_ia32_am_flavour(new_op, am_flav);
1282 set_ia32_ls_mode(new_op, mode);
1284 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1292 * Transforms a Store.
1294 * @param env The transformation environment
1295 * @return the created ia32 Store node
1297 static ir_node *gen_Store(ia32_transform_env_t *env) {
1298 ir_node *node = env->irn;
1299 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1300 ir_node *val = get_Store_value(node);
1301 ir_node *ptr = get_Store_ptr(node);
1302 ir_node *sptr = ptr;
1303 ir_node *mem = get_Store_mem(node);
1304 ir_mode *mode = get_irn_mode(val);
1305 ir_node *sval = val;
1308 ia32_am_flavour_t am_flav = ia32_B;
1309 ia32_immop_type_t immop = ia32_ImmNone;
1311 if (! mode_is_float(mode)) {
1312 /* in case of storing a const (but not a symconst) -> make it an attribute */
1313 if (is_ia32_Cnst(val)) {
1314 switch (get_ia32_op_type(val)) {
1316 immop = ia32_ImmConst;
1319 immop = ia32_ImmSymConst;
1322 assert(0 && "unsupported Const type");
1328 /* address might be a constant (symconst or absolute address) */
1329 if (is_ia32_Const(ptr)) {
1334 if (mode_is_float(mode)) {
1336 if (USE_SSE2(env->cg))
1337 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1339 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1341 else if (get_mode_size_bits(mode) == 8) {
1342 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1345 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem);
1348 /* stored const is an attribute (saves a register) */
1349 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1350 set_ia32_Immop_attr(new_op, val);
1353 /* base is an constant address */
1355 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1356 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1359 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1365 set_ia32_am_support(new_op, ia32_am_Dest);
1366 set_ia32_op_type(new_op, ia32_AddrModeD);
1367 set_ia32_am_flavour(new_op, am_flav);
1368 set_ia32_ls_mode(new_op, get_irn_mode(val));
1369 set_ia32_immop_type(new_op, immop);
1371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1379 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1381 * @param env The transformation environment
1382 * @return The transformed node.
1384 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1385 dbg_info *dbg = env->dbg;
1386 ir_graph *irg = env->irg;
1387 ir_node *block = env->block;
1388 ir_node *node = env->irn;
1389 ir_node *sel = get_Cond_selector(node);
1390 ir_mode *sel_mode = get_irn_mode(sel);
1391 ir_node *res = NULL;
1392 ir_node *pred = NULL;
1393 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1394 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1396 if (is_Proj(sel) && sel_mode == mode_b) {
1397 ir_node *nomem = new_NoMem();
1399 pred = get_Proj_pred(sel);
1401 /* get both compare operators */
1402 cmp_a = get_Cmp_left(pred);
1403 cmp_b = get_Cmp_right(pred);
1405 /* check if we can use a CondJmp with immediate */
1406 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1407 expr = get_expr_op(cmp_a, cmp_b);
1410 pn_Cmp pnc = get_Proj_proj(sel);
1412 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1413 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1414 /* a Cmp A =/!= 0 */
1415 ir_node *op1 = expr;
1416 ir_node *op2 = expr;
1417 ir_node *and = skip_Proj(expr);
1418 const char *cnst = NULL;
1420 /* check, if expr is an only once used And operation */
1421 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1422 op1 = get_irn_n(and, 2);
1423 op2 = get_irn_n(and, 3);
1425 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1427 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1428 set_ia32_pncode(res, get_Proj_proj(sel));
1429 set_ia32_res_mode(res, get_irn_mode(op1));
1432 copy_ia32_Immop_attr(res, and);
1435 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1440 if (mode_is_float(get_irn_mode(expr))) {
1442 if (USE_SSE2(env->cg))
1443 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1449 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1451 set_ia32_Immop_attr(res, cnst);
1452 set_ia32_res_mode(res, get_irn_mode(expr));
1455 if (mode_is_float(get_irn_mode(cmp_a))) {
1457 if (USE_SSE2(env->cg))
1458 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1461 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1462 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1463 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1467 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1469 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1472 set_ia32_pncode(res, get_Proj_proj(sel));
1473 set_ia32_am_support(res, ia32_am_Source);
1476 /* determine the smallest switch case value */
1477 int switch_min = INT_MAX;
1478 const ir_edge_t *edge;
1481 foreach_out_edge(node, edge) {
1482 int pn = get_Proj_proj(get_edge_src_irn(edge));
1483 switch_min = pn < switch_min ? pn : switch_min;
1487 /* if smallest switch case is not 0 we need an additional sub */
1488 snprintf(buf, sizeof(buf), "%d", switch_min);
1489 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1490 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1491 sub_ia32_am_offs(res, buf);
1492 set_ia32_am_flavour(res, ia32_am_OB);
1493 set_ia32_am_support(res, ia32_am_Source);
1494 set_ia32_op_type(res, ia32_AddrModeS);
1497 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1498 set_ia32_pncode(res, get_Cond_defaultProj(node));
1499 set_ia32_res_mode(res, get_irn_mode(sel));
1502 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1509 * Transforms a CopyB node.
1511 * @param env The transformation environment
1512 * @return The transformed node.
1514 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1515 ir_node *res = NULL;
1516 dbg_info *dbg = env->dbg;
1517 ir_graph *irg = env->irg;
1518 ir_mode *mode = env->mode;
1519 ir_node *block = env->block;
1520 ir_node *node = env->irn;
1521 ir_node *src = get_CopyB_src(node);
1522 ir_node *dst = get_CopyB_dst(node);
1523 ir_node *mem = get_CopyB_mem(node);
1524 int size = get_type_size_bytes(get_CopyB_type(node));
1527 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1528 /* then we need the size explicitly in ECX. */
1529 if (size >= 16 * 4) {
1530 rem = size & 0x3; /* size % 4 */
1533 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1534 set_ia32_op_type(res, ia32_Const);
1535 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1537 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1538 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1541 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1542 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1543 set_ia32_immop_type(res, ia32_ImmConst);
1546 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1554 * Transforms a Mux node into CMov.
1556 * @param env The transformation environment
1557 * @return The transformed node.
1559 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1560 ir_node *node = env->irn;
1561 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1562 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1564 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1571 * Following conversion rules apply:
1575 * 1) n bit -> m bit n > m (downscale)
1576 * a) target is signed: movsx
1577 * b) target is unsigned: and with lower bits sets
1578 * 2) n bit -> m bit n == m (sign change)
1580 * 3) n bit -> m bit n < m (upscale)
1581 * a) source is signed: movsx
1582 * b) source is unsigned: and with lower bits sets
1586 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1590 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1591 * if target mode < 32bit: additional INT -> INT conversion (see above)
1595 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1596 * x87 is mode_E internally, conversions happen only at load and store
1597 * in non-strict semantic
1601 * Create a conversion from x87 state register to general purpose.
1603 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1604 ia32_code_gen_t *cg = env->cg;
1605 entity *ent = cg->fp_to_gp;
1606 ir_graph *irg = env->irg;
1607 ir_node *block = env->block;
1608 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1609 ir_node *op = get_Conv_op(env->irn);
1610 ir_node *fist, *mem, *load;
1613 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1614 ent = cg->fp_to_gp =
1615 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1619 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1621 set_ia32_frame_ent(fist, ent);
1622 set_ia32_use_frame(fist);
1623 set_ia32_am_support(fist, ia32_am_Dest);
1624 set_ia32_op_type(fist, ia32_AddrModeD);
1625 set_ia32_am_flavour(fist, ia32_B);
1626 set_ia32_ls_mode(fist, mode_E);
1628 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1631 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1633 set_ia32_frame_ent(load, ent);
1634 set_ia32_use_frame(load);
1635 set_ia32_am_support(load, ia32_am_Source);
1636 set_ia32_op_type(load, ia32_AddrModeS);
1637 set_ia32_am_flavour(load, ia32_B);
1638 set_ia32_ls_mode(load, tgt_mode);
1640 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1644 * Create a conversion from x87 state register to general purpose.
1646 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1647 ia32_code_gen_t *cg = env->cg;
1648 entity *ent = cg->gp_to_fp;
1649 ir_graph *irg = env->irg;
1650 ir_node *block = env->block;
1651 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1652 ir_node *nomem = get_irg_no_mem(irg);
1653 ir_node *op = get_Conv_op(env->irn);
1654 ir_node *fild, *store, *mem;
1658 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1659 ent = cg->gp_to_fp =
1660 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1663 /* first convert to 32 bit */
1664 src_bits = get_mode_size_bits(src_mode);
1665 if (src_bits == 8) {
1666 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1667 op = new_r_Proj(irg, block, op, mode_Is, 0);
1669 else if (src_bits < 32) {
1670 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1671 op = new_r_Proj(irg, block, op, mode_Is, 0);
1675 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1677 set_ia32_frame_ent(store, ent);
1678 set_ia32_use_frame(store);
1680 set_ia32_am_support(store, ia32_am_Dest);
1681 set_ia32_op_type(store, ia32_AddrModeD);
1682 set_ia32_am_flavour(store, ia32_B);
1683 set_ia32_ls_mode(store, mode_Is);
1685 mem = new_r_Proj(irg, block, store, mode_M, 0);
1688 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1690 set_ia32_frame_ent(fild, ent);
1691 set_ia32_use_frame(fild);
1692 set_ia32_am_support(fild, ia32_am_Source);
1693 set_ia32_op_type(fild, ia32_AddrModeS);
1694 set_ia32_am_flavour(fild, ia32_B);
1695 set_ia32_ls_mode(fild, mode_E);
1697 return new_r_Proj(irg, block, fild, mode_E, 0);
1701 * Transforms a Conv node.
1703 * @param env The transformation environment
1704 * @return The created ia32 Conv node
1706 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1707 dbg_info *dbg = env->dbg;
1708 ir_graph *irg = env->irg;
1709 ir_node *op = get_Conv_op(env->irn);
1710 ir_mode *src_mode = get_irn_mode(op);
1711 ir_mode *tgt_mode = env->mode;
1712 int src_bits = get_mode_size_bits(src_mode);
1713 int tgt_bits = get_mode_size_bits(tgt_mode);
1714 ir_node *block = env->block;
1715 ir_node *new_op = NULL;
1716 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1717 ir_node *nomem = new_rd_NoMem(irg);
1719 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1721 if (src_mode == tgt_mode) {
1722 /* this can happen when changing mode_P to mode_Is */
1723 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1724 edges_reroute(env->irn, op, irg);
1726 else if (mode_is_float(src_mode)) {
1727 /* we convert from float ... */
1728 if (mode_is_float(tgt_mode)) {
1730 if (USE_SSE2(env->cg)) {
1731 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1732 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1735 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1736 edges_reroute(env->irn, op, irg);
1741 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1742 if (USE_SSE2(env->cg))
1743 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1745 return gen_x87_fp_to_gp(env, tgt_mode);
1747 /* if target mode is not int: add an additional downscale convert */
1748 if (tgt_bits < 32) {
1749 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1750 set_ia32_am_support(new_op, ia32_am_Source);
1751 set_ia32_tgt_mode(new_op, tgt_mode);
1752 set_ia32_src_mode(new_op, src_mode);
1754 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1756 if (tgt_bits == 8 || src_bits == 8) {
1757 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1760 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1766 /* we convert from int ... */
1767 if (mode_is_float(tgt_mode)) {
1770 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1771 if (USE_SSE2(env->cg))
1772 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1774 return gen_x87_gp_to_fp(env, src_mode);
1778 if (get_mode_size_bits(src_mode) == tgt_bits) {
1779 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1780 edges_reroute(env->irn, op, irg);
1783 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1784 if (tgt_bits == 8 || src_bits == 8) {
1785 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1788 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1796 set_ia32_tgt_mode(new_op, tgt_mode);
1797 set_ia32_src_mode(new_op, src_mode);
1799 set_ia32_am_support(new_op, ia32_am_Source);
1801 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1809 /********************************************
1812 * | |__ ___ _ __ ___ __| | ___ ___
1813 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1814 * | |_) | __/ | | | (_) | (_| | __/\__ \
1815 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1817 ********************************************/
1819 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1820 ir_node *new_op = NULL;
1821 ir_node *node = env->irn;
1822 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1823 ir_node *mem = new_rd_NoMem(env->irg);
1824 ir_node *ptr = get_irn_n(node, 0);
1825 entity *ent = be_get_frame_entity(node);
1826 ir_mode *mode = env->mode;
1828 // /* If the StackParam has only one user -> */
1829 // /* put it in the Block where the user resides */
1830 // if (get_irn_n_edges(node) == 1) {
1831 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1834 if (mode_is_float(mode)) {
1836 if (USE_SSE2(env->cg))
1837 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1839 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1842 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1845 set_ia32_frame_ent(new_op, ent);
1846 set_ia32_use_frame(new_op);
1848 set_ia32_am_support(new_op, ia32_am_Source);
1849 set_ia32_op_type(new_op, ia32_AddrModeS);
1850 set_ia32_am_flavour(new_op, ia32_B);
1851 set_ia32_ls_mode(new_op, mode);
1853 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1855 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1859 * Transforms a FrameAddr into an ia32 Add.
1861 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1862 ir_node *new_op = NULL;
1863 ir_node *node = env->irn;
1864 ir_node *op = get_irn_n(node, 0);
1865 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1866 ir_node *nomem = new_rd_NoMem(env->irg);
1868 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
1869 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1870 set_ia32_am_support(new_op, ia32_am_Full);
1871 set_ia32_use_frame(new_op);
1872 set_ia32_immop_type(new_op, ia32_ImmConst);
1873 set_ia32_commutative(new_op);
1875 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1877 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
1881 * Transforms a FrameLoad into an ia32 Load.
1883 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1884 ir_node *new_op = NULL;
1885 ir_node *node = env->irn;
1886 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1887 ir_node *mem = get_irn_n(node, 0);
1888 ir_node *ptr = get_irn_n(node, 1);
1889 entity *ent = be_get_frame_entity(node);
1890 ir_mode *mode = get_type_mode(get_entity_type(ent));
1892 if (mode_is_float(mode)) {
1894 if (USE_SSE2(env->cg))
1895 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1897 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1900 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1902 set_ia32_frame_ent(new_op, ent);
1903 set_ia32_use_frame(new_op);
1905 set_ia32_am_support(new_op, ia32_am_Source);
1906 set_ia32_op_type(new_op, ia32_AddrModeS);
1907 set_ia32_am_flavour(new_op, ia32_B);
1908 set_ia32_ls_mode(new_op, mode);
1910 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1917 * Transforms a FrameStore into an ia32 Store.
1919 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
1920 ir_node *new_op = NULL;
1921 ir_node *node = env->irn;
1922 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1923 ir_node *mem = get_irn_n(node, 0);
1924 ir_node *ptr = get_irn_n(node, 1);
1925 ir_node *val = get_irn_n(node, 2);
1926 entity *ent = be_get_frame_entity(node);
1927 ir_mode *mode = get_irn_mode(val);
1929 if (mode_is_float(mode)) {
1931 if (USE_SSE2(env->cg))
1932 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1934 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1936 else if (get_mode_size_bits(mode) == 8) {
1937 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1940 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1943 set_ia32_frame_ent(new_op, ent);
1944 set_ia32_use_frame(new_op);
1946 set_ia32_am_support(new_op, ia32_am_Dest);
1947 set_ia32_op_type(new_op, ia32_AddrModeD);
1948 set_ia32_am_flavour(new_op, ia32_B);
1949 set_ia32_ls_mode(new_op, mode);
1951 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1957 * This function just sets the register for the Unknown node
1958 * as this is not done during register allocation because Unknown
1959 * is an "ignore" node.
1961 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
1962 ir_mode *mode = env->mode;
1963 ir_node *irn = env->irn;
1965 if (mode_is_float(mode)) {
1966 if (USE_SSE2(env->cg))
1967 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
1969 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
1971 else if (mode_is_int(mode) || mode_is_reference(mode)) {
1972 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
1975 assert(0 && "unsupported Unknown-Mode");
1982 /*********************************************************
1985 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1986 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1987 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1988 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1990 *********************************************************/
1993 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
1994 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1996 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1997 ia32_transform_env_t tenv;
1998 ir_node *in1, *in2, *noreg, *nomem, *res;
1999 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2001 /* Return if AM node or not a Sub or xSub */
2002 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2005 noreg = ia32_new_NoReg_gp(cg);
2006 nomem = new_rd_NoMem(cg->irg);
2007 in1 = get_irn_n(irn, 2);
2008 in2 = get_irn_n(irn, 3);
2009 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2010 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2011 out_reg = get_ia32_out_reg(irn, 0);
2013 tenv.block = get_nodes_block(irn);
2014 tenv.dbg = get_irn_dbg_info(irn);
2017 tenv.mode = get_ia32_res_mode(irn);
2019 DEBUG_ONLY(tenv.mod = cg->mod;)
2021 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2022 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2023 /* generate the neg src2 */
2024 res = gen_Minus_ex(&tenv, in2);
2025 arch_set_irn_register(cg->arch_env, res, in2_reg);
2027 /* add to schedule */
2028 sched_add_before(irn, res);
2030 /* generate the add */
2031 if (mode_is_float(tenv.mode)) {
2032 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2033 set_ia32_am_support(res, ia32_am_Source);
2036 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2037 set_ia32_am_support(res, ia32_am_Full);
2038 set_ia32_commutative(res);
2041 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2043 slots = get_ia32_slots(res);
2046 /* add to schedule */
2047 sched_add_before(irn, res);
2049 /* remove the old sub */
2052 DBG_OPT_SUB2NEGADD(irn, res);
2054 /* exchange the add and the sub */
2060 * Transforms a LEA into an Add if possible
2061 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2063 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2064 ia32_am_flavour_t am_flav;
2066 ir_node *res = NULL;
2067 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2069 ia32_transform_env_t tenv;
2070 const arch_register_t *out_reg, *base_reg, *index_reg;
2073 if (! is_ia32_Lea(irn))
2076 am_flav = get_ia32_am_flavour(irn);
2078 /* only some LEAs can be transformed to an Add */
2079 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2082 noreg = ia32_new_NoReg_gp(cg);
2083 nomem = new_rd_NoMem(cg->irg);
2086 base = get_irn_n(irn, 0);
2087 index = get_irn_n(irn,1);
2089 offs = get_ia32_am_offs(irn);
2091 /* offset has a explicit sign -> we need to skip + */
2092 if (offs && offs[0] == '+')
2095 out_reg = arch_get_irn_register(cg->arch_env, irn);
2096 base_reg = arch_get_irn_register(cg->arch_env, base);
2097 index_reg = arch_get_irn_register(cg->arch_env, index);
2099 tenv.block = get_nodes_block(irn);
2100 tenv.dbg = get_irn_dbg_info(irn);
2103 DEBUG_ONLY(tenv.mod = cg->mod;)
2104 tenv.mode = get_irn_mode(irn);
2107 switch(get_ia32_am_flavour(irn)) {
2109 /* out register must be same as base register */
2110 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2116 /* out register must be same as base register */
2117 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2124 /* out register must be same as index register */
2125 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2132 /* out register must be same as one in register */
2133 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2137 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2142 /* in registers a different from out -> no Add possible */
2149 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2150 arch_set_irn_register(cg->arch_env, res, out_reg);
2151 set_ia32_op_type(res, ia32_Normal);
2152 set_ia32_commutative(res);
2155 set_ia32_cnst(res, offs);
2156 set_ia32_immop_type(res, ia32_ImmConst);
2159 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2161 /* add Add to schedule */
2162 sched_add_before(irn, res);
2164 DBG_OPT_LEA2ADD(irn, res);
2166 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2168 /* add result Proj to schedule */
2169 sched_add_before(irn, res);
2171 /* remove the old LEA */
2174 /* exchange the Add and the LEA */
2179 * the BAD transformer.
2181 static ir_node *bad_transform(ia32_transform_env_t *env) {
2182 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2188 * Enters all transform functions into the generic pointer
2190 void ia32_register_transformers(void) {
2191 ir_op *op_Max, *op_Min, *op_Mulh;
2193 /* first clear the generic function pointer for all ops */
2194 clear_irp_opcodes_generic_func();
2196 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2197 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2243 /* constant transformation happens earlier */
2267 /* set the register for all Unknown nodes */
2270 op_Max = get_op_Max();
2273 op_Min = get_op_Min();
2276 op_Mulh = get_op_Mulh();
2285 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2288 * Transforms the given firm node (and maybe some other related nodes)
2289 * into one or more assembler nodes.
2291 * @param node the firm node
2292 * @param env the debug module
2294 void ia32_transform_node(ir_node *node, void *env) {
2295 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2296 ir_op *op = get_irn_op(node);
2297 ir_node *asm_node = NULL;
2302 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2303 if (op->ops.generic) {
2304 ia32_transform_env_t tenv;
2305 transform_func *transform = (transform_func *)op->ops.generic;
2307 tenv.block = get_nodes_block(node);
2308 tenv.dbg = get_irn_dbg_info(node);
2309 tenv.irg = current_ir_graph;
2311 tenv.mode = get_irn_mode(node);
2313 DEBUG_ONLY(tenv.mod = cg->mod;)
2315 asm_node = (*transform)(&tenv);
2318 /* exchange nodes if a new one was generated */
2320 exchange(node, asm_node);
2321 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2324 DB((cg->mod, LEVEL_1, "ignored\n"));