2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 if (USE_SSE2(env_cg)) {
556 set_ia32_ls_mode(new_node, mode);
559 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
565 * Construct a standard binary operation, set AM and immediate if required.
567 * @param op1 The first operand
568 * @param op2 The second operand
569 * @param func The node constructor function
570 * @return The constructed ia32 node.
572 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
573 construct_binop_float_func *func)
575 ir_node *block = be_transform_node(get_nodes_block(node));
576 ir_node *new_op1 = be_transform_node(op1);
577 ir_node *new_op2 = be_transform_node(op2);
578 ir_node *new_node = NULL;
579 dbg_info *dbgi = get_irn_dbg_info(node);
580 ir_graph *irg = current_ir_graph;
581 ir_mode *mode = get_irn_mode(node);
582 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
583 ir_node *nomem = new_NoMem();
584 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
585 &ia32_fp_cw_regs[REG_FPCW]);
587 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
589 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
590 if (is_op_commutative(get_irn_op(node))) {
591 set_ia32_commutative(new_node);
593 if (USE_SSE2(env_cg)) {
594 set_ia32_ls_mode(new_node, mode);
597 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
603 * Construct a shift/rotate binary operation, sets AM and immediate if required.
605 * @param op1 The first operand
606 * @param op2 The second operand
607 * @param func The node constructor function
608 * @return The constructed ia32 node.
610 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
611 construct_binop_func *func)
613 ir_node *block = be_transform_node(get_nodes_block(node));
614 ir_node *new_op1 = be_transform_node(op1);
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = current_ir_graph;
619 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
620 ir_node *nomem = new_NoMem();
622 assert(! mode_is_float(get_irn_mode(node))
623 && "Shift/Rotate with float not supported");
625 new_op2 = create_immediate_or_transform(op2, 'N');
627 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
630 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
632 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
634 set_ia32_emit_cl(new_op);
641 * Construct a standard unary operation, set AM and immediate if required.
643 * @param op The operand
644 * @param func The node constructor function
645 * @return The constructed ia32 node.
647 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
649 ir_node *block = be_transform_node(get_nodes_block(node));
650 ir_node *new_op = be_transform_node(op);
651 ir_node *new_node = NULL;
652 ir_graph *irg = current_ir_graph;
653 dbg_info *dbgi = get_irn_dbg_info(node);
654 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
655 ir_node *nomem = new_NoMem();
657 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
658 DB((dbg, LEVEL_1, "INT unop ..."));
659 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
667 * Creates an ia32 Add.
669 * @return the created ia32 Add node
671 static ir_node *gen_Add(ir_node *node) {
672 ir_node *block = be_transform_node(get_nodes_block(node));
673 ir_node *op1 = get_Add_left(node);
674 ir_node *new_op1 = be_transform_node(op1);
675 ir_node *op2 = get_Add_right(node);
676 ir_node *new_op2 = be_transform_node(op2);
677 ir_node *new_op = NULL;
678 ir_graph *irg = current_ir_graph;
679 dbg_info *dbgi = get_irn_dbg_info(node);
680 ir_mode *mode = get_irn_mode(node);
681 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
682 ir_node *nomem = new_NoMem();
683 ir_node *expr_op, *imm_op;
685 /* Check if immediate optimization is on and */
686 /* if it's an operation with immediate. */
687 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
688 expr_op = get_expr_op(new_op1, new_op2);
690 assert((expr_op || imm_op) && "invalid operands");
692 if (mode_is_float(mode)) {
694 if (USE_SSE2(env_cg))
695 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
697 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
702 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
703 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
705 /* No expr_op means, that we have two const - one symconst and */
706 /* one tarval or another symconst - because this case is not */
707 /* covered by constant folding */
708 /* We need to check for: */
709 /* 1) symconst + const -> becomes a LEA */
710 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
711 /* linker doesn't support two symconsts */
713 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
714 /* this is the 2nd case */
715 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
716 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
717 set_ia32_am_flavour(new_op, ia32_am_B);
718 set_ia32_op_type(new_op, ia32_AddrModeS);
720 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
721 } else if (tp1 == ia32_ImmSymConst) {
722 tarval *tv = get_ia32_Immop_tarval(new_op2);
723 long offs = get_tarval_long(tv);
725 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
726 add_irn_dep(new_op, get_irg_frame(irg));
727 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
730 add_ia32_am_offs_int(new_op, offs);
731 set_ia32_am_flavour(new_op, ia32_am_OB);
732 set_ia32_op_type(new_op, ia32_AddrModeS);
733 } else if (tp2 == ia32_ImmSymConst) {
734 tarval *tv = get_ia32_Immop_tarval(new_op1);
735 long offs = get_tarval_long(tv);
737 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
738 add_irn_dep(new_op, get_irg_frame(irg));
739 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 add_ia32_am_offs_int(new_op, offs);
742 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
743 set_ia32_am_flavour(new_op, ia32_am_OB);
744 set_ia32_op_type(new_op, ia32_AddrModeS);
746 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
747 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
748 tarval *restv = tarval_add(tv1, tv2);
750 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
752 new_op = new_rd_ia32_Const(dbgi, irg, block);
753 set_ia32_Const_tarval(new_op, restv);
754 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
757 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
760 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
761 tarval_classification_t class_tv, class_negtv;
762 tarval *tv = get_ia32_Immop_tarval(imm_op);
764 /* optimize tarvals */
765 class_tv = classify_tarval(tv);
766 class_negtv = classify_tarval(tarval_neg(tv));
768 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
769 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
770 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
771 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
773 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
774 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
775 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
782 /* This is a normal add */
783 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
786 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
787 set_ia32_commutative(new_op);
789 fold_immediate(new_op, 2, 3);
791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
797 * Creates an ia32 Mul.
799 * @return the created ia32 Mul node
801 static ir_node *gen_Mul(ir_node *node) {
802 ir_node *op1 = get_Mul_left(node);
803 ir_node *op2 = get_Mul_right(node);
804 ir_mode *mode = get_irn_mode(node);
806 if (mode_is_float(mode)) {
808 if (USE_SSE2(env_cg))
809 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
811 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
815 for the lower 32bit of the result it doesn't matter whether we use
816 signed or unsigned multiplication so we use IMul as it has fewer
819 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
823 * Creates an ia32 Mulh.
824 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
825 * this result while Mul returns the lower 32 bit.
827 * @return the created ia32 Mulh node
829 static ir_node *gen_Mulh(ir_node *node) {
830 ir_node *block = be_transform_node(get_nodes_block(node));
831 ir_node *op1 = get_irn_n(node, 0);
832 ir_node *new_op1 = be_transform_node(op1);
833 ir_node *op2 = get_irn_n(node, 1);
834 ir_node *new_op2 = be_transform_node(op2);
835 ir_graph *irg = current_ir_graph;
836 dbg_info *dbgi = get_irn_dbg_info(node);
837 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
838 ir_mode *mode = get_irn_mode(node);
839 ir_node *proj_EAX, *proj_EDX, *res;
842 assert(!mode_is_float(mode) && "Mulh with float not supported");
843 if (mode_is_signed(mode)) {
844 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
846 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
849 set_ia32_commutative(res);
850 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
852 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
853 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
857 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
865 * Creates an ia32 And.
867 * @return The created ia32 And node
869 static ir_node *gen_And(ir_node *node) {
870 ir_node *op1 = get_And_left(node);
871 ir_node *op2 = get_And_right(node);
873 assert (! mode_is_float(get_irn_mode(node)));
874 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
880 * Creates an ia32 Or.
882 * @return The created ia32 Or node
884 static ir_node *gen_Or(ir_node *node) {
885 ir_node *op1 = get_Or_left(node);
886 ir_node *op2 = get_Or_right(node);
888 assert (! mode_is_float(get_irn_mode(node)));
889 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
895 * Creates an ia32 Eor.
897 * @return The created ia32 Eor node
899 static ir_node *gen_Eor(ir_node *node) {
900 ir_node *op1 = get_Eor_left(node);
901 ir_node *op2 = get_Eor_right(node);
903 assert(! mode_is_float(get_irn_mode(node)));
904 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
910 * Creates an ia32 Max.
912 * @return the created ia32 Max node
914 static ir_node *gen_Max(ir_node *node) {
915 ir_node *block = be_transform_node(get_nodes_block(node));
916 ir_node *op1 = get_irn_n(node, 0);
917 ir_node *new_op1 = be_transform_node(op1);
918 ir_node *op2 = get_irn_n(node, 1);
919 ir_node *new_op2 = be_transform_node(op2);
920 ir_graph *irg = current_ir_graph;
921 ir_mode *mode = get_irn_mode(node);
922 dbg_info *dbgi = get_irn_dbg_info(node);
923 ir_mode *op_mode = get_irn_mode(op1);
926 assert(get_mode_size_bits(mode) == 32);
928 if (mode_is_float(mode)) {
930 if (USE_SSE2(env_cg)) {
931 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
933 panic("Can't create Max node");
936 long pnc = pn_Cmp_Gt;
937 if (! mode_is_signed(op_mode)) {
938 pnc |= ia32_pn_Cmp_Unsigned;
940 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
941 new_op1, new_op2, pnc);
943 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
949 * Creates an ia32 Min.
951 * @return the created ia32 Min node
953 static ir_node *gen_Min(ir_node *node) {
954 ir_node *block = be_transform_node(get_nodes_block(node));
955 ir_node *op1 = get_irn_n(node, 0);
956 ir_node *new_op1 = be_transform_node(op1);
957 ir_node *op2 = get_irn_n(node, 1);
958 ir_node *new_op2 = be_transform_node(op2);
959 ir_graph *irg = current_ir_graph;
960 ir_mode *mode = get_irn_mode(node);
961 dbg_info *dbgi = get_irn_dbg_info(node);
962 ir_mode *op_mode = get_irn_mode(op1);
965 assert(get_mode_size_bits(mode) == 32);
967 if (mode_is_float(mode)) {
969 if (USE_SSE2(env_cg)) {
970 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
972 panic("can't create Min node");
975 long pnc = pn_Cmp_Lt;
976 if (! mode_is_signed(op_mode)) {
977 pnc |= ia32_pn_Cmp_Unsigned;
979 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
980 new_op1, new_op2, pnc);
982 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
989 * Creates an ia32 Sub.
991 * @return The created ia32 Sub node
993 static ir_node *gen_Sub(ir_node *node) {
994 ir_node *block = be_transform_node(get_nodes_block(node));
995 ir_node *op1 = get_Sub_left(node);
996 ir_node *new_op1 = be_transform_node(op1);
997 ir_node *op2 = get_Sub_right(node);
998 ir_node *new_op2 = be_transform_node(op2);
999 ir_node *new_op = NULL;
1000 ir_graph *irg = current_ir_graph;
1001 dbg_info *dbgi = get_irn_dbg_info(node);
1002 ir_mode *mode = get_irn_mode(node);
1003 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1004 ir_node *nomem = new_NoMem();
1005 ir_node *expr_op, *imm_op;
1007 /* Check if immediate optimization is on and */
1008 /* if it's an operation with immediate. */
1009 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1010 expr_op = get_expr_op(new_op1, new_op2);
1012 assert((expr_op || imm_op) && "invalid operands");
1014 if (mode_is_float(mode)) {
1016 if (USE_SSE2(env_cg))
1017 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1019 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1024 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1025 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1027 /* No expr_op means, that we have two const - one symconst and */
1028 /* one tarval or another symconst - because this case is not */
1029 /* covered by constant folding */
1030 /* We need to check for: */
1031 /* 1) symconst - const -> becomes a LEA */
1032 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1033 /* linker doesn't support two symconsts */
1034 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1035 /* this is the 2nd case */
1036 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1037 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1038 set_ia32_am_sc_sign(new_op);
1039 set_ia32_am_flavour(new_op, ia32_am_B);
1041 DBG_OPT_LEA3(op1, op2, node, new_op);
1042 } else if (tp1 == ia32_ImmSymConst) {
1043 tarval *tv = get_ia32_Immop_tarval(new_op2);
1044 long offs = get_tarval_long(tv);
1046 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1047 add_irn_dep(new_op, get_irg_frame(irg));
1048 DBG_OPT_LEA3(op1, op2, node, new_op);
1050 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1051 add_ia32_am_offs_int(new_op, -offs);
1052 set_ia32_am_flavour(new_op, ia32_am_OB);
1053 set_ia32_op_type(new_op, ia32_AddrModeS);
1054 } else if (tp2 == ia32_ImmSymConst) {
1055 tarval *tv = get_ia32_Immop_tarval(new_op1);
1056 long offs = get_tarval_long(tv);
1058 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1059 add_irn_dep(new_op, get_irg_frame(irg));
1060 DBG_OPT_LEA3(op1, op2, node, new_op);
1062 add_ia32_am_offs_int(new_op, offs);
1063 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1064 set_ia32_am_sc_sign(new_op);
1065 set_ia32_am_flavour(new_op, ia32_am_OB);
1066 set_ia32_op_type(new_op, ia32_AddrModeS);
1068 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1069 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1070 tarval *restv = tarval_sub(tv1, tv2);
1072 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1074 new_op = new_rd_ia32_Const(dbgi, irg, block);
1075 set_ia32_Const_tarval(new_op, restv);
1076 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1079 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1081 } else if (imm_op) {
1082 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1083 tarval_classification_t class_tv, class_negtv;
1084 tarval *tv = get_ia32_Immop_tarval(imm_op);
1086 /* optimize tarvals */
1087 class_tv = classify_tarval(tv);
1088 class_negtv = classify_tarval(tarval_neg(tv));
1090 if (class_tv == TV_CLASSIFY_ONE) {
1091 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1092 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1093 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1095 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1096 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1097 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1098 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1104 /* This is a normal sub */
1105 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1107 /* set AM support */
1108 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1110 fold_immediate(new_op, 2, 3);
1112 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1120 * Generates an ia32 DivMod with additional infrastructure for the
1121 * register allocator if needed.
1123 * @param dividend -no comment- :)
1124 * @param divisor -no comment- :)
1125 * @param dm_flav flavour_Div/Mod/DivMod
1126 * @return The created ia32 DivMod node
1128 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1129 ir_node *divisor, ia32_op_flavour_t dm_flav)
1131 ir_node *block = be_transform_node(get_nodes_block(node));
1132 ir_node *new_dividend = be_transform_node(dividend);
1133 ir_node *new_divisor = be_transform_node(divisor);
1134 ir_graph *irg = current_ir_graph;
1135 dbg_info *dbgi = get_irn_dbg_info(node);
1136 ir_mode *mode = get_irn_mode(node);
1137 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1138 ir_node *res, *proj_div, *proj_mod;
1139 ir_node *sign_extension;
1140 ir_node *in_keep[2];
1141 ir_node *mem, *new_mem;
1142 ir_node *projs[pn_DivMod_max];
1145 ia32_collect_Projs(node, projs, pn_DivMod_max);
1147 proj_div = proj_mod = NULL;
1151 mem = get_Div_mem(node);
1152 mode = get_Div_resmode(node);
1153 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1154 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1157 mem = get_Mod_mem(node);
1158 mode = get_Mod_resmode(node);
1159 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1160 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1162 case flavour_DivMod:
1163 mem = get_DivMod_mem(node);
1164 mode = get_DivMod_resmode(node);
1165 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1166 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1167 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1170 panic("invalid divmod flavour!");
1172 new_mem = be_transform_node(mem);
1174 if (mode_is_signed(mode)) {
1175 /* in signed mode, we need to sign extend the dividend */
1176 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1178 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1179 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1181 add_irn_dep(sign_extension, get_irg_frame(irg));
1184 if (mode_is_signed(mode)) {
1185 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1186 sign_extension, new_divisor, new_mem, dm_flav);
1188 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1189 sign_extension, new_divisor, new_mem, dm_flav);
1192 set_ia32_exc_label(res, has_exc);
1193 set_irn_pinned(res, get_irn_pinned(node));
1195 /* Matze: code can't handle this at the moment... */
1197 /* set AM support */
1198 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1201 /* check, which Proj-Keep, we need to add */
1203 if (proj_div == NULL) {
1204 /* We have only mod result: add div res Proj-Keep */
1205 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1208 if (proj_mod == NULL) {
1209 /* We have only div result: add mod res Proj-Keep */
1210 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1214 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1216 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1223 * Wrapper for generate_DivMod. Sets flavour_Mod.
1226 static ir_node *gen_Mod(ir_node *node) {
1227 return generate_DivMod(node, get_Mod_left(node),
1228 get_Mod_right(node), flavour_Mod);
1232 * Wrapper for generate_DivMod. Sets flavour_Div.
1235 static ir_node *gen_Div(ir_node *node) {
1236 return generate_DivMod(node, get_Div_left(node),
1237 get_Div_right(node), flavour_Div);
1241 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1243 static ir_node *gen_DivMod(ir_node *node) {
1244 return generate_DivMod(node, get_DivMod_left(node),
1245 get_DivMod_right(node), flavour_DivMod);
1251 * Creates an ia32 floating Div.
1253 * @return The created ia32 xDiv node
1255 static ir_node *gen_Quot(ir_node *node) {
1256 ir_node *block = be_transform_node(get_nodes_block(node));
1257 ir_node *op1 = get_Quot_left(node);
1258 ir_node *new_op1 = be_transform_node(op1);
1259 ir_node *op2 = get_Quot_right(node);
1260 ir_node *new_op2 = be_transform_node(op2);
1261 ir_graph *irg = current_ir_graph;
1262 dbg_info *dbgi = get_irn_dbg_info(node);
1263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1264 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1268 if (USE_SSE2(env_cg)) {
1269 ir_mode *mode = get_irn_mode(op1);
1270 if (is_ia32_xConst(new_op2)) {
1271 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1272 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1273 copy_ia32_Immop_attr(new_op, new_op2);
1275 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1276 // Matze: disabled for now, spillslot coalescer fails
1277 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1279 set_ia32_ls_mode(new_op, mode);
1281 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1282 &ia32_fp_cw_regs[REG_FPCW]);
1283 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1284 new_op2, nomem, fpcw);
1285 // Matze: disabled for now (spillslot coalescer fails)
1286 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1288 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1294 * Creates an ia32 Shl.
1296 * @return The created ia32 Shl node
1298 static ir_node *gen_Shl(ir_node *node) {
1299 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1306 * Creates an ia32 Shr.
1308 * @return The created ia32 Shr node
1310 static ir_node *gen_Shr(ir_node *node) {
1311 return gen_shift_binop(node, get_Shr_left(node),
1312 get_Shr_right(node), new_rd_ia32_Shr);
1318 * Creates an ia32 Sar.
1320 * @return The created ia32 Shrs node
1322 static ir_node *gen_Shrs(ir_node *node) {
1323 ir_node *left = get_Shrs_left(node);
1324 ir_node *right = get_Shrs_right(node);
1325 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1326 tarval *tv = get_Const_tarval(right);
1327 long val = get_tarval_long(tv);
1329 /* this is a sign extension */
1330 ir_graph *irg = current_ir_graph;
1331 dbg_info *dbgi = get_irn_dbg_info(node);
1332 ir_node *block = be_transform_node(get_nodes_block(node));
1334 ir_node *new_op = be_transform_node(op);
1336 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1340 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1346 * Creates an ia32 RotL.
1348 * @param op1 The first operator
1349 * @param op2 The second operator
1350 * @return The created ia32 RotL node
1352 static ir_node *gen_RotL(ir_node *node,
1353 ir_node *op1, ir_node *op2) {
1354 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1360 * Creates an ia32 RotR.
1361 * NOTE: There is no RotR with immediate because this would always be a RotL
1362 * "imm-mode_size_bits" which can be pre-calculated.
1364 * @param op1 The first operator
1365 * @param op2 The second operator
1366 * @return The created ia32 RotR node
1368 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1370 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1376 * Creates an ia32 RotR or RotL (depending on the found pattern).
1378 * @return The created ia32 RotL or RotR node
1380 static ir_node *gen_Rot(ir_node *node) {
1381 ir_node *rotate = NULL;
1382 ir_node *op1 = get_Rot_left(node);
1383 ir_node *op2 = get_Rot_right(node);
1385 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1386 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1387 that means we can create a RotR instead of an Add and a RotL */
1389 if (get_irn_op(op2) == op_Add) {
1391 ir_node *left = get_Add_left(add);
1392 ir_node *right = get_Add_right(add);
1393 if (is_Const(right)) {
1394 tarval *tv = get_Const_tarval(right);
1395 ir_mode *mode = get_irn_mode(node);
1396 long bits = get_mode_size_bits(mode);
1398 if (get_irn_op(left) == op_Minus &&
1399 tarval_is_long(tv) &&
1400 get_tarval_long(tv) == bits)
1402 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1403 rotate = gen_RotR(node, op1, get_Minus_op(left));
1408 if (rotate == NULL) {
1409 rotate = gen_RotL(node, op1, op2);
1418 * Transforms a Minus node.
1420 * @param op The Minus operand
1421 * @return The created ia32 Minus node
1423 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1424 ir_node *block = be_transform_node(get_nodes_block(node));
1425 ir_graph *irg = current_ir_graph;
1426 dbg_info *dbgi = get_irn_dbg_info(node);
1427 ir_mode *mode = get_irn_mode(node);
1432 if (mode_is_float(mode)) {
1433 ir_node *new_op = be_transform_node(op);
1435 if (USE_SSE2(env_cg)) {
1436 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1437 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1438 ir_node *nomem = new_rd_NoMem(irg);
1440 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1442 size = get_mode_size_bits(mode);
1443 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1445 set_ia32_am_sc(res, ent);
1446 set_ia32_op_type(res, ia32_AddrModeS);
1447 set_ia32_ls_mode(res, mode);
1449 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1452 res = gen_unop(node, op, new_rd_ia32_Neg);
1455 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1461 * Transforms a Minus node.
1463 * @return The created ia32 Minus node
1465 static ir_node *gen_Minus(ir_node *node) {
1466 return gen_Minus_ex(node, get_Minus_op(node));
1471 * Transforms a Not node.
1473 * @return The created ia32 Not node
1475 static ir_node *gen_Not(ir_node *node) {
1476 ir_node *op = get_Not_op(node);
1478 assert (! mode_is_float(get_irn_mode(node)));
1479 return gen_unop(node, op, new_rd_ia32_Not);
1485 * Transforms an Abs node.
1487 * @return The created ia32 Abs node
1489 static ir_node *gen_Abs(ir_node *node) {
1490 ir_node *block = be_transform_node(get_nodes_block(node));
1491 ir_node *op = get_Abs_op(node);
1492 ir_node *new_op = be_transform_node(op);
1493 ir_graph *irg = current_ir_graph;
1494 dbg_info *dbgi = get_irn_dbg_info(node);
1495 ir_mode *mode = get_irn_mode(node);
1496 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1497 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1498 ir_node *nomem = new_NoMem();
1503 if (mode_is_float(mode)) {
1505 if (USE_SSE2(env_cg)) {
1506 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1508 size = get_mode_size_bits(mode);
1509 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1511 set_ia32_am_sc(res, ent);
1513 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1515 set_ia32_op_type(res, ia32_AddrModeS);
1516 set_ia32_ls_mode(res, mode);
1519 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1520 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1524 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1525 SET_IA32_ORIG_NODE(sign_extension,
1526 ia32_get_old_node_name(env_cg, node));
1528 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1529 sign_extension, nomem);
1530 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1532 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1533 sign_extension, nomem);
1534 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1543 * Transforms a Load.
1545 * @return the created ia32 Load node
1547 static ir_node *gen_Load(ir_node *node) {
1548 ir_node *block = be_transform_node(get_nodes_block(node));
1549 ir_node *ptr = get_Load_ptr(node);
1550 ir_node *new_ptr = be_transform_node(ptr);
1551 ir_node *mem = get_Load_mem(node);
1552 ir_node *new_mem = be_transform_node(mem);
1553 ir_graph *irg = current_ir_graph;
1554 dbg_info *dbgi = get_irn_dbg_info(node);
1555 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1556 ir_mode *mode = get_Load_mode(node);
1558 ir_node *lptr = new_ptr;
1561 ir_node *projs[pn_Load_max];
1562 ia32_am_flavour_t am_flav = ia32_am_B;
1564 ia32_collect_Projs(node, projs, pn_Load_max);
1566 /* address might be a constant (symconst or absolute address) */
1567 if (is_ia32_Const(new_ptr)) {
1572 if (mode_is_float(mode)) {
1574 if (USE_SSE2(env_cg)) {
1575 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1576 res_mode = mode_xmm;
1578 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1579 res_mode = mode_vfp;
1582 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1587 check for special case: the loaded value might not be used
1589 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1590 /* add a result proj and a Keep to produce a pseudo use */
1591 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1593 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1596 /* base is a constant address */
1598 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1599 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1600 am_flav = ia32_am_N;
1602 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1603 long offs = get_tarval_long(tv);
1605 add_ia32_am_offs_int(new_op, offs);
1606 am_flav = ia32_am_O;
1610 set_irn_pinned(new_op, get_irn_pinned(node));
1611 set_ia32_op_type(new_op, ia32_AddrModeS);
1612 set_ia32_am_flavour(new_op, am_flav);
1613 set_ia32_ls_mode(new_op, mode);
1615 /* make sure we are scheduled behind the initial IncSP/Barrier
1616 * to avoid spills being placed before it
1618 if (block == get_irg_start_block(irg)) {
1619 add_irn_dep(new_op, get_irg_frame(irg));
1622 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1623 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1631 * Transforms a Store.
1633 * @return the created ia32 Store node
1635 static ir_node *gen_Store(ir_node *node) {
1636 ir_node *block = be_transform_node(get_nodes_block(node));
1637 ir_node *ptr = get_Store_ptr(node);
1638 ir_node *new_ptr = be_transform_node(ptr);
1639 ir_node *val = get_Store_value(node);
1641 ir_node *mem = get_Store_mem(node);
1642 ir_node *new_mem = be_transform_node(mem);
1643 ir_graph *irg = current_ir_graph;
1644 dbg_info *dbgi = get_irn_dbg_info(node);
1645 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1646 ir_node *sptr = new_ptr;
1647 ir_mode *mode = get_irn_mode(val);
1650 ia32_am_flavour_t am_flav = ia32_am_B;
1652 /* address might be a constant (symconst or absolute address) */
1653 if (is_ia32_Const(new_ptr)) {
1658 if (mode_is_float(mode)) {
1661 new_val = be_transform_node(val);
1662 if (USE_SSE2(env_cg)) {
1663 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1666 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1670 new_val = create_immediate_or_transform(val, 0);
1672 if (get_mode_size_bits(mode) == 8) {
1673 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1676 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1681 /* base is an constant address */
1683 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1684 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1685 am_flav = ia32_am_N;
1687 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1688 long offs = get_tarval_long(tv);
1690 add_ia32_am_offs_int(new_op, offs);
1691 am_flav = ia32_am_O;
1695 set_irn_pinned(new_op, get_irn_pinned(node));
1696 set_ia32_op_type(new_op, ia32_AddrModeD);
1697 set_ia32_am_flavour(new_op, am_flav);
1698 set_ia32_ls_mode(new_op, mode);
1700 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1701 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1706 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1708 ir_node *cmp_a = get_Cmp_left(node);
1710 ir_node *cmp_b = get_Cmp_right(node);
1720 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
1723 if(!is_Const(cmp_b))
1726 tv = get_Const_tarval(cmp_b);
1727 if(!tarval_is_null(tv))
1731 /* only fold if we're the only user of the And (it's not 100% clear that
1732 * this is better, as we could have a series of Conds as users...)
1734 if(get_irn_n_edges(cmp_a) > 1)
1737 and_left = get_And_left(cmp_a);
1738 and_right = get_And_right(cmp_a);
1740 dbgi = get_irn_dbg_info(node);
1741 noreg = ia32_new_NoReg_gp(env_cg);
1742 nomem = new_NoMem();
1743 new_cmp_a = be_transform_node(and_left);
1744 new_cmp_b = create_immediate_or_transform(and_right, 0);
1746 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1747 new_cmp_a, new_cmp_b, nomem, pnc);
1748 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1749 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1754 static ir_node *create_Switch(ir_node *node)
1756 ir_graph *irg = current_ir_graph;
1757 dbg_info *dbgi = get_irn_dbg_info(node);
1758 ir_node *block = be_transform_node(get_nodes_block(node));
1759 ir_node *sel = get_Cond_selector(node);
1760 ir_node *new_sel = be_transform_node(sel);
1762 int switch_min = INT_MAX;
1763 const ir_edge_t *edge;
1765 /* determine the smallest switch case value */
1766 foreach_out_edge(node, edge) {
1767 ir_node *proj = get_edge_src_irn(edge);
1768 int pn = get_Proj_proj(proj);
1773 if (switch_min != 0) {
1774 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1776 /* if smallest switch case is not 0 we need an additional sub */
1777 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1778 add_ia32_am_offs_int(new_sel, -switch_min);
1779 set_ia32_am_flavour(new_sel, ia32_am_OB);
1780 set_ia32_op_type(new_sel, ia32_AddrModeS);
1782 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1785 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1786 set_ia32_pncode(res, get_Cond_defaultProj(node));
1788 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1794 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1796 * @return The transformed node.
1798 static ir_node *gen_Cond(ir_node *node) {
1799 ir_node *block = be_transform_node(get_nodes_block(node));
1800 ir_graph *irg = current_ir_graph;
1801 dbg_info *dbgi = get_irn_dbg_info(node);
1802 ir_node *sel = get_Cond_selector(node);
1803 ir_mode *sel_mode = get_irn_mode(sel);
1804 ir_node *res = NULL;
1805 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1812 ir_node *nomem = new_NoMem();
1815 if (sel_mode != mode_b) {
1816 return create_Switch(node);
1819 cmp = get_Proj_pred(sel);
1820 cmp_a = get_Cmp_left(cmp);
1821 cmp_b = get_Cmp_right(cmp);
1822 cmp_mode = get_irn_mode(cmp_a);
1823 pnc = get_Proj_proj(sel);
1824 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1825 pnc |= ia32_pn_Cmp_Unsigned;
1828 if(mode_needs_gp_reg(cmp_mode)) {
1829 res = try_create_TestJmp(block, cmp, pnc);
1834 new_cmp_a = be_transform_node(cmp_a);
1835 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1837 if (mode_is_float(cmp_mode)) {
1839 if (USE_SSE2(env_cg)) {
1840 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1842 set_ia32_commutative(res);
1843 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1844 set_ia32_ls_mode(res, cmp_mode);
1847 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1848 set_ia32_commutative(res);
1849 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1850 pn_ia32_vfCondJmp_temp_reg_eax);
1851 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1855 assert(get_mode_size_bits(cmp_mode) == 32);
1856 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1857 new_cmp_a, new_cmp_b, nomem, pnc);
1858 set_ia32_commutative(res);
1859 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1862 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1870 * Transforms a CopyB node.
1872 * @return The transformed node.
1874 static ir_node *gen_CopyB(ir_node *node) {
1875 ir_node *block = be_transform_node(get_nodes_block(node));
1876 ir_node *src = get_CopyB_src(node);
1877 ir_node *new_src = be_transform_node(src);
1878 ir_node *dst = get_CopyB_dst(node);
1879 ir_node *new_dst = be_transform_node(dst);
1880 ir_node *mem = get_CopyB_mem(node);
1881 ir_node *new_mem = be_transform_node(mem);
1882 ir_node *res = NULL;
1883 ir_graph *irg = current_ir_graph;
1884 dbg_info *dbgi = get_irn_dbg_info(node);
1885 int size = get_type_size_bytes(get_CopyB_type(node));
1886 ir_mode *dst_mode = get_irn_mode(dst);
1887 ir_mode *src_mode = get_irn_mode(src);
1891 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1892 /* then we need the size explicitly in ECX. */
1893 if (size >= 32 * 4) {
1894 rem = size & 0x3; /* size % 4 */
1897 res = new_rd_ia32_Const(dbgi, irg, block);
1898 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1899 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1901 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1902 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1904 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1905 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1906 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1907 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1908 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1911 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1912 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1914 /* ok: now attach Proj's because movsd will destroy esi and edi */
1915 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1916 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1917 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1920 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1926 ir_node *gen_be_Copy(ir_node *node)
1928 ir_node *result = be_duplicate_node(node);
1929 ir_mode *mode = get_irn_mode(result);
1931 if (mode_needs_gp_reg(mode)) {
1932 set_irn_mode(result, mode_Iu);
1941 * Transforms a Mux node into CMov.
1943 * @return The transformed node.
1945 static ir_node *gen_Mux(ir_node *node) {
1946 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1947 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1949 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1955 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1956 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1957 ir_node *psi_default);
1960 * Transforms a Psi node into CMov.
1962 * @return The transformed node.
1964 static ir_node *gen_Psi(ir_node *node) {
1965 ir_node *block = be_transform_node(get_nodes_block(node));
1966 ir_node *psi_true = get_Psi_val(node, 0);
1967 ir_node *psi_default = get_Psi_default(node);
1968 ia32_code_gen_t *cg = env_cg;
1969 ir_graph *irg = current_ir_graph;
1970 dbg_info *dbgi = get_irn_dbg_info(node);
1971 ir_node *cond = get_Psi_cond(node, 0);
1972 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1973 ir_node *nomem = new_NoMem();
1975 ir_node *cmp, *cmp_a, *cmp_b;
1976 ir_node *new_cmp_a, *new_cmp_b;
1980 assert(get_Psi_n_conds(node) == 1);
1981 assert(get_irn_mode(cond) == mode_b);
1983 if(is_And(cond) || is_Or(cond)) {
1984 ir_node *new_cond = be_transform_node(cond);
1985 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
1986 arch_set_irn_register(env_cg->arch_env, zero,
1987 &ia32_gp_regs[REG_GP_NOREG]);
1989 /* we have to compare the result against zero */
1990 new_cmp_a = new_cond;
1995 cmp = get_Proj_pred(cond);
1996 cmp_a = get_Cmp_left(cmp);
1997 cmp_b = get_Cmp_right(cmp);
1998 cmp_mode = get_irn_mode(cmp_a);
1999 pnc = get_Proj_proj(cond);
2001 new_cmp_a = be_transform_node(cmp_a);
2002 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2004 if (!mode_is_signed(cmp_mode)) {
2005 pnc |= ia32_pn_Cmp_Unsigned;
2009 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2010 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2011 new_cmp_a, new_cmp_b, nomem, pnc);
2012 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2013 pnc = get_negated_pnc(pnc, cmp_mode);
2014 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2015 new_cmp_a, new_cmp_b, nomem, pnc);
2017 ir_node *new_psi_true = be_transform_node(psi_true);
2018 ir_node *new_psi_default = be_transform_node(psi_default);
2019 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2020 new_psi_true, new_psi_default, pnc);
2022 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2028 * Following conversion rules apply:
2032 * 1) n bit -> m bit n > m (downscale)
2034 * 2) n bit -> m bit n == m (sign change)
2036 * 3) n bit -> m bit n < m (upscale)
2037 * a) source is signed: movsx
2038 * b) source is unsigned: and with lower bits sets
2042 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2046 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2050 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2051 * x87 is mode_E internally, conversions happen only at load and store
2052 * in non-strict semantic
2056 * Create a conversion from x87 state register to general purpose.
2058 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2059 ir_node *block = be_transform_node(get_nodes_block(node));
2060 ir_node *op = get_Conv_op(node);
2061 ir_node *new_op = be_transform_node(op);
2062 ia32_code_gen_t *cg = env_cg;
2063 ir_graph *irg = current_ir_graph;
2064 dbg_info *dbgi = get_irn_dbg_info(node);
2065 ir_node *noreg = ia32_new_NoReg_gp(cg);
2066 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2067 ir_node *fist, *load;
2070 fist = new_rd_ia32_vfist(dbgi, irg, block,
2071 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2073 set_irn_pinned(fist, op_pin_state_floats);
2074 set_ia32_use_frame(fist);
2075 set_ia32_op_type(fist, ia32_AddrModeD);
2076 set_ia32_am_flavour(fist, ia32_am_B);
2077 set_ia32_ls_mode(fist, mode_Iu);
2078 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2081 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2083 set_irn_pinned(load, op_pin_state_floats);
2084 set_ia32_use_frame(load);
2085 set_ia32_op_type(load, ia32_AddrModeS);
2086 set_ia32_am_flavour(load, ia32_am_B);
2087 set_ia32_ls_mode(load, mode_Iu);
2088 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2090 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2094 * Create a conversion from general purpose to x87 register
2096 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2097 ir_node *block = be_transform_node(get_nodes_block(node));
2098 ir_node *op = get_Conv_op(node);
2099 ir_node *new_op = be_transform_node(op);
2100 ir_graph *irg = current_ir_graph;
2101 dbg_info *dbgi = get_irn_dbg_info(node);
2102 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2103 ir_node *nomem = new_NoMem();
2104 ir_node *fild, *store;
2107 /* first convert to 32 bit if necessary */
2108 src_bits = get_mode_size_bits(src_mode);
2109 if (src_bits == 8) {
2110 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2111 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2112 set_ia32_ls_mode(new_op, src_mode);
2113 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2114 } else if (src_bits < 32) {
2115 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2116 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2117 set_ia32_ls_mode(new_op, src_mode);
2118 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2122 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2124 set_ia32_use_frame(store);
2125 set_ia32_op_type(store, ia32_AddrModeD);
2126 set_ia32_am_flavour(store, ia32_am_OB);
2127 set_ia32_ls_mode(store, mode_Iu);
2130 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2132 set_ia32_use_frame(fild);
2133 set_ia32_op_type(fild, ia32_AddrModeS);
2134 set_ia32_am_flavour(fild, ia32_am_OB);
2135 set_ia32_ls_mode(fild, mode_Iu);
2137 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2140 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2143 ir_node *block = get_nodes_block(node);
2144 ir_graph *irg = current_ir_graph;
2145 dbg_info *dbgi = get_irn_dbg_info(node);
2146 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2147 ir_node *nomem = new_NoMem();
2148 int src_bits = get_mode_size_bits(src_mode);
2149 int tgt_bits = get_mode_size_bits(tgt_mode);
2150 ir_node *frame = get_irg_frame(irg);
2151 ir_mode *smaller_mode;
2152 ir_node *store, *load;
2155 if(src_bits <= tgt_bits)
2156 smaller_mode = src_mode;
2158 smaller_mode = tgt_mode;
2160 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2162 set_ia32_use_frame(store);
2163 set_ia32_op_type(store, ia32_AddrModeD);
2164 set_ia32_am_flavour(store, ia32_am_OB);
2166 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2168 set_ia32_use_frame(load);
2169 set_ia32_op_type(load, ia32_AddrModeS);
2170 set_ia32_am_flavour(load, ia32_am_OB);
2172 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2177 * Transforms a Conv node.
2179 * @return The created ia32 Conv node
2181 static ir_node *gen_Conv(ir_node *node) {
2182 ir_node *block = be_transform_node(get_nodes_block(node));
2183 ir_node *op = get_Conv_op(node);
2184 ir_node *new_op = be_transform_node(op);
2185 ir_graph *irg = current_ir_graph;
2186 dbg_info *dbgi = get_irn_dbg_info(node);
2187 ir_mode *src_mode = get_irn_mode(op);
2188 ir_mode *tgt_mode = get_irn_mode(node);
2189 int src_bits = get_mode_size_bits(src_mode);
2190 int tgt_bits = get_mode_size_bits(tgt_mode);
2191 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2192 ir_node *nomem = new_rd_NoMem(irg);
2195 if (src_mode == tgt_mode) {
2196 if (get_Conv_strict(node)) {
2197 if (USE_SSE2(env_cg)) {
2198 /* when we are in SSE mode, we can kill all strict no-op conversion */
2202 /* this should be optimized already, but who knows... */
2203 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2204 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2209 if (mode_is_float(src_mode)) {
2210 /* we convert from float ... */
2211 if (mode_is_float(tgt_mode)) {
2212 if(src_mode == mode_E && tgt_mode == mode_D
2213 && !get_Conv_strict(node)) {
2214 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2219 if (USE_SSE2(env_cg)) {
2220 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2221 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2222 set_ia32_ls_mode(res, tgt_mode);
2224 // Matze: TODO what about strict convs?
2225 if(get_Conv_strict(node)) {
2226 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2227 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2230 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2235 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2236 if (USE_SSE2(env_cg)) {
2237 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2238 set_ia32_ls_mode(res, src_mode);
2240 return gen_x87_fp_to_gp(node);
2244 /* we convert from int ... */
2245 if (mode_is_float(tgt_mode)) {
2248 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2249 if (USE_SSE2(env_cg)) {
2250 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2251 set_ia32_ls_mode(res, tgt_mode);
2252 if(src_bits == 32) {
2253 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2256 return gen_x87_gp_to_fp(node, src_mode);
2260 ir_mode *smaller_mode;
2263 if (src_bits == tgt_bits) {
2264 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2268 if (src_bits < tgt_bits) {
2269 smaller_mode = src_mode;
2270 smaller_bits = src_bits;
2272 smaller_mode = tgt_mode;
2273 smaller_bits = tgt_bits;
2276 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2277 if (smaller_bits == 8) {
2278 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2279 set_ia32_ls_mode(res, smaller_mode);
2281 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2282 set_ia32_ls_mode(res, smaller_mode);
2284 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2288 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2294 int check_immediate_constraint(long val, char immediate_constraint_type)
2296 switch (immediate_constraint_type) {
2300 return val >= 0 && val <= 32;
2302 return val >= 0 && val <= 63;
2304 return val >= -128 && val <= 127;
2306 return val == 0xff || val == 0xffff;
2308 return val >= 0 && val <= 3;
2310 return val >= 0 && val <= 255;
2312 return val >= 0 && val <= 127;
2316 panic("Invalid immediate constraint found");
2321 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2324 tarval *offset = NULL;
2325 int offset_sign = 0;
2327 ir_entity *symconst_ent = NULL;
2328 int symconst_sign = 0;
2330 ir_node *cnst = NULL;
2331 ir_node *symconst = NULL;
2337 mode = get_irn_mode(node);
2338 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2339 !mode_is_reference(mode)) {
2343 if(is_Minus(node)) {
2345 node = get_Minus_op(node);
2348 if(is_Const(node)) {
2351 offset_sign = minus;
2352 } else if(is_SymConst(node)) {
2355 symconst_sign = minus;
2356 } else if(is_Add(node)) {
2357 ir_node *left = get_Add_left(node);
2358 ir_node *right = get_Add_right(node);
2359 if(is_Const(left) && is_SymConst(right)) {
2362 symconst_sign = minus;
2363 offset_sign = minus;
2364 } else if(is_SymConst(left) && is_Const(right)) {
2367 symconst_sign = minus;
2368 offset_sign = minus;
2370 } else if(is_Sub(node)) {
2371 ir_node *left = get_Sub_left(node);
2372 ir_node *right = get_Sub_right(node);
2373 if(is_Const(left) && is_SymConst(right)) {
2376 symconst_sign = !minus;
2377 offset_sign = minus;
2378 } else if(is_SymConst(left) && is_Const(right)) {
2381 symconst_sign = minus;
2382 offset_sign = !minus;
2389 offset = get_Const_tarval(cnst);
2390 if(tarval_is_long(offset)) {
2391 val = get_tarval_long(offset);
2392 } else if(tarval_is_null(offset)) {
2395 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2400 if(!check_immediate_constraint(val, immediate_constraint_type))
2403 if(symconst != NULL) {
2404 if(immediate_constraint_type != 0) {
2405 /* we need full 32bits for symconsts */
2409 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2411 symconst_ent = get_SymConst_entity(symconst);
2413 if(cnst == NULL && symconst == NULL)
2416 if(offset_sign && offset != NULL) {
2417 offset = tarval_neg(offset);
2420 irg = current_ir_graph;
2421 dbgi = get_irn_dbg_info(node);
2422 block = get_irg_start_block(irg);
2423 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2425 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2427 /* make sure we don't schedule stuff before the barrier */
2428 add_irn_dep(res, get_irg_frame(irg));
2434 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2436 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2437 if (new_node == NULL) {
2438 new_node = be_transform_node(node);
2443 typedef struct constraint_t constraint_t;
2444 struct constraint_t {
2447 const arch_register_req_t **out_reqs;
2449 const arch_register_req_t *req;
2450 unsigned immediate_possible;
2451 char immediate_type;
2454 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2456 int immediate_possible = 0;
2457 char immediate_type = 0;
2458 unsigned limited = 0;
2459 const arch_register_class_t *cls = NULL;
2461 struct obstack *obst;
2462 arch_register_req_t *req;
2463 unsigned *limited_ptr;
2467 /* TODO: replace all the asserts with nice error messages */
2469 printf("Constraint: %s\n", c);
2479 assert(cls == NULL ||
2480 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2481 cls = &ia32_reg_classes[CLASS_ia32_gp];
2482 limited |= 1 << REG_EAX;
2485 assert(cls == NULL ||
2486 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2487 cls = &ia32_reg_classes[CLASS_ia32_gp];
2488 limited |= 1 << REG_EBX;
2491 assert(cls == NULL ||
2492 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2493 cls = &ia32_reg_classes[CLASS_ia32_gp];
2494 limited |= 1 << REG_ECX;
2497 assert(cls == NULL ||
2498 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2499 cls = &ia32_reg_classes[CLASS_ia32_gp];
2500 limited |= 1 << REG_EDX;
2503 assert(cls == NULL ||
2504 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2505 cls = &ia32_reg_classes[CLASS_ia32_gp];
2506 limited |= 1 << REG_EDI;
2509 assert(cls == NULL ||
2510 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2511 cls = &ia32_reg_classes[CLASS_ia32_gp];
2512 limited |= 1 << REG_ESI;
2515 case 'q': /* q means lower part of the regs only, this makes no
2516 * difference to Q for us (we only assigne whole registers) */
2517 assert(cls == NULL ||
2518 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2519 cls = &ia32_reg_classes[CLASS_ia32_gp];
2520 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2524 assert(cls == NULL ||
2525 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2526 cls = &ia32_reg_classes[CLASS_ia32_gp];
2527 limited |= 1 << REG_EAX | 1 << REG_EDX;
2530 assert(cls == NULL ||
2531 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2532 cls = &ia32_reg_classes[CLASS_ia32_gp];
2533 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2534 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2541 assert(cls == NULL);
2542 cls = &ia32_reg_classes[CLASS_ia32_gp];
2548 /* TODO: mark values so the x87 simulator knows about t and u */
2549 assert(cls == NULL);
2550 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2555 assert(cls == NULL);
2556 /* TODO: check that sse2 is supported */
2557 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2567 assert(!immediate_possible);
2568 immediate_possible = 1;
2569 immediate_type = *c;
2573 assert(!immediate_possible);
2574 immediate_possible = 1;
2578 assert(!immediate_possible && cls == NULL);
2579 immediate_possible = 1;
2580 cls = &ia32_reg_classes[CLASS_ia32_gp];
2593 assert(constraint->is_in && "can only specify same constraint "
2596 sscanf(c, "%d%n", &same_as, &p);
2603 case 'E': /* no float consts yet */
2604 case 'F': /* no float consts yet */
2605 case 's': /* makes no sense on x86 */
2606 case 'X': /* we can't support that in firm */
2610 case '<': /* no autodecrement on x86 */
2611 case '>': /* no autoincrement on x86 */
2612 case 'C': /* sse constant not supported yet */
2613 case 'G': /* 80387 constant not supported yet */
2614 case 'y': /* we don't support mmx registers yet */
2615 case 'Z': /* not available in 32 bit mode */
2616 case 'e': /* not available in 32 bit mode */
2617 assert(0 && "asm constraint not supported");
2620 assert(0 && "unknown asm constraint found");
2627 const arch_register_req_t *other_constr;
2629 assert(cls == NULL && "same as and register constraint not supported");
2630 assert(!immediate_possible && "same as and immediate constraint not "
2632 assert(same_as < constraint->n_outs && "wrong constraint number in "
2633 "same_as constraint");
2635 other_constr = constraint->out_reqs[same_as];
2637 req = obstack_alloc(obst, sizeof(req[0]));
2638 req->cls = other_constr->cls;
2639 req->type = arch_register_req_type_should_be_same;
2640 req->limited = NULL;
2641 req->other_same = pos;
2642 req->other_different = -1;
2644 /* switch constraints. This is because in firm we have same_as
2645 * constraints on the output constraints while in the gcc asm syntax
2646 * they are specified on the input constraints */
2647 constraint->req = other_constr;
2648 constraint->out_reqs[same_as] = req;
2649 constraint->immediate_possible = 0;
2653 if(immediate_possible && cls == NULL) {
2654 cls = &ia32_reg_classes[CLASS_ia32_gp];
2656 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2657 assert(cls != NULL);
2659 if(immediate_possible) {
2660 assert(constraint->is_in
2661 && "imeediates make no sense for output constraints");
2663 /* todo: check types (no float input on 'r' constrainted in and such... */
2665 irg = current_ir_graph;
2666 obst = get_irg_obstack(irg);
2669 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2670 limited_ptr = (unsigned*) (req+1);
2672 req = obstack_alloc(obst, sizeof(req[0]));
2674 memset(req, 0, sizeof(req[0]));
2677 req->type = arch_register_req_type_limited;
2678 *limited_ptr = limited;
2679 req->limited = limited_ptr;
2681 req->type = arch_register_req_type_normal;
2685 constraint->req = req;
2686 constraint->immediate_possible = immediate_possible;
2687 constraint->immediate_type = immediate_type;
2691 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2698 panic("Clobbers not supported yet");
2701 ir_node *gen_ASM(ir_node *node)
2704 ir_graph *irg = current_ir_graph;
2705 ir_node *block = be_transform_node(get_nodes_block(node));
2706 dbg_info *dbgi = get_irn_dbg_info(node);
2713 ia32_asm_attr_t *attr;
2714 const arch_register_req_t **out_reqs;
2715 const arch_register_req_t **in_reqs;
2716 struct obstack *obst;
2717 constraint_t parsed_constraint;
2719 /* assembler could contain float statements */
2722 /* transform inputs */
2723 arity = get_irn_arity(node);
2724 in = alloca(arity * sizeof(in[0]));
2725 memset(in, 0, arity * sizeof(in[0]));
2727 n_outs = get_ASM_n_output_constraints(node);
2728 n_clobbers = get_ASM_n_clobbers(node);
2729 out_arity = n_outs + n_clobbers;
2731 /* construct register constraints */
2732 obst = get_irg_obstack(irg);
2733 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2734 parsed_constraint.out_reqs = out_reqs;
2735 parsed_constraint.n_outs = n_outs;
2736 parsed_constraint.is_in = 0;
2737 for(i = 0; i < out_arity; ++i) {
2741 const ir_asm_constraint *constraint;
2742 constraint = & get_ASM_output_constraints(node) [i];
2743 c = get_id_str(constraint->constraint);
2744 parse_asm_constraint(i, &parsed_constraint, c);
2746 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2747 c = get_id_str(glob_id);
2748 parse_clobber(node, i, &parsed_constraint, c);
2750 out_reqs[i] = parsed_constraint.req;
2753 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2754 parsed_constraint.is_in = 1;
2755 for(i = 0; i < arity; ++i) {
2756 const ir_asm_constraint *constraint;
2760 constraint = & get_ASM_input_constraints(node) [i];
2761 constr_id = constraint->constraint;
2762 c = get_id_str(constr_id);
2763 parse_asm_constraint(i, &parsed_constraint, c);
2764 in_reqs[i] = parsed_constraint.req;
2766 if(parsed_constraint.immediate_possible) {
2767 ir_node *pred = get_irn_n(node, i);
2768 char imm_type = parsed_constraint.immediate_type;
2769 ir_node *immediate = try_create_Immediate(pred, imm_type);
2771 if(immediate != NULL) {
2777 /* transform inputs */
2778 for(i = 0; i < arity; ++i) {
2780 ir_node *transformed;
2785 pred = get_irn_n(node, i);
2786 transformed = be_transform_node(pred);
2787 in[i] = transformed;
2790 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2792 generic_attr = get_irn_generic_attr(res);
2793 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2794 attr->asm_text = get_ASM_text(node);
2795 set_ia32_out_req_all(res, out_reqs);
2796 set_ia32_in_req_all(res, in_reqs);
2798 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2803 /********************************************
2806 * | |__ ___ _ __ ___ __| | ___ ___
2807 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2808 * | |_) | __/ | | | (_) | (_| | __/\__ \
2809 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2811 ********************************************/
2813 static ir_node *gen_be_StackParam(ir_node *node) {
2814 ir_node *block = be_transform_node(get_nodes_block(node));
2815 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2816 ir_node *new_ptr = be_transform_node(ptr);
2817 ir_node *new_op = NULL;
2818 ir_graph *irg = current_ir_graph;
2819 dbg_info *dbgi = get_irn_dbg_info(node);
2820 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2821 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2822 ir_mode *load_mode = get_irn_mode(node);
2823 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2827 if (mode_is_float(load_mode)) {
2829 if (USE_SSE2(env_cg)) {
2830 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2831 pn_res = pn_ia32_xLoad_res;
2832 proj_mode = mode_xmm;
2834 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2835 pn_res = pn_ia32_vfld_res;
2836 proj_mode = mode_vfp;
2839 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2840 proj_mode = mode_Iu;
2841 pn_res = pn_ia32_Load_res;
2844 set_irn_pinned(new_op, op_pin_state_floats);
2845 set_ia32_frame_ent(new_op, ent);
2846 set_ia32_use_frame(new_op);
2848 set_ia32_op_type(new_op, ia32_AddrModeS);
2849 set_ia32_am_flavour(new_op, ia32_am_B);
2850 set_ia32_ls_mode(new_op, load_mode);
2851 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2853 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2855 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2859 * Transforms a FrameAddr into an ia32 Add.
2861 static ir_node *gen_be_FrameAddr(ir_node *node) {
2862 ir_node *block = be_transform_node(get_nodes_block(node));
2863 ir_node *op = be_get_FrameAddr_frame(node);
2864 ir_node *new_op = be_transform_node(op);
2865 ir_graph *irg = current_ir_graph;
2866 dbg_info *dbgi = get_irn_dbg_info(node);
2867 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2870 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2871 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2872 set_ia32_use_frame(res);
2873 set_ia32_am_flavour(res, ia32_am_OB);
2875 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2881 * Transforms a FrameLoad into an ia32 Load.
2883 static ir_node *gen_be_FrameLoad(ir_node *node) {
2884 ir_node *block = be_transform_node(get_nodes_block(node));
2885 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2886 ir_node *new_mem = be_transform_node(mem);
2887 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2888 ir_node *new_ptr = be_transform_node(ptr);
2889 ir_node *new_op = NULL;
2890 ir_graph *irg = current_ir_graph;
2891 dbg_info *dbgi = get_irn_dbg_info(node);
2892 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2893 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2894 ir_mode *mode = get_type_mode(get_entity_type(ent));
2895 ir_node *projs[pn_Load_max];
2897 ia32_collect_Projs(node, projs, pn_Load_max);
2899 if (mode_is_float(mode)) {
2901 if (USE_SSE2(env_cg)) {
2902 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2905 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2909 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2912 set_irn_pinned(new_op, op_pin_state_floats);
2913 set_ia32_frame_ent(new_op, ent);
2914 set_ia32_use_frame(new_op);
2916 set_ia32_op_type(new_op, ia32_AddrModeS);
2917 set_ia32_am_flavour(new_op, ia32_am_B);
2918 set_ia32_ls_mode(new_op, mode);
2919 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2928 * Transforms a FrameStore into an ia32 Store.
2930 static ir_node *gen_be_FrameStore(ir_node *node) {
2931 ir_node *block = be_transform_node(get_nodes_block(node));
2932 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2933 ir_node *new_mem = be_transform_node(mem);
2934 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2935 ir_node *new_ptr = be_transform_node(ptr);
2936 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2937 ir_node *new_val = be_transform_node(val);
2938 ir_node *new_op = NULL;
2939 ir_graph *irg = current_ir_graph;
2940 dbg_info *dbgi = get_irn_dbg_info(node);
2941 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2942 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2943 ir_mode *mode = get_irn_mode(val);
2945 if (mode_is_float(mode)) {
2947 if (USE_SSE2(env_cg)) {
2948 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2950 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2952 } else if (get_mode_size_bits(mode) == 8) {
2953 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2955 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2958 set_ia32_frame_ent(new_op, ent);
2959 set_ia32_use_frame(new_op);
2961 set_ia32_op_type(new_op, ia32_AddrModeD);
2962 set_ia32_am_flavour(new_op, ia32_am_B);
2963 set_ia32_ls_mode(new_op, mode);
2965 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2971 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2973 static ir_node *gen_be_Return(ir_node *node) {
2974 ir_graph *irg = current_ir_graph;
2975 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2976 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2977 ir_entity *ent = get_irg_entity(irg);
2978 ir_type *tp = get_entity_type(ent);
2983 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2984 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2987 int pn_ret_val, pn_ret_mem, arity, i;
2989 assert(ret_val != NULL);
2990 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2991 return be_duplicate_node(node);
2994 res_type = get_method_res_type(tp, 0);
2996 if (! is_Primitive_type(res_type)) {
2997 return be_duplicate_node(node);
3000 mode = get_type_mode(res_type);
3001 if (! mode_is_float(mode)) {
3002 return be_duplicate_node(node);
3005 assert(get_method_n_ress(tp) == 1);
3007 pn_ret_val = get_Proj_proj(ret_val);
3008 pn_ret_mem = get_Proj_proj(ret_mem);
3010 /* get the Barrier */
3011 barrier = get_Proj_pred(ret_val);
3013 /* get result input of the Barrier */
3014 ret_val = get_irn_n(barrier, pn_ret_val);
3015 new_ret_val = be_transform_node(ret_val);
3017 /* get memory input of the Barrier */
3018 ret_mem = get_irn_n(barrier, pn_ret_mem);
3019 new_ret_mem = be_transform_node(ret_mem);
3021 frame = get_irg_frame(irg);
3023 dbgi = get_irn_dbg_info(barrier);
3024 block = be_transform_node(get_nodes_block(barrier));
3026 noreg = ia32_new_NoReg_gp(env_cg);
3028 /* store xmm0 onto stack */
3029 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3030 set_ia32_ls_mode(sse_store, mode);
3031 set_ia32_op_type(sse_store, ia32_AddrModeD);
3032 set_ia32_use_frame(sse_store);
3033 set_ia32_am_flavour(sse_store, ia32_am_B);
3036 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3037 set_ia32_ls_mode(fld, mode);
3038 set_ia32_op_type(fld, ia32_AddrModeS);
3039 set_ia32_use_frame(fld);
3040 set_ia32_am_flavour(fld, ia32_am_B);
3042 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3043 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3044 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3046 /* create a new barrier */
3047 arity = get_irn_arity(barrier);
3048 in = alloca(arity * sizeof(in[0]));
3049 for (i = 0; i < arity; ++i) {
3052 if (i == pn_ret_val) {
3054 } else if (i == pn_ret_mem) {
3057 ir_node *in = get_irn_n(barrier, i);
3058 new_in = be_transform_node(in);
3063 new_barrier = new_ir_node(dbgi, irg, block,
3064 get_irn_op(barrier), get_irn_mode(barrier),
3066 copy_node_attr(barrier, new_barrier);
3067 be_duplicate_deps(barrier, new_barrier);
3068 be_set_transformed_node(barrier, new_barrier);
3069 mark_irn_visited(barrier);
3071 /* transform normally */
3072 return be_duplicate_node(node);
3076 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3078 static ir_node *gen_be_AddSP(ir_node *node) {
3079 ir_node *block = be_transform_node(get_nodes_block(node));
3080 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3082 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3083 ir_node *new_sp = be_transform_node(sp);
3084 ir_graph *irg = current_ir_graph;
3085 dbg_info *dbgi = get_irn_dbg_info(node);
3086 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3087 ir_node *nomem = new_NoMem();
3090 new_sz = create_immediate_or_transform(sz, 0);
3092 /* ia32 stack grows in reverse direction, make a SubSP */
3093 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3095 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3096 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3102 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3104 static ir_node *gen_be_SubSP(ir_node *node) {
3105 ir_node *block = be_transform_node(get_nodes_block(node));
3106 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3108 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3109 ir_node *new_sp = be_transform_node(sp);
3110 ir_graph *irg = current_ir_graph;
3111 dbg_info *dbgi = get_irn_dbg_info(node);
3112 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3113 ir_node *nomem = new_NoMem();
3116 new_sz = create_immediate_or_transform(sz, 0);
3118 /* ia32 stack grows in reverse direction, make an AddSP */
3119 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3120 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3121 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3127 * This function just sets the register for the Unknown node
3128 * as this is not done during register allocation because Unknown
3129 * is an "ignore" node.
3131 static ir_node *gen_Unknown(ir_node *node) {
3132 ir_mode *mode = get_irn_mode(node);
3134 if (mode_is_float(mode)) {
3135 if (USE_SSE2(env_cg))
3136 return ia32_new_Unknown_xmm(env_cg);
3138 return ia32_new_Unknown_vfp(env_cg);
3139 } else if (mode_needs_gp_reg(mode)) {
3140 return ia32_new_Unknown_gp(env_cg);
3142 assert(0 && "unsupported Unknown-Mode");
3149 * Change some phi modes
3151 static ir_node *gen_Phi(ir_node *node) {
3152 ir_node *block = be_transform_node(get_nodes_block(node));
3153 ir_graph *irg = current_ir_graph;
3154 dbg_info *dbgi = get_irn_dbg_info(node);
3155 ir_mode *mode = get_irn_mode(node);
3158 if(mode_needs_gp_reg(mode)) {
3159 /* we shouldn't have any 64bit stuff around anymore */
3160 assert(get_mode_size_bits(mode) <= 32);
3161 /* all integer operations are on 32bit registers now */
3163 } else if(mode_is_float(mode)) {
3164 if (USE_SSE2(env_cg)) {
3171 /* phi nodes allow loops, so we use the old arguments for now
3172 * and fix this later */
3173 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3174 copy_node_attr(node, phi);
3175 be_duplicate_deps(node, phi);
3177 be_set_transformed_node(node, phi);
3178 be_enqueue_preds(node);
3183 /**********************************************************************
3186 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3187 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3188 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3189 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3191 **********************************************************************/
3193 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3195 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3198 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3199 ir_node *val, ir_node *mem);
3202 * Transforms a lowered Load into a "real" one.
3204 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3205 ir_node *block = be_transform_node(get_nodes_block(node));
3206 ir_node *ptr = get_irn_n(node, 0);
3207 ir_node *new_ptr = be_transform_node(ptr);
3208 ir_node *mem = get_irn_n(node, 1);
3209 ir_node *new_mem = be_transform_node(mem);
3210 ir_graph *irg = current_ir_graph;
3211 dbg_info *dbgi = get_irn_dbg_info(node);
3212 ir_mode *mode = get_ia32_ls_mode(node);
3213 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3217 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3218 lowering we have x87 nodes, so we need to enforce simulation.
3220 if (mode_is_float(mode)) {
3222 if (fp_unit == fp_x87)
3226 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3228 set_ia32_op_type(new_op, ia32_AddrModeS);
3229 set_ia32_am_flavour(new_op, ia32_am_OB);
3230 set_ia32_am_offs_int(new_op, 0);
3231 set_ia32_am_scale(new_op, 1);
3232 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3233 if (is_ia32_am_sc_sign(node))
3234 set_ia32_am_sc_sign(new_op);
3235 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3236 if (is_ia32_use_frame(node)) {
3237 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3238 set_ia32_use_frame(new_op);
3241 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3247 * Transforms a lowered Store into a "real" one.
3249 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3250 ir_node *block = be_transform_node(get_nodes_block(node));
3251 ir_node *ptr = get_irn_n(node, 0);
3252 ir_node *new_ptr = be_transform_node(ptr);
3253 ir_node *val = get_irn_n(node, 1);
3254 ir_node *new_val = be_transform_node(val);
3255 ir_node *mem = get_irn_n(node, 2);
3256 ir_node *new_mem = be_transform_node(mem);
3257 ir_graph *irg = current_ir_graph;
3258 dbg_info *dbgi = get_irn_dbg_info(node);
3259 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3260 ir_mode *mode = get_ia32_ls_mode(node);
3263 ia32_am_flavour_t am_flav = ia32_B;
3266 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3267 lowering we have x87 nodes, so we need to enforce simulation.
3269 if (mode_is_float(mode)) {
3271 if (fp_unit == fp_x87)
3275 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3277 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3279 add_ia32_am_offs_int(new_op, am_offs);
3282 set_ia32_op_type(new_op, ia32_AddrModeD);
3283 set_ia32_am_flavour(new_op, am_flav);
3284 set_ia32_ls_mode(new_op, mode);
3285 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3286 set_ia32_use_frame(new_op);
3288 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3295 * Transforms an ia32_l_XXX into a "real" XXX node
3297 * @param env The transformation environment
3298 * @return the created ia32 XXX node
3300 #define GEN_LOWERED_OP(op) \
3301 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3302 ir_mode *mode = get_irn_mode(node); \
3303 if (mode_is_float(mode)) \
3305 return gen_binop(node, get_binop_left(node), \
3306 get_binop_right(node), new_rd_ia32_##op,0); \
3309 #define GEN_LOWERED_x87_OP(op) \
3310 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3312 FORCE_x87(env_cg); \
3313 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3314 get_binop_right(node), new_rd_ia32_##op); \
3318 #define GEN_LOWERED_UNOP(op) \
3319 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3320 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3323 #define GEN_LOWERED_SHIFT_OP(op) \
3324 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3325 return gen_shift_binop(node, get_binop_left(node), \
3326 get_binop_right(node), new_rd_ia32_##op); \
3329 #define GEN_LOWERED_LOAD(op, fp_unit) \
3330 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3331 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3334 #define GEN_LOWERED_STORE(op, fp_unit) \
3335 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3336 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3343 GEN_LOWERED_OP(IMul)
3345 GEN_LOWERED_x87_OP(vfprem)
3346 GEN_LOWERED_x87_OP(vfmul)
3347 GEN_LOWERED_x87_OP(vfsub)
3349 GEN_LOWERED_UNOP(Neg)
3351 GEN_LOWERED_LOAD(vfild, fp_x87)
3352 GEN_LOWERED_LOAD(Load, fp_none)
3353 /*GEN_LOWERED_STORE(vfist, fp_x87)
3356 GEN_LOWERED_STORE(Store, fp_none)
3358 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3359 ir_node *block = be_transform_node(get_nodes_block(node));
3360 ir_node *left = get_binop_left(node);
3361 ir_node *new_left = be_transform_node(left);
3362 ir_node *right = get_binop_right(node);
3363 ir_node *new_right = be_transform_node(right);
3364 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3365 ir_graph *irg = current_ir_graph;
3366 dbg_info *dbgi = get_irn_dbg_info(node);
3367 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3368 &ia32_fp_cw_regs[REG_FPCW]);
3371 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3372 new_right, new_NoMem(), fpcw);
3373 clear_ia32_commutative(vfdiv);
3374 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3376 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3384 * Transforms a l_MulS into a "real" MulS node.
3386 * @param env The transformation environment
3387 * @return the created ia32 Mul node
3389 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3390 ir_node *block = be_transform_node(get_nodes_block(node));
3391 ir_node *left = get_binop_left(node);
3392 ir_node *new_left = be_transform_node(left);
3393 ir_node *right = get_binop_right(node);
3394 ir_node *new_right = be_transform_node(right);
3395 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3396 ir_graph *irg = current_ir_graph;
3397 dbg_info *dbgi = get_irn_dbg_info(node);
3400 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3401 /* and then skip the result Proj, because all needed Projs are already there. */
3402 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3403 new_right, new_NoMem());
3404 clear_ia32_commutative(muls);
3405 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3407 /* check if EAX and EDX proj exist, add missing one */
3408 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3409 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3410 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3412 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3417 GEN_LOWERED_SHIFT_OP(Shl)
3418 GEN_LOWERED_SHIFT_OP(Shr)
3419 GEN_LOWERED_SHIFT_OP(Sar)
3422 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3423 * op1 - target to be shifted
3424 * op2 - contains bits to be shifted into target
3426 * Only op3 can be an immediate.
3428 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3429 ir_node *op2, ir_node *count)
3431 ir_node *block = be_transform_node(get_nodes_block(node));
3432 ir_node *new_op1 = be_transform_node(op1);
3433 ir_node *new_op2 = be_transform_node(op2);
3434 ir_node *new_count = be_transform_node(count);
3435 ir_node *new_op = NULL;
3436 ir_graph *irg = current_ir_graph;
3437 dbg_info *dbgi = get_irn_dbg_info(node);
3438 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3439 ir_node *nomem = new_NoMem();
3443 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3445 /* Check if immediate optimization is on and */
3446 /* if it's an operation with immediate. */
3447 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3449 /* Limit imm_op within range imm8 */
3451 tv = get_ia32_Immop_tarval(imm_op);
3454 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3455 set_ia32_Immop_tarval(imm_op, tv);
3462 /* integer operations */
3464 /* This is ShiftD with const */
3465 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3467 if (is_ia32_l_ShlD(node))
3468 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3469 new_op1, new_op2, noreg, nomem);
3471 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3472 new_op1, new_op2, noreg, nomem);
3473 copy_ia32_Immop_attr(new_op, imm_op);
3476 /* This is a normal ShiftD */
3477 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3478 if (is_ia32_l_ShlD(node))
3479 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3480 new_op1, new_op2, new_count, nomem);
3482 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3483 new_op1, new_op2, new_count, nomem);
3486 /* set AM support */
3487 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3489 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3491 set_ia32_emit_cl(new_op);
3496 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3497 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3498 get_irn_n(node, 1), get_irn_n(node, 2));
3501 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3502 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3503 get_irn_n(node, 1), get_irn_n(node, 2));
3507 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3509 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3510 ir_node *block = be_transform_node(get_nodes_block(node));
3511 ir_node *val = get_irn_n(node, 1);
3512 ir_node *new_val = be_transform_node(val);
3513 ia32_code_gen_t *cg = env_cg;
3514 ir_node *res = NULL;
3515 ir_graph *irg = current_ir_graph;
3517 ir_node *noreg, *new_ptr, *new_mem;
3524 mem = get_irn_n(node, 2);
3525 new_mem = be_transform_node(mem);
3526 ptr = get_irn_n(node, 0);
3527 new_ptr = be_transform_node(ptr);
3528 noreg = ia32_new_NoReg_gp(cg);
3529 dbgi = get_irn_dbg_info(node);
3531 /* Store x87 -> MEM */
3532 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3533 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3534 set_ia32_use_frame(res);
3535 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3536 set_ia32_am_flavour(res, ia32_B);
3537 set_ia32_op_type(res, ia32_AddrModeD);
3539 /* Load MEM -> SSE */
3540 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3541 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3542 set_ia32_use_frame(res);
3543 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3544 set_ia32_am_flavour(res, ia32_B);
3545 set_ia32_op_type(res, ia32_AddrModeS);
3546 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3552 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3554 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3555 ir_node *block = be_transform_node(get_nodes_block(node));
3556 ir_node *val = get_irn_n(node, 1);
3557 ir_node *new_val = be_transform_node(val);
3558 ia32_code_gen_t *cg = env_cg;
3559 ir_graph *irg = current_ir_graph;
3560 ir_node *res = NULL;
3561 ir_entity *fent = get_ia32_frame_ent(node);
3562 ir_mode *lsmode = get_ia32_ls_mode(node);
3564 ir_node *noreg, *new_ptr, *new_mem;
3568 if (! USE_SSE2(cg)) {
3569 /* SSE unit is not used -> skip this node. */
3573 ptr = get_irn_n(node, 0);
3574 new_ptr = be_transform_node(ptr);
3575 mem = get_irn_n(node, 2);
3576 new_mem = be_transform_node(mem);
3577 noreg = ia32_new_NoReg_gp(cg);
3578 dbgi = get_irn_dbg_info(node);
3580 /* Store SSE -> MEM */
3581 if (is_ia32_xLoad(skip_Proj(new_val))) {
3582 ir_node *ld = skip_Proj(new_val);
3584 /* we can vfld the value directly into the fpu */
3585 fent = get_ia32_frame_ent(ld);
3586 ptr = get_irn_n(ld, 0);
3587 offs = get_ia32_am_offs_int(ld);
3589 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3590 set_ia32_frame_ent(res, fent);
3591 set_ia32_use_frame(res);
3592 set_ia32_ls_mode(res, lsmode);
3593 set_ia32_am_flavour(res, ia32_B);
3594 set_ia32_op_type(res, ia32_AddrModeD);
3598 /* Load MEM -> x87 */
3599 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3600 set_ia32_frame_ent(res, fent);
3601 set_ia32_use_frame(res);
3602 add_ia32_am_offs_int(res, offs);
3603 set_ia32_am_flavour(res, ia32_B);
3604 set_ia32_op_type(res, ia32_AddrModeS);
3605 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3610 /*********************************************************
3613 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3614 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3615 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3616 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3618 *********************************************************/
3621 * the BAD transformer.
3623 static ir_node *bad_transform(ir_node *node) {
3624 panic("No transform function for %+F available.\n", node);
3629 * Transform the Projs of an AddSP.
3631 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3632 ir_node *block = be_transform_node(get_nodes_block(node));
3633 ir_node *pred = get_Proj_pred(node);
3634 ir_node *new_pred = be_transform_node(pred);
3635 ir_graph *irg = current_ir_graph;
3636 dbg_info *dbgi = get_irn_dbg_info(node);
3637 long proj = get_Proj_proj(node);
3639 if (proj == pn_be_AddSP_res) {
3640 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3641 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3643 } else if (proj == pn_be_AddSP_M) {
3644 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3648 return new_rd_Unknown(irg, get_irn_mode(node));
3652 * Transform the Projs of a SubSP.
3654 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3655 ir_node *block = be_transform_node(get_nodes_block(node));
3656 ir_node *pred = get_Proj_pred(node);
3657 ir_node *new_pred = be_transform_node(pred);
3658 ir_graph *irg = current_ir_graph;
3659 dbg_info *dbgi = get_irn_dbg_info(node);
3660 long proj = get_Proj_proj(node);
3662 if (proj == pn_be_SubSP_res) {
3663 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3664 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3666 } else if (proj == pn_be_SubSP_M) {
3667 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3671 return new_rd_Unknown(irg, get_irn_mode(node));
3675 * Transform and renumber the Projs from a Load.
3677 static ir_node *gen_Proj_Load(ir_node *node) {
3678 ir_node *block = be_transform_node(get_nodes_block(node));
3679 ir_node *pred = get_Proj_pred(node);
3680 ir_node *new_pred = be_transform_node(pred);
3681 ir_graph *irg = current_ir_graph;
3682 dbg_info *dbgi = get_irn_dbg_info(node);
3683 long proj = get_Proj_proj(node);
3685 /* renumber the proj */
3686 if (is_ia32_Load(new_pred)) {
3687 if (proj == pn_Load_res) {
3688 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3689 } else if (proj == pn_Load_M) {
3690 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3692 } else if (is_ia32_xLoad(new_pred)) {
3693 if (proj == pn_Load_res) {
3694 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3695 } else if (proj == pn_Load_M) {
3696 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3698 } else if (is_ia32_vfld(new_pred)) {
3699 if (proj == pn_Load_res) {
3700 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3701 } else if (proj == pn_Load_M) {
3702 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3707 return new_rd_Unknown(irg, get_irn_mode(node));
3711 * Transform and renumber the Projs from a DivMod like instruction.
3713 static ir_node *gen_Proj_DivMod(ir_node *node) {
3714 ir_node *block = be_transform_node(get_nodes_block(node));
3715 ir_node *pred = get_Proj_pred(node);
3716 ir_node *new_pred = be_transform_node(pred);
3717 ir_graph *irg = current_ir_graph;
3718 dbg_info *dbgi = get_irn_dbg_info(node);
3719 ir_mode *mode = get_irn_mode(node);
3720 long proj = get_Proj_proj(node);
3722 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3724 switch (get_irn_opcode(pred)) {
3728 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3730 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3748 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3749 case pn_DivMod_res_div:
3750 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3751 case pn_DivMod_res_mod:
3752 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3762 return new_rd_Unknown(irg, mode);
3766 * Transform and renumber the Projs from a CopyB.
3768 static ir_node *gen_Proj_CopyB(ir_node *node) {
3769 ir_node *block = be_transform_node(get_nodes_block(node));
3770 ir_node *pred = get_Proj_pred(node);
3771 ir_node *new_pred = be_transform_node(pred);
3772 ir_graph *irg = current_ir_graph;
3773 dbg_info *dbgi = get_irn_dbg_info(node);
3774 ir_mode *mode = get_irn_mode(node);
3775 long proj = get_Proj_proj(node);
3778 case pn_CopyB_M_regular:
3779 if (is_ia32_CopyB_i(new_pred)) {
3780 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3781 } else if (is_ia32_CopyB(new_pred)) {
3782 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3790 return new_rd_Unknown(irg, mode);
3794 * Transform and renumber the Projs from a vfdiv.
3796 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3797 ir_node *block = be_transform_node(get_nodes_block(node));
3798 ir_node *pred = get_Proj_pred(node);
3799 ir_node *new_pred = be_transform_node(pred);
3800 ir_graph *irg = current_ir_graph;
3801 dbg_info *dbgi = get_irn_dbg_info(node);
3802 ir_mode *mode = get_irn_mode(node);
3803 long proj = get_Proj_proj(node);
3806 case pn_ia32_l_vfdiv_M:
3807 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3808 case pn_ia32_l_vfdiv_res:
3809 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3814 return new_rd_Unknown(irg, mode);
3818 * Transform and renumber the Projs from a Quot.
3820 static ir_node *gen_Proj_Quot(ir_node *node) {
3821 ir_node *block = be_transform_node(get_nodes_block(node));
3822 ir_node *pred = get_Proj_pred(node);
3823 ir_node *new_pred = be_transform_node(pred);
3824 ir_graph *irg = current_ir_graph;
3825 dbg_info *dbgi = get_irn_dbg_info(node);
3826 ir_mode *mode = get_irn_mode(node);
3827 long proj = get_Proj_proj(node);
3831 if (is_ia32_xDiv(new_pred)) {
3832 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3833 } else if (is_ia32_vfdiv(new_pred)) {
3834 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3838 if (is_ia32_xDiv(new_pred)) {
3839 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3840 } else if (is_ia32_vfdiv(new_pred)) {
3841 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3849 return new_rd_Unknown(irg, mode);
3853 * Transform the Thread Local Storage Proj.
3855 static ir_node *gen_Proj_tls(ir_node *node) {
3856 ir_node *block = be_transform_node(get_nodes_block(node));
3857 ir_graph *irg = current_ir_graph;
3858 dbg_info *dbgi = NULL;
3859 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3865 * Transform the Projs from a be_Call.
3867 static ir_node *gen_Proj_be_Call(ir_node *node) {
3868 ir_node *block = be_transform_node(get_nodes_block(node));
3869 ir_node *call = get_Proj_pred(node);
3870 ir_node *new_call = be_transform_node(call);
3871 ir_graph *irg = current_ir_graph;
3872 dbg_info *dbgi = get_irn_dbg_info(node);
3873 long proj = get_Proj_proj(node);
3874 ir_mode *mode = get_irn_mode(node);
3876 const arch_register_class_t *cls;
3878 /* The following is kinda tricky: If we're using SSE, then we have to
3879 * move the result value of the call in floating point registers to an
3880 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3881 * after the call, we have to make sure to correctly make the
3882 * MemProj and the result Proj use these 2 nodes
3884 if (proj == pn_be_Call_M_regular) {
3885 // get new node for result, are we doing the sse load/store hack?
3886 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3887 ir_node *call_res_new;
3888 ir_node *call_res_pred = NULL;
3890 if (call_res != NULL) {
3891 call_res_new = be_transform_node(call_res);
3892 call_res_pred = get_Proj_pred(call_res_new);
3895 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3896 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3898 assert(is_ia32_xLoad(call_res_pred));
3899 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3902 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3904 ir_node *frame = get_irg_frame(irg);
3905 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3907 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3909 const arch_register_class_t *cls;
3911 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3912 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3914 /* store st(0) onto stack */
3915 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3917 set_ia32_ls_mode(fstp, mode);
3918 set_ia32_op_type(fstp, ia32_AddrModeD);
3919 set_ia32_use_frame(fstp);
3920 set_ia32_am_flavour(fstp, ia32_am_B);
3922 /* load into SSE register */
3923 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3924 set_ia32_ls_mode(sse_load, mode);
3925 set_ia32_op_type(sse_load, ia32_AddrModeS);
3926 set_ia32_use_frame(sse_load);
3927 set_ia32_am_flavour(sse_load, ia32_am_B);
3929 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3931 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3933 /* get a Proj representing a caller save register */
3934 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3935 assert(is_Proj(p) && "Proj expected.");
3937 /* user of the the proj is the Keep */
3938 p = get_edge_src_irn(get_irn_out_edge_first(p));
3939 assert(be_is_Keep(p) && "Keep expected.");
3941 /* keep the result */
3942 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3943 keepin[0] = sse_load;
3944 be_new_Keep(cls, irg, block, 1, keepin);
3949 /* transform call modes */
3950 if (mode_is_data(mode)) {
3951 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3955 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3959 * Transform the Projs from a Cmp.
3961 static ir_node *gen_Proj_Cmp(ir_node *node)
3963 /* normally Cmps are processed when looking at Cond nodes, but this case
3964 * can happen in complicated Psi conditions */
3966 ir_graph *irg = current_ir_graph;
3967 dbg_info *dbgi = get_irn_dbg_info(node);
3968 ir_node *block = be_transform_node(get_nodes_block(node));
3969 ir_node *cmp = get_Proj_pred(node);
3970 long pnc = get_Proj_proj(node);
3971 ir_node *cmp_left = get_Cmp_left(cmp);
3972 ir_node *cmp_right = get_Cmp_right(cmp);
3973 ir_node *new_cmp_left;
3974 ir_node *new_cmp_right;
3975 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3976 ir_node *nomem = new_rd_NoMem(irg);
3977 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3980 assert(!mode_is_float(cmp_mode));
3982 /* (a != b) -> (a ^ b) */
3983 if(pnc == pn_Cmp_Lg) {
3984 if(is_Const_0(cmp_left)) {
3985 new_op = be_transform_node(cmp_right);
3986 } else if(is_Const_0(cmp_right)) {
3987 new_op = be_transform_node(cmp_left);
3989 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
3995 * (a == b) -> !(a ^ b)
3996 * (a < 0) -> (a & 0x80000000) oder a >> 31
3997 * (a >= 0) -> (a >> 31) ^ 1
4000 if(!mode_is_signed(cmp_mode)) {
4001 pnc |= ia32_pn_Cmp_Unsigned;
4004 new_cmp_left = be_transform_node(cmp_left);
4005 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
4007 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4008 new_cmp_right, nomem, pnc);
4009 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4015 * Transform and potentially renumber Proj nodes.
4017 static ir_node *gen_Proj(ir_node *node) {
4018 ir_graph *irg = current_ir_graph;
4019 dbg_info *dbgi = get_irn_dbg_info(node);
4020 ir_node *pred = get_Proj_pred(node);
4021 long proj = get_Proj_proj(node);
4023 if (is_Store(pred) || be_is_FrameStore(pred)) {
4024 if (proj == pn_Store_M) {
4025 return be_transform_node(pred);
4028 return new_r_Bad(irg);
4030 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4031 return gen_Proj_Load(node);
4032 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4033 return gen_Proj_DivMod(node);
4034 } else if (is_CopyB(pred)) {
4035 return gen_Proj_CopyB(node);
4036 } else if (is_Quot(pred)) {
4037 return gen_Proj_Quot(node);
4038 } else if (is_ia32_l_vfdiv(pred)) {
4039 return gen_Proj_l_vfdiv(node);
4040 } else if (be_is_SubSP(pred)) {
4041 return gen_Proj_be_SubSP(node);
4042 } else if (be_is_AddSP(pred)) {
4043 return gen_Proj_be_AddSP(node);
4044 } else if (be_is_Call(pred)) {
4045 return gen_Proj_be_Call(node);
4046 } else if (is_Cmp(pred)) {
4047 return gen_Proj_Cmp(node);
4048 } else if (get_irn_op(pred) == op_Start) {
4049 if (proj == pn_Start_X_initial_exec) {
4050 ir_node *block = get_nodes_block(pred);
4053 /* we exchange the ProjX with a jump */
4054 block = be_transform_node(block);
4055 jump = new_rd_Jmp(dbgi, irg, block);
4058 if (node == be_get_old_anchor(anchor_tls)) {
4059 return gen_Proj_tls(node);
4062 ir_node *new_pred = be_transform_node(pred);
4063 ir_node *block = be_transform_node(get_nodes_block(node));
4064 ir_mode *mode = get_irn_mode(node);
4065 if (mode_needs_gp_reg(mode)) {
4066 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4067 get_Proj_proj(node));
4068 #ifdef DEBUG_libfirm
4069 new_proj->node_nr = node->node_nr;
4075 return be_duplicate_node(node);
4079 * Enters all transform functions into the generic pointer
4081 static void register_transformers(void) {
4082 ir_op *op_Max, *op_Min, *op_Mulh;
4084 /* first clear the generic function pointer for all ops */
4085 clear_irp_opcodes_generic_func();
4087 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4088 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4125 /* transform ops from intrinsic lowering */
4145 /* GEN(ia32_l_vfist); TODO */
4147 GEN(ia32_l_X87toSSE);
4148 GEN(ia32_l_SSEtoX87);
4153 /* we should never see these nodes */
4168 /* handle generic backend nodes */
4179 /* set the register for all Unknown nodes */
4182 op_Max = get_op_Max();
4185 op_Min = get_op_Min();
4188 op_Mulh = get_op_Mulh();
4197 * Pre-transform all unknown and noreg nodes.
4199 static void ia32_pretransform_node(void *arch_cg) {
4200 ia32_code_gen_t *cg = arch_cg;
4202 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4203 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4204 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4205 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4206 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4207 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4210 /* do the transformation */
4211 void ia32_transform_graph(ia32_code_gen_t *cg) {
4212 register_transformers();
4214 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4217 void ia32_init_transform(void)
4219 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");