2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
563 * Construct a standard binary operation, set AM and immediate if required.
565 * @param op1 The first operand
566 * @param op2 The second operand
567 * @param func The node constructor function
568 * @return The constructed ia32 node.
570 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
571 construct_binop_float_func *func)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_node *new_node = NULL;
577 dbg_info *dbgi = get_irn_dbg_info(node);
578 ir_graph *irg = current_ir_graph;
579 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
580 ir_node *nomem = new_NoMem();
581 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
582 &ia32_fp_cw_regs[REG_FPCW]);
584 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
586 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
587 if (is_op_commutative(get_irn_op(node))) {
588 set_ia32_commutative(new_node);
591 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
597 * Construct a shift/rotate binary operation, sets AM and immediate if required.
599 * @param op1 The first operand
600 * @param op2 The second operand
601 * @param func The node constructor function
602 * @return The constructed ia32 node.
604 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
605 construct_binop_func *func)
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *new_op1 = be_transform_node(op1);
610 ir_node *new_op = NULL;
611 dbg_info *dbgi = get_irn_dbg_info(node);
612 ir_graph *irg = current_ir_graph;
613 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
614 ir_node *nomem = new_NoMem();
616 assert(! mode_is_float(get_irn_mode(node))
617 && "Shift/Rotate with float not supported");
619 new_op2 = create_immediate_or_transform(op2, 'N');
621 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
624 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
626 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
628 set_ia32_emit_cl(new_op);
635 * Construct a standard unary operation, set AM and immediate if required.
637 * @param op The operand
638 * @param func The node constructor function
639 * @return The constructed ia32 node.
641 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
643 ir_node *block = be_transform_node(get_nodes_block(node));
644 ir_node *new_op = be_transform_node(op);
645 ir_node *new_node = NULL;
646 ir_graph *irg = current_ir_graph;
647 dbg_info *dbgi = get_irn_dbg_info(node);
648 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
649 ir_node *nomem = new_NoMem();
651 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
652 DB((dbg, LEVEL_1, "INT unop ..."));
653 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
661 * Creates an ia32 Add.
663 * @return the created ia32 Add node
665 static ir_node *gen_Add(ir_node *node) {
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *op1 = get_Add_left(node);
668 ir_node *new_op1 = be_transform_node(op1);
669 ir_node *op2 = get_Add_right(node);
670 ir_node *new_op2 = be_transform_node(op2);
671 ir_node *new_op = NULL;
672 ir_graph *irg = current_ir_graph;
673 dbg_info *dbgi = get_irn_dbg_info(node);
674 ir_mode *mode = get_irn_mode(node);
675 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
676 ir_node *nomem = new_NoMem();
677 ir_node *expr_op, *imm_op;
679 /* Check if immediate optimization is on and */
680 /* if it's an operation with immediate. */
681 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
682 expr_op = get_expr_op(new_op1, new_op2);
684 assert((expr_op || imm_op) && "invalid operands");
686 if (mode_is_float(mode)) {
688 if (USE_SSE2(env_cg))
689 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
691 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
696 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
697 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
699 /* No expr_op means, that we have two const - one symconst and */
700 /* one tarval or another symconst - because this case is not */
701 /* covered by constant folding */
702 /* We need to check for: */
703 /* 1) symconst + const -> becomes a LEA */
704 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
705 /* linker doesn't support two symconsts */
707 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
708 /* this is the 2nd case */
709 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
710 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
711 set_ia32_am_flavour(new_op, ia32_am_B);
712 set_ia32_op_type(new_op, ia32_AddrModeS);
714 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
715 } else if (tp1 == ia32_ImmSymConst) {
716 tarval *tv = get_ia32_Immop_tarval(new_op2);
717 long offs = get_tarval_long(tv);
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
720 add_irn_dep(new_op, get_irg_frame(irg));
721 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
723 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
724 add_ia32_am_offs_int(new_op, offs);
725 set_ia32_am_flavour(new_op, ia32_am_OB);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
727 } else if (tp2 == ia32_ImmSymConst) {
728 tarval *tv = get_ia32_Immop_tarval(new_op1);
729 long offs = get_tarval_long(tv);
731 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
732 add_irn_dep(new_op, get_irg_frame(irg));
733 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
735 add_ia32_am_offs_int(new_op, offs);
736 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
737 set_ia32_am_flavour(new_op, ia32_am_OB);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
741 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
742 tarval *restv = tarval_add(tv1, tv2);
744 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
746 new_op = new_rd_ia32_Const(dbgi, irg, block);
747 set_ia32_Const_tarval(new_op, restv);
748 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
754 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
755 tarval_classification_t class_tv, class_negtv;
756 tarval *tv = get_ia32_Immop_tarval(imm_op);
758 /* optimize tarvals */
759 class_tv = classify_tarval(tv);
760 class_negtv = classify_tarval(tarval_neg(tv));
762 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
763 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
764 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
767 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
768 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
769 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
770 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
776 /* This is a normal add */
777 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
780 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
781 set_ia32_commutative(new_op);
783 fold_immediate(new_op, 2, 3);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
791 * Creates an ia32 Mul.
793 * @return the created ia32 Mul node
795 static ir_node *gen_Mul(ir_node *node) {
796 ir_node *op1 = get_Mul_left(node);
797 ir_node *op2 = get_Mul_right(node);
798 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode)) {
802 if (USE_SSE2(env_cg))
803 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
805 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
809 for the lower 32bit of the result it doesn't matter whether we use
810 signed or unsigned multiplication so we use IMul as it has fewer
813 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
817 * Creates an ia32 Mulh.
818 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
819 * this result while Mul returns the lower 32 bit.
821 * @return the created ia32 Mulh node
823 static ir_node *gen_Mulh(ir_node *node) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *op1 = get_irn_n(node, 0);
826 ir_node *new_op1 = be_transform_node(op1);
827 ir_node *op2 = get_irn_n(node, 1);
828 ir_node *new_op2 = be_transform_node(op2);
829 ir_graph *irg = current_ir_graph;
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
832 ir_mode *mode = get_irn_mode(node);
833 ir_node *proj_EAX, *proj_EDX, *res;
836 assert(!mode_is_float(mode) && "Mulh with float not supported");
837 if (mode_is_signed(mode)) {
838 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
840 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
843 set_ia32_commutative(res);
844 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
846 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
847 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
851 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
859 * Creates an ia32 And.
861 * @return The created ia32 And node
863 static ir_node *gen_And(ir_node *node) {
864 ir_node *op1 = get_And_left(node);
865 ir_node *op2 = get_And_right(node);
867 assert (! mode_is_float(get_irn_mode(node)));
868 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
874 * Creates an ia32 Or.
876 * @return The created ia32 Or node
878 static ir_node *gen_Or(ir_node *node) {
879 ir_node *op1 = get_Or_left(node);
880 ir_node *op2 = get_Or_right(node);
882 assert (! mode_is_float(get_irn_mode(node)));
883 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
889 * Creates an ia32 Eor.
891 * @return The created ia32 Eor node
893 static ir_node *gen_Eor(ir_node *node) {
894 ir_node *op1 = get_Eor_left(node);
895 ir_node *op2 = get_Eor_right(node);
897 assert(! mode_is_float(get_irn_mode(node)));
898 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
904 * Creates an ia32 Max.
906 * @return the created ia32 Max node
908 static ir_node *gen_Max(ir_node *node) {
909 ir_node *block = be_transform_node(get_nodes_block(node));
910 ir_node *op1 = get_irn_n(node, 0);
911 ir_node *new_op1 = be_transform_node(op1);
912 ir_node *op2 = get_irn_n(node, 1);
913 ir_node *new_op2 = be_transform_node(op2);
914 ir_graph *irg = current_ir_graph;
915 ir_mode *mode = get_irn_mode(node);
916 dbg_info *dbgi = get_irn_dbg_info(node);
917 ir_mode *op_mode = get_irn_mode(op1);
920 assert(get_mode_size_bits(mode) == 32);
922 if (mode_is_float(mode)) {
924 if (USE_SSE2(env_cg)) {
925 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
927 panic("Can't create Max node");
930 long pnc = pn_Cmp_Gt;
931 if (! mode_is_signed(op_mode)) {
932 pnc |= ia32_pn_Cmp_Unsigned;
934 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
935 new_op1, new_op2, pnc);
937 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
943 * Creates an ia32 Min.
945 * @return the created ia32 Min node
947 static ir_node *gen_Min(ir_node *node) {
948 ir_node *block = be_transform_node(get_nodes_block(node));
949 ir_node *op1 = get_irn_n(node, 0);
950 ir_node *new_op1 = be_transform_node(op1);
951 ir_node *op2 = get_irn_n(node, 1);
952 ir_node *new_op2 = be_transform_node(op2);
953 ir_graph *irg = current_ir_graph;
954 ir_mode *mode = get_irn_mode(node);
955 dbg_info *dbgi = get_irn_dbg_info(node);
956 ir_mode *op_mode = get_irn_mode(op1);
959 assert(get_mode_size_bits(mode) == 32);
961 if (mode_is_float(mode)) {
963 if (USE_SSE2(env_cg)) {
964 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
966 panic("can't create Min node");
969 long pnc = pn_Cmp_Lt;
970 if (! mode_is_signed(op_mode)) {
971 pnc |= ia32_pn_Cmp_Unsigned;
973 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
974 new_op1, new_op2, pnc);
976 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
983 * Creates an ia32 Sub.
985 * @return The created ia32 Sub node
987 static ir_node *gen_Sub(ir_node *node) {
988 ir_node *block = be_transform_node(get_nodes_block(node));
989 ir_node *op1 = get_Sub_left(node);
990 ir_node *new_op1 = be_transform_node(op1);
991 ir_node *op2 = get_Sub_right(node);
992 ir_node *new_op2 = be_transform_node(op2);
993 ir_node *new_op = NULL;
994 ir_graph *irg = current_ir_graph;
995 dbg_info *dbgi = get_irn_dbg_info(node);
996 ir_mode *mode = get_irn_mode(node);
997 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
998 ir_node *nomem = new_NoMem();
999 ir_node *expr_op, *imm_op;
1001 /* Check if immediate optimization is on and */
1002 /* if it's an operation with immediate. */
1003 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1004 expr_op = get_expr_op(new_op1, new_op2);
1006 assert((expr_op || imm_op) && "invalid operands");
1008 if (mode_is_float(mode)) {
1010 if (USE_SSE2(env_cg))
1011 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1013 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1018 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1019 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1021 /* No expr_op means, that we have two const - one symconst and */
1022 /* one tarval or another symconst - because this case is not */
1023 /* covered by constant folding */
1024 /* We need to check for: */
1025 /* 1) symconst - const -> becomes a LEA */
1026 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1027 /* linker doesn't support two symconsts */
1028 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1029 /* this is the 2nd case */
1030 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1031 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1032 set_ia32_am_sc_sign(new_op);
1033 set_ia32_am_flavour(new_op, ia32_am_B);
1035 DBG_OPT_LEA3(op1, op2, node, new_op);
1036 } else if (tp1 == ia32_ImmSymConst) {
1037 tarval *tv = get_ia32_Immop_tarval(new_op2);
1038 long offs = get_tarval_long(tv);
1040 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1041 add_irn_dep(new_op, get_irg_frame(irg));
1042 DBG_OPT_LEA3(op1, op2, node, new_op);
1044 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1045 add_ia32_am_offs_int(new_op, -offs);
1046 set_ia32_am_flavour(new_op, ia32_am_OB);
1047 set_ia32_op_type(new_op, ia32_AddrModeS);
1048 } else if (tp2 == ia32_ImmSymConst) {
1049 tarval *tv = get_ia32_Immop_tarval(new_op1);
1050 long offs = get_tarval_long(tv);
1052 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1053 add_irn_dep(new_op, get_irg_frame(irg));
1054 DBG_OPT_LEA3(op1, op2, node, new_op);
1056 add_ia32_am_offs_int(new_op, offs);
1057 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1058 set_ia32_am_sc_sign(new_op);
1059 set_ia32_am_flavour(new_op, ia32_am_OB);
1060 set_ia32_op_type(new_op, ia32_AddrModeS);
1062 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1063 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1064 tarval *restv = tarval_sub(tv1, tv2);
1066 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1068 new_op = new_rd_ia32_Const(dbgi, irg, block);
1069 set_ia32_Const_tarval(new_op, restv);
1070 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1073 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1075 } else if (imm_op) {
1076 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1077 tarval_classification_t class_tv, class_negtv;
1078 tarval *tv = get_ia32_Immop_tarval(imm_op);
1080 /* optimize tarvals */
1081 class_tv = classify_tarval(tv);
1082 class_negtv = classify_tarval(tarval_neg(tv));
1084 if (class_tv == TV_CLASSIFY_ONE) {
1085 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1086 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1089 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1090 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1091 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1092 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1098 /* This is a normal sub */
1099 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1101 /* set AM support */
1102 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1104 fold_immediate(new_op, 2, 3);
1106 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1114 * Generates an ia32 DivMod with additional infrastructure for the
1115 * register allocator if needed.
1117 * @param dividend -no comment- :)
1118 * @param divisor -no comment- :)
1119 * @param dm_flav flavour_Div/Mod/DivMod
1120 * @return The created ia32 DivMod node
1122 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1123 ir_node *divisor, ia32_op_flavour_t dm_flav)
1125 ir_node *block = be_transform_node(get_nodes_block(node));
1126 ir_node *new_dividend = be_transform_node(dividend);
1127 ir_node *new_divisor = be_transform_node(divisor);
1128 ir_graph *irg = current_ir_graph;
1129 dbg_info *dbgi = get_irn_dbg_info(node);
1130 ir_mode *mode = get_irn_mode(node);
1131 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1132 ir_node *res, *proj_div, *proj_mod;
1133 ir_node *sign_extension;
1134 ir_node *in_keep[2];
1135 ir_node *mem, *new_mem;
1136 ir_node *projs[pn_DivMod_max];
1139 ia32_collect_Projs(node, projs, pn_DivMod_max);
1141 proj_div = proj_mod = NULL;
1145 mem = get_Div_mem(node);
1146 mode = get_Div_resmode(node);
1147 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1148 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1151 mem = get_Mod_mem(node);
1152 mode = get_Mod_resmode(node);
1153 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1154 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1156 case flavour_DivMod:
1157 mem = get_DivMod_mem(node);
1158 mode = get_DivMod_resmode(node);
1159 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1160 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1161 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1164 panic("invalid divmod flavour!");
1166 new_mem = be_transform_node(mem);
1168 if (mode_is_signed(mode)) {
1169 /* in signed mode, we need to sign extend the dividend */
1170 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1172 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1173 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1175 add_irn_dep(sign_extension, get_irg_frame(irg));
1178 if (mode_is_signed(mode)) {
1179 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1180 sign_extension, new_divisor, new_mem, dm_flav);
1182 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1183 sign_extension, new_divisor, new_mem, dm_flav);
1186 set_ia32_exc_label(res, has_exc);
1187 set_irn_pinned(res, get_irn_pinned(node));
1189 /* Matze: code can't handle this at the moment... */
1191 /* set AM support */
1192 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1195 /* check, which Proj-Keep, we need to add */
1197 if (proj_div == NULL) {
1198 /* We have only mod result: add div res Proj-Keep */
1199 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1202 if (proj_mod == NULL) {
1203 /* We have only div result: add mod res Proj-Keep */
1204 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1208 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1210 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1217 * Wrapper for generate_DivMod. Sets flavour_Mod.
1220 static ir_node *gen_Mod(ir_node *node) {
1221 return generate_DivMod(node, get_Mod_left(node),
1222 get_Mod_right(node), flavour_Mod);
1226 * Wrapper for generate_DivMod. Sets flavour_Div.
1229 static ir_node *gen_Div(ir_node *node) {
1230 return generate_DivMod(node, get_Div_left(node),
1231 get_Div_right(node), flavour_Div);
1235 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1237 static ir_node *gen_DivMod(ir_node *node) {
1238 return generate_DivMod(node, get_DivMod_left(node),
1239 get_DivMod_right(node), flavour_DivMod);
1245 * Creates an ia32 floating Div.
1247 * @return The created ia32 xDiv node
1249 static ir_node *gen_Quot(ir_node *node) {
1250 ir_node *block = be_transform_node(get_nodes_block(node));
1251 ir_node *op1 = get_Quot_left(node);
1252 ir_node *new_op1 = be_transform_node(op1);
1253 ir_node *op2 = get_Quot_right(node);
1254 ir_node *new_op2 = be_transform_node(op2);
1255 ir_graph *irg = current_ir_graph;
1256 dbg_info *dbgi = get_irn_dbg_info(node);
1257 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1258 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1262 if (USE_SSE2(env_cg)) {
1263 ir_mode *mode = get_irn_mode(op1);
1264 if (is_ia32_xConst(new_op2)) {
1265 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1266 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1267 copy_ia32_Immop_attr(new_op, new_op2);
1269 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1270 // Matze: disabled for now, spillslot coalescer fails
1271 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1273 set_ia32_ls_mode(new_op, mode);
1275 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1276 &ia32_fp_cw_regs[REG_FPCW]);
1277 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1278 new_op2, nomem, fpcw);
1279 // Matze: disabled for now (spillslot coalescer fails)
1280 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1282 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1288 * Creates an ia32 Shl.
1290 * @return The created ia32 Shl node
1292 static ir_node *gen_Shl(ir_node *node) {
1293 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1300 * Creates an ia32 Shr.
1302 * @return The created ia32 Shr node
1304 static ir_node *gen_Shr(ir_node *node) {
1305 return gen_shift_binop(node, get_Shr_left(node),
1306 get_Shr_right(node), new_rd_ia32_Shr);
1312 * Creates an ia32 Sar.
1314 * @return The created ia32 Shrs node
1316 static ir_node *gen_Shrs(ir_node *node) {
1317 ir_node *left = get_Shrs_left(node);
1318 ir_node *right = get_Shrs_right(node);
1319 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1320 tarval *tv = get_Const_tarval(right);
1321 long val = get_tarval_long(tv);
1323 /* this is a sign extension */
1324 ir_graph *irg = current_ir_graph;
1325 dbg_info *dbgi = get_irn_dbg_info(node);
1326 ir_node *block = be_transform_node(get_nodes_block(node));
1328 ir_node *new_op = be_transform_node(op);
1330 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1334 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1340 * Creates an ia32 RotL.
1342 * @param op1 The first operator
1343 * @param op2 The second operator
1344 * @return The created ia32 RotL node
1346 static ir_node *gen_RotL(ir_node *node,
1347 ir_node *op1, ir_node *op2) {
1348 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1354 * Creates an ia32 RotR.
1355 * NOTE: There is no RotR with immediate because this would always be a RotL
1356 * "imm-mode_size_bits" which can be pre-calculated.
1358 * @param op1 The first operator
1359 * @param op2 The second operator
1360 * @return The created ia32 RotR node
1362 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1364 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1370 * Creates an ia32 RotR or RotL (depending on the found pattern).
1372 * @return The created ia32 RotL or RotR node
1374 static ir_node *gen_Rot(ir_node *node) {
1375 ir_node *rotate = NULL;
1376 ir_node *op1 = get_Rot_left(node);
1377 ir_node *op2 = get_Rot_right(node);
1379 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1380 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1381 that means we can create a RotR instead of an Add and a RotL */
1383 if (get_irn_op(op2) == op_Add) {
1385 ir_node *left = get_Add_left(add);
1386 ir_node *right = get_Add_right(add);
1387 if (is_Const(right)) {
1388 tarval *tv = get_Const_tarval(right);
1389 ir_mode *mode = get_irn_mode(node);
1390 long bits = get_mode_size_bits(mode);
1392 if (get_irn_op(left) == op_Minus &&
1393 tarval_is_long(tv) &&
1394 get_tarval_long(tv) == bits)
1396 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1397 rotate = gen_RotR(node, op1, get_Minus_op(left));
1402 if (rotate == NULL) {
1403 rotate = gen_RotL(node, op1, op2);
1412 * Transforms a Minus node.
1414 * @param op The Minus operand
1415 * @return The created ia32 Minus node
1417 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1418 ir_node *block = be_transform_node(get_nodes_block(node));
1419 ir_graph *irg = current_ir_graph;
1420 dbg_info *dbgi = get_irn_dbg_info(node);
1421 ir_mode *mode = get_irn_mode(node);
1426 if (mode_is_float(mode)) {
1427 ir_node *new_op = be_transform_node(op);
1429 if (USE_SSE2(env_cg)) {
1430 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1431 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1432 ir_node *nomem = new_rd_NoMem(irg);
1434 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1436 size = get_mode_size_bits(mode);
1437 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1439 set_ia32_am_sc(res, ent);
1440 set_ia32_op_type(res, ia32_AddrModeS);
1441 set_ia32_ls_mode(res, mode);
1443 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1446 res = gen_unop(node, op, new_rd_ia32_Neg);
1449 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1455 * Transforms a Minus node.
1457 * @return The created ia32 Minus node
1459 static ir_node *gen_Minus(ir_node *node) {
1460 return gen_Minus_ex(node, get_Minus_op(node));
1465 * Transforms a Not node.
1467 * @return The created ia32 Not node
1469 static ir_node *gen_Not(ir_node *node) {
1470 ir_node *op = get_Not_op(node);
1472 assert (! mode_is_float(get_irn_mode(node)));
1473 return gen_unop(node, op, new_rd_ia32_Not);
1479 * Transforms an Abs node.
1481 * @return The created ia32 Abs node
1483 static ir_node *gen_Abs(ir_node *node) {
1484 ir_node *block = be_transform_node(get_nodes_block(node));
1485 ir_node *op = get_Abs_op(node);
1486 ir_node *new_op = be_transform_node(op);
1487 ir_graph *irg = current_ir_graph;
1488 dbg_info *dbgi = get_irn_dbg_info(node);
1489 ir_mode *mode = get_irn_mode(node);
1490 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1491 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1492 ir_node *nomem = new_NoMem();
1497 if (mode_is_float(mode)) {
1499 if (USE_SSE2(env_cg)) {
1500 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1502 size = get_mode_size_bits(mode);
1503 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1505 set_ia32_am_sc(res, ent);
1507 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1509 set_ia32_op_type(res, ia32_AddrModeS);
1510 set_ia32_ls_mode(res, mode);
1513 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1514 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1518 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1519 SET_IA32_ORIG_NODE(sign_extension,
1520 ia32_get_old_node_name(env_cg, node));
1522 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1523 sign_extension, nomem);
1524 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1526 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1527 sign_extension, nomem);
1528 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1537 * Transforms a Load.
1539 * @return the created ia32 Load node
1541 static ir_node *gen_Load(ir_node *node) {
1542 ir_node *block = be_transform_node(get_nodes_block(node));
1543 ir_node *ptr = get_Load_ptr(node);
1544 ir_node *new_ptr = be_transform_node(ptr);
1545 ir_node *mem = get_Load_mem(node);
1546 ir_node *new_mem = be_transform_node(mem);
1547 ir_graph *irg = current_ir_graph;
1548 dbg_info *dbgi = get_irn_dbg_info(node);
1549 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1550 ir_mode *mode = get_Load_mode(node);
1552 ir_node *lptr = new_ptr;
1555 ir_node *projs[pn_Load_max];
1556 ia32_am_flavour_t am_flav = ia32_am_B;
1558 ia32_collect_Projs(node, projs, pn_Load_max);
1560 /* address might be a constant (symconst or absolute address) */
1561 if (is_ia32_Const(new_ptr)) {
1566 if (mode_is_float(mode)) {
1568 if (USE_SSE2(env_cg)) {
1569 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1570 res_mode = mode_xmm;
1572 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1573 res_mode = mode_vfp;
1576 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1581 check for special case: the loaded value might not be used
1583 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1584 /* add a result proj and a Keep to produce a pseudo use */
1585 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1587 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1590 /* base is a constant address */
1592 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1593 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1594 am_flav = ia32_am_N;
1596 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1597 long offs = get_tarval_long(tv);
1599 add_ia32_am_offs_int(new_op, offs);
1600 am_flav = ia32_am_O;
1604 set_irn_pinned(new_op, get_irn_pinned(node));
1605 set_ia32_op_type(new_op, ia32_AddrModeS);
1606 set_ia32_am_flavour(new_op, am_flav);
1607 set_ia32_ls_mode(new_op, mode);
1609 /* make sure we are scheduled behind the initial IncSP/Barrier
1610 * to avoid spills being placed before it
1612 if (block == get_irg_start_block(irg)) {
1613 add_irn_dep(new_op, get_irg_frame(irg));
1616 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1617 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1625 * Transforms a Store.
1627 * @return the created ia32 Store node
1629 static ir_node *gen_Store(ir_node *node) {
1630 ir_node *block = be_transform_node(get_nodes_block(node));
1631 ir_node *ptr = get_Store_ptr(node);
1632 ir_node *new_ptr = be_transform_node(ptr);
1633 ir_node *val = get_Store_value(node);
1635 ir_node *mem = get_Store_mem(node);
1636 ir_node *new_mem = be_transform_node(mem);
1637 ir_graph *irg = current_ir_graph;
1638 dbg_info *dbgi = get_irn_dbg_info(node);
1639 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1640 ir_node *sptr = new_ptr;
1641 ir_mode *mode = get_irn_mode(val);
1644 ia32_am_flavour_t am_flav = ia32_am_B;
1646 /* address might be a constant (symconst or absolute address) */
1647 if (is_ia32_Const(new_ptr)) {
1652 if (mode_is_float(mode)) {
1655 new_val = be_transform_node(val);
1656 if (USE_SSE2(env_cg)) {
1657 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1660 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1664 new_val = create_immediate_or_transform(val, 0);
1666 if (get_mode_size_bits(mode) == 8) {
1667 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1670 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1675 /* base is an constant address */
1677 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1678 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1679 am_flav = ia32_am_N;
1681 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1682 long offs = get_tarval_long(tv);
1684 add_ia32_am_offs_int(new_op, offs);
1685 am_flav = ia32_am_O;
1689 set_irn_pinned(new_op, get_irn_pinned(node));
1690 set_ia32_op_type(new_op, ia32_AddrModeD);
1691 set_ia32_am_flavour(new_op, am_flav);
1692 set_ia32_ls_mode(new_op, mode);
1694 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1695 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1700 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1702 ir_node *cmp_a = get_Cmp_left(node);
1704 ir_node *cmp_b = get_Cmp_right(node);
1714 if(!is_Const(cmp_b))
1717 tv = get_Const_tarval(cmp_b);
1718 if(!tarval_is_null(tv))
1722 if(is_And(cmp_a) && (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg)) {
1723 and_left = get_And_left(cmp_a);
1724 and_right = get_And_right(cmp_a);
1726 new_cmp_a = be_transform_node(and_left);
1727 new_cmp_b = create_immediate_or_transform(and_right, 0);
1729 new_cmp_a = be_transform_node(cmp_a);
1730 new_cmp_b = be_transform_node(cmp_a);
1733 dbgi = get_irn_dbg_info(node);
1734 noreg = ia32_new_NoReg_gp(env_cg);
1735 nomem = new_NoMem();
1737 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1738 new_cmp_a, new_cmp_b, nomem, pnc);
1739 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1740 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1745 static ir_node *create_Switch(ir_node *node)
1747 ir_graph *irg = current_ir_graph;
1748 dbg_info *dbgi = get_irn_dbg_info(node);
1749 ir_node *block = be_transform_node(get_nodes_block(node));
1750 ir_node *sel = get_Cond_selector(node);
1751 ir_node *new_sel = be_transform_node(sel);
1753 int switch_min = INT_MAX;
1754 const ir_edge_t *edge;
1756 /* determine the smallest switch case value */
1757 foreach_out_edge(node, edge) {
1758 ir_node *proj = get_edge_src_irn(edge);
1759 int pn = get_Proj_proj(proj);
1764 if (switch_min != 0) {
1765 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1767 /* if smallest switch case is not 0 we need an additional sub */
1768 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1769 add_ia32_am_offs_int(new_sel, -switch_min);
1770 set_ia32_am_flavour(new_sel, ia32_am_OB);
1771 set_ia32_op_type(new_sel, ia32_AddrModeS);
1773 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1776 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1777 set_ia32_pncode(res, get_Cond_defaultProj(node));
1779 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1785 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1787 * @return The transformed node.
1789 static ir_node *gen_Cond(ir_node *node) {
1790 ir_node *block = be_transform_node(get_nodes_block(node));
1791 ir_graph *irg = current_ir_graph;
1792 dbg_info *dbgi = get_irn_dbg_info(node);
1793 ir_node *sel = get_Cond_selector(node);
1794 ir_mode *sel_mode = get_irn_mode(sel);
1795 ir_node *res = NULL;
1796 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1803 ir_node *nomem = new_NoMem();
1806 if (sel_mode != mode_b) {
1807 return create_Switch(node);
1810 cmp = get_Proj_pred(sel);
1811 cmp_a = get_Cmp_left(cmp);
1812 cmp_b = get_Cmp_right(cmp);
1813 cmp_mode = get_irn_mode(cmp_a);
1814 pnc = get_Proj_proj(sel);
1815 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1816 pnc |= ia32_pn_Cmp_Unsigned;
1819 if(mode_needs_gp_reg(cmp_mode)) {
1820 res = try_create_TestJmp(block, cmp, pnc);
1825 new_cmp_a = be_transform_node(cmp_a);
1826 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1828 if (mode_is_float(cmp_mode)) {
1830 if (USE_SSE2(env_cg)) {
1831 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1833 set_ia32_commutative(res);
1834 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1835 set_ia32_ls_mode(res, cmp_mode);
1838 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1839 set_ia32_commutative(res);
1840 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1841 pn_ia32_vfCondJmp_temp_reg_eax);
1842 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1846 assert(get_mode_size_bits(cmp_mode) == 32);
1847 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1848 new_cmp_a, new_cmp_b, nomem, pnc);
1849 set_ia32_commutative(res);
1850 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1853 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1861 * Transforms a CopyB node.
1863 * @return The transformed node.
1865 static ir_node *gen_CopyB(ir_node *node) {
1866 ir_node *block = be_transform_node(get_nodes_block(node));
1867 ir_node *src = get_CopyB_src(node);
1868 ir_node *new_src = be_transform_node(src);
1869 ir_node *dst = get_CopyB_dst(node);
1870 ir_node *new_dst = be_transform_node(dst);
1871 ir_node *mem = get_CopyB_mem(node);
1872 ir_node *new_mem = be_transform_node(mem);
1873 ir_node *res = NULL;
1874 ir_graph *irg = current_ir_graph;
1875 dbg_info *dbgi = get_irn_dbg_info(node);
1876 int size = get_type_size_bytes(get_CopyB_type(node));
1877 ir_mode *dst_mode = get_irn_mode(dst);
1878 ir_mode *src_mode = get_irn_mode(src);
1882 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1883 /* then we need the size explicitly in ECX. */
1884 if (size >= 32 * 4) {
1885 rem = size & 0x3; /* size % 4 */
1888 res = new_rd_ia32_Const(dbgi, irg, block);
1889 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1890 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1892 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1893 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1895 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1896 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1897 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1898 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1899 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1902 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1903 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1905 /* ok: now attach Proj's because movsd will destroy esi and edi */
1906 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1907 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1908 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1911 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1917 ir_node *gen_be_Copy(ir_node *node)
1919 ir_node *result = be_duplicate_node(node);
1920 ir_mode *mode = get_irn_mode(result);
1922 if (mode_needs_gp_reg(mode)) {
1923 set_irn_mode(result, mode_Iu);
1932 * Transforms a Mux node into CMov.
1934 * @return The transformed node.
1936 static ir_node *gen_Mux(ir_node *node) {
1937 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1938 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1940 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1946 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1947 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1948 ir_node *psi_default);
1951 * Transforms a Psi node into CMov.
1953 * @return The transformed node.
1955 static ir_node *gen_Psi(ir_node *node) {
1956 ir_node *block = be_transform_node(get_nodes_block(node));
1957 ir_node *psi_true = get_Psi_val(node, 0);
1958 ir_node *psi_default = get_Psi_default(node);
1959 ia32_code_gen_t *cg = env_cg;
1960 ir_graph *irg = current_ir_graph;
1961 dbg_info *dbgi = get_irn_dbg_info(node);
1962 ir_node *cond = get_Psi_cond(node, 0);
1963 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1964 ir_node *nomem = new_NoMem();
1966 ir_node *cmp, *cmp_a, *cmp_b;
1967 ir_node *new_cmp_a, *new_cmp_b;
1971 assert(get_Psi_n_conds(node) == 1);
1972 assert(get_irn_mode(cond) == mode_b);
1974 if(is_And(cond) || is_Or(cond)) {
1975 ir_node *new_cond = be_transform_node(cond);
1976 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
1977 arch_set_irn_register(env_cg->arch_env, zero,
1978 &ia32_gp_regs[REG_GP_NOREG]);
1980 /* we have to compare the result against zero */
1981 new_cmp_a = new_cond;
1986 cmp = get_Proj_pred(cond);
1987 cmp_a = get_Cmp_left(cmp);
1988 cmp_b = get_Cmp_right(cmp);
1989 cmp_mode = get_irn_mode(cmp_a);
1990 pnc = get_Proj_proj(cond);
1992 new_cmp_a = be_transform_node(cmp_a);
1993 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1995 if (!mode_is_signed(cmp_mode)) {
1996 pnc |= ia32_pn_Cmp_Unsigned;
2000 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2001 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2002 new_cmp_a, new_cmp_b, nomem, pnc);
2003 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2004 pnc = get_negated_pnc(pnc, cmp_mode);
2005 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2006 new_cmp_a, new_cmp_b, nomem, pnc);
2008 ir_node *new_psi_true = be_transform_node(psi_true);
2009 ir_node *new_psi_default = be_transform_node(psi_default);
2010 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2011 new_psi_true, new_psi_default, pnc);
2013 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2019 * Following conversion rules apply:
2023 * 1) n bit -> m bit n > m (downscale)
2025 * 2) n bit -> m bit n == m (sign change)
2027 * 3) n bit -> m bit n < m (upscale)
2028 * a) source is signed: movsx
2029 * b) source is unsigned: and with lower bits sets
2033 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2037 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2041 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2042 * x87 is mode_E internally, conversions happen only at load and store
2043 * in non-strict semantic
2047 * Create a conversion from x87 state register to general purpose.
2049 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2050 ir_node *block = be_transform_node(get_nodes_block(node));
2051 ir_node *op = get_Conv_op(node);
2052 ir_node *new_op = be_transform_node(op);
2053 ia32_code_gen_t *cg = env_cg;
2054 ir_graph *irg = current_ir_graph;
2055 dbg_info *dbgi = get_irn_dbg_info(node);
2056 ir_node *noreg = ia32_new_NoReg_gp(cg);
2057 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2058 ir_node *fist, *load;
2061 fist = new_rd_ia32_vfist(dbgi, irg, block,
2062 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2064 set_irn_pinned(fist, op_pin_state_floats);
2065 set_ia32_use_frame(fist);
2066 set_ia32_op_type(fist, ia32_AddrModeD);
2067 set_ia32_am_flavour(fist, ia32_am_B);
2068 set_ia32_ls_mode(fist, mode_Iu);
2069 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2072 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2074 set_irn_pinned(load, op_pin_state_floats);
2075 set_ia32_use_frame(load);
2076 set_ia32_op_type(load, ia32_AddrModeS);
2077 set_ia32_am_flavour(load, ia32_am_B);
2078 set_ia32_ls_mode(load, mode_Iu);
2079 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2081 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2085 * Create a conversion from general purpose to x87 register
2087 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2088 ir_node *block = be_transform_node(get_nodes_block(node));
2089 ir_node *op = get_Conv_op(node);
2090 ir_node *new_op = be_transform_node(op);
2091 ir_graph *irg = current_ir_graph;
2092 dbg_info *dbgi = get_irn_dbg_info(node);
2093 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2094 ir_node *nomem = new_NoMem();
2095 ir_node *fild, *store;
2098 /* first convert to 32 bit if necessary */
2099 src_bits = get_mode_size_bits(src_mode);
2100 if (src_bits == 8) {
2101 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2102 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2103 set_ia32_ls_mode(new_op, src_mode);
2104 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2105 } else if (src_bits < 32) {
2106 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2107 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2108 set_ia32_ls_mode(new_op, src_mode);
2109 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2113 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2115 set_ia32_use_frame(store);
2116 set_ia32_op_type(store, ia32_AddrModeD);
2117 set_ia32_am_flavour(store, ia32_am_OB);
2118 set_ia32_ls_mode(store, mode_Iu);
2121 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2123 set_ia32_use_frame(fild);
2124 set_ia32_op_type(fild, ia32_AddrModeS);
2125 set_ia32_am_flavour(fild, ia32_am_OB);
2126 set_ia32_ls_mode(fild, mode_Iu);
2128 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2131 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2134 ir_node *block = get_nodes_block(node);
2135 ir_graph *irg = current_ir_graph;
2136 dbg_info *dbgi = get_irn_dbg_info(node);
2137 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2138 ir_node *nomem = new_NoMem();
2139 int src_bits = get_mode_size_bits(src_mode);
2140 int tgt_bits = get_mode_size_bits(tgt_mode);
2141 ir_node *frame = get_irg_frame(irg);
2142 ir_mode *smaller_mode;
2143 ir_node *store, *load;
2146 if(src_bits <= tgt_bits)
2147 smaller_mode = src_mode;
2149 smaller_mode = tgt_mode;
2151 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2153 set_ia32_use_frame(store);
2154 set_ia32_op_type(store, ia32_AddrModeD);
2155 set_ia32_am_flavour(store, ia32_am_OB);
2157 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2159 set_ia32_use_frame(load);
2160 set_ia32_op_type(load, ia32_AddrModeS);
2161 set_ia32_am_flavour(load, ia32_am_OB);
2163 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2168 * Transforms a Conv node.
2170 * @return The created ia32 Conv node
2172 static ir_node *gen_Conv(ir_node *node) {
2173 ir_node *block = be_transform_node(get_nodes_block(node));
2174 ir_node *op = get_Conv_op(node);
2175 ir_node *new_op = be_transform_node(op);
2176 ir_graph *irg = current_ir_graph;
2177 dbg_info *dbgi = get_irn_dbg_info(node);
2178 ir_mode *src_mode = get_irn_mode(op);
2179 ir_mode *tgt_mode = get_irn_mode(node);
2180 int src_bits = get_mode_size_bits(src_mode);
2181 int tgt_bits = get_mode_size_bits(tgt_mode);
2182 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2183 ir_node *nomem = new_rd_NoMem(irg);
2186 if (src_mode == tgt_mode) {
2187 if (get_Conv_strict(node)) {
2188 if (USE_SSE2(env_cg)) {
2189 /* when we are in SSE mode, we can kill all strict no-op conversion */
2193 /* this should be optimized already, but who knows... */
2194 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2195 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2200 if (mode_is_float(src_mode)) {
2201 /* we convert from float ... */
2202 if (mode_is_float(tgt_mode)) {
2203 if(src_mode == mode_E && tgt_mode == mode_D
2204 && !get_Conv_strict(node)) {
2205 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2210 if (USE_SSE2(env_cg)) {
2211 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2212 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2213 set_ia32_ls_mode(res, tgt_mode);
2215 // Matze: TODO what about strict convs?
2216 if(get_Conv_strict(node)) {
2217 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2218 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2221 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2226 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2227 if (USE_SSE2(env_cg)) {
2228 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2229 set_ia32_ls_mode(res, src_mode);
2231 return gen_x87_fp_to_gp(node);
2235 /* we convert from int ... */
2236 if (mode_is_float(tgt_mode)) {
2239 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2240 if (USE_SSE2(env_cg)) {
2241 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2242 set_ia32_ls_mode(res, tgt_mode);
2243 if(src_bits == 32) {
2244 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2247 return gen_x87_gp_to_fp(node, src_mode);
2251 ir_mode *smaller_mode;
2254 if (src_bits == tgt_bits) {
2255 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2259 if (src_bits < tgt_bits) {
2260 smaller_mode = src_mode;
2261 smaller_bits = src_bits;
2263 smaller_mode = tgt_mode;
2264 smaller_bits = tgt_bits;
2267 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2268 if (smaller_bits == 8) {
2269 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2270 set_ia32_ls_mode(res, smaller_mode);
2272 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2273 set_ia32_ls_mode(res, smaller_mode);
2275 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2279 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2285 int check_immediate_constraint(long val, char immediate_constraint_type)
2287 switch (immediate_constraint_type) {
2291 return val >= 0 && val <= 32;
2293 return val >= 0 && val <= 63;
2295 return val >= -128 && val <= 127;
2297 return val == 0xff || val == 0xffff;
2299 return val >= 0 && val <= 3;
2301 return val >= 0 && val <= 255;
2303 return val >= 0 && val <= 127;
2307 panic("Invalid immediate constraint found");
2312 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2315 tarval *offset = NULL;
2316 int offset_sign = 0;
2318 ir_entity *symconst_ent = NULL;
2319 int symconst_sign = 0;
2321 ir_node *cnst = NULL;
2322 ir_node *symconst = NULL;
2328 mode = get_irn_mode(node);
2329 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2330 !mode_is_reference(mode)) {
2334 if(is_Minus(node)) {
2336 node = get_Minus_op(node);
2339 if(is_Const(node)) {
2342 offset_sign = minus;
2343 } else if(is_SymConst(node)) {
2346 symconst_sign = minus;
2347 } else if(is_Add(node)) {
2348 ir_node *left = get_Add_left(node);
2349 ir_node *right = get_Add_right(node);
2350 if(is_Const(left) && is_SymConst(right)) {
2353 symconst_sign = minus;
2354 offset_sign = minus;
2355 } else if(is_SymConst(left) && is_Const(right)) {
2358 symconst_sign = minus;
2359 offset_sign = minus;
2361 } else if(is_Sub(node)) {
2362 ir_node *left = get_Sub_left(node);
2363 ir_node *right = get_Sub_right(node);
2364 if(is_Const(left) && is_SymConst(right)) {
2367 symconst_sign = !minus;
2368 offset_sign = minus;
2369 } else if(is_SymConst(left) && is_Const(right)) {
2372 symconst_sign = minus;
2373 offset_sign = !minus;
2380 offset = get_Const_tarval(cnst);
2381 if(tarval_is_long(offset)) {
2382 val = get_tarval_long(offset);
2383 } else if(tarval_is_null(offset)) {
2386 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2391 if(!check_immediate_constraint(val, immediate_constraint_type))
2394 if(symconst != NULL) {
2395 if(immediate_constraint_type != 0) {
2396 /* we need full 32bits for symconsts */
2400 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2402 symconst_ent = get_SymConst_entity(symconst);
2404 if(cnst == NULL && symconst == NULL)
2407 if(offset_sign && offset != NULL) {
2408 offset = tarval_neg(offset);
2411 irg = current_ir_graph;
2412 dbgi = get_irn_dbg_info(node);
2413 block = get_irg_start_block(irg);
2414 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2416 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2418 /* make sure we don't schedule stuff before the barrier */
2419 add_irn_dep(res, get_irg_frame(irg));
2425 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2427 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2428 if (new_node == NULL) {
2429 new_node = be_transform_node(node);
2434 typedef struct constraint_t constraint_t;
2435 struct constraint_t {
2438 const arch_register_req_t **out_reqs;
2440 const arch_register_req_t *req;
2441 unsigned immediate_possible;
2442 char immediate_type;
2445 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2447 int immediate_possible = 0;
2448 char immediate_type = 0;
2449 unsigned limited = 0;
2450 const arch_register_class_t *cls = NULL;
2452 struct obstack *obst;
2453 arch_register_req_t *req;
2454 unsigned *limited_ptr;
2458 /* TODO: replace all the asserts with nice error messages */
2460 printf("Constraint: %s\n", c);
2470 assert(cls == NULL ||
2471 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2472 cls = &ia32_reg_classes[CLASS_ia32_gp];
2473 limited |= 1 << REG_EAX;
2476 assert(cls == NULL ||
2477 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2478 cls = &ia32_reg_classes[CLASS_ia32_gp];
2479 limited |= 1 << REG_EBX;
2482 assert(cls == NULL ||
2483 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2484 cls = &ia32_reg_classes[CLASS_ia32_gp];
2485 limited |= 1 << REG_ECX;
2488 assert(cls == NULL ||
2489 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2490 cls = &ia32_reg_classes[CLASS_ia32_gp];
2491 limited |= 1 << REG_EDX;
2494 assert(cls == NULL ||
2495 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2496 cls = &ia32_reg_classes[CLASS_ia32_gp];
2497 limited |= 1 << REG_EDI;
2500 assert(cls == NULL ||
2501 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2502 cls = &ia32_reg_classes[CLASS_ia32_gp];
2503 limited |= 1 << REG_ESI;
2506 case 'q': /* q means lower part of the regs only, this makes no
2507 * difference to Q for us (we only assigne whole registers) */
2508 assert(cls == NULL ||
2509 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2510 cls = &ia32_reg_classes[CLASS_ia32_gp];
2511 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2515 assert(cls == NULL ||
2516 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2517 cls = &ia32_reg_classes[CLASS_ia32_gp];
2518 limited |= 1 << REG_EAX | 1 << REG_EDX;
2521 assert(cls == NULL ||
2522 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2523 cls = &ia32_reg_classes[CLASS_ia32_gp];
2524 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2525 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2532 assert(cls == NULL);
2533 cls = &ia32_reg_classes[CLASS_ia32_gp];
2539 /* TODO: mark values so the x87 simulator knows about t and u */
2540 assert(cls == NULL);
2541 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2546 assert(cls == NULL);
2547 /* TODO: check that sse2 is supported */
2548 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2558 assert(!immediate_possible);
2559 immediate_possible = 1;
2560 immediate_type = *c;
2564 assert(!immediate_possible);
2565 immediate_possible = 1;
2569 assert(!immediate_possible && cls == NULL);
2570 immediate_possible = 1;
2571 cls = &ia32_reg_classes[CLASS_ia32_gp];
2584 assert(constraint->is_in && "can only specify same constraint "
2587 sscanf(c, "%d%n", &same_as, &p);
2594 case 'E': /* no float consts yet */
2595 case 'F': /* no float consts yet */
2596 case 's': /* makes no sense on x86 */
2597 case 'X': /* we can't support that in firm */
2601 case '<': /* no autodecrement on x86 */
2602 case '>': /* no autoincrement on x86 */
2603 case 'C': /* sse constant not supported yet */
2604 case 'G': /* 80387 constant not supported yet */
2605 case 'y': /* we don't support mmx registers yet */
2606 case 'Z': /* not available in 32 bit mode */
2607 case 'e': /* not available in 32 bit mode */
2608 assert(0 && "asm constraint not supported");
2611 assert(0 && "unknown asm constraint found");
2618 const arch_register_req_t *other_constr;
2620 assert(cls == NULL && "same as and register constraint not supported");
2621 assert(!immediate_possible && "same as and immediate constraint not "
2623 assert(same_as < constraint->n_outs && "wrong constraint number in "
2624 "same_as constraint");
2626 other_constr = constraint->out_reqs[same_as];
2628 req = obstack_alloc(obst, sizeof(req[0]));
2629 req->cls = other_constr->cls;
2630 req->type = arch_register_req_type_should_be_same;
2631 req->limited = NULL;
2632 req->other_same = pos;
2633 req->other_different = -1;
2635 /* switch constraints. This is because in firm we have same_as
2636 * constraints on the output constraints while in the gcc asm syntax
2637 * they are specified on the input constraints */
2638 constraint->req = other_constr;
2639 constraint->out_reqs[same_as] = req;
2640 constraint->immediate_possible = 0;
2644 if(immediate_possible && cls == NULL) {
2645 cls = &ia32_reg_classes[CLASS_ia32_gp];
2647 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2648 assert(cls != NULL);
2650 if(immediate_possible) {
2651 assert(constraint->is_in
2652 && "imeediates make no sense for output constraints");
2654 /* todo: check types (no float input on 'r' constrainted in and such... */
2656 irg = current_ir_graph;
2657 obst = get_irg_obstack(irg);
2660 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2661 limited_ptr = (unsigned*) (req+1);
2663 req = obstack_alloc(obst, sizeof(req[0]));
2665 memset(req, 0, sizeof(req[0]));
2668 req->type = arch_register_req_type_limited;
2669 *limited_ptr = limited;
2670 req->limited = limited_ptr;
2672 req->type = arch_register_req_type_normal;
2676 constraint->req = req;
2677 constraint->immediate_possible = immediate_possible;
2678 constraint->immediate_type = immediate_type;
2682 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2689 panic("Clobbers not supported yet");
2692 ir_node *gen_ASM(ir_node *node)
2695 ir_graph *irg = current_ir_graph;
2696 ir_node *block = be_transform_node(get_nodes_block(node));
2697 dbg_info *dbgi = get_irn_dbg_info(node);
2704 ia32_asm_attr_t *attr;
2705 const arch_register_req_t **out_reqs;
2706 const arch_register_req_t **in_reqs;
2707 struct obstack *obst;
2708 constraint_t parsed_constraint;
2710 /* assembler could contain float statements */
2713 /* transform inputs */
2714 arity = get_irn_arity(node);
2715 in = alloca(arity * sizeof(in[0]));
2716 memset(in, 0, arity * sizeof(in[0]));
2718 n_outs = get_ASM_n_output_constraints(node);
2719 n_clobbers = get_ASM_n_clobbers(node);
2720 out_arity = n_outs + n_clobbers;
2722 /* construct register constraints */
2723 obst = get_irg_obstack(irg);
2724 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2725 parsed_constraint.out_reqs = out_reqs;
2726 parsed_constraint.n_outs = n_outs;
2727 parsed_constraint.is_in = 0;
2728 for(i = 0; i < out_arity; ++i) {
2732 const ir_asm_constraint *constraint;
2733 constraint = & get_ASM_output_constraints(node) [i];
2734 c = get_id_str(constraint->constraint);
2735 parse_asm_constraint(i, &parsed_constraint, c);
2737 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2738 c = get_id_str(glob_id);
2739 parse_clobber(node, i, &parsed_constraint, c);
2741 out_reqs[i] = parsed_constraint.req;
2744 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2745 parsed_constraint.is_in = 1;
2746 for(i = 0; i < arity; ++i) {
2747 const ir_asm_constraint *constraint;
2751 constraint = & get_ASM_input_constraints(node) [i];
2752 constr_id = constraint->constraint;
2753 c = get_id_str(constr_id);
2754 parse_asm_constraint(i, &parsed_constraint, c);
2755 in_reqs[i] = parsed_constraint.req;
2757 if(parsed_constraint.immediate_possible) {
2758 ir_node *pred = get_irn_n(node, i);
2759 char imm_type = parsed_constraint.immediate_type;
2760 ir_node *immediate = try_create_Immediate(pred, imm_type);
2762 if(immediate != NULL) {
2768 /* transform inputs */
2769 for(i = 0; i < arity; ++i) {
2771 ir_node *transformed;
2776 pred = get_irn_n(node, i);
2777 transformed = be_transform_node(pred);
2778 in[i] = transformed;
2781 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2783 generic_attr = get_irn_generic_attr(res);
2784 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2785 attr->asm_text = get_ASM_text(node);
2786 set_ia32_out_req_all(res, out_reqs);
2787 set_ia32_in_req_all(res, in_reqs);
2789 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2794 /********************************************
2797 * | |__ ___ _ __ ___ __| | ___ ___
2798 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2799 * | |_) | __/ | | | (_) | (_| | __/\__ \
2800 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2802 ********************************************/
2804 static ir_node *gen_be_StackParam(ir_node *node) {
2805 ir_node *block = be_transform_node(get_nodes_block(node));
2806 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2807 ir_node *new_ptr = be_transform_node(ptr);
2808 ir_node *new_op = NULL;
2809 ir_graph *irg = current_ir_graph;
2810 dbg_info *dbgi = get_irn_dbg_info(node);
2811 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2812 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2813 ir_mode *load_mode = get_irn_mode(node);
2814 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2818 if (mode_is_float(load_mode)) {
2820 if (USE_SSE2(env_cg)) {
2821 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2822 pn_res = pn_ia32_xLoad_res;
2823 proj_mode = mode_xmm;
2825 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2826 pn_res = pn_ia32_vfld_res;
2827 proj_mode = mode_vfp;
2830 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2831 proj_mode = mode_Iu;
2832 pn_res = pn_ia32_Load_res;
2835 set_irn_pinned(new_op, op_pin_state_floats);
2836 set_ia32_frame_ent(new_op, ent);
2837 set_ia32_use_frame(new_op);
2839 set_ia32_op_type(new_op, ia32_AddrModeS);
2840 set_ia32_am_flavour(new_op, ia32_am_B);
2841 set_ia32_ls_mode(new_op, load_mode);
2842 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2844 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2846 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2850 * Transforms a FrameAddr into an ia32 Add.
2852 static ir_node *gen_be_FrameAddr(ir_node *node) {
2853 ir_node *block = be_transform_node(get_nodes_block(node));
2854 ir_node *op = be_get_FrameAddr_frame(node);
2855 ir_node *new_op = be_transform_node(op);
2856 ir_graph *irg = current_ir_graph;
2857 dbg_info *dbgi = get_irn_dbg_info(node);
2858 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2861 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2862 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2863 set_ia32_use_frame(res);
2864 set_ia32_am_flavour(res, ia32_am_OB);
2866 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2872 * Transforms a FrameLoad into an ia32 Load.
2874 static ir_node *gen_be_FrameLoad(ir_node *node) {
2875 ir_node *block = be_transform_node(get_nodes_block(node));
2876 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2877 ir_node *new_mem = be_transform_node(mem);
2878 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2879 ir_node *new_ptr = be_transform_node(ptr);
2880 ir_node *new_op = NULL;
2881 ir_graph *irg = current_ir_graph;
2882 dbg_info *dbgi = get_irn_dbg_info(node);
2883 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2884 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2885 ir_mode *mode = get_type_mode(get_entity_type(ent));
2886 ir_node *projs[pn_Load_max];
2888 ia32_collect_Projs(node, projs, pn_Load_max);
2890 if (mode_is_float(mode)) {
2892 if (USE_SSE2(env_cg)) {
2893 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2896 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2900 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2903 set_irn_pinned(new_op, op_pin_state_floats);
2904 set_ia32_frame_ent(new_op, ent);
2905 set_ia32_use_frame(new_op);
2907 set_ia32_op_type(new_op, ia32_AddrModeS);
2908 set_ia32_am_flavour(new_op, ia32_am_B);
2909 set_ia32_ls_mode(new_op, mode);
2910 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2919 * Transforms a FrameStore into an ia32 Store.
2921 static ir_node *gen_be_FrameStore(ir_node *node) {
2922 ir_node *block = be_transform_node(get_nodes_block(node));
2923 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2924 ir_node *new_mem = be_transform_node(mem);
2925 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2926 ir_node *new_ptr = be_transform_node(ptr);
2927 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2928 ir_node *new_val = be_transform_node(val);
2929 ir_node *new_op = NULL;
2930 ir_graph *irg = current_ir_graph;
2931 dbg_info *dbgi = get_irn_dbg_info(node);
2932 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2933 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2934 ir_mode *mode = get_irn_mode(val);
2936 if (mode_is_float(mode)) {
2938 if (USE_SSE2(env_cg)) {
2939 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2941 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2943 } else if (get_mode_size_bits(mode) == 8) {
2944 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2946 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2949 set_ia32_frame_ent(new_op, ent);
2950 set_ia32_use_frame(new_op);
2952 set_ia32_op_type(new_op, ia32_AddrModeD);
2953 set_ia32_am_flavour(new_op, ia32_am_B);
2954 set_ia32_ls_mode(new_op, mode);
2956 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2962 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2964 static ir_node *gen_be_Return(ir_node *node) {
2965 ir_graph *irg = current_ir_graph;
2966 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2967 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2968 ir_entity *ent = get_irg_entity(irg);
2969 ir_type *tp = get_entity_type(ent);
2974 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2975 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2978 int pn_ret_val, pn_ret_mem, arity, i;
2980 assert(ret_val != NULL);
2981 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2982 return be_duplicate_node(node);
2985 res_type = get_method_res_type(tp, 0);
2987 if (! is_Primitive_type(res_type)) {
2988 return be_duplicate_node(node);
2991 mode = get_type_mode(res_type);
2992 if (! mode_is_float(mode)) {
2993 return be_duplicate_node(node);
2996 assert(get_method_n_ress(tp) == 1);
2998 pn_ret_val = get_Proj_proj(ret_val);
2999 pn_ret_mem = get_Proj_proj(ret_mem);
3001 /* get the Barrier */
3002 barrier = get_Proj_pred(ret_val);
3004 /* get result input of the Barrier */
3005 ret_val = get_irn_n(barrier, pn_ret_val);
3006 new_ret_val = be_transform_node(ret_val);
3008 /* get memory input of the Barrier */
3009 ret_mem = get_irn_n(barrier, pn_ret_mem);
3010 new_ret_mem = be_transform_node(ret_mem);
3012 frame = get_irg_frame(irg);
3014 dbgi = get_irn_dbg_info(barrier);
3015 block = be_transform_node(get_nodes_block(barrier));
3017 noreg = ia32_new_NoReg_gp(env_cg);
3019 /* store xmm0 onto stack */
3020 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3021 set_ia32_ls_mode(sse_store, mode);
3022 set_ia32_op_type(sse_store, ia32_AddrModeD);
3023 set_ia32_use_frame(sse_store);
3024 set_ia32_am_flavour(sse_store, ia32_am_B);
3027 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3028 set_ia32_ls_mode(fld, mode);
3029 set_ia32_op_type(fld, ia32_AddrModeS);
3030 set_ia32_use_frame(fld);
3031 set_ia32_am_flavour(fld, ia32_am_B);
3033 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3034 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3035 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3037 /* create a new barrier */
3038 arity = get_irn_arity(barrier);
3039 in = alloca(arity * sizeof(in[0]));
3040 for (i = 0; i < arity; ++i) {
3043 if (i == pn_ret_val) {
3045 } else if (i == pn_ret_mem) {
3048 ir_node *in = get_irn_n(barrier, i);
3049 new_in = be_transform_node(in);
3054 new_barrier = new_ir_node(dbgi, irg, block,
3055 get_irn_op(barrier), get_irn_mode(barrier),
3057 copy_node_attr(barrier, new_barrier);
3058 be_duplicate_deps(barrier, new_barrier);
3059 be_set_transformed_node(barrier, new_barrier);
3060 mark_irn_visited(barrier);
3062 /* transform normally */
3063 return be_duplicate_node(node);
3067 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3069 static ir_node *gen_be_AddSP(ir_node *node) {
3070 ir_node *block = be_transform_node(get_nodes_block(node));
3071 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3073 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3074 ir_node *new_sp = be_transform_node(sp);
3075 ir_graph *irg = current_ir_graph;
3076 dbg_info *dbgi = get_irn_dbg_info(node);
3077 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3078 ir_node *nomem = new_NoMem();
3081 new_sz = create_immediate_or_transform(sz, 0);
3083 /* ia32 stack grows in reverse direction, make a SubSP */
3084 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3086 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3093 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3095 static ir_node *gen_be_SubSP(ir_node *node) {
3096 ir_node *block = be_transform_node(get_nodes_block(node));
3097 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3099 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3100 ir_node *new_sp = be_transform_node(sp);
3101 ir_graph *irg = current_ir_graph;
3102 dbg_info *dbgi = get_irn_dbg_info(node);
3103 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3104 ir_node *nomem = new_NoMem();
3107 new_sz = create_immediate_or_transform(sz, 0);
3109 /* ia32 stack grows in reverse direction, make an AddSP */
3110 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3111 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3112 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3118 * This function just sets the register for the Unknown node
3119 * as this is not done during register allocation because Unknown
3120 * is an "ignore" node.
3122 static ir_node *gen_Unknown(ir_node *node) {
3123 ir_mode *mode = get_irn_mode(node);
3125 if (mode_is_float(mode)) {
3126 if (USE_SSE2(env_cg))
3127 return ia32_new_Unknown_xmm(env_cg);
3129 return ia32_new_Unknown_vfp(env_cg);
3130 } else if (mode_needs_gp_reg(mode)) {
3131 return ia32_new_Unknown_gp(env_cg);
3133 assert(0 && "unsupported Unknown-Mode");
3140 * Change some phi modes
3142 static ir_node *gen_Phi(ir_node *node) {
3143 ir_node *block = be_transform_node(get_nodes_block(node));
3144 ir_graph *irg = current_ir_graph;
3145 dbg_info *dbgi = get_irn_dbg_info(node);
3146 ir_mode *mode = get_irn_mode(node);
3149 if(mode_needs_gp_reg(mode)) {
3150 /* we shouldn't have any 64bit stuff around anymore */
3151 assert(get_mode_size_bits(mode) <= 32);
3152 /* all integer operations are on 32bit registers now */
3154 } else if(mode_is_float(mode)) {
3155 if (USE_SSE2(env_cg)) {
3162 /* phi nodes allow loops, so we use the old arguments for now
3163 * and fix this later */
3164 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3165 copy_node_attr(node, phi);
3166 be_duplicate_deps(node, phi);
3168 be_set_transformed_node(node, phi);
3169 be_enqueue_preds(node);
3174 /**********************************************************************
3177 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3178 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3179 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3180 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3182 **********************************************************************/
3184 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3186 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3189 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3190 ir_node *val, ir_node *mem);
3193 * Transforms a lowered Load into a "real" one.
3195 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3196 ir_node *block = be_transform_node(get_nodes_block(node));
3197 ir_node *ptr = get_irn_n(node, 0);
3198 ir_node *new_ptr = be_transform_node(ptr);
3199 ir_node *mem = get_irn_n(node, 1);
3200 ir_node *new_mem = be_transform_node(mem);
3201 ir_graph *irg = current_ir_graph;
3202 dbg_info *dbgi = get_irn_dbg_info(node);
3203 ir_mode *mode = get_ia32_ls_mode(node);
3204 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3208 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3209 lowering we have x87 nodes, so we need to enforce simulation.
3211 if (mode_is_float(mode)) {
3213 if (fp_unit == fp_x87)
3217 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3219 set_ia32_op_type(new_op, ia32_AddrModeS);
3220 set_ia32_am_flavour(new_op, ia32_am_OB);
3221 set_ia32_am_offs_int(new_op, 0);
3222 set_ia32_am_scale(new_op, 1);
3223 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3224 if (is_ia32_am_sc_sign(node))
3225 set_ia32_am_sc_sign(new_op);
3226 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3227 if (is_ia32_use_frame(node)) {
3228 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3229 set_ia32_use_frame(new_op);
3232 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3238 * Transforms a lowered Store into a "real" one.
3240 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3241 ir_node *block = be_transform_node(get_nodes_block(node));
3242 ir_node *ptr = get_irn_n(node, 0);
3243 ir_node *new_ptr = be_transform_node(ptr);
3244 ir_node *val = get_irn_n(node, 1);
3245 ir_node *new_val = be_transform_node(val);
3246 ir_node *mem = get_irn_n(node, 2);
3247 ir_node *new_mem = be_transform_node(mem);
3248 ir_graph *irg = current_ir_graph;
3249 dbg_info *dbgi = get_irn_dbg_info(node);
3250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3251 ir_mode *mode = get_ia32_ls_mode(node);
3254 ia32_am_flavour_t am_flav = ia32_B;
3257 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3258 lowering we have x87 nodes, so we need to enforce simulation.
3260 if (mode_is_float(mode)) {
3262 if (fp_unit == fp_x87)
3266 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3268 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3270 add_ia32_am_offs_int(new_op, am_offs);
3273 set_ia32_op_type(new_op, ia32_AddrModeD);
3274 set_ia32_am_flavour(new_op, am_flav);
3275 set_ia32_ls_mode(new_op, mode);
3276 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3277 set_ia32_use_frame(new_op);
3279 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3286 * Transforms an ia32_l_XXX into a "real" XXX node
3288 * @param env The transformation environment
3289 * @return the created ia32 XXX node
3291 #define GEN_LOWERED_OP(op) \
3292 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3293 ir_mode *mode = get_irn_mode(node); \
3294 if (mode_is_float(mode)) \
3296 return gen_binop(node, get_binop_left(node), \
3297 get_binop_right(node), new_rd_ia32_##op,0); \
3300 #define GEN_LOWERED_x87_OP(op) \
3301 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3303 FORCE_x87(env_cg); \
3304 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3305 get_binop_right(node), new_rd_ia32_##op); \
3309 #define GEN_LOWERED_UNOP(op) \
3310 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3311 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3314 #define GEN_LOWERED_SHIFT_OP(op) \
3315 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3316 return gen_shift_binop(node, get_binop_left(node), \
3317 get_binop_right(node), new_rd_ia32_##op); \
3320 #define GEN_LOWERED_LOAD(op, fp_unit) \
3321 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3322 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3325 #define GEN_LOWERED_STORE(op, fp_unit) \
3326 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3327 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3334 GEN_LOWERED_OP(IMul)
3336 GEN_LOWERED_x87_OP(vfprem)
3337 GEN_LOWERED_x87_OP(vfmul)
3338 GEN_LOWERED_x87_OP(vfsub)
3340 GEN_LOWERED_UNOP(Neg)
3342 GEN_LOWERED_LOAD(vfild, fp_x87)
3343 GEN_LOWERED_LOAD(Load, fp_none)
3344 /*GEN_LOWERED_STORE(vfist, fp_x87)
3347 GEN_LOWERED_STORE(Store, fp_none)
3349 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3350 ir_node *block = be_transform_node(get_nodes_block(node));
3351 ir_node *left = get_binop_left(node);
3352 ir_node *new_left = be_transform_node(left);
3353 ir_node *right = get_binop_right(node);
3354 ir_node *new_right = be_transform_node(right);
3355 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3356 ir_graph *irg = current_ir_graph;
3357 dbg_info *dbgi = get_irn_dbg_info(node);
3358 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3359 &ia32_fp_cw_regs[REG_FPCW]);
3362 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3363 new_right, new_NoMem(), fpcw);
3364 clear_ia32_commutative(vfdiv);
3365 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3367 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3375 * Transforms a l_MulS into a "real" MulS node.
3377 * @param env The transformation environment
3378 * @return the created ia32 Mul node
3380 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3381 ir_node *block = be_transform_node(get_nodes_block(node));
3382 ir_node *left = get_binop_left(node);
3383 ir_node *new_left = be_transform_node(left);
3384 ir_node *right = get_binop_right(node);
3385 ir_node *new_right = be_transform_node(right);
3386 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3387 ir_graph *irg = current_ir_graph;
3388 dbg_info *dbgi = get_irn_dbg_info(node);
3391 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3392 /* and then skip the result Proj, because all needed Projs are already there. */
3393 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3394 new_right, new_NoMem());
3395 clear_ia32_commutative(muls);
3396 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3398 /* check if EAX and EDX proj exist, add missing one */
3399 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3400 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3401 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3403 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3408 GEN_LOWERED_SHIFT_OP(Shl)
3409 GEN_LOWERED_SHIFT_OP(Shr)
3410 GEN_LOWERED_SHIFT_OP(Sar)
3413 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3414 * op1 - target to be shifted
3415 * op2 - contains bits to be shifted into target
3417 * Only op3 can be an immediate.
3419 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3420 ir_node *op2, ir_node *count)
3422 ir_node *block = be_transform_node(get_nodes_block(node));
3423 ir_node *new_op1 = be_transform_node(op1);
3424 ir_node *new_op2 = be_transform_node(op2);
3425 ir_node *new_count = be_transform_node(count);
3426 ir_node *new_op = NULL;
3427 ir_graph *irg = current_ir_graph;
3428 dbg_info *dbgi = get_irn_dbg_info(node);
3429 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3430 ir_node *nomem = new_NoMem();
3434 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3436 /* Check if immediate optimization is on and */
3437 /* if it's an operation with immediate. */
3438 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3440 /* Limit imm_op within range imm8 */
3442 tv = get_ia32_Immop_tarval(imm_op);
3445 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3446 set_ia32_Immop_tarval(imm_op, tv);
3453 /* integer operations */
3455 /* This is ShiftD with const */
3456 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3458 if (is_ia32_l_ShlD(node))
3459 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3460 new_op1, new_op2, noreg, nomem);
3462 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3463 new_op1, new_op2, noreg, nomem);
3464 copy_ia32_Immop_attr(new_op, imm_op);
3467 /* This is a normal ShiftD */
3468 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3469 if (is_ia32_l_ShlD(node))
3470 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3471 new_op1, new_op2, new_count, nomem);
3473 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3474 new_op1, new_op2, new_count, nomem);
3477 /* set AM support */
3478 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3480 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3482 set_ia32_emit_cl(new_op);
3487 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3488 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3489 get_irn_n(node, 1), get_irn_n(node, 2));
3492 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3493 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3494 get_irn_n(node, 1), get_irn_n(node, 2));
3498 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3500 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3501 ir_node *block = be_transform_node(get_nodes_block(node));
3502 ir_node *val = get_irn_n(node, 1);
3503 ir_node *new_val = be_transform_node(val);
3504 ia32_code_gen_t *cg = env_cg;
3505 ir_node *res = NULL;
3506 ir_graph *irg = current_ir_graph;
3508 ir_node *noreg, *new_ptr, *new_mem;
3515 mem = get_irn_n(node, 2);
3516 new_mem = be_transform_node(mem);
3517 ptr = get_irn_n(node, 0);
3518 new_ptr = be_transform_node(ptr);
3519 noreg = ia32_new_NoReg_gp(cg);
3520 dbgi = get_irn_dbg_info(node);
3522 /* Store x87 -> MEM */
3523 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3524 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3525 set_ia32_use_frame(res);
3526 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3527 set_ia32_am_flavour(res, ia32_B);
3528 set_ia32_op_type(res, ia32_AddrModeD);
3530 /* Load MEM -> SSE */
3531 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3532 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3533 set_ia32_use_frame(res);
3534 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3535 set_ia32_am_flavour(res, ia32_B);
3536 set_ia32_op_type(res, ia32_AddrModeS);
3537 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3543 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3545 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3546 ir_node *block = be_transform_node(get_nodes_block(node));
3547 ir_node *val = get_irn_n(node, 1);
3548 ir_node *new_val = be_transform_node(val);
3549 ia32_code_gen_t *cg = env_cg;
3550 ir_graph *irg = current_ir_graph;
3551 ir_node *res = NULL;
3552 ir_entity *fent = get_ia32_frame_ent(node);
3553 ir_mode *lsmode = get_ia32_ls_mode(node);
3555 ir_node *noreg, *new_ptr, *new_mem;
3559 if (! USE_SSE2(cg)) {
3560 /* SSE unit is not used -> skip this node. */
3564 ptr = get_irn_n(node, 0);
3565 new_ptr = be_transform_node(ptr);
3566 mem = get_irn_n(node, 2);
3567 new_mem = be_transform_node(mem);
3568 noreg = ia32_new_NoReg_gp(cg);
3569 dbgi = get_irn_dbg_info(node);
3571 /* Store SSE -> MEM */
3572 if (is_ia32_xLoad(skip_Proj(new_val))) {
3573 ir_node *ld = skip_Proj(new_val);
3575 /* we can vfld the value directly into the fpu */
3576 fent = get_ia32_frame_ent(ld);
3577 ptr = get_irn_n(ld, 0);
3578 offs = get_ia32_am_offs_int(ld);
3580 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3581 set_ia32_frame_ent(res, fent);
3582 set_ia32_use_frame(res);
3583 set_ia32_ls_mode(res, lsmode);
3584 set_ia32_am_flavour(res, ia32_B);
3585 set_ia32_op_type(res, ia32_AddrModeD);
3589 /* Load MEM -> x87 */
3590 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3591 set_ia32_frame_ent(res, fent);
3592 set_ia32_use_frame(res);
3593 add_ia32_am_offs_int(res, offs);
3594 set_ia32_am_flavour(res, ia32_B);
3595 set_ia32_op_type(res, ia32_AddrModeS);
3596 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3601 /*********************************************************
3604 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3605 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3606 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3607 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3609 *********************************************************/
3612 * the BAD transformer.
3614 static ir_node *bad_transform(ir_node *node) {
3615 panic("No transform function for %+F available.\n", node);
3620 * Transform the Projs of an AddSP.
3622 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3623 ir_node *block = be_transform_node(get_nodes_block(node));
3624 ir_node *pred = get_Proj_pred(node);
3625 ir_node *new_pred = be_transform_node(pred);
3626 ir_graph *irg = current_ir_graph;
3627 dbg_info *dbgi = get_irn_dbg_info(node);
3628 long proj = get_Proj_proj(node);
3630 if (proj == pn_be_AddSP_res) {
3631 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3632 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3634 } else if (proj == pn_be_AddSP_M) {
3635 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3639 return new_rd_Unknown(irg, get_irn_mode(node));
3643 * Transform the Projs of a SubSP.
3645 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3646 ir_node *block = be_transform_node(get_nodes_block(node));
3647 ir_node *pred = get_Proj_pred(node);
3648 ir_node *new_pred = be_transform_node(pred);
3649 ir_graph *irg = current_ir_graph;
3650 dbg_info *dbgi = get_irn_dbg_info(node);
3651 long proj = get_Proj_proj(node);
3653 if (proj == pn_be_SubSP_res) {
3654 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3655 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3657 } else if (proj == pn_be_SubSP_M) {
3658 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3662 return new_rd_Unknown(irg, get_irn_mode(node));
3666 * Transform and renumber the Projs from a Load.
3668 static ir_node *gen_Proj_Load(ir_node *node) {
3669 ir_node *block = be_transform_node(get_nodes_block(node));
3670 ir_node *pred = get_Proj_pred(node);
3671 ir_node *new_pred = be_transform_node(pred);
3672 ir_graph *irg = current_ir_graph;
3673 dbg_info *dbgi = get_irn_dbg_info(node);
3674 long proj = get_Proj_proj(node);
3676 /* renumber the proj */
3677 if (is_ia32_Load(new_pred)) {
3678 if (proj == pn_Load_res) {
3679 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3680 } else if (proj == pn_Load_M) {
3681 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3683 } else if (is_ia32_xLoad(new_pred)) {
3684 if (proj == pn_Load_res) {
3685 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3686 } else if (proj == pn_Load_M) {
3687 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3689 } else if (is_ia32_vfld(new_pred)) {
3690 if (proj == pn_Load_res) {
3691 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3692 } else if (proj == pn_Load_M) {
3693 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3698 return new_rd_Unknown(irg, get_irn_mode(node));
3702 * Transform and renumber the Projs from a DivMod like instruction.
3704 static ir_node *gen_Proj_DivMod(ir_node *node) {
3705 ir_node *block = be_transform_node(get_nodes_block(node));
3706 ir_node *pred = get_Proj_pred(node);
3707 ir_node *new_pred = be_transform_node(pred);
3708 ir_graph *irg = current_ir_graph;
3709 dbg_info *dbgi = get_irn_dbg_info(node);
3710 ir_mode *mode = get_irn_mode(node);
3711 long proj = get_Proj_proj(node);
3713 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3715 switch (get_irn_opcode(pred)) {
3719 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3721 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3729 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3731 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3739 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3740 case pn_DivMod_res_div:
3741 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3742 case pn_DivMod_res_mod:
3743 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3753 return new_rd_Unknown(irg, mode);
3757 * Transform and renumber the Projs from a CopyB.
3759 static ir_node *gen_Proj_CopyB(ir_node *node) {
3760 ir_node *block = be_transform_node(get_nodes_block(node));
3761 ir_node *pred = get_Proj_pred(node);
3762 ir_node *new_pred = be_transform_node(pred);
3763 ir_graph *irg = current_ir_graph;
3764 dbg_info *dbgi = get_irn_dbg_info(node);
3765 ir_mode *mode = get_irn_mode(node);
3766 long proj = get_Proj_proj(node);
3769 case pn_CopyB_M_regular:
3770 if (is_ia32_CopyB_i(new_pred)) {
3771 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3772 } else if (is_ia32_CopyB(new_pred)) {
3773 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3781 return new_rd_Unknown(irg, mode);
3785 * Transform and renumber the Projs from a vfdiv.
3787 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3788 ir_node *block = be_transform_node(get_nodes_block(node));
3789 ir_node *pred = get_Proj_pred(node);
3790 ir_node *new_pred = be_transform_node(pred);
3791 ir_graph *irg = current_ir_graph;
3792 dbg_info *dbgi = get_irn_dbg_info(node);
3793 ir_mode *mode = get_irn_mode(node);
3794 long proj = get_Proj_proj(node);
3797 case pn_ia32_l_vfdiv_M:
3798 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3799 case pn_ia32_l_vfdiv_res:
3800 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3805 return new_rd_Unknown(irg, mode);
3809 * Transform and renumber the Projs from a Quot.
3811 static ir_node *gen_Proj_Quot(ir_node *node) {
3812 ir_node *block = be_transform_node(get_nodes_block(node));
3813 ir_node *pred = get_Proj_pred(node);
3814 ir_node *new_pred = be_transform_node(pred);
3815 ir_graph *irg = current_ir_graph;
3816 dbg_info *dbgi = get_irn_dbg_info(node);
3817 ir_mode *mode = get_irn_mode(node);
3818 long proj = get_Proj_proj(node);
3822 if (is_ia32_xDiv(new_pred)) {
3823 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3824 } else if (is_ia32_vfdiv(new_pred)) {
3825 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3829 if (is_ia32_xDiv(new_pred)) {
3830 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3831 } else if (is_ia32_vfdiv(new_pred)) {
3832 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3840 return new_rd_Unknown(irg, mode);
3844 * Transform the Thread Local Storage Proj.
3846 static ir_node *gen_Proj_tls(ir_node *node) {
3847 ir_node *block = be_transform_node(get_nodes_block(node));
3848 ir_graph *irg = current_ir_graph;
3849 dbg_info *dbgi = NULL;
3850 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3856 * Transform the Projs from a be_Call.
3858 static ir_node *gen_Proj_be_Call(ir_node *node) {
3859 ir_node *block = be_transform_node(get_nodes_block(node));
3860 ir_node *call = get_Proj_pred(node);
3861 ir_node *new_call = be_transform_node(call);
3862 ir_graph *irg = current_ir_graph;
3863 dbg_info *dbgi = get_irn_dbg_info(node);
3864 long proj = get_Proj_proj(node);
3865 ir_mode *mode = get_irn_mode(node);
3867 const arch_register_class_t *cls;
3869 /* The following is kinda tricky: If we're using SSE, then we have to
3870 * move the result value of the call in floating point registers to an
3871 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3872 * after the call, we have to make sure to correctly make the
3873 * MemProj and the result Proj use these 2 nodes
3875 if (proj == pn_be_Call_M_regular) {
3876 // get new node for result, are we doing the sse load/store hack?
3877 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3878 ir_node *call_res_new;
3879 ir_node *call_res_pred = NULL;
3881 if (call_res != NULL) {
3882 call_res_new = be_transform_node(call_res);
3883 call_res_pred = get_Proj_pred(call_res_new);
3886 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3887 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3889 assert(is_ia32_xLoad(call_res_pred));
3890 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3893 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3895 ir_node *frame = get_irg_frame(irg);
3896 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3898 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3900 const arch_register_class_t *cls;
3902 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3903 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3905 /* store st(0) onto stack */
3906 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3908 set_ia32_ls_mode(fstp, mode);
3909 set_ia32_op_type(fstp, ia32_AddrModeD);
3910 set_ia32_use_frame(fstp);
3911 set_ia32_am_flavour(fstp, ia32_am_B);
3913 /* load into SSE register */
3914 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3915 set_ia32_ls_mode(sse_load, mode);
3916 set_ia32_op_type(sse_load, ia32_AddrModeS);
3917 set_ia32_use_frame(sse_load);
3918 set_ia32_am_flavour(sse_load, ia32_am_B);
3920 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3922 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3924 /* get a Proj representing a caller save register */
3925 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3926 assert(is_Proj(p) && "Proj expected.");
3928 /* user of the the proj is the Keep */
3929 p = get_edge_src_irn(get_irn_out_edge_first(p));
3930 assert(be_is_Keep(p) && "Keep expected.");
3932 /* keep the result */
3933 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3934 keepin[0] = sse_load;
3935 be_new_Keep(cls, irg, block, 1, keepin);
3940 /* transform call modes */
3941 if (mode_is_data(mode)) {
3942 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3946 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3950 * Transform the Projs from a Cmp.
3952 static ir_node *gen_Proj_Cmp(ir_node *node)
3954 /* normally Cmps are processed when looking at Cond nodes, but this case
3955 * can happen in complicated Psi conditions */
3957 ir_graph *irg = current_ir_graph;
3958 dbg_info *dbgi = get_irn_dbg_info(node);
3959 ir_node *block = be_transform_node(get_nodes_block(node));
3960 ir_node *cmp = get_Proj_pred(node);
3961 long pnc = get_Proj_proj(node);
3962 ir_node *cmp_left = get_Cmp_left(cmp);
3963 ir_node *cmp_right = get_Cmp_right(cmp);
3964 ir_node *new_cmp_left;
3965 ir_node *new_cmp_right;
3966 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3967 ir_node *nomem = new_rd_NoMem(irg);
3968 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3971 assert(!mode_is_float(cmp_mode));
3973 /* (a != b) -> (a ^ b) */
3974 if(pnc == pn_Cmp_Lg) {
3975 if(is_Const_0(cmp_left)) {
3976 new_op = be_transform_node(cmp_right);
3977 } else if(is_Const_0(cmp_right)) {
3978 new_op = be_transform_node(cmp_left);
3980 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
3986 * (a == b) -> !(a ^ b)
3987 * (a < 0) -> (a & 0x80000000) oder a >> 31
3988 * (a >= 0) -> (a >> 31) ^ 1
3991 if(!mode_is_signed(cmp_mode)) {
3992 pnc |= ia32_pn_Cmp_Unsigned;
3995 new_cmp_left = be_transform_node(cmp_left);
3996 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
3998 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
3999 new_cmp_right, nomem, pnc);
4000 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4006 * Transform and potentially renumber Proj nodes.
4008 static ir_node *gen_Proj(ir_node *node) {
4009 ir_graph *irg = current_ir_graph;
4010 dbg_info *dbgi = get_irn_dbg_info(node);
4011 ir_node *pred = get_Proj_pred(node);
4012 long proj = get_Proj_proj(node);
4014 if (is_Store(pred) || be_is_FrameStore(pred)) {
4015 if (proj == pn_Store_M) {
4016 return be_transform_node(pred);
4019 return new_r_Bad(irg);
4021 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4022 return gen_Proj_Load(node);
4023 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4024 return gen_Proj_DivMod(node);
4025 } else if (is_CopyB(pred)) {
4026 return gen_Proj_CopyB(node);
4027 } else if (is_Quot(pred)) {
4028 return gen_Proj_Quot(node);
4029 } else if (is_ia32_l_vfdiv(pred)) {
4030 return gen_Proj_l_vfdiv(node);
4031 } else if (be_is_SubSP(pred)) {
4032 return gen_Proj_be_SubSP(node);
4033 } else if (be_is_AddSP(pred)) {
4034 return gen_Proj_be_AddSP(node);
4035 } else if (be_is_Call(pred)) {
4036 return gen_Proj_be_Call(node);
4037 } else if (is_Cmp(pred)) {
4038 return gen_Proj_Cmp(node);
4039 } else if (get_irn_op(pred) == op_Start) {
4040 if (proj == pn_Start_X_initial_exec) {
4041 ir_node *block = get_nodes_block(pred);
4044 /* we exchange the ProjX with a jump */
4045 block = be_transform_node(block);
4046 jump = new_rd_Jmp(dbgi, irg, block);
4049 if (node == be_get_old_anchor(anchor_tls)) {
4050 return gen_Proj_tls(node);
4053 ir_node *new_pred = be_transform_node(pred);
4054 ir_node *block = be_transform_node(get_nodes_block(node));
4055 ir_mode *mode = get_irn_mode(node);
4056 if (mode_needs_gp_reg(mode)) {
4057 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4058 get_Proj_proj(node));
4059 #ifdef DEBUG_libfirm
4060 new_proj->node_nr = node->node_nr;
4066 return be_duplicate_node(node);
4070 * Enters all transform functions into the generic pointer
4072 static void register_transformers(void) {
4073 ir_op *op_Max, *op_Min, *op_Mulh;
4075 /* first clear the generic function pointer for all ops */
4076 clear_irp_opcodes_generic_func();
4078 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4079 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4116 /* transform ops from intrinsic lowering */
4136 /* GEN(ia32_l_vfist); TODO */
4138 GEN(ia32_l_X87toSSE);
4139 GEN(ia32_l_SSEtoX87);
4144 /* we should never see these nodes */
4159 /* handle generic backend nodes */
4170 /* set the register for all Unknown nodes */
4173 op_Max = get_op_Max();
4176 op_Min = get_op_Min();
4179 op_Mulh = get_op_Mulh();
4188 * Pre-transform all unknown and noreg nodes.
4190 static void ia32_pretransform_node(void *arch_cg) {
4191 ia32_code_gen_t *cg = arch_cg;
4193 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4194 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4195 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4196 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4197 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4198 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4201 /* do the transformation */
4202 void ia32_transform_graph(ia32_code_gen_t *cg) {
4203 register_transformers();
4205 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4208 void ia32_init_transform(void)
4210 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");