2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
33 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "../arch/archop.h" /* we need this for Min and Max nodes */
37 #include "ia32_transform.h"
38 #include "ia32_new_nodes.h"
39 #include "ia32_map_regs.h"
40 #include "ia32_dbg_stat.h"
42 #include "gen_ia32_regalloc_if.h"
44 #define SFP_SIGN "0x80000000"
45 #define DFP_SIGN "0x8000000000000000"
46 #define SFP_ABS "0x7FFFFFFF"
47 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
49 #define TP_SFP_SIGN "ia32_sfp_sign"
50 #define TP_DFP_SIGN "ia32_dfp_sign"
51 #define TP_SFP_ABS "ia32_sfp_abs"
52 #define TP_DFP_ABS "ia32_dfp_abs"
54 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
55 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
56 #define ENT_SFP_ABS "IA32_SFP_ABS"
57 #define ENT_DFP_ABS "IA32_DFP_ABS"
59 extern ir_op *get_op_Mulh(void);
61 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op1, ir_node *op2, ir_node *mem);
64 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op, ir_node *mem);
68 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
71 /****************************************************************************************************
73 * | | | | / _| | | (_)
74 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
75 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
76 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
77 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
79 ****************************************************************************************************/
82 * Returns the Proj representing the UNKNOWN register for given mode.
84 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
85 be_abi_irg_t *babi = cg->birg->abi;
86 const arch_register_t *unknwn_reg = NULL;
88 if (mode_is_float(mode)) {
89 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
92 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
95 return be_abi_get_callee_save_irn(babi, unknwn_reg);
99 * Gets the Proj with number pn from irn.
101 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
102 const ir_edge_t *edge;
104 assert(get_irn_mode(irn) == mode_T && "need mode_T");
106 foreach_out_edge(irn, edge) {
107 proj = get_edge_src_irn(edge);
109 if (get_Proj_proj(proj) == pn)
116 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
117 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
118 static const struct {
120 const char *ent_name;
121 const char *cnst_str;
122 } names [ia32_known_const_max] = {
123 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
124 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
125 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
126 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
128 static struct entity *ent_cache[ia32_known_const_max];
130 const char *tp_name, *ent_name, *cnst_str;
137 ent_name = names[kct].ent_name;
138 if (! ent_cache[kct]) {
139 tp_name = names[kct].tp_name;
140 cnst_str = names[kct].cnst_str;
142 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
143 tp = new_type_primitive(new_id_from_str(tp_name), mode);
144 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
146 set_entity_ld_ident(ent, get_entity_ident(ent));
147 set_entity_visibility(ent, visibility_local);
148 set_entity_variability(ent, variability_constant);
149 set_entity_allocation(ent, allocation_static);
151 /* we create a new entity here: It's initialization must resist on the
153 rem = current_ir_graph;
154 current_ir_graph = get_const_code_irg();
155 cnst = new_Const(mode, tv);
156 current_ir_graph = rem;
158 set_atomic_ent_value(ent, cnst);
160 /* cache the entry */
161 ent_cache[kct] = ent;
164 return get_entity_ident(ent_cache[kct]);
169 * Prints the old node name on cg obst and returns a pointer to it.
171 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
172 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
174 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
175 obstack_1grow(isa->name_obst, 0);
176 isa->name_obst_size += obstack_object_size(isa->name_obst);
177 return obstack_finish(isa->name_obst);
181 /* determine if one operator is an Imm */
182 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
184 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
185 else return is_ia32_Cnst(op2) ? op2 : NULL;
188 /* determine if one operator is not an Imm */
189 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
190 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
195 * Construct a standard binary operation, set AM and immediate if required.
197 * @param env The transformation environment
198 * @param op1 The first operand
199 * @param op2 The second operand
200 * @param func The node constructor function
201 * @return The constructed ia32 node.
203 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
204 ir_node *new_op = NULL;
205 ir_mode *mode = env->mode;
206 dbg_info *dbg = env->dbg;
207 ir_graph *irg = env->irg;
208 ir_node *block = env->block;
209 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
210 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
211 ir_node *nomem = new_NoMem();
212 ir_node *expr_op, *imm_op;
213 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
215 /* Check if immediate optimization is on and */
216 /* if it's an operation with immediate. */
217 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
221 else if (is_op_commutative(get_irn_op(env->irn))) {
222 imm_op = get_immediate_op(op1, op2);
223 expr_op = get_expr_op(op1, op2);
226 imm_op = get_immediate_op(NULL, op2);
227 expr_op = get_expr_op(op1, op2);
230 assert((expr_op || imm_op) && "invalid operands");
233 /* We have two consts here: not yet supported */
237 if (mode_is_float(mode)) {
238 /* floating point operations */
240 DB((mod, LEVEL_1, "FP with immediate ..."));
241 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
242 set_ia32_Immop_attr(new_op, imm_op);
243 set_ia32_am_support(new_op, ia32_am_None);
246 DB((mod, LEVEL_1, "FP binop ..."));
247 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
248 set_ia32_am_support(new_op, ia32_am_Source);
250 set_ia32_ls_mode(new_op, mode);
253 /* integer operations */
255 /* This is expr + const */
256 DB((mod, LEVEL_1, "INT with immediate ..."));
257 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
258 set_ia32_Immop_attr(new_op, imm_op);
261 set_ia32_am_support(new_op, ia32_am_Dest);
264 DB((mod, LEVEL_1, "INT binop ..."));
265 /* This is a normal operation */
266 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
269 set_ia32_am_support(new_op, ia32_am_Full);
273 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
275 set_ia32_res_mode(new_op, mode);
277 if (is_op_commutative(get_irn_op(env->irn))) {
278 set_ia32_commutative(new_op);
281 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
287 * Construct a shift/rotate binary operation, sets AM and immediate if required.
289 * @param env The transformation environment
290 * @param op1 The first operand
291 * @param op2 The second operand
292 * @param func The node constructor function
293 * @return The constructed ia32 node.
295 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
296 ir_node *new_op = NULL;
297 ir_mode *mode = env->mode;
298 dbg_info *dbg = env->dbg;
299 ir_graph *irg = env->irg;
300 ir_node *block = env->block;
301 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
302 ir_node *nomem = new_NoMem();
303 ir_node *expr_op, *imm_op;
305 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
307 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
309 /* Check if immediate optimization is on and */
310 /* if it's an operation with immediate. */
311 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
312 expr_op = get_expr_op(op1, op2);
314 assert((expr_op || imm_op) && "invalid operands");
317 /* We have two consts here: not yet supported */
321 /* Limit imm_op within range imm8 */
323 tv = get_ia32_Immop_tarval(imm_op);
326 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
333 /* integer operations */
335 /* This is shift/rot with const */
336 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
338 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
339 set_ia32_Immop_attr(new_op, imm_op);
342 /* This is a normal shift/rot */
343 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
344 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
348 set_ia32_am_support(new_op, ia32_am_Dest);
350 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
352 set_ia32_res_mode(new_op, mode);
353 set_ia32_emit_cl(new_op);
355 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
360 * Construct a standard unary operation, set AM and immediate if required.
362 * @param env The transformation environment
363 * @param op The operand
364 * @param func The node constructor function
365 * @return The constructed ia32 node.
367 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
368 ir_node *new_op = NULL;
369 ir_mode *mode = env->mode;
370 dbg_info *dbg = env->dbg;
371 ir_graph *irg = env->irg;
372 ir_node *block = env->block;
373 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
374 ir_node *nomem = new_NoMem();
375 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
377 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
379 if (mode_is_float(mode)) {
380 DB((mod, LEVEL_1, "FP unop ..."));
381 /* floating point operations don't support implicit store */
382 set_ia32_am_support(new_op, ia32_am_None);
385 DB((mod, LEVEL_1, "INT unop ..."));
386 set_ia32_am_support(new_op, ia32_am_Dest);
389 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
391 set_ia32_res_mode(new_op, mode);
393 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
399 * Creates an ia32 Add with immediate.
401 * @param env The transformation environment
402 * @param expr_op The expression operator
403 * @param const_op The constant
404 * @return the created ia32 Add node
406 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
407 ir_node *new_op = NULL;
408 tarval *tv = get_ia32_Immop_tarval(const_op);
409 dbg_info *dbg = env->dbg;
410 ir_graph *irg = env->irg;
411 ir_node *block = env->block;
412 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
413 ir_node *nomem = new_NoMem();
415 tarval_classification_t class_tv, class_negtv;
416 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
418 /* try to optimize to inc/dec */
419 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
420 /* optimize tarvals */
421 class_tv = classify_tarval(tv);
422 class_negtv = classify_tarval(tarval_neg(tv));
424 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
425 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
426 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
429 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
430 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
431 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
437 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
438 set_ia32_Immop_attr(new_op, const_op);
439 set_ia32_commutative(new_op);
446 * Creates an ia32 Add.
448 * @param env The transformation environment
449 * @return the created ia32 Add node
451 static ir_node *gen_Add(ia32_transform_env_t *env) {
452 ir_node *new_op = NULL;
453 dbg_info *dbg = env->dbg;
454 ir_mode *mode = env->mode;
455 ir_graph *irg = env->irg;
456 ir_node *block = env->block;
457 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
458 ir_node *nomem = new_NoMem();
459 ir_node *expr_op, *imm_op;
460 ir_node *op1 = get_Add_left(env->irn);
461 ir_node *op2 = get_Add_right(env->irn);
463 /* Check if immediate optimization is on and */
464 /* if it's an operation with immediate. */
465 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
466 expr_op = get_expr_op(op1, op2);
468 assert((expr_op || imm_op) && "invalid operands");
470 if (mode_is_float(mode)) {
472 if (USE_SSE2(env->cg))
473 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
475 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
480 /* No expr_op means, that we have two const - one symconst and */
481 /* one tarval or another symconst - because this case is not */
482 /* covered by constant folding */
483 /* We need to check for: */
484 /* 1) symconst + const -> becomes a LEA */
485 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
486 /* linker doesn't support two symconsts */
488 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
489 /* this is the 2nd case */
490 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
491 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
492 set_ia32_am_flavour(new_op, ia32_am_OB);
494 DBG_OPT_LEA1(op2, new_op);
497 /* this is the 1st case */
498 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
500 DBG_OPT_LEA2(op1, op2, new_op);
502 if (get_ia32_op_type(op1) == ia32_SymConst) {
503 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
504 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
507 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
508 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
510 set_ia32_am_flavour(new_op, ia32_am_O);
514 set_ia32_am_support(new_op, ia32_am_Source);
515 set_ia32_op_type(new_op, ia32_AddrModeS);
517 /* Lea doesn't need a Proj */
521 /* This is expr + const */
522 new_op = gen_imm_Add(env, expr_op, imm_op);
525 set_ia32_am_support(new_op, ia32_am_Dest);
528 /* This is a normal add */
529 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
532 set_ia32_am_support(new_op, ia32_am_Full);
533 set_ia32_commutative(new_op);
537 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
539 set_ia32_res_mode(new_op, mode);
541 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
547 * Creates an ia32 Mul.
549 * @param env The transformation environment
550 * @return the created ia32 Mul node
552 static ir_node *gen_Mul(ia32_transform_env_t *env) {
553 ir_node *op1 = get_Mul_left(env->irn);
554 ir_node *op2 = get_Mul_right(env->irn);
557 if (mode_is_float(env->mode)) {
559 if (USE_SSE2(env->cg))
560 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
562 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
565 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
574 * Creates an ia32 Mulh.
575 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
576 * this result while Mul returns the lower 32 bit.
578 * @param env The transformation environment
579 * @return the created ia32 Mulh node
581 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
582 ir_node *op1 = get_irn_n(env->irn, 0);
583 ir_node *op2 = get_irn_n(env->irn, 1);
584 ir_node *proj_EAX, *proj_EDX, *mulh;
587 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
588 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
589 mulh = get_Proj_pred(proj_EAX);
590 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
592 /* to be on the save side */
593 set_Proj_proj(proj_EAX, pn_EAX);
595 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
596 /* Mulh with const cannot have AM */
597 set_ia32_am_support(mulh, ia32_am_None);
600 /* Mulh cannot have AM for destination */
601 set_ia32_am_support(mulh, ia32_am_Source);
607 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
615 * Creates an ia32 And.
617 * @param env The transformation environment
618 * @return The created ia32 And node
620 static ir_node *gen_And(ia32_transform_env_t *env) {
621 ir_node *op1 = get_And_left(env->irn);
622 ir_node *op2 = get_And_right(env->irn);
624 assert (! mode_is_float(env->mode));
625 return gen_binop(env, op1, op2, new_rd_ia32_And);
631 * Creates an ia32 Or.
633 * @param env The transformation environment
634 * @return The created ia32 Or node
636 static ir_node *gen_Or(ia32_transform_env_t *env) {
637 ir_node *op1 = get_Or_left(env->irn);
638 ir_node *op2 = get_Or_right(env->irn);
640 assert (! mode_is_float(env->mode));
641 return gen_binop(env, op1, op2, new_rd_ia32_Or);
647 * Creates an ia32 Eor.
649 * @param env The transformation environment
650 * @return The created ia32 Eor node
652 static ir_node *gen_Eor(ia32_transform_env_t *env) {
653 ir_node *op1 = get_Eor_left(env->irn);
654 ir_node *op2 = get_Eor_right(env->irn);
656 assert(! mode_is_float(env->mode));
657 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
663 * Creates an ia32 Max.
665 * @param env The transformation environment
666 * @return the created ia32 Max node
668 static ir_node *gen_Max(ia32_transform_env_t *env) {
669 ir_node *op1 = get_irn_n(env->irn, 0);
670 ir_node *op2 = get_irn_n(env->irn, 1);
673 if (mode_is_float(env->mode)) {
675 if (USE_SSE2(env->cg))
676 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
682 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
683 set_ia32_am_support(new_op, ia32_am_None);
684 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
693 * Creates an ia32 Min.
695 * @param env The transformation environment
696 * @return the created ia32 Min node
698 static ir_node *gen_Min(ia32_transform_env_t *env) {
699 ir_node *op1 = get_irn_n(env->irn, 0);
700 ir_node *op2 = get_irn_n(env->irn, 1);
703 if (mode_is_float(env->mode)) {
705 if (USE_SSE2(env->cg))
706 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
712 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
713 set_ia32_am_support(new_op, ia32_am_None);
714 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
723 * Creates an ia32 Sub with immediate.
725 * @param env The transformation environment
726 * @param expr_op The first operator
727 * @param const_op The constant operator
728 * @return The created ia32 Sub node
730 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
731 ir_node *new_op = NULL;
732 tarval *tv = get_ia32_Immop_tarval(const_op);
733 dbg_info *dbg = env->dbg;
734 ir_graph *irg = env->irg;
735 ir_node *block = env->block;
736 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
737 ir_node *nomem = new_NoMem();
739 tarval_classification_t class_tv, class_negtv;
740 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
742 /* try to optimize to inc/dec */
743 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
744 /* optimize tarvals */
745 class_tv = classify_tarval(tv);
746 class_negtv = classify_tarval(tarval_neg(tv));
748 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
749 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
750 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
753 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
754 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
755 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
761 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
762 set_ia32_Immop_attr(new_op, const_op);
769 * Creates an ia32 Sub.
771 * @param env The transformation environment
772 * @return The created ia32 Sub node
774 static ir_node *gen_Sub(ia32_transform_env_t *env) {
775 ir_node *new_op = NULL;
776 dbg_info *dbg = env->dbg;
777 ir_mode *mode = env->mode;
778 ir_graph *irg = env->irg;
779 ir_node *block = env->block;
780 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
781 ir_node *nomem = new_NoMem();
782 ir_node *op1 = get_Sub_left(env->irn);
783 ir_node *op2 = get_Sub_right(env->irn);
784 ir_node *expr_op, *imm_op;
786 /* Check if immediate optimization is on and */
787 /* if it's an operation with immediate. */
788 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
789 expr_op = get_expr_op(op1, op2);
791 assert((expr_op || imm_op) && "invalid operands");
793 if (mode_is_float(mode)) {
795 if (USE_SSE2(env->cg))
796 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
798 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
803 /* No expr_op means, that we have two const - one symconst and */
804 /* one tarval or another symconst - because this case is not */
805 /* covered by constant folding */
806 /* We need to check for: */
807 /* 1) symconst + const -> becomes a LEA */
808 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
809 /* linker doesn't support two symconsts */
811 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
812 /* this is the 2nd case */
813 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
814 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
815 set_ia32_am_sc_sign(new_op);
816 set_ia32_am_flavour(new_op, ia32_am_OB);
818 DBG_OPT_LEA1(op2, new_op);
821 /* this is the 1st case */
822 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
824 DBG_OPT_LEA2(op1, op2, new_op);
826 if (get_ia32_op_type(op1) == ia32_SymConst) {
827 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
828 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
831 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
832 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
833 set_ia32_am_sc_sign(new_op);
835 set_ia32_am_flavour(new_op, ia32_am_O);
839 set_ia32_am_support(new_op, ia32_am_Source);
840 set_ia32_op_type(new_op, ia32_AddrModeS);
842 /* Lea doesn't need a Proj */
846 /* This is expr - const */
847 new_op = gen_imm_Sub(env, expr_op, imm_op);
850 set_ia32_am_support(new_op, ia32_am_Dest);
853 /* This is a normal sub */
854 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
857 set_ia32_am_support(new_op, ia32_am_Full);
861 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
863 set_ia32_res_mode(new_op, mode);
865 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
871 * Generates an ia32 DivMod with additional infrastructure for the
872 * register allocator if needed.
874 * @param env The transformation environment
875 * @param dividend -no comment- :)
876 * @param divisor -no comment- :)
877 * @param dm_flav flavour_Div/Mod/DivMod
878 * @return The created ia32 DivMod node
880 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
882 ir_node *edx_node, *cltd;
884 dbg_info *dbg = env->dbg;
885 ir_graph *irg = env->irg;
886 ir_node *block = env->block;
887 ir_mode *mode = env->mode;
888 ir_node *irn = env->irn;
893 mem = get_Div_mem(irn);
894 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
897 mem = get_Mod_mem(irn);
898 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
901 mem = get_DivMod_mem(irn);
902 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
908 if (mode_is_signed(mode)) {
909 /* in signed mode, we need to sign extend the dividend */
910 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
911 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
912 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
915 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
916 set_ia32_Const_type(edx_node, ia32_Const);
917 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
920 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
922 set_ia32_n_res(res, 2);
924 /* Only one proj is used -> We must add a second proj and */
925 /* connect this one to a Keep node to eat up the second */
926 /* destroyed register. */
927 if (get_irn_n_edges(irn) == 1) {
928 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
929 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
931 if (get_irn_op(irn) == op_Div) {
932 set_Proj_proj(proj, pn_DivMod_res_div);
933 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
936 set_Proj_proj(proj, pn_DivMod_res_mod);
937 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
940 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
943 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
945 set_ia32_res_mode(res, mode_Is);
952 * Wrapper for generate_DivMod. Sets flavour_Mod.
954 * @param env The transformation environment
956 static ir_node *gen_Mod(ia32_transform_env_t *env) {
957 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
961 * Wrapper for generate_DivMod. Sets flavour_Div.
963 * @param env The transformation environment
965 static ir_node *gen_Div(ia32_transform_env_t *env) {
966 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
970 * Wrapper for generate_DivMod. Sets flavour_DivMod.
972 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
973 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
979 * Creates an ia32 floating Div.
981 * @param env The transformation environment
982 * @return The created ia32 xDiv node
984 static ir_node *gen_Quot(ia32_transform_env_t *env) {
985 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
987 ir_node *nomem = new_rd_NoMem(env->irg);
988 ir_node *op1 = get_Quot_left(env->irn);
989 ir_node *op2 = get_Quot_right(env->irn);
992 if (USE_SSE2(env->cg)) {
993 if (is_ia32_xConst(op2)) {
994 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
995 set_ia32_am_support(new_op, ia32_am_None);
996 set_ia32_Immop_attr(new_op, op2);
999 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1000 set_ia32_am_support(new_op, ia32_am_Source);
1004 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1005 set_ia32_am_support(new_op, ia32_am_Source);
1007 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1008 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1016 * Creates an ia32 Shl.
1018 * @param env The transformation environment
1019 * @return The created ia32 Shl node
1021 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1022 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1028 * Creates an ia32 Shr.
1030 * @param env The transformation environment
1031 * @return The created ia32 Shr node
1033 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1034 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1040 * Creates an ia32 Shrs.
1042 * @param env The transformation environment
1043 * @return The created ia32 Shrs node
1045 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1046 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1052 * Creates an ia32 RotL.
1054 * @param env The transformation environment
1055 * @param op1 The first operator
1056 * @param op2 The second operator
1057 * @return The created ia32 RotL node
1059 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1060 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1066 * Creates an ia32 RotR.
1067 * NOTE: There is no RotR with immediate because this would always be a RotL
1068 * "imm-mode_size_bits" which can be pre-calculated.
1070 * @param env The transformation environment
1071 * @param op1 The first operator
1072 * @param op2 The second operator
1073 * @return The created ia32 RotR node
1075 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1076 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1082 * Creates an ia32 RotR or RotL (depending on the found pattern).
1084 * @param env The transformation environment
1085 * @return The created ia32 RotL or RotR node
1087 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1088 ir_node *rotate = NULL;
1089 ir_node *op1 = get_Rot_left(env->irn);
1090 ir_node *op2 = get_Rot_right(env->irn);
1092 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1093 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1094 that means we can create a RotR instead of an Add and a RotL */
1097 ir_node *pred = get_Proj_pred(op2);
1099 if (is_ia32_Add(pred)) {
1100 ir_node *pred_pred = get_irn_n(pred, 2);
1101 tarval *tv = get_ia32_Immop_tarval(pred);
1102 long bits = get_mode_size_bits(env->mode);
1104 if (is_Proj(pred_pred)) {
1105 pred_pred = get_Proj_pred(pred_pred);
1108 if (is_ia32_Minus(pred_pred) &&
1109 tarval_is_long(tv) &&
1110 get_tarval_long(tv) == bits)
1112 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1113 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1120 rotate = gen_RotL(env, op1, op2);
1129 * Transforms a Minus node.
1131 * @param env The transformation environment
1132 * @param op The Minus operand
1133 * @return The created ia32 Minus node
1135 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1140 if (mode_is_float(env->mode)) {
1142 if (USE_SSE2(env->cg)) {
1143 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1144 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1145 ir_node *nomem = new_rd_NoMem(env->irg);
1147 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1149 size = get_mode_size_bits(env->mode);
1150 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1152 set_ia32_sc(new_op, name);
1154 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1156 set_ia32_res_mode(new_op, env->mode);
1157 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1159 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1162 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1163 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1167 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1174 * Transforms a Minus node.
1176 * @param env The transformation environment
1177 * @return The created ia32 Minus node
1179 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1180 return gen_Minus_ex(env, get_Minus_op(env->irn));
1185 * Transforms a Not node.
1187 * @param env The transformation environment
1188 * @return The created ia32 Not node
1190 static ir_node *gen_Not(ia32_transform_env_t *env) {
1191 assert (! mode_is_float(env->mode));
1192 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1198 * Transforms an Abs node.
1200 * @param env The transformation environment
1201 * @return The created ia32 Abs node
1203 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1204 ir_node *res, *p_eax, *p_edx;
1205 dbg_info *dbg = env->dbg;
1206 ir_mode *mode = env->mode;
1207 ir_graph *irg = env->irg;
1208 ir_node *block = env->block;
1209 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1210 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1211 ir_node *nomem = new_NoMem();
1212 ir_node *op = get_Abs_op(env->irn);
1216 if (mode_is_float(mode)) {
1218 if (USE_SSE2(env->cg)) {
1219 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1221 size = get_mode_size_bits(mode);
1222 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1224 set_ia32_sc(res, name);
1226 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1228 set_ia32_res_mode(res, mode);
1229 set_ia32_immop_type(res, ia32_ImmSymConst);
1231 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1234 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1235 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1239 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1240 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1241 set_ia32_res_mode(res, mode);
1243 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1244 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1246 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1247 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1248 set_ia32_res_mode(res, mode);
1250 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1252 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1253 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1254 set_ia32_res_mode(res, mode);
1256 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1265 * Transforms a Load.
1267 * @param env The transformation environment
1268 * @return the created ia32 Load node
1270 static ir_node *gen_Load(ia32_transform_env_t *env) {
1271 ir_node *node = env->irn;
1272 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1273 ir_node *ptr = get_Load_ptr(node);
1274 ir_node *lptr = ptr;
1275 ir_mode *mode = get_Load_mode(node);
1278 ia32_am_flavour_t am_flav = ia32_B;
1280 /* address might be a constant (symconst or absolute address) */
1281 if (is_ia32_Const(ptr)) {
1286 if (mode_is_float(mode)) {
1288 if (USE_SSE2(env->cg))
1289 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1291 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1294 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1297 /* base is an constant address */
1299 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1300 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1303 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1309 set_ia32_am_support(new_op, ia32_am_Source);
1310 set_ia32_op_type(new_op, ia32_AddrModeS);
1311 set_ia32_am_flavour(new_op, am_flav);
1312 set_ia32_ls_mode(new_op, mode);
1314 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1322 * Transforms a Store.
1324 * @param env The transformation environment
1325 * @return the created ia32 Store node
1327 static ir_node *gen_Store(ia32_transform_env_t *env) {
1328 ir_node *node = env->irn;
1329 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1330 ir_node *val = get_Store_value(node);
1331 ir_node *ptr = get_Store_ptr(node);
1332 ir_node *sptr = ptr;
1333 ir_node *mem = get_Store_mem(node);
1334 ir_mode *mode = get_irn_mode(val);
1335 ir_node *sval = val;
1338 ia32_am_flavour_t am_flav = ia32_B;
1339 ia32_immop_type_t immop = ia32_ImmNone;
1341 if (! mode_is_float(mode)) {
1342 /* in case of storing a const (but not a symconst) -> make it an attribute */
1343 if (is_ia32_Cnst(val)) {
1344 switch (get_ia32_op_type(val)) {
1346 immop = ia32_ImmConst;
1349 immop = ia32_ImmSymConst;
1352 assert(0 && "unsupported Const type");
1358 /* address might be a constant (symconst or absolute address) */
1359 if (is_ia32_Const(ptr)) {
1364 if (mode_is_float(mode)) {
1366 if (USE_SSE2(env->cg))
1367 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1369 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1371 else if (get_mode_size_bits(mode) == 8) {
1372 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1375 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1378 /* stored const is an attribute (saves a register) */
1379 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1380 set_ia32_Immop_attr(new_op, val);
1383 /* base is an constant address */
1385 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1386 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1389 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1395 set_ia32_am_support(new_op, ia32_am_Dest);
1396 set_ia32_op_type(new_op, ia32_AddrModeD);
1397 set_ia32_am_flavour(new_op, am_flav);
1398 set_ia32_ls_mode(new_op, get_irn_mode(val));
1399 set_ia32_immop_type(new_op, immop);
1401 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1409 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1411 * @param env The transformation environment
1412 * @return The transformed node.
1414 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1415 dbg_info *dbg = env->dbg;
1416 ir_graph *irg = env->irg;
1417 ir_node *block = env->block;
1418 ir_node *node = env->irn;
1419 ir_node *sel = get_Cond_selector(node);
1420 ir_mode *sel_mode = get_irn_mode(sel);
1421 ir_node *res = NULL;
1422 ir_node *pred = NULL;
1423 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1424 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1426 if (is_Proj(sel) && sel_mode == mode_b) {
1427 ir_node *nomem = new_NoMem();
1429 pred = get_Proj_pred(sel);
1431 /* get both compare operators */
1432 cmp_a = get_Cmp_left(pred);
1433 cmp_b = get_Cmp_right(pred);
1435 /* check if we can use a CondJmp with immediate */
1436 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1437 expr = get_expr_op(cmp_a, cmp_b);
1440 pn_Cmp pnc = get_Proj_proj(sel);
1442 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1443 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1444 /* a Cmp A =/!= 0 */
1445 ir_node *op1 = expr;
1446 ir_node *op2 = expr;
1447 ir_node *and = skip_Proj(expr);
1448 const char *cnst = NULL;
1450 /* check, if expr is an only once used And operation */
1451 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1452 op1 = get_irn_n(and, 2);
1453 op2 = get_irn_n(and, 3);
1455 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1457 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1458 set_ia32_pncode(res, get_Proj_proj(sel));
1459 set_ia32_res_mode(res, get_irn_mode(op1));
1462 copy_ia32_Immop_attr(res, and);
1465 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1470 if (mode_is_float(get_irn_mode(expr))) {
1472 if (USE_SSE2(env->cg))
1473 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1479 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1481 set_ia32_Immop_attr(res, cnst);
1482 set_ia32_res_mode(res, get_irn_mode(expr));
1485 if (mode_is_float(get_irn_mode(cmp_a))) {
1487 if (USE_SSE2(env->cg))
1488 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1491 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1492 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1493 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1497 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1498 set_ia32_commutative(res);
1500 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1503 set_ia32_pncode(res, get_Proj_proj(sel));
1504 //set_ia32_am_support(res, ia32_am_Source);
1507 /* determine the smallest switch case value */
1508 int switch_min = INT_MAX;
1509 const ir_edge_t *edge;
1512 foreach_out_edge(node, edge) {
1513 int pn = get_Proj_proj(get_edge_src_irn(edge));
1514 switch_min = pn < switch_min ? pn : switch_min;
1518 /* if smallest switch case is not 0 we need an additional sub */
1519 snprintf(buf, sizeof(buf), "%d", switch_min);
1520 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1521 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1522 sub_ia32_am_offs(res, buf);
1523 set_ia32_am_flavour(res, ia32_am_OB);
1524 set_ia32_am_support(res, ia32_am_Source);
1525 set_ia32_op_type(res, ia32_AddrModeS);
1528 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1529 set_ia32_pncode(res, get_Cond_defaultProj(node));
1530 set_ia32_res_mode(res, get_irn_mode(sel));
1533 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1540 * Transforms a CopyB node.
1542 * @param env The transformation environment
1543 * @return The transformed node.
1545 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1546 ir_node *res = NULL;
1547 dbg_info *dbg = env->dbg;
1548 ir_graph *irg = env->irg;
1549 ir_mode *mode = env->mode;
1550 ir_node *block = env->block;
1551 ir_node *node = env->irn;
1552 ir_node *src = get_CopyB_src(node);
1553 ir_node *dst = get_CopyB_dst(node);
1554 ir_node *mem = get_CopyB_mem(node);
1555 int size = get_type_size_bytes(get_CopyB_type(node));
1558 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1559 /* then we need the size explicitly in ECX. */
1560 if (size >= 16 * 4) {
1561 rem = size & 0x3; /* size % 4 */
1564 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1565 set_ia32_op_type(res, ia32_Const);
1566 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1568 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1569 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1572 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1573 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1574 set_ia32_immop_type(res, ia32_ImmConst);
1577 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1585 * Transforms a Mux node into CMov.
1587 * @param env The transformation environment
1588 * @return The transformed node.
1590 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1592 ir_node *node = env->irn;
1593 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1594 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1596 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1605 * Transforms a Psi node into CMov.
1607 * @param env The transformation environment
1608 * @return The transformed node.
1610 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1611 ir_node *node = env->irn;
1612 ir_node *cmp_proj = get_Mux_sel(node);
1613 ir_node *cmp, *cmp_a, *cmp_b, *new_op;
1615 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1617 cmp = get_Proj_pred(cmp_proj);
1618 cmp_a = get_Cmp_left(cmp);
1619 cmp_b = get_Cmp_right(cmp);
1622 new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1623 cmp_a, cmp_b, get_Psi_val(node, 0), get_Psi_default(node), env->mode);
1625 set_ia32_pncode(new_op, get_Proj_proj(cmp_proj));
1627 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1634 * Following conversion rules apply:
1638 * 1) n bit -> m bit n > m (downscale)
1639 * a) target is signed: movsx
1640 * b) target is unsigned: and with lower bits sets
1641 * 2) n bit -> m bit n == m (sign change)
1643 * 3) n bit -> m bit n < m (upscale)
1644 * a) source is signed: movsx
1645 * b) source is unsigned: and with lower bits sets
1649 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1653 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1654 * if target mode < 32bit: additional INT -> INT conversion (see above)
1658 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1659 * x87 is mode_E internally, conversions happen only at load and store
1660 * in non-strict semantic
1664 * Create a conversion from x87 state register to general purpose.
1666 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1667 ia32_code_gen_t *cg = env->cg;
1668 entity *ent = cg->fp_to_gp;
1669 ir_graph *irg = env->irg;
1670 ir_node *block = env->block;
1671 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1672 ir_node *op = get_Conv_op(env->irn);
1673 ir_node *fist, *mem, *load;
1676 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1677 ent = cg->fp_to_gp =
1678 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1682 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1684 set_ia32_frame_ent(fist, ent);
1685 set_ia32_use_frame(fist);
1686 set_ia32_am_support(fist, ia32_am_Dest);
1687 set_ia32_op_type(fist, ia32_AddrModeD);
1688 set_ia32_am_flavour(fist, ia32_B);
1689 set_ia32_ls_mode(fist, mode_E);
1691 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1694 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1696 set_ia32_frame_ent(load, ent);
1697 set_ia32_use_frame(load);
1698 set_ia32_am_support(load, ia32_am_Source);
1699 set_ia32_op_type(load, ia32_AddrModeS);
1700 set_ia32_am_flavour(load, ia32_B);
1701 set_ia32_ls_mode(load, tgt_mode);
1703 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1707 * Create a conversion from x87 state register to general purpose.
1709 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1710 ia32_code_gen_t *cg = env->cg;
1711 entity *ent = cg->gp_to_fp;
1712 ir_graph *irg = env->irg;
1713 ir_node *block = env->block;
1714 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1715 ir_node *nomem = get_irg_no_mem(irg);
1716 ir_node *op = get_Conv_op(env->irn);
1717 ir_node *fild, *store, *mem;
1721 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1722 ent = cg->gp_to_fp =
1723 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1726 /* first convert to 32 bit */
1727 src_bits = get_mode_size_bits(src_mode);
1728 if (src_bits == 8) {
1729 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1730 op = new_r_Proj(irg, block, op, mode_Is, 0);
1732 else if (src_bits < 32) {
1733 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1734 op = new_r_Proj(irg, block, op, mode_Is, 0);
1738 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1740 set_ia32_frame_ent(store, ent);
1741 set_ia32_use_frame(store);
1743 set_ia32_am_support(store, ia32_am_Dest);
1744 set_ia32_op_type(store, ia32_AddrModeD);
1745 set_ia32_am_flavour(store, ia32_B);
1746 set_ia32_ls_mode(store, mode_Is);
1748 mem = new_r_Proj(irg, block, store, mode_M, 0);
1751 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1753 set_ia32_frame_ent(fild, ent);
1754 set_ia32_use_frame(fild);
1755 set_ia32_am_support(fild, ia32_am_Source);
1756 set_ia32_op_type(fild, ia32_AddrModeS);
1757 set_ia32_am_flavour(fild, ia32_B);
1758 set_ia32_ls_mode(fild, mode_E);
1760 return new_r_Proj(irg, block, fild, mode_E, 0);
1764 * Transforms a Conv node.
1766 * @param env The transformation environment
1767 * @return The created ia32 Conv node
1769 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1770 dbg_info *dbg = env->dbg;
1771 ir_graph *irg = env->irg;
1772 ir_node *op = get_Conv_op(env->irn);
1773 ir_mode *src_mode = get_irn_mode(op);
1774 ir_mode *tgt_mode = env->mode;
1775 int src_bits = get_mode_size_bits(src_mode);
1776 int tgt_bits = get_mode_size_bits(tgt_mode);
1777 ir_node *block = env->block;
1778 ir_node *new_op = NULL;
1779 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1780 ir_node *nomem = new_rd_NoMem(irg);
1782 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1784 if (src_mode == tgt_mode) {
1785 /* this can happen when changing mode_P to mode_Is */
1786 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1787 edges_reroute(env->irn, op, irg);
1789 else if (mode_is_float(src_mode)) {
1790 /* we convert from float ... */
1791 if (mode_is_float(tgt_mode)) {
1793 if (USE_SSE2(env->cg)) {
1794 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1795 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1798 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1799 edges_reroute(env->irn, op, irg);
1804 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1805 if (USE_SSE2(env->cg))
1806 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1808 return gen_x87_fp_to_gp(env, tgt_mode);
1810 /* if target mode is not int: add an additional downscale convert */
1811 if (tgt_bits < 32) {
1812 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1813 set_ia32_am_support(new_op, ia32_am_Source);
1814 set_ia32_tgt_mode(new_op, tgt_mode);
1815 set_ia32_src_mode(new_op, src_mode);
1817 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1819 if (tgt_bits == 8 || src_bits == 8) {
1820 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1823 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1829 /* we convert from int ... */
1830 if (mode_is_float(tgt_mode)) {
1833 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1834 if (USE_SSE2(env->cg))
1835 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1837 return gen_x87_gp_to_fp(env, src_mode);
1841 if (get_mode_size_bits(src_mode) == tgt_bits) {
1842 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1843 edges_reroute(env->irn, op, irg);
1846 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1847 if (tgt_bits == 8 || src_bits == 8) {
1848 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1851 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1858 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1859 set_ia32_tgt_mode(new_op, tgt_mode);
1860 set_ia32_src_mode(new_op, src_mode);
1862 set_ia32_am_support(new_op, ia32_am_Source);
1864 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1872 /********************************************
1875 * | |__ ___ _ __ ___ __| | ___ ___
1876 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1877 * | |_) | __/ | | | (_) | (_| | __/\__ \
1878 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1880 ********************************************/
1882 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1883 ir_node *new_op = NULL;
1884 ir_node *node = env->irn;
1885 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1886 ir_node *mem = new_rd_NoMem(env->irg);
1887 ir_node *ptr = get_irn_n(node, 0);
1888 entity *ent = be_get_frame_entity(node);
1889 ir_mode *mode = env->mode;
1891 // /* If the StackParam has only one user -> */
1892 // /* put it in the Block where the user resides */
1893 // if (get_irn_n_edges(node) == 1) {
1894 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1897 if (mode_is_float(mode)) {
1899 if (USE_SSE2(env->cg))
1900 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1902 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1905 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1908 set_ia32_frame_ent(new_op, ent);
1909 set_ia32_use_frame(new_op);
1911 set_ia32_am_support(new_op, ia32_am_Source);
1912 set_ia32_op_type(new_op, ia32_AddrModeS);
1913 set_ia32_am_flavour(new_op, ia32_B);
1914 set_ia32_ls_mode(new_op, mode);
1916 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1918 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1922 * Transforms a FrameAddr into an ia32 Add.
1924 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1925 ir_node *new_op = NULL;
1926 ir_node *node = env->irn;
1927 ir_node *op = get_irn_n(node, 0);
1928 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1929 ir_node *nomem = new_rd_NoMem(env->irg);
1931 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
1932 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1933 set_ia32_am_support(new_op, ia32_am_Full);
1934 set_ia32_use_frame(new_op);
1935 set_ia32_immop_type(new_op, ia32_ImmConst);
1936 set_ia32_commutative(new_op);
1938 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1940 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
1944 * Transforms a FrameLoad into an ia32 Load.
1946 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1947 ir_node *new_op = NULL;
1948 ir_node *node = env->irn;
1949 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1950 ir_node *mem = get_irn_n(node, 0);
1951 ir_node *ptr = get_irn_n(node, 1);
1952 entity *ent = be_get_frame_entity(node);
1953 ir_mode *mode = get_type_mode(get_entity_type(ent));
1955 if (mode_is_float(mode)) {
1957 if (USE_SSE2(env->cg))
1958 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1960 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1963 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1965 set_ia32_frame_ent(new_op, ent);
1966 set_ia32_use_frame(new_op);
1968 set_ia32_am_support(new_op, ia32_am_Source);
1969 set_ia32_op_type(new_op, ia32_AddrModeS);
1970 set_ia32_am_flavour(new_op, ia32_B);
1971 set_ia32_ls_mode(new_op, mode);
1973 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1980 * Transforms a FrameStore into an ia32 Store.
1982 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
1983 ir_node *new_op = NULL;
1984 ir_node *node = env->irn;
1985 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1986 ir_node *mem = get_irn_n(node, 0);
1987 ir_node *ptr = get_irn_n(node, 1);
1988 ir_node *val = get_irn_n(node, 2);
1989 entity *ent = be_get_frame_entity(node);
1990 ir_mode *mode = get_irn_mode(val);
1992 if (mode_is_float(mode)) {
1994 if (USE_SSE2(env->cg))
1995 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1997 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1999 else if (get_mode_size_bits(mode) == 8) {
2000 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2003 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2006 set_ia32_frame_ent(new_op, ent);
2007 set_ia32_use_frame(new_op);
2009 set_ia32_am_support(new_op, ia32_am_Dest);
2010 set_ia32_op_type(new_op, ia32_AddrModeD);
2011 set_ia32_am_flavour(new_op, ia32_B);
2012 set_ia32_ls_mode(new_op, mode);
2014 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2020 * This function just sets the register for the Unknown node
2021 * as this is not done during register allocation because Unknown
2022 * is an "ignore" node.
2024 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2025 ir_mode *mode = env->mode;
2026 ir_node *irn = env->irn;
2028 if (mode_is_float(mode)) {
2029 if (USE_SSE2(env->cg))
2030 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2032 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2034 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2035 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2038 assert(0 && "unsupported Unknown-Mode");
2045 /*********************************************************
2048 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2049 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2050 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2051 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2053 *********************************************************/
2056 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2057 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2059 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2060 ia32_transform_env_t tenv;
2061 ir_node *in1, *in2, *noreg, *nomem, *res;
2062 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2064 /* Return if AM node or not a Sub or xSub */
2065 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2068 noreg = ia32_new_NoReg_gp(cg);
2069 nomem = new_rd_NoMem(cg->irg);
2070 in1 = get_irn_n(irn, 2);
2071 in2 = get_irn_n(irn, 3);
2072 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2073 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2074 out_reg = get_ia32_out_reg(irn, 0);
2076 tenv.block = get_nodes_block(irn);
2077 tenv.dbg = get_irn_dbg_info(irn);
2080 tenv.mode = get_ia32_res_mode(irn);
2082 DEBUG_ONLY(tenv.mod = cg->mod;)
2084 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2085 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2086 /* generate the neg src2 */
2087 res = gen_Minus_ex(&tenv, in2);
2088 arch_set_irn_register(cg->arch_env, res, in2_reg);
2090 /* add to schedule */
2091 sched_add_before(irn, res);
2093 /* generate the add */
2094 if (mode_is_float(tenv.mode)) {
2095 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2096 set_ia32_am_support(res, ia32_am_Source);
2099 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2100 set_ia32_am_support(res, ia32_am_Full);
2101 set_ia32_commutative(res);
2103 set_ia32_res_mode(res, tenv.mode);
2105 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2107 slots = get_ia32_slots(res);
2110 /* add to schedule */
2111 sched_add_before(irn, res);
2113 /* remove the old sub */
2116 DBG_OPT_SUB2NEGADD(irn, res);
2118 /* exchange the add and the sub */
2124 * Transforms a LEA into an Add if possible
2125 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2127 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2128 ia32_am_flavour_t am_flav;
2130 ir_node *res = NULL;
2131 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2133 ia32_transform_env_t tenv;
2134 const arch_register_t *out_reg, *base_reg, *index_reg;
2137 if (! is_ia32_Lea(irn))
2140 am_flav = get_ia32_am_flavour(irn);
2142 /* only some LEAs can be transformed to an Add */
2143 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2146 noreg = ia32_new_NoReg_gp(cg);
2147 nomem = new_rd_NoMem(cg->irg);
2150 base = get_irn_n(irn, 0);
2151 index = get_irn_n(irn,1);
2153 offs = get_ia32_am_offs(irn);
2155 /* offset has a explicit sign -> we need to skip + */
2156 if (offs && offs[0] == '+')
2159 out_reg = arch_get_irn_register(cg->arch_env, irn);
2160 base_reg = arch_get_irn_register(cg->arch_env, base);
2161 index_reg = arch_get_irn_register(cg->arch_env, index);
2163 tenv.block = get_nodes_block(irn);
2164 tenv.dbg = get_irn_dbg_info(irn);
2167 DEBUG_ONLY(tenv.mod = cg->mod;)
2168 tenv.mode = get_irn_mode(irn);
2171 switch(get_ia32_am_flavour(irn)) {
2173 /* out register must be same as base register */
2174 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2180 /* out register must be same as base register */
2181 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2188 /* out register must be same as index register */
2189 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2196 /* out register must be same as one in register */
2197 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2201 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2206 /* in registers a different from out -> no Add possible */
2213 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2214 arch_set_irn_register(cg->arch_env, res, out_reg);
2215 set_ia32_op_type(res, ia32_Normal);
2216 set_ia32_commutative(res);
2217 set_ia32_res_mode(res, tenv.mode);
2220 set_ia32_cnst(res, offs);
2221 set_ia32_immop_type(res, ia32_ImmConst);
2224 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2226 /* add Add to schedule */
2227 sched_add_before(irn, res);
2229 DBG_OPT_LEA2ADD(irn, res);
2231 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2233 /* add result Proj to schedule */
2234 sched_add_before(irn, res);
2236 /* remove the old LEA */
2239 /* exchange the Add and the LEA */
2244 * the BAD transformer.
2246 static ir_node *bad_transform(ia32_transform_env_t *env) {
2247 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2253 * Enters all transform functions into the generic pointer
2255 void ia32_register_transformers(void) {
2256 ir_op *op_Max, *op_Min, *op_Mulh;
2258 /* first clear the generic function pointer for all ops */
2259 clear_irp_opcodes_generic_func();
2261 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2262 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2309 /* constant transformation happens earlier */
2333 /* set the register for all Unknown nodes */
2336 op_Max = get_op_Max();
2339 op_Min = get_op_Min();
2342 op_Mulh = get_op_Mulh();
2351 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2354 * Transforms the given firm node (and maybe some other related nodes)
2355 * into one or more assembler nodes.
2357 * @param node the firm node
2358 * @param env the debug module
2360 void ia32_transform_node(ir_node *node, void *env) {
2361 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2362 ir_op *op = get_irn_op(node);
2363 ir_node *asm_node = NULL;
2369 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2370 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2371 if (is_Unknown(get_irn_n(node, i)))
2372 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2375 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2376 if (op->ops.generic) {
2377 ia32_transform_env_t tenv;
2378 transform_func *transform = (transform_func *)op->ops.generic;
2380 tenv.block = get_nodes_block(node);
2381 tenv.dbg = get_irn_dbg_info(node);
2382 tenv.irg = current_ir_graph;
2384 tenv.mode = get_irn_mode(node);
2386 DEBUG_ONLY(tenv.mod = cg->mod;)
2388 asm_node = (*transform)(&tenv);
2391 /* exchange nodes if a new one was generated */
2393 exchange(node, asm_node);
2394 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2397 DB((cg->mod, LEVEL_1, "ignored\n"));