2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)
474 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
490 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
493 /* don't do AM if other node inputs depend on the load (via mem-proj) */
494 if(other != NULL && get_nodes_block(other) == block
495 && heights_reachable_in_block(heights, other, load))
501 typedef struct ia32_address_mode_t ia32_address_mode_t;
502 struct ia32_address_mode_t {
506 ia32_op_type_t op_type;
514 static void build_address(ia32_address_mode_t *am, ir_node *node)
516 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
517 ia32_address_t *addr = &am->addr;
526 ir_entity *entity = create_float_const_entity(node);
527 addr->base = noreg_gp;
528 addr->index = noreg_gp;
529 addr->mem = new_NoMem();
530 addr->symconst_ent = entity;
532 am->ls_mode = get_irn_mode(node);
533 am->pinned = op_pin_state_floats;
537 load = get_Proj_pred(node);
538 ptr = get_Load_ptr(load);
539 mem = get_Load_mem(load);
540 new_mem = be_transform_node(mem);
541 am->pinned = get_irn_pinned(load);
542 am->ls_mode = get_Load_mode(load);
543 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
545 /* construct load address */
546 ia32_create_address_mode(addr, ptr, 0);
553 base = be_transform_node(base);
559 index = be_transform_node(index);
567 static void set_address(ir_node *node, ia32_address_t *addr)
569 set_ia32_am_scale(node, addr->scale);
570 set_ia32_am_sc(node, addr->symconst_ent);
571 set_ia32_am_offs_int(node, addr->offset);
572 if(addr->symconst_sign)
573 set_ia32_am_sc_sign(node);
575 set_ia32_use_frame(node);
576 set_ia32_frame_ent(node, addr->frame_entity);
579 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
581 set_address(node, &am->addr);
583 set_ia32_op_type(node, am->op_type);
584 set_ia32_ls_mode(node, am->ls_mode);
585 set_irn_pinned(node, am->pinned);
587 set_ia32_commutative(node);
591 match_commutative = 1 << 0,
592 match_am_and_immediates = 1 << 1,
593 match_no_am = 1 << 2,
594 match_8_bit_am = 1 << 3,
595 match_16_bit_am = 1 << 4,
596 match_no_immediate = 1 << 5,
597 match_force_32bit_op = 1 << 6
600 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
601 ir_node *op1, ir_node *op2, match_flags_t flags)
603 ia32_address_t *addr = &am->addr;
604 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
607 ir_mode *mode = get_irn_mode(op2);
610 int use_am_and_immediates;
612 int mode_bits = get_mode_size_bits(mode);
614 memset(am, 0, sizeof(am[0]));
616 commutative = (flags & match_commutative) != 0;
617 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
618 use_am = ! (flags & match_no_am);
619 use_immediate = !(flags & match_no_immediate);
622 assert(!commutative || op1 != NULL);
624 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
626 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
630 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
631 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
632 build_address(am, op2);
633 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
634 if(mode_is_float(mode)) {
635 new_op2 = ia32_new_NoReg_vfp(env_cg);
639 am->op_type = ia32_AddrModeS;
640 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
641 use_am && use_source_address_mode(block, op1, op2)) {
643 build_address(am, op1);
645 if(mode_is_float(mode)) {
646 noreg = ia32_new_NoReg_vfp(env_cg);
651 if(new_op2 != NULL) {
654 new_op1 = be_transform_node(op2);
656 am->ins_permuted = 1;
658 am->op_type = ia32_AddrModeS;
660 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
662 new_op2 = be_transform_node(op2);
663 am->op_type = ia32_Normal;
664 if(flags & match_force_32bit_op) {
665 am->ls_mode = mode_Iu;
667 am->ls_mode = get_irn_mode(op2);
670 if(addr->base == NULL)
671 addr->base = noreg_gp;
672 if(addr->index == NULL)
673 addr->index = noreg_gp;
674 if(addr->mem == NULL)
675 addr->mem = new_NoMem();
677 am->new_op1 = new_op1;
678 am->new_op2 = new_op2;
679 am->commutative = commutative;
682 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
684 ir_graph *irg = current_ir_graph;
688 if(am->mem_proj == NULL)
691 /* we have to create a mode_T so the old MemProj can attach to us */
692 mode = get_irn_mode(node);
693 load = get_Proj_pred(am->mem_proj);
695 mark_irn_visited(load);
696 be_set_transformed_node(load, node);
699 set_irn_mode(node, mode_T);
700 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
707 * Construct a standard binary operation, set AM and immediate if required.
709 * @param op1 The first operand
710 * @param op2 The second operand
711 * @param func The node constructor function
712 * @return The constructed ia32 node.
714 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
715 construct_binop_func *func, match_flags_t flags)
717 ir_node *block = get_nodes_block(node);
718 ir_node *new_block = be_transform_node(block);
719 ir_graph *irg = current_ir_graph;
720 dbg_info *dbgi = get_irn_dbg_info(node);
722 ia32_address_mode_t am;
723 ia32_address_t *addr = &am.addr;
725 flags |= match_force_32bit_op;
727 match_arguments(&am, block, op1, op2, flags);
729 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
730 am.new_op1, am.new_op2);
731 set_am_attributes(new_node, &am);
732 /* we can't use source address mode anymore when using immediates */
733 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
734 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
735 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
737 new_node = fix_mem_proj(new_node, &am);
744 n_ia32_l_binop_right,
745 n_ia32_l_binop_eflags
747 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
748 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
749 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
750 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
751 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
752 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
755 * Construct a binary operation which also consumes the eflags.
757 * @param node The node to transform
758 * @param func The node constructor function
759 * @param flags The match flags
760 * @return The constructor ia32 node
762 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
765 ir_node *src_block = get_nodes_block(node);
766 ir_node *block = be_transform_node(src_block);
767 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
768 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
769 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
770 ir_node *new_eflags = be_transform_node(eflags);
771 ir_graph *irg = current_ir_graph;
772 dbg_info *dbgi = get_irn_dbg_info(node);
774 ia32_address_mode_t am;
775 ia32_address_t *addr = &am.addr;
777 match_arguments(&am, src_block, op1, op2, flags);
779 new_node = func(dbgi, irg, block, addr->base, addr->index,
780 addr->mem, am.new_op1, am.new_op2, new_eflags);
781 set_am_attributes(new_node, &am);
782 /* we can't use source address mode anymore when using immediates */
783 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
784 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
785 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
787 new_node = fix_mem_proj(new_node, &am);
793 * Construct a standard binary operation, set AM and immediate if required.
795 * @param op1 The first operand
796 * @param op2 The second operand
797 * @param func The node constructor function
798 * @return The constructed ia32 node.
800 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
801 construct_binop_func *func,
804 ir_node *block = get_nodes_block(node);
805 ir_node *new_block = be_transform_node(block);
806 dbg_info *dbgi = get_irn_dbg_info(node);
807 ir_graph *irg = current_ir_graph;
809 ia32_address_mode_t am;
810 ia32_address_t *addr = &am.addr;
812 match_arguments(&am, block, op1, op2, flags);
814 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
815 am.new_op1, am.new_op2);
816 set_am_attributes(new_node, &am);
818 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
820 new_node = fix_mem_proj(new_node, &am);
825 static ir_node *get_fpcw(void)
828 if(initial_fpcw != NULL)
831 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
832 &ia32_fp_cw_regs[REG_FPCW]);
833 initial_fpcw = be_transform_node(fpcw);
839 * Construct a standard binary operation, set AM and immediate if required.
841 * @param op1 The first operand
842 * @param op2 The second operand
843 * @param func The node constructor function
844 * @return The constructed ia32 node.
846 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
847 construct_binop_float_func *func,
850 ir_graph *irg = current_ir_graph;
851 dbg_info *dbgi = get_irn_dbg_info(node);
852 ir_node *block = get_nodes_block(node);
853 ir_node *new_block = be_transform_node(block);
855 ia32_address_mode_t am;
856 ia32_address_t *addr = &am.addr;
858 match_arguments(&am, block, op1, op2, flags);
860 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
861 am.new_op1, am.new_op2, get_fpcw());
862 set_am_attributes(new_node, &am);
864 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
866 new_node = fix_mem_proj(new_node, &am);
872 * Construct a shift/rotate binary operation, sets AM and immediate if required.
874 * @param op1 The first operand
875 * @param op2 The second operand
876 * @param func The node constructor function
877 * @return The constructed ia32 node.
879 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
880 construct_shift_func *func)
882 dbg_info *dbgi = get_irn_dbg_info(node);
883 ir_graph *irg = current_ir_graph;
884 ir_node *block = get_nodes_block(node);
885 ir_node *new_block = be_transform_node(block);
886 ir_node *new_op1 = be_transform_node(op1);
887 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
890 assert(! mode_is_float(get_irn_mode(node))
891 && "Shift/Rotate with float not supported");
893 res = func(dbgi, irg, new_block, new_op1, new_op2);
894 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
896 /* lowered shift instruction may have a dependency operand, handle it here */
897 if (get_irn_arity(node) == 3) {
898 /* we have a dependency */
899 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
900 add_irn_dep(res, new_dep);
908 * Construct a standard unary operation, set AM and immediate if required.
910 * @param op The operand
911 * @param func The node constructor function
912 * @return The constructed ia32 node.
914 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
916 ir_node *block = be_transform_node(get_nodes_block(node));
917 ir_node *new_op = be_transform_node(op);
918 ir_node *new_node = NULL;
919 ir_graph *irg = current_ir_graph;
920 dbg_info *dbgi = get_irn_dbg_info(node);
922 new_node = func(dbgi, irg, block, new_op);
924 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
929 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
930 ia32_address_t *addr)
932 ir_graph *irg = current_ir_graph;
933 ir_node *base = addr->base;
934 ir_node *index = addr->index;
938 base = ia32_new_NoReg_gp(env_cg);
940 base = be_transform_node(base);
944 index = ia32_new_NoReg_gp(env_cg);
946 index = be_transform_node(index);
949 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
950 set_address(res, addr);
955 static int am_has_immediates(const ia32_address_t *addr)
957 return addr->offset != 0 || addr->symconst_ent != NULL
958 || addr->frame_entity || addr->use_frame;
962 * Creates an ia32 Add.
964 * @return the created ia32 Add node
966 static ir_node *gen_Add(ir_node *node) {
967 ir_graph *irg = current_ir_graph;
968 dbg_info *dbgi = get_irn_dbg_info(node);
969 ir_node *block = get_nodes_block(node);
970 ir_node *new_block = be_transform_node(block);
971 ir_node *op1 = get_Add_left(node);
972 ir_node *op2 = get_Add_right(node);
973 ir_mode *mode = get_irn_mode(node);
974 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
977 ir_node *add_immediate_op;
979 ia32_address_mode_t am;
981 if (mode_is_float(mode)) {
982 if (USE_SSE2(env_cg))
983 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
985 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
990 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
991 * 1. Add with immediate -> Lea
992 * 2. Add with possible source address mode -> Add
993 * 3. Otherwise -> Lea
995 memset(&addr, 0, sizeof(addr));
996 ia32_create_address_mode(&addr, node, 1);
997 add_immediate_op = NULL;
999 if(addr.base == NULL && addr.index == NULL) {
1000 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1001 addr.symconst_sign, addr.offset);
1002 add_irn_dep(new_node, get_irg_frame(irg));
1003 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1006 /* add with immediate? */
1007 if(addr.index == NULL) {
1008 add_immediate_op = addr.base;
1009 } else if(addr.base == NULL && addr.scale == 0) {
1010 add_immediate_op = addr.index;
1013 if(add_immediate_op != NULL) {
1014 if(!am_has_immediates(&addr)) {
1015 #ifdef DEBUG_libfirm
1016 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1019 return be_transform_node(add_immediate_op);
1022 new_node = create_lea_from_address(dbgi, new_block, &addr);
1023 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1027 /* test if we can use source address mode */
1028 memset(&am, 0, sizeof(am));
1030 if(use_source_address_mode(block, op2, op1)) {
1031 build_address(&am, op2);
1032 new_op1 = be_transform_node(op1);
1033 } else if(use_source_address_mode(block, op1, op2)) {
1034 build_address(&am, op1);
1035 new_op1 = be_transform_node(op2);
1037 /* construct an Add with source address mode */
1038 if(new_op1 != NULL) {
1039 ia32_address_t *am_addr = &am.addr;
1040 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1041 am_addr->index, am_addr->mem, new_op1, noreg);
1042 set_address(new_node, am_addr);
1043 set_ia32_op_type(new_node, ia32_AddrModeS);
1044 set_ia32_ls_mode(new_node, am.ls_mode);
1045 set_ia32_commutative(new_node);
1046 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1048 new_node = fix_mem_proj(new_node, &am);
1053 /* otherwise construct a lea */
1054 new_node = create_lea_from_address(dbgi, new_block, &addr);
1055 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1060 * Creates an ia32 Mul.
1062 * @return the created ia32 Mul node
1064 static ir_node *gen_Mul(ir_node *node) {
1065 ir_node *op1 = get_Mul_left(node);
1066 ir_node *op2 = get_Mul_right(node);
1067 ir_mode *mode = get_irn_mode(node);
1069 if (mode_is_float(mode)) {
1070 if (USE_SSE2(env_cg))
1071 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1073 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1077 for the lower 32bit of the result it doesn't matter whether we use
1078 signed or unsigned multiplication so we use IMul as it has fewer
1081 return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative);
1085 * Creates an ia32 Mulh.
1086 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1087 * this result while Mul returns the lower 32 bit.
1089 * @return the created ia32 Mulh node
1091 static ir_node *gen_Mulh(ir_node *node) {
1092 ir_node *block = be_transform_node(get_nodes_block(node));
1093 ir_node *op1 = get_irn_n(node, 0);
1094 ir_node *new_op1 = be_transform_node(op1);
1095 ir_node *op2 = get_irn_n(node, 1);
1096 ir_node *new_op2 = be_transform_node(op2);
1097 ir_graph *irg = current_ir_graph;
1098 dbg_info *dbgi = get_irn_dbg_info(node);
1099 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1100 ir_mode *mode = get_irn_mode(node);
1101 ir_node *proj_EDX, *res;
1103 assert(!mode_is_float(mode) && "Mulh with float not supported");
1104 if (mode_is_signed(mode)) {
1105 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
1108 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1112 set_ia32_commutative(res);
1114 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_IMul1OP_EDX);
1122 * Creates an ia32 And.
1124 * @return The created ia32 And node
1126 static ir_node *gen_And(ir_node *node) {
1127 ir_node *op1 = get_And_left(node);
1128 ir_node *op2 = get_And_right(node);
1129 assert(! mode_is_float(get_irn_mode(node)));
1131 /* is it a zero extension? */
1132 if (is_Const(op2)) {
1133 tarval *tv = get_Const_tarval(op2);
1134 long v = get_tarval_long(tv);
1136 if (v == 0xFF || v == 0xFFFF) {
1137 dbg_info *dbgi = get_irn_dbg_info(node);
1138 ir_node *block = get_nodes_block(node);
1145 assert(v == 0xFFFF);
1148 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1154 return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative);
1160 * Creates an ia32 Or.
1162 * @return The created ia32 Or node
1164 static ir_node *gen_Or(ir_node *node) {
1165 ir_node *op1 = get_Or_left(node);
1166 ir_node *op2 = get_Or_right(node);
1168 assert (! mode_is_float(get_irn_mode(node)));
1169 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative);
1175 * Creates an ia32 Eor.
1177 * @return The created ia32 Eor node
1179 static ir_node *gen_Eor(ir_node *node) {
1180 ir_node *op1 = get_Eor_left(node);
1181 ir_node *op2 = get_Eor_right(node);
1183 assert(! mode_is_float(get_irn_mode(node)));
1184 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative);
1189 * Creates an ia32 Sub.
1191 * @return The created ia32 Sub node
1193 static ir_node *gen_Sub(ir_node *node) {
1194 ir_node *op1 = get_Sub_left(node);
1195 ir_node *op2 = get_Sub_right(node);
1196 ir_mode *mode = get_irn_mode(node);
1198 if (mode_is_float(mode)) {
1199 if (USE_SSE2(env_cg))
1200 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1202 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1206 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1210 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1213 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1216 * Generates an ia32 DivMod with additional infrastructure for the
1217 * register allocator if needed.
1219 * @param dividend -no comment- :)
1220 * @param divisor -no comment- :)
1221 * @param dm_flav flavour_Div/Mod/DivMod
1222 * @return The created ia32 DivMod node
1224 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1225 ir_node *divisor, ia32_op_flavour_t dm_flav)
1227 ir_node *block = be_transform_node(get_nodes_block(node));
1228 ir_node *new_dividend = be_transform_node(dividend);
1229 ir_node *new_divisor = be_transform_node(divisor);
1230 ir_graph *irg = current_ir_graph;
1231 dbg_info *dbgi = get_irn_dbg_info(node);
1232 ir_mode *mode = get_irn_mode(node);
1233 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1234 ir_node *res, *proj_div, *proj_mod;
1235 ir_node *sign_extension;
1236 ir_node *mem, *new_mem;
1239 proj_div = proj_mod = NULL;
1243 mem = get_Div_mem(node);
1244 mode = get_Div_resmode(node);
1245 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1246 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1249 mem = get_Mod_mem(node);
1250 mode = get_Mod_resmode(node);
1251 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1252 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1254 case flavour_DivMod:
1255 mem = get_DivMod_mem(node);
1256 mode = get_DivMod_resmode(node);
1257 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1258 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1259 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1262 panic("invalid divmod flavour!");
1264 new_mem = be_transform_node(mem);
1266 if (mode_is_signed(mode)) {
1267 /* in signed mode, we need to sign extend the dividend */
1268 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1269 add_irn_dep(produceval, get_irg_frame(irg));
1270 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1273 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1274 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1275 add_irn_dep(sign_extension, get_irg_frame(irg));
1278 if (mode_is_signed(mode)) {
1279 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1280 new_dividend, sign_extension, new_divisor);
1282 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1283 new_dividend, sign_extension, new_divisor);
1286 set_ia32_exc_label(res, has_exc);
1287 set_irn_pinned(res, get_irn_pinned(node));
1289 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1296 * Wrapper for generate_DivMod. Sets flavour_Mod.
1299 static ir_node *gen_Mod(ir_node *node) {
1300 return generate_DivMod(node, get_Mod_left(node),
1301 get_Mod_right(node), flavour_Mod);
1305 * Wrapper for generate_DivMod. Sets flavour_Div.
1308 static ir_node *gen_Div(ir_node *node) {
1309 return generate_DivMod(node, get_Div_left(node),
1310 get_Div_right(node), flavour_Div);
1314 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1316 static ir_node *gen_DivMod(ir_node *node) {
1317 return generate_DivMod(node, get_DivMod_left(node),
1318 get_DivMod_right(node), flavour_DivMod);
1324 * Creates an ia32 floating Div.
1326 * @return The created ia32 xDiv node
1328 static ir_node *gen_Quot(ir_node *node)
1330 ir_node *op1 = get_Quot_left(node);
1331 ir_node *op2 = get_Quot_right(node);
1333 if (USE_SSE2(env_cg)) {
1334 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1336 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1342 * Creates an ia32 Shl.
1344 * @return The created ia32 Shl node
1346 static ir_node *gen_Shl(ir_node *node) {
1347 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1354 * Creates an ia32 Shr.
1356 * @return The created ia32 Shr node
1358 static ir_node *gen_Shr(ir_node *node) {
1359 return gen_shift_binop(node, get_Shr_left(node),
1360 get_Shr_right(node), new_rd_ia32_Shr);
1366 * Creates an ia32 Sar.
1368 * @return The created ia32 Shrs node
1370 static ir_node *gen_Shrs(ir_node *node) {
1371 ir_node *left = get_Shrs_left(node);
1372 ir_node *right = get_Shrs_right(node);
1373 ir_mode *mode = get_irn_mode(node);
1374 if(is_Const(right) && mode == mode_Is) {
1375 tarval *tv = get_Const_tarval(right);
1376 long val = get_tarval_long(tv);
1378 /* this is a sign extension */
1379 ir_graph *irg = current_ir_graph;
1380 dbg_info *dbgi = get_irn_dbg_info(node);
1381 ir_node *block = be_transform_node(get_nodes_block(node));
1383 ir_node *new_op = be_transform_node(op);
1384 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1385 add_irn_dep(pval, get_irg_frame(irg));
1387 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1391 /* 8 or 16 bit sign extension? */
1392 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1393 ir_node *shl_left = get_Shl_left(left);
1394 ir_node *shl_right = get_Shl_right(left);
1395 if(is_Const(shl_right)) {
1396 tarval *tv1 = get_Const_tarval(right);
1397 tarval *tv2 = get_Const_tarval(shl_right);
1398 if(tv1 == tv2 && tarval_is_long(tv1)) {
1399 long val = get_tarval_long(tv1);
1400 if(val == 16 || val == 24) {
1401 dbg_info *dbgi = get_irn_dbg_info(node);
1402 ir_node *block = get_nodes_block(node);
1412 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1421 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1427 * Creates an ia32 RotL.
1429 * @param op1 The first operator
1430 * @param op2 The second operator
1431 * @return The created ia32 RotL node
1433 static ir_node *gen_RotL(ir_node *node,
1434 ir_node *op1, ir_node *op2) {
1435 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1441 * Creates an ia32 RotR.
1442 * NOTE: There is no RotR with immediate because this would always be a RotL
1443 * "imm-mode_size_bits" which can be pre-calculated.
1445 * @param op1 The first operator
1446 * @param op2 The second operator
1447 * @return The created ia32 RotR node
1449 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1451 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1457 * Creates an ia32 RotR or RotL (depending on the found pattern).
1459 * @return The created ia32 RotL or RotR node
1461 static ir_node *gen_Rot(ir_node *node) {
1462 ir_node *rotate = NULL;
1463 ir_node *op1 = get_Rot_left(node);
1464 ir_node *op2 = get_Rot_right(node);
1466 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1467 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1468 that means we can create a RotR instead of an Add and a RotL */
1470 if (get_irn_op(op2) == op_Add) {
1472 ir_node *left = get_Add_left(add);
1473 ir_node *right = get_Add_right(add);
1474 if (is_Const(right)) {
1475 tarval *tv = get_Const_tarval(right);
1476 ir_mode *mode = get_irn_mode(node);
1477 long bits = get_mode_size_bits(mode);
1479 if (get_irn_op(left) == op_Minus &&
1480 tarval_is_long(tv) &&
1481 get_tarval_long(tv) == bits)
1483 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1484 rotate = gen_RotR(node, op1, get_Minus_op(left));
1489 if (rotate == NULL) {
1490 rotate = gen_RotL(node, op1, op2);
1499 * Transforms a Minus node.
1501 * @return The created ia32 Minus node
1503 static ir_node *gen_Minus(ir_node *node)
1505 ir_node *op = get_Minus_op(node);
1506 ir_node *block = be_transform_node(get_nodes_block(node));
1507 ir_graph *irg = current_ir_graph;
1508 dbg_info *dbgi = get_irn_dbg_info(node);
1509 ir_mode *mode = get_irn_mode(node);
1514 if (mode_is_float(mode)) {
1515 ir_node *new_op = be_transform_node(op);
1516 if (USE_SSE2(env_cg)) {
1517 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1518 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1519 ir_node *nomem = new_rd_NoMem(irg);
1521 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1524 size = get_mode_size_bits(mode);
1525 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1527 set_ia32_am_sc(res, ent);
1528 set_ia32_op_type(res, ia32_AddrModeS);
1529 set_ia32_ls_mode(res, mode);
1531 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1534 res = gen_unop(node, op, new_rd_ia32_Neg);
1537 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1543 * Transforms a Not node.
1545 * @return The created ia32 Not node
1547 static ir_node *gen_Not(ir_node *node) {
1548 ir_node *op = get_Not_op(node);
1549 ir_mode *mode = get_irn_mode(node);
1551 assert(mode != mode_b); /* should be lowered already */
1553 assert (! mode_is_float(get_irn_mode(node)));
1554 return gen_unop(node, op, new_rd_ia32_Not);
1560 * Transforms an Abs node.
1562 * @return The created ia32 Abs node
1564 static ir_node *gen_Abs(ir_node *node)
1566 ir_node *block = be_transform_node(get_nodes_block(node));
1567 ir_node *op = get_Abs_op(node);
1568 ir_node *new_op = be_transform_node(op);
1569 ir_graph *irg = current_ir_graph;
1570 dbg_info *dbgi = get_irn_dbg_info(node);
1571 ir_mode *mode = get_irn_mode(node);
1572 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1573 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1574 ir_node *nomem = new_NoMem();
1579 if (mode_is_float(mode)) {
1580 if (USE_SSE2(env_cg)) {
1581 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1583 size = get_mode_size_bits(mode);
1584 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1586 set_ia32_am_sc(res, ent);
1588 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1590 set_ia32_op_type(res, ia32_AddrModeS);
1591 set_ia32_ls_mode(res, mode);
1593 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1594 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1598 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1599 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1602 add_irn_dep(pval, get_irg_frame(irg));
1603 SET_IA32_ORIG_NODE(sign_extension,
1604 ia32_get_old_node_name(env_cg, node));
1606 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1608 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1610 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1612 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1619 * Transforms a Load.
1621 * @return the created ia32 Load node
1623 static ir_node *gen_Load(ir_node *node) {
1624 ir_node *old_block = get_nodes_block(node);
1625 ir_node *block = be_transform_node(old_block);
1626 ir_node *ptr = get_Load_ptr(node);
1627 ir_node *mem = get_Load_mem(node);
1628 ir_node *new_mem = be_transform_node(mem);
1631 ir_graph *irg = current_ir_graph;
1632 dbg_info *dbgi = get_irn_dbg_info(node);
1633 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1634 ir_mode *mode = get_Load_mode(node);
1637 ia32_address_t addr;
1639 /* construct load address */
1640 memset(&addr, 0, sizeof(addr));
1641 ia32_create_address_mode(&addr, ptr, 0);
1648 base = be_transform_node(base);
1654 index = be_transform_node(index);
1657 if (mode_is_float(mode)) {
1658 if (USE_SSE2(env_cg)) {
1659 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1661 res_mode = mode_xmm;
1663 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1665 res_mode = mode_vfp;
1671 /* create a conv node with address mode for smaller modes */
1672 if(get_mode_size_bits(mode) < 32) {
1673 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1674 new_mem, noreg, mode);
1676 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1681 set_irn_pinned(new_op, get_irn_pinned(node));
1682 set_ia32_op_type(new_op, ia32_AddrModeS);
1683 set_ia32_ls_mode(new_op, mode);
1684 set_address(new_op, &addr);
1686 /* make sure we are scheduled behind the initial IncSP/Barrier
1687 * to avoid spills being placed before it
1689 if (block == get_irg_start_block(irg)) {
1690 add_irn_dep(new_op, get_irg_frame(irg));
1693 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1694 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1699 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1700 ir_node *ptr, ir_mode *mode, ir_node *other)
1707 /* we only use address mode if we're the only user of the load */
1708 if(get_irn_n_edges(node) > 1)
1711 load = get_Proj_pred(node);
1714 if(get_nodes_block(load) != block)
1717 /* Store should be attached to the load */
1718 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1720 /* store should have the same pointer as the load */
1721 if(get_Load_ptr(load) != ptr)
1724 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1725 if(other != NULL && get_nodes_block(other) == block
1726 && heights_reachable_in_block(heights, other, load))
1729 assert(get_Load_mode(load) == mode);
1734 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1735 ir_node *mem, ir_node *ptr, ir_mode *mode,
1736 construct_binop_dest_func *func,
1737 construct_binop_dest_func *func8bit,
1740 ir_node *src_block = get_nodes_block(node);
1742 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1743 ir_graph *irg = current_ir_graph;
1747 ia32_address_mode_t am;
1748 ia32_address_t *addr = &am.addr;
1749 memset(&am, 0, sizeof(am));
1751 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1752 build_address(&am, op1);
1753 new_op = create_immediate_or_transform(op2, 0);
1754 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1755 build_address(&am, op2);
1756 new_op = create_immediate_or_transform(op1, 0);
1761 if(addr->base == NULL)
1762 addr->base = noreg_gp;
1763 if(addr->index == NULL)
1764 addr->index = noreg_gp;
1765 if(addr->mem == NULL)
1766 addr->mem = new_NoMem();
1768 dbgi = get_irn_dbg_info(node);
1769 block = be_transform_node(src_block);
1770 if(get_mode_size_bits(mode) == 8) {
1771 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1774 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1777 set_address(new_node, addr);
1778 set_ia32_op_type(new_node, ia32_AddrModeD);
1779 set_ia32_ls_mode(new_node, mode);
1780 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1785 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1786 ir_node *ptr, ir_mode *mode,
1787 construct_unop_dest_func *func)
1789 ir_node *src_block = get_nodes_block(node);
1791 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1792 ir_graph *irg = current_ir_graph;
1795 ia32_address_mode_t am;
1796 ia32_address_t *addr = &am.addr;
1797 memset(&am, 0, sizeof(am));
1799 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1802 build_address(&am, op);
1804 if(addr->base == NULL)
1805 addr->base = noreg_gp;
1806 if(addr->index == NULL)
1807 addr->index = noreg_gp;
1808 if(addr->mem == NULL)
1809 addr->mem = new_NoMem();
1811 dbgi = get_irn_dbg_info(node);
1812 block = be_transform_node(src_block);
1813 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1814 set_address(new_node, addr);
1815 set_ia32_op_type(new_node, ia32_AddrModeD);
1816 set_ia32_ls_mode(new_node, mode);
1817 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1822 static ir_node *try_create_dest_am(ir_node *node) {
1823 ir_node *val = get_Store_value(node);
1824 ir_node *mem = get_Store_mem(node);
1825 ir_node *ptr = get_Store_ptr(node);
1826 ir_mode *mode = get_irn_mode(val);
1831 /* handle only GP modes for now... */
1832 if(!mode_needs_gp_reg(mode))
1835 /* store must be the only user of the val node */
1836 if(get_irn_n_edges(val) > 1)
1839 switch(get_irn_opcode(val)) {
1841 op1 = get_Add_left(val);
1842 op2 = get_Add_right(val);
1843 if(is_Const_1(op2)) {
1844 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1845 new_rd_ia32_IncMem);
1847 } else if(is_Const_Minus_1(op2)) {
1848 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1849 new_rd_ia32_DecMem);
1852 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1853 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1856 op1 = get_Sub_left(val);
1857 op2 = get_Sub_right(val);
1859 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1862 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1863 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1866 op1 = get_And_left(val);
1867 op2 = get_And_right(val);
1868 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1869 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1872 op1 = get_Or_left(val);
1873 op2 = get_Or_right(val);
1874 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1875 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1878 op1 = get_Eor_left(val);
1879 op2 = get_Eor_right(val);
1880 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1881 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1884 op1 = get_Shl_left(val);
1885 op2 = get_Shl_right(val);
1886 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1887 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1890 op1 = get_Shr_left(val);
1891 op2 = get_Shr_right(val);
1892 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1893 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1896 op1 = get_Shrs_left(val);
1897 op2 = get_Shrs_right(val);
1898 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1899 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1902 op1 = get_Rot_left(val);
1903 op2 = get_Rot_right(val);
1904 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1905 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1907 /* TODO: match ROR patterns... */
1909 op1 = get_Minus_op(val);
1910 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1913 /* should be lowered already */
1914 assert(mode != mode_b);
1915 op1 = get_Not_op(val);
1916 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1926 * Transforms a Store.
1928 * @return the created ia32 Store node
1930 static ir_node *gen_Store(ir_node *node) {
1931 ir_node *block = be_transform_node(get_nodes_block(node));
1932 ir_node *ptr = get_Store_ptr(node);
1935 ir_node *val = get_Store_value(node);
1937 ir_node *mem = get_Store_mem(node);
1938 ir_node *new_mem = be_transform_node(mem);
1939 ir_graph *irg = current_ir_graph;
1940 dbg_info *dbgi = get_irn_dbg_info(node);
1941 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1942 ir_mode *mode = get_irn_mode(val);
1944 ia32_address_t addr;
1946 /* check for destination address mode */
1947 new_op = try_create_dest_am(node);
1951 /* construct store address */
1952 memset(&addr, 0, sizeof(addr));
1953 ia32_create_address_mode(&addr, ptr, 0);
1960 base = be_transform_node(base);
1966 index = be_transform_node(index);
1969 if (mode_is_float(mode)) {
1970 new_val = be_transform_node(val);
1971 if (USE_SSE2(env_cg)) {
1972 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1975 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1979 new_val = create_immediate_or_transform(val, 0);
1983 if (get_mode_size_bits(mode) == 8) {
1984 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1987 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1992 set_irn_pinned(new_op, get_irn_pinned(node));
1993 set_ia32_op_type(new_op, ia32_AddrModeD);
1994 set_ia32_ls_mode(new_op, mode);
1996 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1997 set_address(new_op, &addr);
1998 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2003 static ir_node *create_Switch(ir_node *node)
2005 ir_graph *irg = current_ir_graph;
2006 dbg_info *dbgi = get_irn_dbg_info(node);
2007 ir_node *block = be_transform_node(get_nodes_block(node));
2008 ir_node *sel = get_Cond_selector(node);
2009 ir_node *new_sel = be_transform_node(sel);
2011 int switch_min = INT_MAX;
2012 const ir_edge_t *edge;
2014 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2016 /* determine the smallest switch case value */
2017 foreach_out_edge(node, edge) {
2018 ir_node *proj = get_edge_src_irn(edge);
2019 int pn = get_Proj_proj(proj);
2024 if (switch_min != 0) {
2025 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2027 /* if smallest switch case is not 0 we need an additional sub */
2028 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2029 add_ia32_am_offs_int(new_sel, -switch_min);
2030 set_ia32_op_type(new_sel, ia32_AddrModeS);
2032 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2035 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2036 set_ia32_pncode(res, get_Cond_defaultProj(node));
2038 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2043 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2045 ir_graph *irg = current_ir_graph;
2053 /* we have a Cmp as input */
2055 ir_node *pred = get_Proj_pred(node);
2057 flags = be_transform_node(pred);
2058 *pnc_out = get_Proj_proj(node);
2063 /* a mode_b value, we have to compare it against 0 */
2064 dbgi = get_irn_dbg_info(node);
2065 new_block = be_transform_node(get_nodes_block(node));
2066 new_op = be_transform_node(node);
2067 noreg = ia32_new_NoReg_gp(env_cg);
2068 nomem = new_NoMem();
2069 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2070 new_op, new_op, 0, 0);
2071 *pnc_out = pn_Cmp_Lg;
2075 static ir_node *gen_Cond(ir_node *node) {
2076 ir_node *block = get_nodes_block(node);
2077 ir_node *new_block = be_transform_node(block);
2078 ir_graph *irg = current_ir_graph;
2079 dbg_info *dbgi = get_irn_dbg_info(node);
2080 ir_node *sel = get_Cond_selector(node);
2081 ir_mode *sel_mode = get_irn_mode(sel);
2083 ir_node *flags = NULL;
2086 if (sel_mode != mode_b) {
2087 return create_Switch(node);
2090 /* we get flags from a cmp */
2091 flags = get_flags_node(sel, &pnc);
2093 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2094 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2102 * Transforms a CopyB node.
2104 * @return The transformed node.
2106 static ir_node *gen_CopyB(ir_node *node) {
2107 ir_node *block = be_transform_node(get_nodes_block(node));
2108 ir_node *src = get_CopyB_src(node);
2109 ir_node *new_src = be_transform_node(src);
2110 ir_node *dst = get_CopyB_dst(node);
2111 ir_node *new_dst = be_transform_node(dst);
2112 ir_node *mem = get_CopyB_mem(node);
2113 ir_node *new_mem = be_transform_node(mem);
2114 ir_node *res = NULL;
2115 ir_graph *irg = current_ir_graph;
2116 dbg_info *dbgi = get_irn_dbg_info(node);
2117 int size = get_type_size_bytes(get_CopyB_type(node));
2120 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2121 /* then we need the size explicitly in ECX. */
2122 if (size >= 32 * 4) {
2123 rem = size & 0x3; /* size % 4 */
2126 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2128 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2130 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2132 add_irn_dep(res, get_irg_frame(irg));
2134 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2135 /* we misuse the pncode field for the copyb size */
2136 set_ia32_pncode(res, rem);
2138 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2139 set_ia32_pncode(res, size);
2142 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2147 static ir_node *gen_be_Copy(ir_node *node)
2149 ir_node *result = be_duplicate_node(node);
2150 ir_mode *mode = get_irn_mode(result);
2152 if (mode_needs_gp_reg(mode)) {
2153 set_irn_mode(result, mode_Iu);
2160 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2161 * to fold an and into a test node
2163 static int can_fold_test_and(ir_node *node)
2165 const ir_edge_t *edge;
2167 /** we can only have eq and lg projs */
2168 foreach_out_edge(node, edge) {
2169 ir_node *proj = get_edge_src_irn(edge);
2170 pn_Cmp pnc = get_Proj_proj(proj);
2171 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2178 static ir_node *try_create_Test(ir_node *node)
2180 ir_graph *irg = current_ir_graph;
2181 dbg_info *dbgi = get_irn_dbg_info(node);
2182 ir_node *block = get_nodes_block(node);
2183 ir_node *new_block = be_transform_node(block);
2184 ir_node *cmp_left = get_Cmp_left(node);
2185 ir_node *cmp_right = get_Cmp_right(node);
2190 ia32_address_mode_t am;
2191 ia32_address_t *addr = &am.addr;
2194 /* can we use a test instruction? */
2195 if(!is_Const_0(cmp_right))
2198 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2199 can_fold_test_and(node)) {
2200 ir_node *and_left = get_And_left(cmp_left);
2201 ir_node *and_right = get_And_right(cmp_left);
2203 mode = get_irn_mode(and_left);
2207 mode = get_irn_mode(cmp_left);
2212 assert(get_mode_size_bits(mode) <= 32);
2214 match_arguments(&am, block, left, right, match_commutative |
2215 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2217 cmp_unsigned = !mode_is_signed(mode);
2218 if(get_mode_size_bits(mode) == 8) {
2219 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2220 addr->index, addr->mem, am.new_op1,
2221 am.new_op2, am.ins_permuted, cmp_unsigned);
2223 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2224 addr->mem, am.new_op1, am.new_op2,
2225 am.ins_permuted, cmp_unsigned);
2227 set_am_attributes(res, &am);
2228 assert(mode != NULL);
2229 set_ia32_ls_mode(res, mode);
2231 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2233 res = fix_mem_proj(res, &am);
2237 static ir_node *create_Fucom(ir_node *node)
2239 ir_graph *irg = current_ir_graph;
2240 dbg_info *dbgi = get_irn_dbg_info(node);
2241 ir_node *block = get_nodes_block(node);
2242 ir_node *new_block = be_transform_node(block);
2243 ir_node *left = get_Cmp_left(node);
2244 ir_node *new_left = be_transform_node(left);
2245 ir_node *right = get_Cmp_right(node);
2249 if(transform_config.use_fucomi) {
2250 new_right = be_transform_node(right);
2251 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2252 set_ia32_commutative(res);
2253 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2255 if(transform_config.use_ftst && is_Const_null(right)) {
2256 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2258 new_right = be_transform_node(right);
2259 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2263 set_ia32_commutative(res);
2265 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2267 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2268 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2274 static ir_node *create_Ucomi(ir_node *node)
2276 ir_graph *irg = current_ir_graph;
2277 dbg_info *dbgi = get_irn_dbg_info(node);
2278 ir_node *src_block = get_nodes_block(node);
2279 ir_node *new_block = be_transform_node(src_block);
2280 ir_node *left = get_Cmp_left(node);
2281 ir_node *right = get_Cmp_right(node);
2283 ia32_address_mode_t am;
2284 ia32_address_t *addr = &am.addr;
2286 match_arguments(&am, src_block, left, right, match_commutative);
2288 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2289 addr->mem, am.new_op1, am.new_op2,
2291 set_am_attributes(new_node, &am);
2293 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2295 new_node = fix_mem_proj(new_node, &am);
2300 static ir_node *gen_Cmp(ir_node *node)
2302 ir_graph *irg = current_ir_graph;
2303 dbg_info *dbgi = get_irn_dbg_info(node);
2304 ir_node *block = get_nodes_block(node);
2305 ir_node *new_block = be_transform_node(block);
2306 ir_node *left = get_Cmp_left(node);
2307 ir_node *right = get_Cmp_right(node);
2308 ir_mode *cmp_mode = get_irn_mode(left);
2310 ia32_address_mode_t am;
2311 ia32_address_t *addr = &am.addr;
2314 if(mode_is_float(cmp_mode)) {
2315 if (USE_SSE2(env_cg)) {
2316 return create_Ucomi(node);
2318 return create_Fucom(node);
2322 assert(mode_needs_gp_reg(cmp_mode));
2324 /* we prefer the Test instruction where possible except cases where
2325 * we can use SourceAM */
2326 if(!use_source_address_mode(block, left, right) &&
2327 !use_source_address_mode(block, right, left)) {
2328 res = try_create_Test(node);
2333 match_arguments(&am, block, left, right,
2334 match_commutative | match_8_bit_am | match_16_bit_am |
2335 match_am_and_immediates);
2337 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2338 if(get_mode_size_bits(cmp_mode) == 8) {
2339 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2340 addr->mem, am.new_op1, am.new_op2,
2341 am.ins_permuted, cmp_unsigned);
2343 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2344 addr->mem, am.new_op1, am.new_op2,
2345 am.ins_permuted, cmp_unsigned);
2347 set_am_attributes(res, &am);
2348 assert(cmp_mode != NULL);
2349 set_ia32_ls_mode(res, cmp_mode);
2351 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2353 res = fix_mem_proj(res, &am);
2358 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2360 ir_graph *irg = current_ir_graph;
2361 dbg_info *dbgi = get_irn_dbg_info(node);
2362 ir_node *block = get_nodes_block(node);
2363 ir_node *new_block = be_transform_node(block);
2364 ir_node *val_true = get_Psi_val(node, 0);
2365 ir_node *val_false = get_Psi_default(node);
2367 match_flags_t match_flags;
2368 ia32_address_mode_t am;
2369 ia32_address_t *addr;
2371 assert(transform_config.use_cmov);
2372 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2376 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2377 | match_force_32bit_op;
2379 match_arguments(&am, block, val_false, val_true, match_flags);
2381 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2382 addr->mem, am.new_op1, am.new_op2, new_flags,
2383 am.ins_permuted, pnc);
2384 set_am_attributes(new_node, &am);
2386 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2388 new_node = fix_mem_proj(new_node, &am);
2395 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2396 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2399 ir_graph *irg = current_ir_graph;
2400 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2401 ir_node *nomem = new_NoMem();
2404 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2405 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2406 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2407 nomem, res, mode_Bu);
2408 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2414 * Transforms a Psi node into CMov.
2416 * @return The transformed node.
2418 static ir_node *gen_Psi(ir_node *node)
2420 dbg_info *dbgi = get_irn_dbg_info(node);
2421 ir_node *block = get_nodes_block(node);
2422 ir_node *new_block = be_transform_node(block);
2423 ir_node *psi_true = get_Psi_val(node, 0);
2424 ir_node *psi_default = get_Psi_default(node);
2425 ir_node *cond = get_Psi_cond(node, 0);
2426 ir_node *flags = NULL;
2430 assert(get_Psi_n_conds(node) == 1);
2431 assert(get_irn_mode(cond) == mode_b);
2432 assert(mode_needs_gp_reg(get_irn_mode(node)));
2434 flags = get_flags_node(cond, &pnc);
2436 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2437 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2438 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2439 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2441 res = create_CMov(node, flags, pnc);
2448 * Create a conversion from x87 state register to general purpose.
2450 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2451 ir_node *block = be_transform_node(get_nodes_block(node));
2452 ir_node *op = get_Conv_op(node);
2453 ir_node *new_op = be_transform_node(op);
2454 ia32_code_gen_t *cg = env_cg;
2455 ir_graph *irg = current_ir_graph;
2456 dbg_info *dbgi = get_irn_dbg_info(node);
2457 ir_node *noreg = ia32_new_NoReg_gp(cg);
2458 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2459 ir_mode *mode = get_irn_mode(node);
2460 ir_node *fist, *load;
2463 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2464 new_NoMem(), new_op, trunc_mode);
2466 set_irn_pinned(fist, op_pin_state_floats);
2467 set_ia32_use_frame(fist);
2468 set_ia32_op_type(fist, ia32_AddrModeD);
2470 assert(get_mode_size_bits(mode) <= 32);
2471 /* exception we can only store signed 32 bit integers, so for unsigned
2472 we store a 64bit (signed) integer and load the lower bits */
2473 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2474 set_ia32_ls_mode(fist, mode_Ls);
2476 set_ia32_ls_mode(fist, mode_Is);
2478 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2481 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2483 set_irn_pinned(load, op_pin_state_floats);
2484 set_ia32_use_frame(load);
2485 set_ia32_op_type(load, ia32_AddrModeS);
2486 set_ia32_ls_mode(load, mode_Is);
2487 if(get_ia32_ls_mode(fist) == mode_Ls) {
2488 ia32_attr_t *attr = get_ia32_attr(load);
2489 attr->data.need_64bit_stackent = 1;
2491 ia32_attr_t *attr = get_ia32_attr(load);
2492 attr->data.need_32bit_stackent = 1;
2494 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2496 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2500 * Creates a x87 strict Conv by placing a Sore and a Load
2502 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2504 ir_node *block = get_nodes_block(node);
2505 ir_graph *irg = current_ir_graph;
2506 dbg_info *dbgi = get_irn_dbg_info(node);
2507 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2508 ir_node *nomem = new_NoMem();
2509 ir_node *frame = get_irg_frame(irg);
2510 ir_node *store, *load;
2513 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2515 set_ia32_use_frame(store);
2516 set_ia32_op_type(store, ia32_AddrModeD);
2517 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2519 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2521 set_ia32_use_frame(load);
2522 set_ia32_op_type(load, ia32_AddrModeS);
2523 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2525 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2529 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2531 ir_graph *irg = current_ir_graph;
2532 ir_node *start_block = get_irg_start_block(irg);
2533 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2534 symconst, symconst_sign, val);
2535 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2541 * Create a conversion from general purpose to x87 register
2543 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2544 ir_node *src_block = get_nodes_block(node);
2545 ir_node *block = be_transform_node(src_block);
2546 ir_graph *irg = current_ir_graph;
2547 dbg_info *dbgi = get_irn_dbg_info(node);
2548 ir_node *op = get_Conv_op(node);
2553 ir_mode *store_mode;
2559 /* fild can use source AM if the operand is a signed 32bit integer */
2560 if (src_mode == mode_Is) {
2561 ia32_address_mode_t am;
2563 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2564 if (am.op_type == ia32_AddrModeS) {
2565 ia32_address_t *addr = &am.addr;
2567 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2568 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2570 set_am_attributes(fild, &am);
2571 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2573 fix_mem_proj(fild, &am);
2577 new_op = am.new_op2;
2579 new_op = be_transform_node(op);
2582 noreg = ia32_new_NoReg_gp(env_cg);
2583 nomem = new_NoMem();
2584 mode = get_irn_mode(op);
2586 /* first convert to 32 bit signed if necessary */
2587 src_bits = get_mode_size_bits(src_mode);
2588 if (src_bits == 8) {
2589 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2591 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2593 } else if (src_bits < 32) {
2594 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2596 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2600 assert(get_mode_size_bits(mode) == 32);
2603 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2606 set_ia32_use_frame(store);
2607 set_ia32_op_type(store, ia32_AddrModeD);
2608 set_ia32_ls_mode(store, mode_Iu);
2610 /* exception for 32bit unsigned, do a 64bit spill+load */
2611 if(!mode_is_signed(mode)) {
2614 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2616 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2617 get_irg_frame(irg), noreg, nomem,
2620 set_ia32_use_frame(zero_store);
2621 set_ia32_op_type(zero_store, ia32_AddrModeD);
2622 add_ia32_am_offs_int(zero_store, 4);
2623 set_ia32_ls_mode(zero_store, mode_Iu);
2628 store = new_rd_Sync(dbgi, irg, block, 2, in);
2629 store_mode = mode_Ls;
2631 store_mode = mode_Is;
2635 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2637 set_ia32_use_frame(fild);
2638 set_ia32_op_type(fild, ia32_AddrModeS);
2639 set_ia32_ls_mode(fild, store_mode);
2641 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2647 * Crete a conversion from one integer mode into another one
2649 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2650 dbg_info *dbgi, ir_node *block, ir_node *op,
2653 ir_graph *irg = current_ir_graph;
2654 int src_bits = get_mode_size_bits(src_mode);
2655 int tgt_bits = get_mode_size_bits(tgt_mode);
2656 ir_node *new_block = be_transform_node(block);
2657 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2660 ir_mode *smaller_mode;
2662 ia32_address_mode_t am;
2663 ia32_address_t *addr = &am.addr;
2665 if (src_bits < tgt_bits) {
2666 smaller_mode = src_mode;
2667 smaller_bits = src_bits;
2669 smaller_mode = tgt_mode;
2670 smaller_bits = tgt_bits;
2673 memset(&am, 0, sizeof(am));
2674 if(use_source_address_mode(block, op, NULL)) {
2675 build_address(&am, op);
2677 am.op_type = ia32_AddrModeS;
2679 new_op = be_transform_node(op);
2680 am.op_type = ia32_Normal;
2682 if(addr->base == NULL)
2684 if(addr->index == NULL)
2685 addr->index = noreg;
2686 if(addr->mem == NULL)
2687 addr->mem = new_NoMem();
2689 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2690 if (smaller_bits == 8) {
2691 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2692 addr->index, addr->mem, new_op,
2695 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2696 addr->index, addr->mem, new_op,
2700 set_am_attributes(res, &am);
2701 set_ia32_ls_mode(res, smaller_mode);
2702 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2703 res = fix_mem_proj(res, &am);
2709 * Transforms a Conv node.
2711 * @return The created ia32 Conv node
2713 static ir_node *gen_Conv(ir_node *node) {
2714 ir_node *block = get_nodes_block(node);
2715 ir_node *new_block = be_transform_node(block);
2716 ir_node *op = get_Conv_op(node);
2717 ir_node *new_op = NULL;
2718 ir_graph *irg = current_ir_graph;
2719 dbg_info *dbgi = get_irn_dbg_info(node);
2720 ir_mode *src_mode = get_irn_mode(op);
2721 ir_mode *tgt_mode = get_irn_mode(node);
2722 int src_bits = get_mode_size_bits(src_mode);
2723 int tgt_bits = get_mode_size_bits(tgt_mode);
2724 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2725 ir_node *nomem = new_rd_NoMem(irg);
2726 ir_node *res = NULL;
2728 if (src_mode == mode_b) {
2729 assert(mode_is_int(tgt_mode));
2730 /* nothing to do, we already model bools as 0/1 ints */
2731 return be_transform_node(op);
2734 if (src_mode == tgt_mode) {
2735 if (get_Conv_strict(node)) {
2736 if (USE_SSE2(env_cg)) {
2737 /* when we are in SSE mode, we can kill all strict no-op conversion */
2738 return be_transform_node(op);
2741 /* this should be optimized already, but who knows... */
2742 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2743 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2744 return be_transform_node(op);
2748 if (mode_is_float(src_mode)) {
2749 new_op = be_transform_node(op);
2750 /* we convert from float ... */
2751 if (mode_is_float(tgt_mode)) {
2752 if(src_mode == mode_E && tgt_mode == mode_D
2753 && !get_Conv_strict(node)) {
2754 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2759 if (USE_SSE2(env_cg)) {
2760 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2761 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2763 set_ia32_ls_mode(res, tgt_mode);
2765 if(get_Conv_strict(node)) {
2766 res = gen_x87_strict_conv(tgt_mode, new_op);
2767 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2770 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2775 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2776 if (USE_SSE2(env_cg)) {
2777 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2779 set_ia32_ls_mode(res, src_mode);
2781 return gen_x87_fp_to_gp(node);
2785 /* we convert from int ... */
2786 if (mode_is_float(tgt_mode)) {
2788 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2789 if (USE_SSE2(env_cg)) {
2790 new_op = be_transform_node(op);
2791 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2793 set_ia32_ls_mode(res, tgt_mode);
2795 res = gen_x87_gp_to_fp(node, src_mode);
2796 if(get_Conv_strict(node)) {
2797 res = gen_x87_strict_conv(tgt_mode, res);
2798 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2799 ia32_get_old_node_name(env_cg, node));
2803 } else if(tgt_mode == mode_b) {
2804 /* mode_b lowering already took care that we only have 0/1 values */
2805 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2806 src_mode, tgt_mode));
2807 return be_transform_node(op);
2810 if (src_bits == tgt_bits) {
2811 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2812 src_mode, tgt_mode));
2813 return be_transform_node(op);
2816 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2824 static int check_immediate_constraint(long val, char immediate_constraint_type)
2826 switch (immediate_constraint_type) {
2830 return val >= 0 && val <= 32;
2832 return val >= 0 && val <= 63;
2834 return val >= -128 && val <= 127;
2836 return val == 0xff || val == 0xffff;
2838 return val >= 0 && val <= 3;
2840 return val >= 0 && val <= 255;
2842 return val >= 0 && val <= 127;
2846 panic("Invalid immediate constraint found");
2850 static ir_node *try_create_Immediate(ir_node *node,
2851 char immediate_constraint_type)
2854 tarval *offset = NULL;
2855 int offset_sign = 0;
2857 ir_entity *symconst_ent = NULL;
2858 int symconst_sign = 0;
2860 ir_node *cnst = NULL;
2861 ir_node *symconst = NULL;
2864 mode = get_irn_mode(node);
2865 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2869 if(is_Minus(node)) {
2871 node = get_Minus_op(node);
2874 if(is_Const(node)) {
2877 offset_sign = minus;
2878 } else if(is_SymConst(node)) {
2881 symconst_sign = minus;
2882 } else if(is_Add(node)) {
2883 ir_node *left = get_Add_left(node);
2884 ir_node *right = get_Add_right(node);
2885 if(is_Const(left) && is_SymConst(right)) {
2888 symconst_sign = minus;
2889 offset_sign = minus;
2890 } else if(is_SymConst(left) && is_Const(right)) {
2893 symconst_sign = minus;
2894 offset_sign = minus;
2896 } else if(is_Sub(node)) {
2897 ir_node *left = get_Sub_left(node);
2898 ir_node *right = get_Sub_right(node);
2899 if(is_Const(left) && is_SymConst(right)) {
2902 symconst_sign = !minus;
2903 offset_sign = minus;
2904 } else if(is_SymConst(left) && is_Const(right)) {
2907 symconst_sign = minus;
2908 offset_sign = !minus;
2915 offset = get_Const_tarval(cnst);
2916 if(tarval_is_long(offset)) {
2917 val = get_tarval_long(offset);
2919 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2924 if(!check_immediate_constraint(val, immediate_constraint_type))
2927 if(symconst != NULL) {
2928 if(immediate_constraint_type != 0) {
2929 /* we need full 32bits for symconsts */
2933 /* unfortunately the assembler/linker doesn't support -symconst */
2937 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2939 symconst_ent = get_SymConst_entity(symconst);
2941 if(cnst == NULL && symconst == NULL)
2944 if(offset_sign && offset != NULL) {
2945 offset = tarval_neg(offset);
2948 res = create_Immediate(symconst_ent, symconst_sign, val);
2953 static ir_node *create_immediate_or_transform(ir_node *node,
2954 char immediate_constraint_type)
2956 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2957 if (new_node == NULL) {
2958 new_node = be_transform_node(node);
2963 static const arch_register_req_t no_register_req = {
2964 arch_register_req_type_none,
2965 NULL, /* regclass */
2966 NULL, /* limit bitset */
2967 { -1, -1 }, /* same pos */
2968 -1 /* different pos */
2972 * An assembler constraint.
2974 typedef struct constraint_t constraint_t;
2975 struct constraint_t {
2978 const arch_register_req_t **out_reqs;
2980 const arch_register_req_t *req;
2981 unsigned immediate_possible;
2982 char immediate_type;
2985 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2987 int immediate_possible = 0;
2988 char immediate_type = 0;
2989 unsigned limited = 0;
2990 const arch_register_class_t *cls = NULL;
2991 ir_graph *irg = current_ir_graph;
2992 struct obstack *obst = get_irg_obstack(irg);
2993 arch_register_req_t *req;
2994 unsigned *limited_ptr;
2998 /* TODO: replace all the asserts with nice error messages */
3001 /* a memory constraint: no need to do anything in backend about it
3002 * (the dependencies are already respected by the memory edge of
3004 constraint->req = &no_register_req;
3016 assert(cls == NULL ||
3017 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3018 cls = &ia32_reg_classes[CLASS_ia32_gp];
3019 limited |= 1 << REG_EAX;
3022 assert(cls == NULL ||
3023 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3024 cls = &ia32_reg_classes[CLASS_ia32_gp];
3025 limited |= 1 << REG_EBX;
3028 assert(cls == NULL ||
3029 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3030 cls = &ia32_reg_classes[CLASS_ia32_gp];
3031 limited |= 1 << REG_ECX;
3034 assert(cls == NULL ||
3035 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3036 cls = &ia32_reg_classes[CLASS_ia32_gp];
3037 limited |= 1 << REG_EDX;
3040 assert(cls == NULL ||
3041 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3042 cls = &ia32_reg_classes[CLASS_ia32_gp];
3043 limited |= 1 << REG_EDI;
3046 assert(cls == NULL ||
3047 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3048 cls = &ia32_reg_classes[CLASS_ia32_gp];
3049 limited |= 1 << REG_ESI;
3052 case 'q': /* q means lower part of the regs only, this makes no
3053 * difference to Q for us (we only assigne whole registers) */
3054 assert(cls == NULL ||
3055 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3056 cls = &ia32_reg_classes[CLASS_ia32_gp];
3057 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3061 assert(cls == NULL ||
3062 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3063 cls = &ia32_reg_classes[CLASS_ia32_gp];
3064 limited |= 1 << REG_EAX | 1 << REG_EDX;
3067 assert(cls == NULL ||
3068 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3069 cls = &ia32_reg_classes[CLASS_ia32_gp];
3070 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3071 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3078 assert(cls == NULL);
3079 cls = &ia32_reg_classes[CLASS_ia32_gp];
3085 /* TODO: mark values so the x87 simulator knows about t and u */
3086 assert(cls == NULL);
3087 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3092 assert(cls == NULL);
3093 /* TODO: check that sse2 is supported */
3094 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3104 assert(!immediate_possible);
3105 immediate_possible = 1;
3106 immediate_type = *c;
3110 assert(!immediate_possible);
3111 immediate_possible = 1;
3115 assert(!immediate_possible && cls == NULL);
3116 immediate_possible = 1;
3117 cls = &ia32_reg_classes[CLASS_ia32_gp];
3130 assert(constraint->is_in && "can only specify same constraint "
3133 sscanf(c, "%d%n", &same_as, &p);
3141 /* memory constraint no need to do anything in backend about it
3142 * (the dependencies are already respected by the memory edge of
3144 constraint->req = &no_register_req;
3147 case 'E': /* no float consts yet */
3148 case 'F': /* no float consts yet */
3149 case 's': /* makes no sense on x86 */
3150 case 'X': /* we can't support that in firm */
3153 case '<': /* no autodecrement on x86 */
3154 case '>': /* no autoincrement on x86 */
3155 case 'C': /* sse constant not supported yet */
3156 case 'G': /* 80387 constant not supported yet */
3157 case 'y': /* we don't support mmx registers yet */
3158 case 'Z': /* not available in 32 bit mode */
3159 case 'e': /* not available in 32 bit mode */
3160 panic("unsupported asm constraint '%c' found in (%+F)",
3161 *c, current_ir_graph);
3164 panic("unknown asm constraint '%c' found in (%+F)", *c,
3172 const arch_register_req_t *other_constr;
3174 assert(cls == NULL && "same as and register constraint not supported");
3175 assert(!immediate_possible && "same as and immediate constraint not "
3177 assert(same_as < constraint->n_outs && "wrong constraint number in "
3178 "same_as constraint");
3180 other_constr = constraint->out_reqs[same_as];
3182 req = obstack_alloc(obst, sizeof(req[0]));
3183 req->cls = other_constr->cls;
3184 req->type = arch_register_req_type_should_be_same;
3185 req->limited = NULL;
3186 req->other_same[0] = pos;
3187 req->other_same[1] = -1;
3188 req->other_different = -1;
3190 /* switch constraints. This is because in firm we have same_as
3191 * constraints on the output constraints while in the gcc asm syntax
3192 * they are specified on the input constraints */
3193 constraint->req = other_constr;
3194 constraint->out_reqs[same_as] = req;
3195 constraint->immediate_possible = 0;
3199 if(immediate_possible && cls == NULL) {
3200 cls = &ia32_reg_classes[CLASS_ia32_gp];
3202 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3203 assert(cls != NULL);
3205 if(immediate_possible) {
3206 assert(constraint->is_in
3207 && "immediate make no sense for output constraints");
3209 /* todo: check types (no float input on 'r' constrained in and such... */
3212 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3213 limited_ptr = (unsigned*) (req+1);
3215 req = obstack_alloc(obst, sizeof(req[0]));
3217 memset(req, 0, sizeof(req[0]));
3220 req->type = arch_register_req_type_limited;
3221 *limited_ptr = limited;
3222 req->limited = limited_ptr;
3224 req->type = arch_register_req_type_normal;
3228 constraint->req = req;
3229 constraint->immediate_possible = immediate_possible;
3230 constraint->immediate_type = immediate_type;
3233 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3240 panic("Clobbers not supported yet");
3243 static int is_memory_op(const ir_asm_constraint *constraint)
3245 ident *id = constraint->constraint;
3246 const char *str = get_id_str(id);
3249 for(c = str; *c != '\0'; ++c) {
3258 * generates code for a ASM node
3260 static ir_node *gen_ASM(ir_node *node)
3263 ir_graph *irg = current_ir_graph;
3264 ir_node *block = get_nodes_block(node);
3265 ir_node *new_block = be_transform_node(block);
3266 dbg_info *dbgi = get_irn_dbg_info(node);
3270 int n_out_constraints;
3272 const arch_register_req_t **out_reg_reqs;
3273 const arch_register_req_t **in_reg_reqs;
3274 ia32_asm_reg_t *register_map;
3275 unsigned reg_map_size = 0;
3276 struct obstack *obst;
3277 const ir_asm_constraint *in_constraints;
3278 const ir_asm_constraint *out_constraints;
3280 constraint_t parsed_constraint;
3282 arity = get_irn_arity(node);
3283 in = alloca(arity * sizeof(in[0]));
3284 memset(in, 0, arity * sizeof(in[0]));
3286 n_out_constraints = get_ASM_n_output_constraints(node);
3287 n_clobbers = get_ASM_n_clobbers(node);
3288 out_arity = n_out_constraints + n_clobbers;
3290 in_constraints = get_ASM_input_constraints(node);
3291 out_constraints = get_ASM_output_constraints(node);
3292 clobbers = get_ASM_clobbers(node);
3294 /* construct output constraints */
3295 obst = get_irg_obstack(irg);
3296 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3297 parsed_constraint.out_reqs = out_reg_reqs;
3298 parsed_constraint.n_outs = n_out_constraints;
3299 parsed_constraint.is_in = 0;
3301 for(i = 0; i < out_arity; ++i) {
3304 if(i < n_out_constraints) {
3305 const ir_asm_constraint *constraint = &out_constraints[i];
3306 c = get_id_str(constraint->constraint);
3307 parse_asm_constraint(i, &parsed_constraint, c);
3309 if(constraint->pos > reg_map_size)
3310 reg_map_size = constraint->pos;
3312 ident *glob_id = clobbers [i - n_out_constraints];
3313 c = get_id_str(glob_id);
3314 parse_clobber(node, i, &parsed_constraint, c);
3317 out_reg_reqs[i] = parsed_constraint.req;
3320 /* construct input constraints */
3321 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3322 parsed_constraint.is_in = 1;
3323 for(i = 0; i < arity; ++i) {
3324 const ir_asm_constraint *constraint = &in_constraints[i];
3325 ident *constr_id = constraint->constraint;
3326 const char *c = get_id_str(constr_id);
3328 parse_asm_constraint(i, &parsed_constraint, c);
3329 in_reg_reqs[i] = parsed_constraint.req;
3331 if(constraint->pos > reg_map_size)
3332 reg_map_size = constraint->pos;
3334 if(parsed_constraint.immediate_possible) {
3335 ir_node *pred = get_irn_n(node, i);
3336 char imm_type = parsed_constraint.immediate_type;
3337 ir_node *immediate = try_create_Immediate(pred, imm_type);
3339 if(immediate != NULL) {
3346 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3347 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3349 for(i = 0; i < n_out_constraints; ++i) {
3350 const ir_asm_constraint *constraint = &out_constraints[i];
3351 unsigned pos = constraint->pos;
3353 assert(pos < reg_map_size);
3354 register_map[pos].use_input = 0;
3355 register_map[pos].valid = 1;
3356 register_map[pos].memory = is_memory_op(constraint);
3357 register_map[pos].inout_pos = i;
3358 register_map[pos].mode = constraint->mode;
3361 /* transform inputs */
3362 for(i = 0; i < arity; ++i) {
3363 const ir_asm_constraint *constraint = &in_constraints[i];
3364 unsigned pos = constraint->pos;
3365 ir_node *pred = get_irn_n(node, i);
3366 ir_node *transformed;
3368 assert(pos < reg_map_size);
3369 register_map[pos].use_input = 1;
3370 register_map[pos].valid = 1;
3371 register_map[pos].memory = is_memory_op(constraint);
3372 register_map[pos].inout_pos = i;
3373 register_map[pos].mode = constraint->mode;
3378 transformed = be_transform_node(pred);
3379 in[i] = transformed;
3382 res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3383 get_ASM_text(node), register_map);
3385 set_ia32_out_req_all(res, out_reg_reqs);
3386 set_ia32_in_req_all(res, in_reg_reqs);
3388 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3393 /********************************************
3396 * | |__ ___ _ __ ___ __| | ___ ___
3397 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3398 * | |_) | __/ | | | (_) | (_| | __/\__ \
3399 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3401 ********************************************/
3404 * Transforms a FrameAddr into an ia32 Add.
3406 static ir_node *gen_be_FrameAddr(ir_node *node) {
3407 ir_node *block = be_transform_node(get_nodes_block(node));
3408 ir_node *op = be_get_FrameAddr_frame(node);
3409 ir_node *new_op = be_transform_node(op);
3410 ir_graph *irg = current_ir_graph;
3411 dbg_info *dbgi = get_irn_dbg_info(node);
3412 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3415 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3416 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3417 set_ia32_use_frame(res);
3419 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3425 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3427 static ir_node *gen_be_Return(ir_node *node) {
3428 ir_graph *irg = current_ir_graph;
3429 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3430 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3431 ir_entity *ent = get_irg_entity(irg);
3432 ir_type *tp = get_entity_type(ent);
3437 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3438 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3441 int pn_ret_val, pn_ret_mem, arity, i;
3443 assert(ret_val != NULL);
3444 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3445 return be_duplicate_node(node);
3448 res_type = get_method_res_type(tp, 0);
3450 if (! is_Primitive_type(res_type)) {
3451 return be_duplicate_node(node);
3454 mode = get_type_mode(res_type);
3455 if (! mode_is_float(mode)) {
3456 return be_duplicate_node(node);
3459 assert(get_method_n_ress(tp) == 1);
3461 pn_ret_val = get_Proj_proj(ret_val);
3462 pn_ret_mem = get_Proj_proj(ret_mem);
3464 /* get the Barrier */
3465 barrier = get_Proj_pred(ret_val);
3467 /* get result input of the Barrier */
3468 ret_val = get_irn_n(barrier, pn_ret_val);
3469 new_ret_val = be_transform_node(ret_val);
3471 /* get memory input of the Barrier */
3472 ret_mem = get_irn_n(barrier, pn_ret_mem);
3473 new_ret_mem = be_transform_node(ret_mem);
3475 frame = get_irg_frame(irg);
3477 dbgi = get_irn_dbg_info(barrier);
3478 block = be_transform_node(get_nodes_block(barrier));
3480 noreg = ia32_new_NoReg_gp(env_cg);
3482 /* store xmm0 onto stack */
3483 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3484 new_ret_mem, new_ret_val);
3485 set_ia32_ls_mode(sse_store, mode);
3486 set_ia32_op_type(sse_store, ia32_AddrModeD);
3487 set_ia32_use_frame(sse_store);
3489 /* load into x87 register */
3490 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3491 set_ia32_op_type(fld, ia32_AddrModeS);
3492 set_ia32_use_frame(fld);
3494 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3495 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3497 /* create a new barrier */
3498 arity = get_irn_arity(barrier);
3499 in = alloca(arity * sizeof(in[0]));
3500 for (i = 0; i < arity; ++i) {
3503 if (i == pn_ret_val) {
3505 } else if (i == pn_ret_mem) {
3508 ir_node *in = get_irn_n(barrier, i);
3509 new_in = be_transform_node(in);
3514 new_barrier = new_ir_node(dbgi, irg, block,
3515 get_irn_op(barrier), get_irn_mode(barrier),
3517 copy_node_attr(barrier, new_barrier);
3518 be_duplicate_deps(barrier, new_barrier);
3519 be_set_transformed_node(barrier, new_barrier);
3520 mark_irn_visited(barrier);
3522 /* transform normally */
3523 return be_duplicate_node(node);
3527 * Transform a be_AddSP into an ia32_SubSP.
3529 static ir_node *gen_be_AddSP(ir_node *node)
3531 ir_node *src_block = get_nodes_block(node);
3532 ir_node *new_block = be_transform_node(src_block);
3533 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3534 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3535 ir_graph *irg = current_ir_graph;
3536 dbg_info *dbgi = get_irn_dbg_info(node);
3538 ia32_address_mode_t am;
3539 ia32_address_t *addr = &am.addr;
3540 match_flags_t flags = 0;
3542 match_arguments(&am, src_block, sp, sz, flags);
3544 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3545 addr->mem, am.new_op1, am.new_op2);
3546 set_am_attributes(new_node, &am);
3547 /* we can't use source address mode anymore when using immediates */
3548 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3549 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3550 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3552 new_node = fix_mem_proj(new_node, &am);
3558 * Transform a be_SubSP into an ia32_AddSP
3560 static ir_node *gen_be_SubSP(ir_node *node)
3562 ir_node *src_block = get_nodes_block(node);
3563 ir_node *new_block = be_transform_node(src_block);
3564 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3565 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3566 ir_graph *irg = current_ir_graph;
3567 dbg_info *dbgi = get_irn_dbg_info(node);
3569 ia32_address_mode_t am;
3570 ia32_address_t *addr = &am.addr;
3571 match_flags_t flags = 0;
3573 match_arguments(&am, src_block, sp, sz, flags);
3575 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3576 addr->mem, am.new_op1, am.new_op2);
3577 set_am_attributes(new_node, &am);
3578 /* we can't use source address mode anymore when using immediates */
3579 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3580 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3581 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3583 new_node = fix_mem_proj(new_node, &am);
3589 * This function just sets the register for the Unknown node
3590 * as this is not done during register allocation because Unknown
3591 * is an "ignore" node.
3593 static ir_node *gen_Unknown(ir_node *node) {
3594 ir_mode *mode = get_irn_mode(node);
3596 if (mode_is_float(mode)) {
3597 if (USE_SSE2(env_cg)) {
3598 return ia32_new_Unknown_xmm(env_cg);
3600 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3601 ir_graph *irg = current_ir_graph;
3602 dbg_info *dbgi = get_irn_dbg_info(node);
3603 ir_node *block = get_irg_start_block(irg);
3604 return new_rd_ia32_vfldz(dbgi, irg, block);
3606 } else if (mode_needs_gp_reg(mode)) {
3607 return ia32_new_Unknown_gp(env_cg);
3609 assert(0 && "unsupported Unknown-Mode");
3616 * Change some phi modes
3618 static ir_node *gen_Phi(ir_node *node) {
3619 ir_node *block = be_transform_node(get_nodes_block(node));
3620 ir_graph *irg = current_ir_graph;
3621 dbg_info *dbgi = get_irn_dbg_info(node);
3622 ir_mode *mode = get_irn_mode(node);
3625 if(mode_needs_gp_reg(mode)) {
3626 /* we shouldn't have any 64bit stuff around anymore */
3627 assert(get_mode_size_bits(mode) <= 32);
3628 /* all integer operations are on 32bit registers now */
3630 } else if(mode_is_float(mode)) {
3631 if (USE_SSE2(env_cg)) {
3638 /* phi nodes allow loops, so we use the old arguments for now
3639 * and fix this later */
3640 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3641 get_irn_in(node) + 1);
3642 copy_node_attr(node, phi);
3643 be_duplicate_deps(node, phi);
3645 be_set_transformed_node(node, phi);
3646 be_enqueue_preds(node);
3654 static ir_node *gen_IJmp(ir_node *node) {
3655 /* TODO: support AM */
3656 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3660 /**********************************************************************
3663 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3664 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3665 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3666 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3668 **********************************************************************/
3670 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3672 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3675 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3676 ir_node *val, ir_node *mem);
3679 * Transforms a lowered Load into a "real" one.
3681 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3683 ir_node *block = be_transform_node(get_nodes_block(node));
3684 ir_node *ptr = get_irn_n(node, 0);
3685 ir_node *new_ptr = be_transform_node(ptr);
3686 ir_node *mem = get_irn_n(node, 1);
3687 ir_node *new_mem = be_transform_node(mem);
3688 ir_graph *irg = current_ir_graph;
3689 dbg_info *dbgi = get_irn_dbg_info(node);
3690 ir_mode *mode = get_ia32_ls_mode(node);
3691 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3694 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3696 set_ia32_op_type(new_op, ia32_AddrModeS);
3697 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3698 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3699 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3700 if (is_ia32_am_sc_sign(node))
3701 set_ia32_am_sc_sign(new_op);
3702 set_ia32_ls_mode(new_op, mode);
3703 if (is_ia32_use_frame(node)) {
3704 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3705 set_ia32_use_frame(new_op);
3708 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3714 * Transforms a lowered Store into a "real" one.
3716 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3718 ir_node *block = be_transform_node(get_nodes_block(node));
3719 ir_node *ptr = get_irn_n(node, 0);
3720 ir_node *new_ptr = be_transform_node(ptr);
3721 ir_node *val = get_irn_n(node, 1);
3722 ir_node *new_val = be_transform_node(val);
3723 ir_node *mem = get_irn_n(node, 2);
3724 ir_node *new_mem = be_transform_node(mem);
3725 ir_graph *irg = current_ir_graph;
3726 dbg_info *dbgi = get_irn_dbg_info(node);
3727 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3728 ir_mode *mode = get_ia32_ls_mode(node);
3732 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3734 am_offs = get_ia32_am_offs_int(node);
3735 add_ia32_am_offs_int(new_op, am_offs);
3737 set_ia32_op_type(new_op, ia32_AddrModeD);
3738 set_ia32_ls_mode(new_op, mode);
3739 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3740 set_ia32_use_frame(new_op);
3742 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3749 * Transforms an ia32_l_XXX into a "real" XXX node
3751 * @param node The node to transform
3752 * @return the created ia32 XXX node
3754 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3755 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3756 return gen_shift_binop(node, get_irn_n(node, 0), \
3757 get_irn_n(node, 1), new_rd_ia32_##op); \
3760 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3761 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3762 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3764 static ir_node *gen_ia32_l_Add(ir_node *node) {
3765 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3766 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3767 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3769 if(is_Proj(lowered)) {
3770 lowered = get_Proj_pred(lowered);
3772 assert(is_ia32_Add(lowered));
3773 set_irn_mode(lowered, mode_T);
3779 static ir_node *gen_ia32_l_Adc(ir_node *node)
3781 return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative);
3785 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3787 * @param node The node to transform
3788 * @return the created ia32 Neg node
3790 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3791 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3795 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3797 * @param node The node to transform
3798 * @return the created ia32 vfild node
3800 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3801 return gen_lowered_Load(node, new_rd_ia32_vfild);
3805 * Transforms an ia32_l_Load into a "real" ia32_Load node
3807 * @param node The node to transform
3808 * @return the created ia32 Load node
3810 static ir_node *gen_ia32_l_Load(ir_node *node) {
3811 return gen_lowered_Load(node, new_rd_ia32_Load);
3815 * Transforms an ia32_l_Store into a "real" ia32_Store node
3817 * @param node The node to transform
3818 * @return the created ia32 Store node
3820 static ir_node *gen_ia32_l_Store(ir_node *node) {
3821 return gen_lowered_Store(node, new_rd_ia32_Store);
3825 * Transforms a l_vfist into a "real" vfist node.
3827 * @param node The node to transform
3828 * @return the created ia32 vfist node
3830 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3831 ir_node *block = be_transform_node(get_nodes_block(node));
3832 ir_node *ptr = get_irn_n(node, 0);
3833 ir_node *new_ptr = be_transform_node(ptr);
3834 ir_node *val = get_irn_n(node, 1);
3835 ir_node *new_val = be_transform_node(val);
3836 ir_node *mem = get_irn_n(node, 2);
3837 ir_node *new_mem = be_transform_node(mem);
3838 ir_graph *irg = current_ir_graph;
3839 dbg_info *dbgi = get_irn_dbg_info(node);
3840 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3841 ir_mode *mode = get_ia32_ls_mode(node);
3842 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3846 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3847 new_val, trunc_mode);
3849 am_offs = get_ia32_am_offs_int(node);
3850 add_ia32_am_offs_int(new_op, am_offs);
3852 set_ia32_op_type(new_op, ia32_AddrModeD);
3853 set_ia32_ls_mode(new_op, mode);
3854 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3855 set_ia32_use_frame(new_op);
3857 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3863 * Transforms a l_MulS into a "real" MulS node.
3865 * @return the created ia32 Mul node
3867 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3868 ir_node *left = get_binop_left(node);
3869 ir_node *right = get_binop_right(node);
3871 return gen_binop(node, left, right, new_rd_ia32_Mul,
3872 match_commutative | match_no_immediate);
3876 * Transforms a l_IMulS into a "real" IMul1OPS node.
3878 * @return the created ia32 IMul1OP node
3880 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3881 ir_node *left = get_binop_left(node);
3882 ir_node *right = get_binop_right(node);
3884 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3885 match_commutative | match_no_immediate);
3888 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3889 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3890 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3891 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3893 if(is_Proj(lowered)) {
3894 lowered = get_Proj_pred(lowered);
3896 assert(is_ia32_Sub(lowered));
3897 set_irn_mode(lowered, mode_T);
3903 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3904 return gen_binop_flags(node, new_rd_ia32_Sbb, 0);
3908 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3909 * op1 - target to be shifted
3910 * op2 - contains bits to be shifted into target
3912 * Only op3 can be an immediate.
3914 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3915 ir_node *op2, ir_node *count)
3917 ir_node *block = be_transform_node(get_nodes_block(node));
3918 ir_node *new_op = NULL;
3919 ir_graph *irg = current_ir_graph;
3920 dbg_info *dbgi = get_irn_dbg_info(node);
3921 ir_node *new_op1 = be_transform_node(op1);
3922 ir_node *new_op2 = be_transform_node(op2);
3923 ir_node *new_count = create_immediate_or_transform(count, 'I');
3925 /* TODO proper AM support */
3927 if (is_ia32_l_ShlD(node))
3928 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3930 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3932 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3937 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3938 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3939 get_irn_n(node, 1), get_irn_n(node, 2));
3942 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3943 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3944 get_irn_n(node, 1), get_irn_n(node, 2));
3948 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3950 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3951 ir_node *block = be_transform_node(get_nodes_block(node));
3952 ir_node *val = get_irn_n(node, 1);
3953 ir_node *new_val = be_transform_node(val);
3954 ia32_code_gen_t *cg = env_cg;
3955 ir_node *res = NULL;
3956 ir_graph *irg = current_ir_graph;
3958 ir_node *noreg, *new_ptr, *new_mem;
3965 mem = get_irn_n(node, 2);
3966 new_mem = be_transform_node(mem);
3967 ptr = get_irn_n(node, 0);
3968 new_ptr = be_transform_node(ptr);
3969 noreg = ia32_new_NoReg_gp(cg);
3970 dbgi = get_irn_dbg_info(node);
3972 /* Store x87 -> MEM */
3973 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3974 get_ia32_ls_mode(node));
3975 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3976 set_ia32_use_frame(res);
3977 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3978 set_ia32_op_type(res, ia32_AddrModeD);
3980 /* Load MEM -> SSE */
3981 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3982 get_ia32_ls_mode(node));
3983 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3984 set_ia32_use_frame(res);
3985 set_ia32_op_type(res, ia32_AddrModeS);
3986 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3992 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3994 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3995 ir_node *block = be_transform_node(get_nodes_block(node));
3996 ir_node *val = get_irn_n(node, 1);
3997 ir_node *new_val = be_transform_node(val);
3998 ia32_code_gen_t *cg = env_cg;
3999 ir_graph *irg = current_ir_graph;
4000 ir_node *res = NULL;
4001 ir_entity *fent = get_ia32_frame_ent(node);
4002 ir_mode *lsmode = get_ia32_ls_mode(node);
4004 ir_node *noreg, *new_ptr, *new_mem;
4008 if (! USE_SSE2(cg)) {
4009 /* SSE unit is not used -> skip this node. */
4013 ptr = get_irn_n(node, 0);
4014 new_ptr = be_transform_node(ptr);
4015 mem = get_irn_n(node, 2);
4016 new_mem = be_transform_node(mem);
4017 noreg = ia32_new_NoReg_gp(cg);
4018 dbgi = get_irn_dbg_info(node);
4020 /* Store SSE -> MEM */
4021 if (is_ia32_xLoad(skip_Proj(new_val))) {
4022 ir_node *ld = skip_Proj(new_val);
4024 /* we can vfld the value directly into the fpu */
4025 fent = get_ia32_frame_ent(ld);
4026 ptr = get_irn_n(ld, 0);
4027 offs = get_ia32_am_offs_int(ld);
4029 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4031 set_ia32_frame_ent(res, fent);
4032 set_ia32_use_frame(res);
4033 set_ia32_ls_mode(res, lsmode);
4034 set_ia32_op_type(res, ia32_AddrModeD);
4038 /* Load MEM -> x87 */
4039 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4040 set_ia32_frame_ent(res, fent);
4041 set_ia32_use_frame(res);
4042 add_ia32_am_offs_int(res, offs);
4043 set_ia32_op_type(res, ia32_AddrModeS);
4044 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4049 /*********************************************************
4052 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4053 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4054 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4055 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4057 *********************************************************/
4060 * the BAD transformer.
4062 static ir_node *bad_transform(ir_node *node) {
4063 panic("No transform function for %+F available.\n", node);
4068 * Transform the Projs of an AddSP.
4070 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4071 ir_node *block = be_transform_node(get_nodes_block(node));
4072 ir_node *pred = get_Proj_pred(node);
4073 ir_node *new_pred = be_transform_node(pred);
4074 ir_graph *irg = current_ir_graph;
4075 dbg_info *dbgi = get_irn_dbg_info(node);
4076 long proj = get_Proj_proj(node);
4078 if (proj == pn_be_AddSP_sp) {
4079 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4080 pn_ia32_SubSP_stack);
4081 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4083 } else if(proj == pn_be_AddSP_res) {
4084 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4085 pn_ia32_SubSP_addr);
4086 } else if (proj == pn_be_AddSP_M) {
4087 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4091 return new_rd_Unknown(irg, get_irn_mode(node));
4095 * Transform the Projs of a SubSP.
4097 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4098 ir_node *block = be_transform_node(get_nodes_block(node));
4099 ir_node *pred = get_Proj_pred(node);
4100 ir_node *new_pred = be_transform_node(pred);
4101 ir_graph *irg = current_ir_graph;
4102 dbg_info *dbgi = get_irn_dbg_info(node);
4103 long proj = get_Proj_proj(node);
4105 if (proj == pn_be_SubSP_sp) {
4106 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4107 pn_ia32_AddSP_stack);
4108 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4110 } else if (proj == pn_be_SubSP_M) {
4111 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4115 return new_rd_Unknown(irg, get_irn_mode(node));
4119 * Transform and renumber the Projs from a Load.
4121 static ir_node *gen_Proj_Load(ir_node *node) {
4123 ir_node *block = be_transform_node(get_nodes_block(node));
4124 ir_node *pred = get_Proj_pred(node);
4125 ir_graph *irg = current_ir_graph;
4126 dbg_info *dbgi = get_irn_dbg_info(node);
4127 long proj = get_Proj_proj(node);
4130 /* loads might be part of source address mode matches, so we don't
4131 transform the ProjMs yet (with the exception of loads whose result is
4134 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4137 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4139 /* this is needed, because sometimes we have loops that are only
4140 reachable through the ProjM */
4141 be_enqueue_preds(node);
4142 /* do it in 2 steps, to silence firm verifier */
4143 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4144 set_Proj_proj(res, pn_ia32_Load_M);
4148 /* renumber the proj */
4149 new_pred = be_transform_node(pred);
4150 if (is_ia32_Load(new_pred)) {
4151 if (proj == pn_Load_res) {
4152 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4154 } else if (proj == pn_Load_M) {
4155 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4158 } else if(is_ia32_Conv_I2I(new_pred)) {
4159 set_irn_mode(new_pred, mode_T);
4160 if (proj == pn_Load_res) {
4161 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4162 } else if (proj == pn_Load_M) {
4163 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4165 } else if (is_ia32_xLoad(new_pred)) {
4166 if (proj == pn_Load_res) {
4167 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4169 } else if (proj == pn_Load_M) {
4170 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4173 } else if (is_ia32_vfld(new_pred)) {
4174 if (proj == pn_Load_res) {
4175 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4177 } else if (proj == pn_Load_M) {
4178 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4182 /* can happen for ProJMs when source address mode happened for the
4185 /* however it should not be the result proj, as that would mean the
4186 load had multiple users and should not have been used for
4188 if(proj != pn_Load_M) {
4189 panic("internal error: transformed node not a Load");
4191 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4195 return new_rd_Unknown(irg, get_irn_mode(node));
4199 * Transform and renumber the Projs from a DivMod like instruction.
4201 static ir_node *gen_Proj_DivMod(ir_node *node) {
4202 ir_node *block = be_transform_node(get_nodes_block(node));
4203 ir_node *pred = get_Proj_pred(node);
4204 ir_node *new_pred = be_transform_node(pred);
4205 ir_graph *irg = current_ir_graph;
4206 dbg_info *dbgi = get_irn_dbg_info(node);
4207 ir_mode *mode = get_irn_mode(node);
4208 long proj = get_Proj_proj(node);
4210 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4212 switch (get_irn_opcode(pred)) {
4216 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4218 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4226 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4228 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4236 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4237 case pn_DivMod_res_div:
4238 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4239 case pn_DivMod_res_mod:
4240 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4250 return new_rd_Unknown(irg, mode);
4254 * Transform and renumber the Projs from a CopyB.
4256 static ir_node *gen_Proj_CopyB(ir_node *node) {
4257 ir_node *block = be_transform_node(get_nodes_block(node));
4258 ir_node *pred = get_Proj_pred(node);
4259 ir_node *new_pred = be_transform_node(pred);
4260 ir_graph *irg = current_ir_graph;
4261 dbg_info *dbgi = get_irn_dbg_info(node);
4262 ir_mode *mode = get_irn_mode(node);
4263 long proj = get_Proj_proj(node);
4266 case pn_CopyB_M_regular:
4267 if (is_ia32_CopyB_i(new_pred)) {
4268 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4269 } else if (is_ia32_CopyB(new_pred)) {
4270 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4278 return new_rd_Unknown(irg, mode);
4282 * Transform and renumber the Projs from a Quot.
4284 static ir_node *gen_Proj_Quot(ir_node *node) {
4285 ir_node *block = be_transform_node(get_nodes_block(node));
4286 ir_node *pred = get_Proj_pred(node);
4287 ir_node *new_pred = be_transform_node(pred);
4288 ir_graph *irg = current_ir_graph;
4289 dbg_info *dbgi = get_irn_dbg_info(node);
4290 ir_mode *mode = get_irn_mode(node);
4291 long proj = get_Proj_proj(node);
4295 if (is_ia32_xDiv(new_pred)) {
4296 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4297 } else if (is_ia32_vfdiv(new_pred)) {
4298 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4302 if (is_ia32_xDiv(new_pred)) {
4303 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4304 } else if (is_ia32_vfdiv(new_pred)) {
4305 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4313 return new_rd_Unknown(irg, mode);
4317 * Transform the Thread Local Storage Proj.
4319 static ir_node *gen_Proj_tls(ir_node *node) {
4320 ir_node *block = be_transform_node(get_nodes_block(node));
4321 ir_graph *irg = current_ir_graph;
4322 dbg_info *dbgi = NULL;
4323 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4328 static ir_node *gen_be_Call(ir_node *node) {
4329 ir_node *res = be_duplicate_node(node);
4330 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4335 static ir_node *gen_be_IncSP(ir_node *node) {
4336 ir_node *res = be_duplicate_node(node);
4337 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4343 * Transform the Projs from a be_Call.
4345 static ir_node *gen_Proj_be_Call(ir_node *node) {
4346 ir_node *block = be_transform_node(get_nodes_block(node));
4347 ir_node *call = get_Proj_pred(node);
4348 ir_node *new_call = be_transform_node(call);
4349 ir_graph *irg = current_ir_graph;
4350 dbg_info *dbgi = get_irn_dbg_info(node);
4351 ir_type *method_type = be_Call_get_type(call);
4352 int n_res = get_method_n_ress(method_type);
4353 long proj = get_Proj_proj(node);
4354 ir_mode *mode = get_irn_mode(node);
4356 const arch_register_class_t *cls;
4358 /* The following is kinda tricky: If we're using SSE, then we have to
4359 * move the result value of the call in floating point registers to an
4360 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4361 * after the call, we have to make sure to correctly make the
4362 * MemProj and the result Proj use these 2 nodes
4364 if (proj == pn_be_Call_M_regular) {
4365 // get new node for result, are we doing the sse load/store hack?
4366 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4367 ir_node *call_res_new;
4368 ir_node *call_res_pred = NULL;
4370 if (call_res != NULL) {
4371 call_res_new = be_transform_node(call_res);
4372 call_res_pred = get_Proj_pred(call_res_new);
4375 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4376 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4377 pn_be_Call_M_regular);
4379 assert(is_ia32_xLoad(call_res_pred));
4380 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4384 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4385 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4386 && USE_SSE2(env_cg)) {
4388 ir_node *frame = get_irg_frame(irg);
4389 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4391 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4394 /* in case there is no memory output: create one to serialize the copy
4396 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4397 pn_be_Call_M_regular);
4398 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4399 pn_be_Call_first_res);
4401 /* store st(0) onto stack */
4402 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4404 set_ia32_op_type(fstp, ia32_AddrModeD);
4405 set_ia32_use_frame(fstp);
4407 /* load into SSE register */
4408 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4410 set_ia32_op_type(sse_load, ia32_AddrModeS);
4411 set_ia32_use_frame(sse_load);
4413 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4419 /* transform call modes */
4420 if (mode_is_data(mode)) {
4421 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4425 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4429 * Transform the Projs from a Cmp.
4431 static ir_node *gen_Proj_Cmp(ir_node *node)
4433 /* normally Cmps are processed when looking at Cond nodes, but this case
4434 * can happen in complicated Psi conditions */
4435 dbg_info *dbgi = get_irn_dbg_info(node);
4436 ir_node *block = get_nodes_block(node);
4437 ir_node *new_block = be_transform_node(block);
4438 ir_node *cmp = get_Proj_pred(node);
4439 ir_node *new_cmp = be_transform_node(cmp);
4440 long pnc = get_Proj_proj(node);
4443 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4449 * Transform and potentially renumber Proj nodes.
4451 static ir_node *gen_Proj(ir_node *node) {
4452 ir_graph *irg = current_ir_graph;
4453 dbg_info *dbgi = get_irn_dbg_info(node);
4454 ir_node *pred = get_Proj_pred(node);
4455 long proj = get_Proj_proj(node);
4457 if (is_Store(pred)) {
4458 if (proj == pn_Store_M) {
4459 return be_transform_node(pred);
4462 return new_r_Bad(irg);
4464 } else if (is_Load(pred)) {
4465 return gen_Proj_Load(node);
4466 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4467 return gen_Proj_DivMod(node);
4468 } else if (is_CopyB(pred)) {
4469 return gen_Proj_CopyB(node);
4470 } else if (is_Quot(pred)) {
4471 return gen_Proj_Quot(node);
4472 } else if (be_is_SubSP(pred)) {
4473 return gen_Proj_be_SubSP(node);
4474 } else if (be_is_AddSP(pred)) {
4475 return gen_Proj_be_AddSP(node);
4476 } else if (be_is_Call(pred)) {
4477 return gen_Proj_be_Call(node);
4478 } else if (is_Cmp(pred)) {
4479 return gen_Proj_Cmp(node);
4480 } else if (get_irn_op(pred) == op_Start) {
4481 if (proj == pn_Start_X_initial_exec) {
4482 ir_node *block = get_nodes_block(pred);
4485 /* we exchange the ProjX with a jump */
4486 block = be_transform_node(block);
4487 jump = new_rd_Jmp(dbgi, irg, block);
4490 if (node == be_get_old_anchor(anchor_tls)) {
4491 return gen_Proj_tls(node);
4494 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4498 ir_node *new_pred = be_transform_node(pred);
4499 ir_node *block = be_transform_node(get_nodes_block(node));
4500 ir_mode *mode = get_irn_mode(node);
4501 if (mode_needs_gp_reg(mode)) {
4502 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4503 get_Proj_proj(node));
4504 #ifdef DEBUG_libfirm
4505 new_proj->node_nr = node->node_nr;
4511 return be_duplicate_node(node);
4515 * Enters all transform functions into the generic pointer
4517 static void register_transformers(void)
4521 /* first clear the generic function pointer for all ops */
4522 clear_irp_opcodes_generic_func();
4524 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4525 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4563 /* transform ops from intrinsic lowering */
4580 GEN(ia32_l_X87toSSE);
4581 GEN(ia32_l_SSEtoX87);
4587 /* we should never see these nodes */
4602 /* handle generic backend nodes */
4611 op_Mulh = get_op_Mulh();
4620 * Pre-transform all unknown and noreg nodes.
4622 static void ia32_pretransform_node(void *arch_cg) {
4623 ia32_code_gen_t *cg = arch_cg;
4625 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4626 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4627 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4628 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4629 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4630 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4635 * Walker, checks if all ia32 nodes producing more than one result have
4636 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4638 static void add_missing_keep_walker(ir_node *node, void *data)
4641 unsigned found_projs = 0;
4642 const ir_edge_t *edge;
4643 ir_mode *mode = get_irn_mode(node);
4648 if(!is_ia32_irn(node))
4651 n_outs = get_ia32_n_res(node);
4654 if(is_ia32_SwitchJmp(node))
4657 assert(n_outs < (int) sizeof(unsigned) * 8);
4658 foreach_out_edge(node, edge) {
4659 ir_node *proj = get_edge_src_irn(edge);
4660 int pn = get_Proj_proj(proj);
4662 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4663 found_projs |= 1 << pn;
4667 /* are keeps missing? */
4669 for(i = 0; i < n_outs; ++i) {
4672 const arch_register_req_t *req;
4673 const arch_register_class_t *class;
4675 if(found_projs & (1 << i)) {
4679 req = get_ia32_out_req(node, i);
4684 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4688 block = get_nodes_block(node);
4689 in[0] = new_r_Proj(current_ir_graph, block, node,
4690 arch_register_class_mode(class), i);
4691 if(last_keep != NULL) {
4692 be_Keep_add_node(last_keep, class, in[0]);
4694 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4695 if(sched_is_scheduled(node)) {
4696 sched_add_after(node, last_keep);
4703 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4706 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4708 ir_graph *irg = be_get_birg_irg(cg->birg);
4709 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4712 /* do the transformation */
4713 void ia32_transform_graph(ia32_code_gen_t *cg) {
4715 ir_graph *irg = cg->irg;
4717 /* TODO: look at cpu and fill transform config in with that... */
4718 transform_config.use_incdec = 1;
4719 transform_config.use_sse2 = 0;
4720 transform_config.use_ffreep = 0;
4721 transform_config.use_ftst = 0;
4722 transform_config.use_femms = 0;
4723 transform_config.use_fucomi = 1;
4724 transform_config.use_cmov = 1;
4726 register_transformers();
4728 initial_fpcw = NULL;
4730 heights = heights_new(irg);
4731 calculate_non_address_mode_nodes(irg);
4733 /* the transform phase is not safe for CSE (yet) because several nodes get
4734 * attributes set after their creation */
4735 cse_last = get_opt_cse();
4738 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4740 set_opt_cse(cse_last);
4742 free_non_address_mode_nodes();
4743 heights_free(heights);
4747 void ia32_init_transform(void)
4749 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");