2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
91 extern ir_op *get_op_Mulh(void);
93 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
94 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
95 ir_node *op2, ir_node *mem);
97 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
98 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
99 ir_node *op2, ir_node *mem, ir_node *fpcw);
101 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
105 /****************************************************************************************************
107 * | | | | / _| | | (_)
108 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
109 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
110 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
111 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
113 ****************************************************************************************************/
115 static ir_node *try_create_Immediate(ir_node *node,
116 char immediate_constraint_type);
118 static ir_node *create_immediate_or_transform(ir_node *node,
119 char immediate_constraint_type);
122 * Return true if a mode can be stored in the GP register set
124 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
125 if(mode == mode_fpcw)
127 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
131 * Returns 1 if irn is a Const representing 0, 0 otherwise
133 static INLINE int is_ia32_Const_0(ir_node *irn) {
134 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
135 && tarval_is_null(get_ia32_Immop_tarval(irn));
139 * Returns 1 if irn is a Const representing 1, 0 otherwise
141 static INLINE int is_ia32_Const_1(ir_node *irn) {
142 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
143 && tarval_is_one(get_ia32_Immop_tarval(irn));
147 * Collects all Projs of a node into the node array. Index is the projnum.
148 * BEWARE: The caller has to assure the appropriate array size!
150 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
151 const ir_edge_t *edge;
152 assert(get_irn_mode(irn) == mode_T && "need mode_T");
154 memset(projs, 0, size * sizeof(projs[0]));
156 foreach_out_edge(irn, edge) {
157 ir_node *proj = get_edge_src_irn(edge);
158 int proj_proj = get_Proj_proj(proj);
159 assert(proj_proj < size);
160 projs[proj_proj] = proj;
165 * Renumbers the proj having pn_old in the array tp pn_new
166 * and removes the proj from the array.
168 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
169 fprintf(stderr, "Warning: renumber_Proj used!\n");
171 set_Proj_proj(projs[pn_old], pn_new);
172 projs[pn_old] = NULL;
177 * creates a unique ident by adding a number to a tag
179 * @param tag the tag string, must contain a %d if a number
182 static ident *unique_id(const char *tag)
184 static unsigned id = 0;
187 snprintf(str, sizeof(str), tag, ++id);
188 return new_id_from_str(str);
192 * Get a primitive type for a mode.
194 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
196 pmap_entry *e = pmap_find(types, mode);
201 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
202 res = new_type_primitive(new_id_from_str(buf), mode);
203 set_type_alignment_bytes(res, 16);
204 pmap_insert(types, mode, res);
212 * Get an entity that is initialized with a tarval
214 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
216 tarval *tv = get_Const_tarval(cnst);
217 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
222 ir_mode *mode = get_irn_mode(cnst);
223 ir_type *tp = get_Const_type(cnst);
224 if (tp == firm_unknown_type)
225 tp = get_prim_type(cg->isa->types, mode);
227 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
229 set_entity_ld_ident(res, get_entity_ident(res));
230 set_entity_visibility(res, visibility_local);
231 set_entity_variability(res, variability_constant);
232 set_entity_allocation(res, allocation_static);
234 /* we create a new entity here: It's initialization must resist on the
236 rem = current_ir_graph;
237 current_ir_graph = get_const_code_irg();
238 set_atomic_ent_value(res, new_Const_type(tv, tp));
239 current_ir_graph = rem;
241 pmap_insert(cg->isa->tv_ent, tv, res);
249 static int is_Const_0(ir_node *node) {
253 return classify_Const(node) == CNST_NULL;
256 static int is_Const_1(ir_node *node) {
260 return classify_Const(node) == CNST_ONE;
264 * Transforms a Const.
266 static ir_node *gen_Const(ir_node *node) {
267 ir_graph *irg = current_ir_graph;
268 ir_node *old_block = get_nodes_block(node);
269 ir_node *block = be_transform_node(old_block);
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
280 if (! USE_SSE2(env_cg)) {
281 cnst_classify_t clss = classify_Const(node);
283 if (clss == CNST_NULL) {
284 load = new_rd_ia32_vfldz(dbgi, irg, block);
286 } else if (clss == CNST_ONE) {
287 load = new_rd_ia32_vfld1(dbgi, irg, block);
290 floatent = get_entity_for_tv(env_cg, node);
292 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
293 set_ia32_op_type(load, ia32_AddrModeS);
294 set_ia32_am_flavour(load, ia32_am_N);
295 set_ia32_am_sc(load, floatent);
296 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
297 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
299 set_ia32_ls_mode(load, mode);
301 floatent = get_entity_for_tv(env_cg, node);
303 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
304 set_ia32_op_type(load, ia32_AddrModeS);
305 set_ia32_am_flavour(load, ia32_am_N);
306 set_ia32_am_sc(load, floatent);
307 set_ia32_ls_mode(load, mode);
308 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
310 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
313 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
315 /* Const Nodes before the initial IncSP are a bad idea, because
316 * they could be spilled and we have no SP ready at that point yet.
317 * So add a dependency to the initial frame pointer calculation to
318 * avoid that situation.
320 if (get_irg_start_block(irg) == block) {
321 add_irn_dep(load, get_irg_frame(irg));
324 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
327 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
330 if (get_irg_start_block(irg) == block) {
331 add_irn_dep(cnst, get_irg_frame(irg));
334 set_ia32_Const_attr(cnst, node);
335 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
340 return new_r_Bad(irg);
344 * Transforms a SymConst.
346 static ir_node *gen_SymConst(ir_node *node) {
347 ir_graph *irg = current_ir_graph;
348 ir_node *old_block = get_nodes_block(node);
349 ir_node *block = be_transform_node(old_block);
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
355 if (USE_SSE2(env_cg))
356 cnst = new_rd_ia32_xConst(dbgi, irg, block);
358 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
359 //set_ia32_ls_mode(cnst, mode);
360 set_ia32_ls_mode(cnst, mode_E);
362 cnst = new_rd_ia32_Const(dbgi, irg, block);
365 /* Const Nodes before the initial IncSP are a bad idea, because
366 * they could be spilled and we have no SP ready at that point yet
368 if (get_irg_start_block(irg) == block) {
369 add_irn_dep(cnst, get_irg_frame(irg));
372 set_ia32_Const_attr(cnst, node);
373 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
378 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
379 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
380 static const struct {
382 const char *ent_name;
383 const char *cnst_str;
384 } names [ia32_known_const_max] = {
385 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
386 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
387 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
388 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
390 static ir_entity *ent_cache[ia32_known_const_max];
392 const char *tp_name, *ent_name, *cnst_str;
400 ent_name = names[kct].ent_name;
401 if (! ent_cache[kct]) {
402 tp_name = names[kct].tp_name;
403 cnst_str = names[kct].cnst_str;
405 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
407 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
408 tp = new_type_primitive(new_id_from_str(tp_name), mode);
409 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
411 set_entity_ld_ident(ent, get_entity_ident(ent));
412 set_entity_visibility(ent, visibility_local);
413 set_entity_variability(ent, variability_constant);
414 set_entity_allocation(ent, allocation_static);
416 /* we create a new entity here: It's initialization must resist on the
418 rem = current_ir_graph;
419 current_ir_graph = get_const_code_irg();
420 cnst = new_Const(mode, tv);
421 current_ir_graph = rem;
423 set_atomic_ent_value(ent, cnst);
425 /* cache the entry */
426 ent_cache[kct] = ent;
429 return ent_cache[kct];
434 * Prints the old node name on cg obst and returns a pointer to it.
436 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
437 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
439 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
440 obstack_1grow(isa->name_obst, 0);
441 return obstack_finish(isa->name_obst);
445 /* determine if one operator is an Imm */
446 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
448 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
450 return is_ia32_Cnst(op2) ? op2 : NULL;
454 /* determine if one operator is not an Imm */
455 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
456 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
459 static void fold_immediate(ir_node *node, int in1, int in2) {
463 if (!(env_cg->opt & IA32_OPT_IMMOPS))
466 left = get_irn_n(node, in1);
467 right = get_irn_n(node, in2);
468 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
469 /* we can only set right operand to immediate */
470 if(!is_ia32_commutative(node))
472 /* exchange left/right */
473 set_irn_n(node, in1, right);
474 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
475 copy_ia32_Immop_attr(node, left);
476 } else if(is_ia32_Cnst(right)) {
477 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
478 copy_ia32_Immop_attr(node, right);
483 clear_ia32_commutative(node);
484 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
485 get_ia32_am_arity(node));
489 * Construct a standard binary operation, set AM and immediate if required.
491 * @param op1 The first operand
492 * @param op2 The second operand
493 * @param func The node constructor function
494 * @return The constructed ia32 node.
496 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
497 construct_binop_func *func, int commutative)
499 ir_node *block = be_transform_node(get_nodes_block(node));
500 ir_graph *irg = current_ir_graph;
501 dbg_info *dbgi = get_irn_dbg_info(node);
502 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
503 ir_node *nomem = new_NoMem();
506 ir_node *new_op1 = be_transform_node(op1);
507 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
508 if (is_ia32_Immediate(new_op2)) {
512 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
513 if (func == new_rd_ia32_IMul) {
514 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
516 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
519 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
521 set_ia32_commutative(new_node);
528 * Construct a standard binary operation, set AM and immediate if required.
530 * @param op1 The first operand
531 * @param op2 The second operand
532 * @param func The node constructor function
533 * @return The constructed ia32 node.
535 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
536 construct_binop_func *func)
538 ir_node *block = be_transform_node(get_nodes_block(node));
539 ir_node *new_op1 = be_transform_node(op1);
540 ir_node *new_op2 = be_transform_node(op2);
541 ir_node *new_node = NULL;
542 dbg_info *dbgi = get_irn_dbg_info(node);
543 ir_graph *irg = current_ir_graph;
544 ir_mode *mode = get_irn_mode(node);
545 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
546 ir_node *nomem = new_NoMem();
548 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
550 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
551 if (is_op_commutative(get_irn_op(node))) {
552 set_ia32_commutative(new_node);
554 set_ia32_ls_mode(new_node, mode);
556 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
562 * Construct a standard binary operation, set AM and immediate if required.
564 * @param op1 The first operand
565 * @param op2 The second operand
566 * @param func The node constructor function
567 * @return The constructed ia32 node.
569 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
570 construct_binop_float_func *func)
572 ir_node *block = be_transform_node(get_nodes_block(node));
573 ir_node *new_op1 = be_transform_node(op1);
574 ir_node *new_op2 = be_transform_node(op2);
575 ir_node *new_node = NULL;
576 dbg_info *dbgi = get_irn_dbg_info(node);
577 ir_graph *irg = current_ir_graph;
578 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
579 ir_node *nomem = new_NoMem();
580 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
581 &ia32_fp_cw_regs[REG_FPCW]);
583 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
585 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
586 if (is_op_commutative(get_irn_op(node))) {
587 set_ia32_commutative(new_node);
590 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
596 * Construct a shift/rotate binary operation, sets AM and immediate if required.
598 * @param op1 The first operand
599 * @param op2 The second operand
600 * @param func The node constructor function
601 * @return The constructed ia32 node.
603 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
604 construct_binop_func *func)
606 ir_node *block = be_transform_node(get_nodes_block(node));
607 ir_node *new_op1 = be_transform_node(op1);
609 ir_node *new_op = NULL;
610 dbg_info *dbgi = get_irn_dbg_info(node);
611 ir_graph *irg = current_ir_graph;
612 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
613 ir_node *nomem = new_NoMem();
615 assert(! mode_is_float(get_irn_mode(node))
616 && "Shift/Rotate with float not supported");
618 new_op2 = create_immediate_or_transform(op2, 'N');
620 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
623 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
625 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
627 set_ia32_emit_cl(new_op);
634 * Construct a standard unary operation, set AM and immediate if required.
636 * @param op The operand
637 * @param func The node constructor function
638 * @return The constructed ia32 node.
640 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
642 ir_node *block = be_transform_node(get_nodes_block(node));
643 ir_node *new_op = be_transform_node(op);
644 ir_node *new_node = NULL;
645 ir_graph *irg = current_ir_graph;
646 dbg_info *dbgi = get_irn_dbg_info(node);
647 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
648 ir_node *nomem = new_NoMem();
650 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
651 DB((dbg, LEVEL_1, "INT unop ..."));
652 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
654 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
660 * Creates an ia32 Add.
662 * @return the created ia32 Add node
664 static ir_node *gen_Add(ir_node *node) {
665 ir_node *block = be_transform_node(get_nodes_block(node));
666 ir_node *op1 = get_Add_left(node);
667 ir_node *new_op1 = be_transform_node(op1);
668 ir_node *op2 = get_Add_right(node);
669 ir_node *new_op2 = be_transform_node(op2);
670 ir_node *new_op = NULL;
671 ir_graph *irg = current_ir_graph;
672 dbg_info *dbgi = get_irn_dbg_info(node);
673 ir_mode *mode = get_irn_mode(node);
674 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
675 ir_node *nomem = new_NoMem();
676 ir_node *expr_op, *imm_op;
678 /* Check if immediate optimization is on and */
679 /* if it's an operation with immediate. */
680 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
681 expr_op = get_expr_op(new_op1, new_op2);
683 assert((expr_op || imm_op) && "invalid operands");
685 if (mode_is_float(mode)) {
686 if (USE_SSE2(env_cg))
687 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
689 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
694 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
695 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
697 /* No expr_op means, that we have two const - one symconst and */
698 /* one tarval or another symconst - because this case is not */
699 /* covered by constant folding */
700 /* We need to check for: */
701 /* 1) symconst + const -> becomes a LEA */
702 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
703 /* linker doesn't support two symconsts */
705 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
706 /* this is the 2nd case */
707 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
708 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
709 set_ia32_am_flavour(new_op, ia32_am_B);
710 set_ia32_op_type(new_op, ia32_AddrModeS);
712 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
713 } else if (tp1 == ia32_ImmSymConst) {
714 tarval *tv = get_ia32_Immop_tarval(new_op2);
715 long offs = get_tarval_long(tv);
717 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
718 add_irn_dep(new_op, get_irg_frame(irg));
719 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
721 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
722 add_ia32_am_offs_int(new_op, offs);
723 set_ia32_am_flavour(new_op, ia32_am_OB);
724 set_ia32_op_type(new_op, ia32_AddrModeS);
725 } else if (tp2 == ia32_ImmSymConst) {
726 tarval *tv = get_ia32_Immop_tarval(new_op1);
727 long offs = get_tarval_long(tv);
729 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
730 add_irn_dep(new_op, get_irg_frame(irg));
731 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
733 add_ia32_am_offs_int(new_op, offs);
734 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
735 set_ia32_am_flavour(new_op, ia32_am_OB);
736 set_ia32_op_type(new_op, ia32_AddrModeS);
738 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
739 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
740 tarval *restv = tarval_add(tv1, tv2);
742 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
744 new_op = new_rd_ia32_Const(dbgi, irg, block);
745 set_ia32_Const_tarval(new_op, restv);
746 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
752 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
753 tarval_classification_t class_tv, class_negtv;
754 tarval *tv = get_ia32_Immop_tarval(imm_op);
756 /* optimize tarvals */
757 class_tv = classify_tarval(tv);
758 class_negtv = classify_tarval(tarval_neg(tv));
760 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
761 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
762 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
763 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
765 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
766 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
767 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
768 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
774 /* This is a normal add */
775 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
778 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
779 set_ia32_commutative(new_op);
781 fold_immediate(new_op, 2, 3);
783 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
789 * Creates an ia32 Mul.
791 * @return the created ia32 Mul node
793 static ir_node *gen_Mul(ir_node *node) {
794 ir_node *op1 = get_Mul_left(node);
795 ir_node *op2 = get_Mul_right(node);
796 ir_mode *mode = get_irn_mode(node);
798 if (mode_is_float(mode)) {
799 if (USE_SSE2(env_cg))
800 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
802 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
806 for the lower 32bit of the result it doesn't matter whether we use
807 signed or unsigned multiplication so we use IMul as it has fewer
810 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
814 * Creates an ia32 Mulh.
815 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
816 * this result while Mul returns the lower 32 bit.
818 * @return the created ia32 Mulh node
820 static ir_node *gen_Mulh(ir_node *node) {
821 ir_node *block = be_transform_node(get_nodes_block(node));
822 ir_node *op1 = get_irn_n(node, 0);
823 ir_node *new_op1 = be_transform_node(op1);
824 ir_node *op2 = get_irn_n(node, 1);
825 ir_node *new_op2 = be_transform_node(op2);
826 ir_graph *irg = current_ir_graph;
827 dbg_info *dbgi = get_irn_dbg_info(node);
828 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
829 ir_mode *mode = get_irn_mode(node);
830 ir_node *proj_EDX, *res;
832 assert(!mode_is_float(mode) && "Mulh with float not supported");
833 if (mode_is_signed(mode)) {
834 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
835 new_op2, new_NoMem());
837 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
841 set_ia32_commutative(res);
842 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
844 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
852 * Creates an ia32 And.
854 * @return The created ia32 And node
856 static ir_node *gen_And(ir_node *node) {
857 ir_node *op1 = get_And_left(node);
858 ir_node *op2 = get_And_right(node);
860 assert (! mode_is_float(get_irn_mode(node)));
861 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
867 * Creates an ia32 Or.
869 * @return The created ia32 Or node
871 static ir_node *gen_Or(ir_node *node) {
872 ir_node *op1 = get_Or_left(node);
873 ir_node *op2 = get_Or_right(node);
875 assert (! mode_is_float(get_irn_mode(node)));
876 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
882 * Creates an ia32 Eor.
884 * @return The created ia32 Eor node
886 static ir_node *gen_Eor(ir_node *node) {
887 ir_node *op1 = get_Eor_left(node);
888 ir_node *op2 = get_Eor_right(node);
890 assert(! mode_is_float(get_irn_mode(node)));
891 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
896 * Creates an ia32 Sub.
898 * @return The created ia32 Sub node
900 static ir_node *gen_Sub(ir_node *node) {
901 ir_node *block = be_transform_node(get_nodes_block(node));
902 ir_node *op1 = get_Sub_left(node);
903 ir_node *new_op1 = be_transform_node(op1);
904 ir_node *op2 = get_Sub_right(node);
905 ir_node *new_op2 = be_transform_node(op2);
906 ir_node *new_op = NULL;
907 ir_graph *irg = current_ir_graph;
908 dbg_info *dbgi = get_irn_dbg_info(node);
909 ir_mode *mode = get_irn_mode(node);
910 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
911 ir_node *nomem = new_NoMem();
912 ir_node *expr_op, *imm_op;
914 /* Check if immediate optimization is on and */
915 /* if it's an operation with immediate. */
916 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
917 expr_op = get_expr_op(new_op1, new_op2);
919 assert((expr_op || imm_op) && "invalid operands");
921 if (mode_is_float(mode)) {
922 if (USE_SSE2(env_cg))
923 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
925 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
930 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
931 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
933 /* No expr_op means, that we have two const - one symconst and */
934 /* one tarval or another symconst - because this case is not */
935 /* covered by constant folding */
936 /* We need to check for: */
937 /* 1) symconst - const -> becomes a LEA */
938 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
939 /* linker doesn't support two symconsts */
940 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
941 /* this is the 2nd case */
942 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
943 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
944 set_ia32_am_sc_sign(new_op);
945 set_ia32_am_flavour(new_op, ia32_am_B);
947 DBG_OPT_LEA3(op1, op2, node, new_op);
948 } else if (tp1 == ia32_ImmSymConst) {
949 tarval *tv = get_ia32_Immop_tarval(new_op2);
950 long offs = get_tarval_long(tv);
952 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
953 add_irn_dep(new_op, get_irg_frame(irg));
954 DBG_OPT_LEA3(op1, op2, node, new_op);
956 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
957 add_ia32_am_offs_int(new_op, -offs);
958 set_ia32_am_flavour(new_op, ia32_am_OB);
959 set_ia32_op_type(new_op, ia32_AddrModeS);
960 } else if (tp2 == ia32_ImmSymConst) {
961 tarval *tv = get_ia32_Immop_tarval(new_op1);
962 long offs = get_tarval_long(tv);
964 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
965 add_irn_dep(new_op, get_irg_frame(irg));
966 DBG_OPT_LEA3(op1, op2, node, new_op);
968 add_ia32_am_offs_int(new_op, offs);
969 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
970 set_ia32_am_sc_sign(new_op);
971 set_ia32_am_flavour(new_op, ia32_am_OB);
972 set_ia32_op_type(new_op, ia32_AddrModeS);
974 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
975 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
976 tarval *restv = tarval_sub(tv1, tv2);
978 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
980 new_op = new_rd_ia32_Const(dbgi, irg, block);
981 set_ia32_Const_tarval(new_op, restv);
982 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
985 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
988 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
989 tarval_classification_t class_tv, class_negtv;
990 tarval *tv = get_ia32_Immop_tarval(imm_op);
992 /* optimize tarvals */
993 class_tv = classify_tarval(tv);
994 class_negtv = classify_tarval(tarval_neg(tv));
996 if (class_tv == TV_CLASSIFY_ONE) {
997 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
998 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
999 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1001 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1002 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1003 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1004 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1010 /* This is a normal sub */
1011 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1013 /* set AM support */
1014 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1016 fold_immediate(new_op, 2, 3);
1018 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1026 * Generates an ia32 DivMod with additional infrastructure for the
1027 * register allocator if needed.
1029 * @param dividend -no comment- :)
1030 * @param divisor -no comment- :)
1031 * @param dm_flav flavour_Div/Mod/DivMod
1032 * @return The created ia32 DivMod node
1034 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1035 ir_node *divisor, ia32_op_flavour_t dm_flav)
1037 ir_node *block = be_transform_node(get_nodes_block(node));
1038 ir_node *new_dividend = be_transform_node(dividend);
1039 ir_node *new_divisor = be_transform_node(divisor);
1040 ir_graph *irg = current_ir_graph;
1041 dbg_info *dbgi = get_irn_dbg_info(node);
1042 ir_mode *mode = get_irn_mode(node);
1043 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1044 ir_node *res, *proj_div, *proj_mod;
1045 ir_node *sign_extension;
1046 ir_node *mem, *new_mem;
1047 ir_node *projs[pn_DivMod_max];
1050 ia32_collect_Projs(node, projs, pn_DivMod_max);
1052 proj_div = proj_mod = NULL;
1056 mem = get_Div_mem(node);
1057 mode = get_Div_resmode(node);
1058 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1059 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1062 mem = get_Mod_mem(node);
1063 mode = get_Mod_resmode(node);
1064 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1065 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1067 case flavour_DivMod:
1068 mem = get_DivMod_mem(node);
1069 mode = get_DivMod_resmode(node);
1070 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1071 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1072 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1075 panic("invalid divmod flavour!");
1077 new_mem = be_transform_node(mem);
1079 if (mode_is_signed(mode)) {
1080 /* in signed mode, we need to sign extend the dividend */
1081 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1082 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1085 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1086 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1088 add_irn_dep(sign_extension, get_irg_frame(irg));
1091 if (mode_is_signed(mode)) {
1092 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1093 sign_extension, new_divisor, new_mem, dm_flav);
1095 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1096 sign_extension, new_divisor, new_mem, dm_flav);
1099 set_ia32_exc_label(res, has_exc);
1100 set_irn_pinned(res, get_irn_pinned(node));
1101 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1103 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1110 * Wrapper for generate_DivMod. Sets flavour_Mod.
1113 static ir_node *gen_Mod(ir_node *node) {
1114 return generate_DivMod(node, get_Mod_left(node),
1115 get_Mod_right(node), flavour_Mod);
1119 * Wrapper for generate_DivMod. Sets flavour_Div.
1122 static ir_node *gen_Div(ir_node *node) {
1123 return generate_DivMod(node, get_Div_left(node),
1124 get_Div_right(node), flavour_Div);
1128 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1130 static ir_node *gen_DivMod(ir_node *node) {
1131 return generate_DivMod(node, get_DivMod_left(node),
1132 get_DivMod_right(node), flavour_DivMod);
1138 * Creates an ia32 floating Div.
1140 * @return The created ia32 xDiv node
1142 static ir_node *gen_Quot(ir_node *node) {
1143 ir_node *block = be_transform_node(get_nodes_block(node));
1144 ir_node *op1 = get_Quot_left(node);
1145 ir_node *new_op1 = be_transform_node(op1);
1146 ir_node *op2 = get_Quot_right(node);
1147 ir_node *new_op2 = be_transform_node(op2);
1148 ir_graph *irg = current_ir_graph;
1149 dbg_info *dbgi = get_irn_dbg_info(node);
1150 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1151 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1154 if (USE_SSE2(env_cg)) {
1155 ir_mode *mode = get_irn_mode(op1);
1156 if (is_ia32_xConst(new_op2)) {
1157 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1158 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1159 copy_ia32_Immop_attr(new_op, new_op2);
1161 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1162 // Matze: disabled for now, spillslot coalescer fails
1163 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1165 set_ia32_ls_mode(new_op, mode);
1167 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1168 &ia32_fp_cw_regs[REG_FPCW]);
1169 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1170 new_op2, nomem, fpcw);
1171 // Matze: disabled for now (spillslot coalescer fails)
1172 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1174 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1180 * Creates an ia32 Shl.
1182 * @return The created ia32 Shl node
1184 static ir_node *gen_Shl(ir_node *node) {
1185 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1192 * Creates an ia32 Shr.
1194 * @return The created ia32 Shr node
1196 static ir_node *gen_Shr(ir_node *node) {
1197 return gen_shift_binop(node, get_Shr_left(node),
1198 get_Shr_right(node), new_rd_ia32_Shr);
1204 * Creates an ia32 Sar.
1206 * @return The created ia32 Shrs node
1208 static ir_node *gen_Shrs(ir_node *node) {
1209 ir_node *left = get_Shrs_left(node);
1210 ir_node *right = get_Shrs_right(node);
1211 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1212 tarval *tv = get_Const_tarval(right);
1213 long val = get_tarval_long(tv);
1215 /* this is a sign extension */
1216 ir_graph *irg = current_ir_graph;
1217 dbg_info *dbgi = get_irn_dbg_info(node);
1218 ir_node *block = be_transform_node(get_nodes_block(node));
1220 ir_node *new_op = be_transform_node(op);
1221 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1223 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1227 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1233 * Creates an ia32 RotL.
1235 * @param op1 The first operator
1236 * @param op2 The second operator
1237 * @return The created ia32 RotL node
1239 static ir_node *gen_RotL(ir_node *node,
1240 ir_node *op1, ir_node *op2) {
1241 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1247 * Creates an ia32 RotR.
1248 * NOTE: There is no RotR with immediate because this would always be a RotL
1249 * "imm-mode_size_bits" which can be pre-calculated.
1251 * @param op1 The first operator
1252 * @param op2 The second operator
1253 * @return The created ia32 RotR node
1255 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1257 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1263 * Creates an ia32 RotR or RotL (depending on the found pattern).
1265 * @return The created ia32 RotL or RotR node
1267 static ir_node *gen_Rot(ir_node *node) {
1268 ir_node *rotate = NULL;
1269 ir_node *op1 = get_Rot_left(node);
1270 ir_node *op2 = get_Rot_right(node);
1272 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1273 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1274 that means we can create a RotR instead of an Add and a RotL */
1276 if (get_irn_op(op2) == op_Add) {
1278 ir_node *left = get_Add_left(add);
1279 ir_node *right = get_Add_right(add);
1280 if (is_Const(right)) {
1281 tarval *tv = get_Const_tarval(right);
1282 ir_mode *mode = get_irn_mode(node);
1283 long bits = get_mode_size_bits(mode);
1285 if (get_irn_op(left) == op_Minus &&
1286 tarval_is_long(tv) &&
1287 get_tarval_long(tv) == bits)
1289 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1290 rotate = gen_RotR(node, op1, get_Minus_op(left));
1295 if (rotate == NULL) {
1296 rotate = gen_RotL(node, op1, op2);
1305 * Transforms a Minus node.
1307 * @param op The Minus operand
1308 * @return The created ia32 Minus node
1310 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1311 ir_node *block = be_transform_node(get_nodes_block(node));
1312 ir_graph *irg = current_ir_graph;
1313 dbg_info *dbgi = get_irn_dbg_info(node);
1314 ir_mode *mode = get_irn_mode(node);
1319 if (mode_is_float(mode)) {
1320 ir_node *new_op = be_transform_node(op);
1321 if (USE_SSE2(env_cg)) {
1322 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1323 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1324 ir_node *nomem = new_rd_NoMem(irg);
1326 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1328 size = get_mode_size_bits(mode);
1329 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1331 set_ia32_am_sc(res, ent);
1332 set_ia32_op_type(res, ia32_AddrModeS);
1333 set_ia32_ls_mode(res, mode);
1335 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1338 res = gen_unop(node, op, new_rd_ia32_Neg);
1341 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1347 * Transforms a Minus node.
1349 * @return The created ia32 Minus node
1351 static ir_node *gen_Minus(ir_node *node) {
1352 return gen_Minus_ex(node, get_Minus_op(node));
1355 static ir_node *gen_bin_Not(ir_node *node)
1357 ir_graph *irg = current_ir_graph;
1358 dbg_info *dbgi = get_irn_dbg_info(node);
1359 ir_node *block = be_transform_node(get_nodes_block(node));
1360 ir_node *op = get_Not_op(node);
1361 ir_node *new_op = be_transform_node(op);
1362 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1363 ir_node *nomem = new_NoMem();
1364 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1365 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1367 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1371 * Transforms a Not node.
1373 * @return The created ia32 Not node
1375 static ir_node *gen_Not(ir_node *node) {
1376 ir_node *op = get_Not_op(node);
1377 ir_mode *mode = get_irn_mode(node);
1379 if(mode == mode_b) {
1380 return gen_bin_Not(node);
1383 assert (! mode_is_float(get_irn_mode(node)));
1384 return gen_unop(node, op, new_rd_ia32_Not);
1390 * Transforms an Abs node.
1392 * @return The created ia32 Abs node
1394 static ir_node *gen_Abs(ir_node *node) {
1395 ir_node *block = be_transform_node(get_nodes_block(node));
1396 ir_node *op = get_Abs_op(node);
1397 ir_node *new_op = be_transform_node(op);
1398 ir_graph *irg = current_ir_graph;
1399 dbg_info *dbgi = get_irn_dbg_info(node);
1400 ir_mode *mode = get_irn_mode(node);
1401 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1402 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1403 ir_node *nomem = new_NoMem();
1408 if (mode_is_float(mode)) {
1409 if (USE_SSE2(env_cg)) {
1410 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1412 size = get_mode_size_bits(mode);
1413 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1415 set_ia32_am_sc(res, ent);
1417 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1419 set_ia32_op_type(res, ia32_AddrModeS);
1420 set_ia32_ls_mode(res, mode);
1423 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1424 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1428 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1429 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1431 SET_IA32_ORIG_NODE(sign_extension,
1432 ia32_get_old_node_name(env_cg, node));
1434 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1435 sign_extension, nomem);
1436 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1438 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1439 sign_extension, nomem);
1440 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1449 * Transforms a Load.
1451 * @return the created ia32 Load node
1453 static ir_node *gen_Load(ir_node *node) {
1454 ir_node *old_block = get_nodes_block(node);
1455 ir_node *block = be_transform_node(old_block);
1456 ir_node *ptr = get_Load_ptr(node);
1457 ir_node *new_ptr = be_transform_node(ptr);
1458 ir_node *mem = get_Load_mem(node);
1459 ir_node *new_mem = be_transform_node(mem);
1460 ir_graph *irg = current_ir_graph;
1461 dbg_info *dbgi = get_irn_dbg_info(node);
1462 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1463 ir_mode *mode = get_Load_mode(node);
1465 ir_node *lptr = new_ptr;
1468 ia32_am_flavour_t am_flav = ia32_am_B;
1470 /* address might be a constant (symconst or absolute address) */
1471 if (is_ia32_Const(new_ptr)) {
1476 if (mode_is_float(mode)) {
1477 if (USE_SSE2(env_cg)) {
1478 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1479 res_mode = mode_xmm;
1481 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1482 res_mode = mode_vfp;
1485 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1489 /* base is a constant address */
1491 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1492 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1493 am_flav = ia32_am_N;
1495 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1496 long offs = get_tarval_long(tv);
1498 add_ia32_am_offs_int(new_op, offs);
1499 am_flav = ia32_am_O;
1503 set_irn_pinned(new_op, get_irn_pinned(node));
1504 set_ia32_op_type(new_op, ia32_AddrModeS);
1505 set_ia32_am_flavour(new_op, am_flav);
1506 set_ia32_ls_mode(new_op, mode);
1508 /* make sure we are scheduled behind the initial IncSP/Barrier
1509 * to avoid spills being placed before it
1511 if (block == get_irg_start_block(irg)) {
1512 add_irn_dep(new_op, get_irg_frame(irg));
1515 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1516 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1524 * Transforms a Store.
1526 * @return the created ia32 Store node
1528 static ir_node *gen_Store(ir_node *node) {
1529 ir_node *block = be_transform_node(get_nodes_block(node));
1530 ir_node *ptr = get_Store_ptr(node);
1531 ir_node *new_ptr = be_transform_node(ptr);
1532 ir_node *val = get_Store_value(node);
1534 ir_node *mem = get_Store_mem(node);
1535 ir_node *new_mem = be_transform_node(mem);
1536 ir_graph *irg = current_ir_graph;
1537 dbg_info *dbgi = get_irn_dbg_info(node);
1538 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1539 ir_node *sptr = new_ptr;
1540 ir_mode *mode = get_irn_mode(val);
1543 ia32_am_flavour_t am_flav = ia32_am_B;
1545 /* address might be a constant (symconst or absolute address) */
1546 if (is_ia32_Const(new_ptr)) {
1551 if (mode_is_float(mode)) {
1552 new_val = be_transform_node(val);
1553 if (USE_SSE2(env_cg)) {
1554 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1557 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1561 new_val = create_immediate_or_transform(val, 0);
1563 if (get_mode_size_bits(mode) == 8) {
1564 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1567 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1572 /* base is an constant address */
1574 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1575 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1576 am_flav = ia32_am_N;
1578 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1579 long offs = get_tarval_long(tv);
1581 add_ia32_am_offs_int(new_op, offs);
1582 am_flav = ia32_am_O;
1586 set_irn_pinned(new_op, get_irn_pinned(node));
1587 set_ia32_op_type(new_op, ia32_AddrModeD);
1588 set_ia32_am_flavour(new_op, am_flav);
1589 set_ia32_ls_mode(new_op, mode);
1591 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1592 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1597 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1598 ir_node *cmp_left, ir_node *cmp_right)
1600 ir_node *new_cmp_left;
1601 ir_node *new_cmp_right;
1607 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1609 if(cmp_right != NULL && !is_Const_0(cmp_right))
1612 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1613 and_left = get_And_left(cmp_left);
1614 and_right = get_And_right(cmp_left);
1616 new_cmp_left = be_transform_node(and_left);
1617 new_cmp_right = create_immediate_or_transform(and_right, 0);
1619 new_cmp_left = be_transform_node(cmp_left);
1620 new_cmp_right = be_transform_node(cmp_left);
1623 noreg = ia32_new_NoReg_gp(env_cg);
1624 nomem = new_NoMem();
1626 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1627 new_cmp_left, new_cmp_right, nomem, pnc);
1628 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1633 static ir_node *create_Switch(ir_node *node)
1635 ir_graph *irg = current_ir_graph;
1636 dbg_info *dbgi = get_irn_dbg_info(node);
1637 ir_node *block = be_transform_node(get_nodes_block(node));
1638 ir_node *sel = get_Cond_selector(node);
1639 ir_node *new_sel = be_transform_node(sel);
1641 int switch_min = INT_MAX;
1642 const ir_edge_t *edge;
1644 /* determine the smallest switch case value */
1645 foreach_out_edge(node, edge) {
1646 ir_node *proj = get_edge_src_irn(edge);
1647 int pn = get_Proj_proj(proj);
1652 if (switch_min != 0) {
1653 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1655 /* if smallest switch case is not 0 we need an additional sub */
1656 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1657 add_ia32_am_offs_int(new_sel, -switch_min);
1658 set_ia32_am_flavour(new_sel, ia32_am_OB);
1659 set_ia32_op_type(new_sel, ia32_AddrModeS);
1661 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1664 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1665 set_ia32_pncode(res, get_Cond_defaultProj(node));
1667 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1673 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1675 * @return The transformed node.
1677 static ir_node *gen_Cond(ir_node *node) {
1678 ir_node *block = be_transform_node(get_nodes_block(node));
1679 ir_graph *irg = current_ir_graph;
1680 dbg_info *dbgi = get_irn_dbg_info(node);
1681 ir_node *sel = get_Cond_selector(node);
1682 ir_mode *sel_mode = get_irn_mode(sel);
1683 ir_node *res = NULL;
1684 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1691 ir_node *nomem = new_NoMem();
1694 if (sel_mode != mode_b) {
1695 return create_Switch(node);
1698 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1699 /* it's some mode_b value not a direct comparison -> create a testjmp */
1700 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1701 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1705 cmp = get_Proj_pred(sel);
1706 cmp_a = get_Cmp_left(cmp);
1707 cmp_b = get_Cmp_right(cmp);
1708 cmp_mode = get_irn_mode(cmp_a);
1709 pnc = get_Proj_proj(sel);
1710 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1711 pnc |= ia32_pn_Cmp_Unsigned;
1714 if(mode_needs_gp_reg(cmp_mode)) {
1715 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1717 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1722 new_cmp_a = be_transform_node(cmp_a);
1723 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1725 if (mode_is_float(cmp_mode)) {
1726 if (USE_SSE2(env_cg)) {
1727 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1729 set_ia32_commutative(res);
1730 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1731 set_ia32_ls_mode(res, cmp_mode);
1733 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1734 set_ia32_commutative(res);
1737 assert(get_mode_size_bits(cmp_mode) == 32);
1738 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1739 new_cmp_a, new_cmp_b, nomem, pnc);
1740 set_ia32_commutative(res);
1741 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1744 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1752 * Transforms a CopyB node.
1754 * @return The transformed node.
1756 static ir_node *gen_CopyB(ir_node *node) {
1757 ir_node *block = be_transform_node(get_nodes_block(node));
1758 ir_node *src = get_CopyB_src(node);
1759 ir_node *new_src = be_transform_node(src);
1760 ir_node *dst = get_CopyB_dst(node);
1761 ir_node *new_dst = be_transform_node(dst);
1762 ir_node *mem = get_CopyB_mem(node);
1763 ir_node *new_mem = be_transform_node(mem);
1764 ir_node *res = NULL;
1765 ir_graph *irg = current_ir_graph;
1766 dbg_info *dbgi = get_irn_dbg_info(node);
1767 int size = get_type_size_bytes(get_CopyB_type(node));
1770 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1771 /* then we need the size explicitly in ECX. */
1772 if (size >= 32 * 4) {
1773 rem = size & 0x3; /* size % 4 */
1776 res = new_rd_ia32_Const(dbgi, irg, block);
1777 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1778 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1780 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1781 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1783 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1784 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1787 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1793 ir_node *gen_be_Copy(ir_node *node)
1795 ir_node *result = be_duplicate_node(node);
1796 ir_mode *mode = get_irn_mode(result);
1798 if (mode_needs_gp_reg(mode)) {
1799 set_irn_mode(result, mode_Iu);
1806 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1807 dbg_info *dbgi, ir_node *block)
1809 ir_graph *irg = current_ir_graph;
1810 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1811 ir_node *nomem = new_rd_NoMem(irg);
1812 ir_node *new_cmp_left;
1813 ir_node *new_cmp_right;
1816 /* can we use a test instruction? */
1817 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1818 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1819 if(is_And(cmp_left) &&
1820 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1821 ir_node *and_left = get_And_left(cmp_left);
1822 ir_node *and_right = get_And_right(cmp_left);
1824 new_cmp_left = be_transform_node(and_left);
1825 new_cmp_right = create_immediate_or_transform(and_right, 0);
1827 new_cmp_left = be_transform_node(cmp_left);
1828 new_cmp_right = be_transform_node(cmp_left);
1831 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1832 new_cmp_left, new_cmp_right, nomem, pnc);
1833 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1838 new_cmp_left = be_transform_node(cmp_left);
1839 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1840 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1841 new_cmp_left, new_cmp_right, nomem, pnc);
1846 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1847 ir_node *val_true, ir_node *val_false,
1848 dbg_info *dbgi, ir_node *block)
1850 ir_graph *irg = current_ir_graph;
1851 ir_node *new_val_true = be_transform_node(val_true);
1852 ir_node *new_val_false = be_transform_node(val_false);
1853 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1854 ir_node *nomem = new_NoMem();
1855 ir_node *new_cmp_left;
1856 ir_node *new_cmp_right;
1859 /* cmovs with unknowns are pointless... */
1860 if(is_Unknown(val_true)) {
1861 #ifdef DEBUG_libfirm
1862 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1864 return new_val_false;
1866 if(is_Unknown(val_false)) {
1867 #ifdef DEBUG_libfirm
1868 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1870 return new_val_true;
1873 /* can we use a test instruction? */
1874 if(is_Const_0(cmp_right)) {
1875 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1876 if(is_And(cmp_left) &&
1877 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1878 ir_node *and_left = get_And_left(cmp_left);
1879 ir_node *and_right = get_And_right(cmp_left);
1881 new_cmp_left = be_transform_node(and_left);
1882 new_cmp_right = create_immediate_or_transform(and_right, 0);
1884 new_cmp_left = be_transform_node(cmp_left);
1885 new_cmp_right = be_transform_node(cmp_left);
1888 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1889 new_cmp_left, new_cmp_right, nomem,
1890 new_val_true, new_val_false, pnc);
1891 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1896 new_cmp_left = be_transform_node(cmp_left);
1897 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1899 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1900 new_cmp_right, nomem, new_val_true, new_val_false,
1902 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1909 * Transforms a Psi node into CMov.
1911 * @return The transformed node.
1913 static ir_node *gen_Psi(ir_node *node) {
1914 ir_node *psi_true = get_Psi_val(node, 0);
1915 ir_node *psi_default = get_Psi_default(node);
1916 ia32_code_gen_t *cg = env_cg;
1917 ir_node *cond = get_Psi_cond(node, 0);
1918 ir_node *block = be_transform_node(get_nodes_block(node));
1919 dbg_info *dbgi = get_irn_dbg_info(node);
1926 assert(get_Psi_n_conds(node) == 1);
1927 assert(get_irn_mode(cond) == mode_b);
1929 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1930 /* a mode_b value, we have to compare it against 0 */
1932 cmp_right = new_Const_long(mode_Iu, 0);
1936 ir_node *cmp = get_Proj_pred(cond);
1938 cmp_left = get_Cmp_left(cmp);
1939 cmp_right = get_Cmp_right(cmp);
1940 cmp_mode = get_irn_mode(cmp_left);
1941 pnc = get_Proj_proj(cond);
1943 assert(!mode_is_float(cmp_mode));
1945 if (!mode_is_signed(cmp_mode)) {
1946 pnc |= ia32_pn_Cmp_Unsigned;
1950 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1951 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1952 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1953 pnc = get_negated_pnc(pnc, cmp_mode);
1954 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1956 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1959 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1965 * Following conversion rules apply:
1969 * 1) n bit -> m bit n > m (downscale)
1971 * 2) n bit -> m bit n == m (sign change)
1973 * 3) n bit -> m bit n < m (upscale)
1974 * a) source is signed: movsx
1975 * b) source is unsigned: and with lower bits sets
1979 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1983 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1987 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1988 * x87 is mode_E internally, conversions happen only at load and store
1989 * in non-strict semantic
1993 * Create a conversion from x87 state register to general purpose.
1995 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
1996 ir_node *block = be_transform_node(get_nodes_block(node));
1997 ir_node *op = get_Conv_op(node);
1998 ir_node *new_op = be_transform_node(op);
1999 ia32_code_gen_t *cg = env_cg;
2000 ir_graph *irg = current_ir_graph;
2001 dbg_info *dbgi = get_irn_dbg_info(node);
2002 ir_node *noreg = ia32_new_NoReg_gp(cg);
2003 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2004 ir_node *fist, *load;
2007 fist = new_rd_ia32_vfist(dbgi, irg, block,
2008 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2010 set_irn_pinned(fist, op_pin_state_floats);
2011 set_ia32_use_frame(fist);
2012 set_ia32_op_type(fist, ia32_AddrModeD);
2013 set_ia32_am_flavour(fist, ia32_am_B);
2014 set_ia32_ls_mode(fist, mode_Iu);
2015 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2018 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2020 set_irn_pinned(load, op_pin_state_floats);
2021 set_ia32_use_frame(load);
2022 set_ia32_op_type(load, ia32_AddrModeS);
2023 set_ia32_am_flavour(load, ia32_am_B);
2024 set_ia32_ls_mode(load, mode_Iu);
2025 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2027 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2030 static ir_node *create_strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2033 ir_node *block = get_nodes_block(node);
2034 ir_graph *irg = current_ir_graph;
2035 dbg_info *dbgi = get_irn_dbg_info(node);
2036 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2037 ir_node *nomem = new_NoMem();
2038 int src_bits = get_mode_size_bits(src_mode);
2039 int tgt_bits = get_mode_size_bits(tgt_mode);
2040 ir_node *frame = get_irg_frame(irg);
2041 ir_mode *smaller_mode;
2042 ir_node *store, *load;
2045 if(src_bits <= tgt_bits)
2046 smaller_mode = src_mode;
2048 smaller_mode = tgt_mode;
2050 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2052 set_ia32_use_frame(store);
2053 set_ia32_op_type(store, ia32_AddrModeD);
2054 set_ia32_am_flavour(store, ia32_am_OB);
2055 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2057 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2059 set_ia32_use_frame(load);
2060 set_ia32_op_type(load, ia32_AddrModeS);
2061 set_ia32_am_flavour(load, ia32_am_OB);
2062 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2064 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2069 * Create a conversion from general purpose to x87 register
2071 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2072 ir_node *block = be_transform_node(get_nodes_block(node));
2073 ir_node *op = get_Conv_op(node);
2074 ir_node *new_op = be_transform_node(op);
2075 ir_graph *irg = current_ir_graph;
2076 dbg_info *dbgi = get_irn_dbg_info(node);
2077 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2078 ir_node *nomem = new_NoMem();
2079 ir_node *fild, *store;
2083 /* first convert to 32 bit if necessary */
2084 src_bits = get_mode_size_bits(src_mode);
2085 if (src_bits == 8) {
2086 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2087 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2088 set_ia32_ls_mode(new_op, src_mode);
2089 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2090 } else if (src_bits < 32) {
2091 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2092 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2093 set_ia32_ls_mode(new_op, src_mode);
2094 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2098 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2100 set_ia32_use_frame(store);
2101 set_ia32_op_type(store, ia32_AddrModeD);
2102 set_ia32_am_flavour(store, ia32_am_OB);
2103 set_ia32_ls_mode(store, mode_Iu);
2106 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2108 set_ia32_use_frame(fild);
2109 set_ia32_op_type(fild, ia32_AddrModeS);
2110 set_ia32_am_flavour(fild, ia32_am_OB);
2111 set_ia32_ls_mode(fild, mode_Iu);
2113 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2115 if(get_irg_fp_model(irg) & fp_explicit_rounding) {
2116 res = create_strict_conv(mode_E, get_irn_mode(node), res);
2123 * Transforms a Conv node.
2125 * @return The created ia32 Conv node
2127 static ir_node *gen_Conv(ir_node *node) {
2128 ir_node *block = be_transform_node(get_nodes_block(node));
2129 ir_node *op = get_Conv_op(node);
2130 ir_node *new_op = be_transform_node(op);
2131 ir_graph *irg = current_ir_graph;
2132 dbg_info *dbgi = get_irn_dbg_info(node);
2133 ir_mode *src_mode = get_irn_mode(op);
2134 ir_mode *tgt_mode = get_irn_mode(node);
2135 int src_bits = get_mode_size_bits(src_mode);
2136 int tgt_bits = get_mode_size_bits(tgt_mode);
2137 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2138 ir_node *nomem = new_rd_NoMem(irg);
2141 if (src_mode == mode_b) {
2142 assert(mode_is_int(tgt_mode));
2143 /* nothing to do, we already model bools as 0/1 ints */
2147 if (src_mode == tgt_mode) {
2148 if (get_Conv_strict(node)) {
2149 if (USE_SSE2(env_cg)) {
2150 /* when we are in SSE mode, we can kill all strict no-op conversion */
2154 /* this should be optimized already, but who knows... */
2155 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2156 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2161 if (mode_is_float(src_mode)) {
2162 /* we convert from float ... */
2163 if (mode_is_float(tgt_mode)) {
2164 if(src_mode == mode_E && tgt_mode == mode_D
2165 && !get_Conv_strict(node)) {
2166 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2171 if (USE_SSE2(env_cg)) {
2172 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2173 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2174 set_ia32_ls_mode(res, tgt_mode);
2176 // Matze: TODO what about strict convs?
2177 if(get_Conv_strict(node)) {
2178 res = create_strict_conv(src_mode, tgt_mode, new_op);
2179 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2182 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2187 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2188 if (USE_SSE2(env_cg)) {
2189 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2190 set_ia32_ls_mode(res, src_mode);
2192 return gen_x87_fp_to_gp(node);
2196 /* we convert from int ... */
2197 if (mode_is_float(tgt_mode)) {
2199 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2200 if (USE_SSE2(env_cg)) {
2201 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2202 set_ia32_ls_mode(res, tgt_mode);
2203 if(src_bits == 32) {
2204 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2207 return gen_x87_gp_to_fp(node, src_mode);
2209 } else if(tgt_mode == mode_b) {
2212 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2214 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2219 ir_mode *smaller_mode;
2222 if (src_bits == tgt_bits) {
2223 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2224 src_mode, tgt_mode));
2228 if (src_bits < tgt_bits) {
2229 smaller_mode = src_mode;
2230 smaller_bits = src_bits;
2232 smaller_mode = tgt_mode;
2233 smaller_bits = tgt_bits;
2236 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2237 if (smaller_bits == 8) {
2238 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2239 set_ia32_ls_mode(res, smaller_mode);
2241 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2242 set_ia32_ls_mode(res, smaller_mode);
2244 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2248 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2254 int check_immediate_constraint(long val, char immediate_constraint_type)
2256 switch (immediate_constraint_type) {
2260 return val >= 0 && val <= 32;
2262 return val >= 0 && val <= 63;
2264 return val >= -128 && val <= 127;
2266 return val == 0xff || val == 0xffff;
2268 return val >= 0 && val <= 3;
2270 return val >= 0 && val <= 255;
2272 return val >= 0 && val <= 127;
2276 panic("Invalid immediate constraint found");
2281 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2284 tarval *offset = NULL;
2285 int offset_sign = 0;
2287 ir_entity *symconst_ent = NULL;
2288 int symconst_sign = 0;
2290 ir_node *cnst = NULL;
2291 ir_node *symconst = NULL;
2297 mode = get_irn_mode(node);
2298 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2302 if(is_Minus(node)) {
2304 node = get_Minus_op(node);
2307 if(is_Const(node)) {
2310 offset_sign = minus;
2311 } else if(is_SymConst(node)) {
2314 symconst_sign = minus;
2315 } else if(is_Add(node)) {
2316 ir_node *left = get_Add_left(node);
2317 ir_node *right = get_Add_right(node);
2318 if(is_Const(left) && is_SymConst(right)) {
2321 symconst_sign = minus;
2322 offset_sign = minus;
2323 } else if(is_SymConst(left) && is_Const(right)) {
2326 symconst_sign = minus;
2327 offset_sign = minus;
2329 } else if(is_Sub(node)) {
2330 ir_node *left = get_Sub_left(node);
2331 ir_node *right = get_Sub_right(node);
2332 if(is_Const(left) && is_SymConst(right)) {
2335 symconst_sign = !minus;
2336 offset_sign = minus;
2337 } else if(is_SymConst(left) && is_Const(right)) {
2340 symconst_sign = minus;
2341 offset_sign = !minus;
2348 offset = get_Const_tarval(cnst);
2349 if(tarval_is_long(offset)) {
2350 val = get_tarval_long(offset);
2351 } else if(tarval_is_null(offset)) {
2354 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2359 if(!check_immediate_constraint(val, immediate_constraint_type))
2362 if(symconst != NULL) {
2363 if(immediate_constraint_type != 0) {
2364 /* we need full 32bits for symconsts */
2368 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2370 symconst_ent = get_SymConst_entity(symconst);
2372 if(cnst == NULL && symconst == NULL)
2375 if(offset_sign && offset != NULL) {
2376 offset = tarval_neg(offset);
2379 irg = current_ir_graph;
2380 dbgi = get_irn_dbg_info(node);
2381 block = get_irg_start_block(irg);
2382 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2383 symconst_sign, val);
2384 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2390 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2392 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2393 if (new_node == NULL) {
2394 new_node = be_transform_node(node);
2399 typedef struct constraint_t constraint_t;
2400 struct constraint_t {
2403 const arch_register_req_t **out_reqs;
2405 const arch_register_req_t *req;
2406 unsigned immediate_possible;
2407 char immediate_type;
2410 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2412 int immediate_possible = 0;
2413 char immediate_type = 0;
2414 unsigned limited = 0;
2415 const arch_register_class_t *cls = NULL;
2417 struct obstack *obst;
2418 arch_register_req_t *req;
2419 unsigned *limited_ptr;
2423 /* TODO: replace all the asserts with nice error messages */
2425 printf("Constraint: %s\n", c);
2435 assert(cls == NULL ||
2436 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2437 cls = &ia32_reg_classes[CLASS_ia32_gp];
2438 limited |= 1 << REG_EAX;
2441 assert(cls == NULL ||
2442 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2443 cls = &ia32_reg_classes[CLASS_ia32_gp];
2444 limited |= 1 << REG_EBX;
2447 assert(cls == NULL ||
2448 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2449 cls = &ia32_reg_classes[CLASS_ia32_gp];
2450 limited |= 1 << REG_ECX;
2453 assert(cls == NULL ||
2454 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2455 cls = &ia32_reg_classes[CLASS_ia32_gp];
2456 limited |= 1 << REG_EDX;
2459 assert(cls == NULL ||
2460 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2461 cls = &ia32_reg_classes[CLASS_ia32_gp];
2462 limited |= 1 << REG_EDI;
2465 assert(cls == NULL ||
2466 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2467 cls = &ia32_reg_classes[CLASS_ia32_gp];
2468 limited |= 1 << REG_ESI;
2471 case 'q': /* q means lower part of the regs only, this makes no
2472 * difference to Q for us (we only assigne whole registers) */
2473 assert(cls == NULL ||
2474 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2475 cls = &ia32_reg_classes[CLASS_ia32_gp];
2476 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2480 assert(cls == NULL ||
2481 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2482 cls = &ia32_reg_classes[CLASS_ia32_gp];
2483 limited |= 1 << REG_EAX | 1 << REG_EDX;
2486 assert(cls == NULL ||
2487 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2488 cls = &ia32_reg_classes[CLASS_ia32_gp];
2489 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2490 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2497 assert(cls == NULL);
2498 cls = &ia32_reg_classes[CLASS_ia32_gp];
2504 /* TODO: mark values so the x87 simulator knows about t and u */
2505 assert(cls == NULL);
2506 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2511 assert(cls == NULL);
2512 /* TODO: check that sse2 is supported */
2513 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2523 assert(!immediate_possible);
2524 immediate_possible = 1;
2525 immediate_type = *c;
2529 assert(!immediate_possible);
2530 immediate_possible = 1;
2534 assert(!immediate_possible && cls == NULL);
2535 immediate_possible = 1;
2536 cls = &ia32_reg_classes[CLASS_ia32_gp];
2549 assert(constraint->is_in && "can only specify same constraint "
2552 sscanf(c, "%d%n", &same_as, &p);
2559 case 'E': /* no float consts yet */
2560 case 'F': /* no float consts yet */
2561 case 's': /* makes no sense on x86 */
2562 case 'X': /* we can't support that in firm */
2566 case '<': /* no autodecrement on x86 */
2567 case '>': /* no autoincrement on x86 */
2568 case 'C': /* sse constant not supported yet */
2569 case 'G': /* 80387 constant not supported yet */
2570 case 'y': /* we don't support mmx registers yet */
2571 case 'Z': /* not available in 32 bit mode */
2572 case 'e': /* not available in 32 bit mode */
2573 assert(0 && "asm constraint not supported");
2576 assert(0 && "unknown asm constraint found");
2583 const arch_register_req_t *other_constr;
2585 assert(cls == NULL && "same as and register constraint not supported");
2586 assert(!immediate_possible && "same as and immediate constraint not "
2588 assert(same_as < constraint->n_outs && "wrong constraint number in "
2589 "same_as constraint");
2591 other_constr = constraint->out_reqs[same_as];
2593 req = obstack_alloc(obst, sizeof(req[0]));
2594 req->cls = other_constr->cls;
2595 req->type = arch_register_req_type_should_be_same;
2596 req->limited = NULL;
2597 req->other_same = pos;
2598 req->other_different = -1;
2600 /* switch constraints. This is because in firm we have same_as
2601 * constraints on the output constraints while in the gcc asm syntax
2602 * they are specified on the input constraints */
2603 constraint->req = other_constr;
2604 constraint->out_reqs[same_as] = req;
2605 constraint->immediate_possible = 0;
2609 if(immediate_possible && cls == NULL) {
2610 cls = &ia32_reg_classes[CLASS_ia32_gp];
2612 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2613 assert(cls != NULL);
2615 if(immediate_possible) {
2616 assert(constraint->is_in
2617 && "imeediates make no sense for output constraints");
2619 /* todo: check types (no float input on 'r' constrainted in and such... */
2621 irg = current_ir_graph;
2622 obst = get_irg_obstack(irg);
2625 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2626 limited_ptr = (unsigned*) (req+1);
2628 req = obstack_alloc(obst, sizeof(req[0]));
2630 memset(req, 0, sizeof(req[0]));
2633 req->type = arch_register_req_type_limited;
2634 *limited_ptr = limited;
2635 req->limited = limited_ptr;
2637 req->type = arch_register_req_type_normal;
2641 constraint->req = req;
2642 constraint->immediate_possible = immediate_possible;
2643 constraint->immediate_type = immediate_type;
2647 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2654 panic("Clobbers not supported yet");
2657 ir_node *gen_ASM(ir_node *node)
2660 ir_graph *irg = current_ir_graph;
2661 ir_node *block = be_transform_node(get_nodes_block(node));
2662 dbg_info *dbgi = get_irn_dbg_info(node);
2669 ia32_asm_attr_t *attr;
2670 const arch_register_req_t **out_reqs;
2671 const arch_register_req_t **in_reqs;
2672 struct obstack *obst;
2673 constraint_t parsed_constraint;
2675 /* transform inputs */
2676 arity = get_irn_arity(node);
2677 in = alloca(arity * sizeof(in[0]));
2678 memset(in, 0, arity * sizeof(in[0]));
2680 n_outs = get_ASM_n_output_constraints(node);
2681 n_clobbers = get_ASM_n_clobbers(node);
2682 out_arity = n_outs + n_clobbers;
2684 /* construct register constraints */
2685 obst = get_irg_obstack(irg);
2686 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2687 parsed_constraint.out_reqs = out_reqs;
2688 parsed_constraint.n_outs = n_outs;
2689 parsed_constraint.is_in = 0;
2690 for(i = 0; i < out_arity; ++i) {
2694 const ir_asm_constraint *constraint;
2695 constraint = & get_ASM_output_constraints(node) [i];
2696 c = get_id_str(constraint->constraint);
2697 parse_asm_constraint(i, &parsed_constraint, c);
2699 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2700 c = get_id_str(glob_id);
2701 parse_clobber(node, i, &parsed_constraint, c);
2703 out_reqs[i] = parsed_constraint.req;
2706 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2707 parsed_constraint.is_in = 1;
2708 for(i = 0; i < arity; ++i) {
2709 const ir_asm_constraint *constraint;
2713 constraint = & get_ASM_input_constraints(node) [i];
2714 constr_id = constraint->constraint;
2715 c = get_id_str(constr_id);
2716 parse_asm_constraint(i, &parsed_constraint, c);
2717 in_reqs[i] = parsed_constraint.req;
2719 if(parsed_constraint.immediate_possible) {
2720 ir_node *pred = get_irn_n(node, i);
2721 char imm_type = parsed_constraint.immediate_type;
2722 ir_node *immediate = try_create_Immediate(pred, imm_type);
2724 if(immediate != NULL) {
2730 /* transform inputs */
2731 for(i = 0; i < arity; ++i) {
2733 ir_node *transformed;
2738 pred = get_irn_n(node, i);
2739 transformed = be_transform_node(pred);
2740 in[i] = transformed;
2743 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2745 generic_attr = get_irn_generic_attr(res);
2746 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2747 attr->asm_text = get_ASM_text(node);
2748 set_ia32_out_req_all(res, out_reqs);
2749 set_ia32_in_req_all(res, in_reqs);
2751 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2756 /********************************************
2759 * | |__ ___ _ __ ___ __| | ___ ___
2760 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2761 * | |_) | __/ | | | (_) | (_| | __/\__ \
2762 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2764 ********************************************/
2766 static ir_node *gen_be_StackParam(ir_node *node) {
2767 ir_node *block = be_transform_node(get_nodes_block(node));
2768 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2769 ir_node *new_ptr = be_transform_node(ptr);
2770 ir_node *new_op = NULL;
2771 ir_graph *irg = current_ir_graph;
2772 dbg_info *dbgi = get_irn_dbg_info(node);
2773 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2774 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2775 ir_mode *load_mode = get_irn_mode(node);
2776 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2780 if (mode_is_float(load_mode)) {
2781 if (USE_SSE2(env_cg)) {
2782 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2783 pn_res = pn_ia32_xLoad_res;
2784 proj_mode = mode_xmm;
2786 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2787 pn_res = pn_ia32_vfld_res;
2788 proj_mode = mode_vfp;
2791 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2792 proj_mode = mode_Iu;
2793 pn_res = pn_ia32_Load_res;
2796 set_irn_pinned(new_op, op_pin_state_floats);
2797 set_ia32_frame_ent(new_op, ent);
2798 set_ia32_use_frame(new_op);
2800 set_ia32_op_type(new_op, ia32_AddrModeS);
2801 set_ia32_am_flavour(new_op, ia32_am_B);
2802 set_ia32_ls_mode(new_op, load_mode);
2803 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2805 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2807 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2811 * Transforms a FrameAddr into an ia32 Add.
2813 static ir_node *gen_be_FrameAddr(ir_node *node) {
2814 ir_node *block = be_transform_node(get_nodes_block(node));
2815 ir_node *op = be_get_FrameAddr_frame(node);
2816 ir_node *new_op = be_transform_node(op);
2817 ir_graph *irg = current_ir_graph;
2818 dbg_info *dbgi = get_irn_dbg_info(node);
2819 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2822 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2823 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2824 set_ia32_use_frame(res);
2825 set_ia32_am_flavour(res, ia32_am_OB);
2827 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2833 * Transforms a FrameLoad into an ia32 Load.
2835 static ir_node *gen_be_FrameLoad(ir_node *node) {
2836 ir_node *block = be_transform_node(get_nodes_block(node));
2837 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2838 ir_node *new_mem = be_transform_node(mem);
2839 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2840 ir_node *new_ptr = be_transform_node(ptr);
2841 ir_node *new_op = NULL;
2842 ir_graph *irg = current_ir_graph;
2843 dbg_info *dbgi = get_irn_dbg_info(node);
2844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2845 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2846 ir_mode *mode = get_type_mode(get_entity_type(ent));
2847 ir_node *projs[pn_Load_max];
2849 ia32_collect_Projs(node, projs, pn_Load_max);
2851 if (mode_is_float(mode)) {
2852 if (USE_SSE2(env_cg)) {
2853 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2856 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2860 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2863 set_irn_pinned(new_op, op_pin_state_floats);
2864 set_ia32_frame_ent(new_op, ent);
2865 set_ia32_use_frame(new_op);
2867 set_ia32_op_type(new_op, ia32_AddrModeS);
2868 set_ia32_am_flavour(new_op, ia32_am_B);
2869 set_ia32_ls_mode(new_op, mode);
2870 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2872 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2879 * Transforms a FrameStore into an ia32 Store.
2881 static ir_node *gen_be_FrameStore(ir_node *node) {
2882 ir_node *block = be_transform_node(get_nodes_block(node));
2883 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2884 ir_node *new_mem = be_transform_node(mem);
2885 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2886 ir_node *new_ptr = be_transform_node(ptr);
2887 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2888 ir_node *new_val = be_transform_node(val);
2889 ir_node *new_op = NULL;
2890 ir_graph *irg = current_ir_graph;
2891 dbg_info *dbgi = get_irn_dbg_info(node);
2892 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2893 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2894 ir_mode *mode = get_irn_mode(val);
2896 if (mode_is_float(mode)) {
2897 if (USE_SSE2(env_cg)) {
2898 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2900 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2902 } else if (get_mode_size_bits(mode) == 8) {
2903 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2905 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2908 set_ia32_frame_ent(new_op, ent);
2909 set_ia32_use_frame(new_op);
2911 set_ia32_op_type(new_op, ia32_AddrModeD);
2912 set_ia32_am_flavour(new_op, ia32_am_B);
2913 set_ia32_ls_mode(new_op, mode);
2915 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2921 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2923 static ir_node *gen_be_Return(ir_node *node) {
2924 ir_graph *irg = current_ir_graph;
2925 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2926 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2927 ir_entity *ent = get_irg_entity(irg);
2928 ir_type *tp = get_entity_type(ent);
2933 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2934 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2937 int pn_ret_val, pn_ret_mem, arity, i;
2939 assert(ret_val != NULL);
2940 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2941 return be_duplicate_node(node);
2944 res_type = get_method_res_type(tp, 0);
2946 if (! is_Primitive_type(res_type)) {
2947 return be_duplicate_node(node);
2950 mode = get_type_mode(res_type);
2951 if (! mode_is_float(mode)) {
2952 return be_duplicate_node(node);
2955 assert(get_method_n_ress(tp) == 1);
2957 pn_ret_val = get_Proj_proj(ret_val);
2958 pn_ret_mem = get_Proj_proj(ret_mem);
2960 /* get the Barrier */
2961 barrier = get_Proj_pred(ret_val);
2963 /* get result input of the Barrier */
2964 ret_val = get_irn_n(barrier, pn_ret_val);
2965 new_ret_val = be_transform_node(ret_val);
2967 /* get memory input of the Barrier */
2968 ret_mem = get_irn_n(barrier, pn_ret_mem);
2969 new_ret_mem = be_transform_node(ret_mem);
2971 frame = get_irg_frame(irg);
2973 dbgi = get_irn_dbg_info(barrier);
2974 block = be_transform_node(get_nodes_block(barrier));
2976 noreg = ia32_new_NoReg_gp(env_cg);
2978 /* store xmm0 onto stack */
2979 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
2980 new_ret_val, new_ret_mem);
2981 set_ia32_ls_mode(sse_store, mode);
2982 set_ia32_op_type(sse_store, ia32_AddrModeD);
2983 set_ia32_use_frame(sse_store);
2984 set_ia32_am_flavour(sse_store, ia32_am_B);
2986 /* load into x87 register */
2987 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
2988 set_ia32_op_type(fld, ia32_AddrModeS);
2989 set_ia32_use_frame(fld);
2990 set_ia32_am_flavour(fld, ia32_am_B);
2992 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
2993 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
2995 /* create a new barrier */
2996 arity = get_irn_arity(barrier);
2997 in = alloca(arity * sizeof(in[0]));
2998 for (i = 0; i < arity; ++i) {
3001 if (i == pn_ret_val) {
3003 } else if (i == pn_ret_mem) {
3006 ir_node *in = get_irn_n(barrier, i);
3007 new_in = be_transform_node(in);
3012 new_barrier = new_ir_node(dbgi, irg, block,
3013 get_irn_op(barrier), get_irn_mode(barrier),
3015 copy_node_attr(barrier, new_barrier);
3016 be_duplicate_deps(barrier, new_barrier);
3017 be_set_transformed_node(barrier, new_barrier);
3018 mark_irn_visited(barrier);
3020 /* transform normally */
3021 return be_duplicate_node(node);
3025 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3027 static ir_node *gen_be_AddSP(ir_node *node) {
3028 ir_node *block = be_transform_node(get_nodes_block(node));
3029 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3031 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3032 ir_node *new_sp = be_transform_node(sp);
3033 ir_graph *irg = current_ir_graph;
3034 dbg_info *dbgi = get_irn_dbg_info(node);
3035 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3036 ir_node *nomem = new_NoMem();
3039 new_sz = create_immediate_or_transform(sz, 0);
3041 /* ia32 stack grows in reverse direction, make a SubSP */
3042 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3044 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3051 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3053 static ir_node *gen_be_SubSP(ir_node *node) {
3054 ir_node *block = be_transform_node(get_nodes_block(node));
3055 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3057 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3058 ir_node *new_sp = be_transform_node(sp);
3059 ir_graph *irg = current_ir_graph;
3060 dbg_info *dbgi = get_irn_dbg_info(node);
3061 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3062 ir_node *nomem = new_NoMem();
3065 new_sz = create_immediate_or_transform(sz, 0);
3067 /* ia32 stack grows in reverse direction, make an AddSP */
3068 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3069 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3070 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3076 * This function just sets the register for the Unknown node
3077 * as this is not done during register allocation because Unknown
3078 * is an "ignore" node.
3080 static ir_node *gen_Unknown(ir_node *node) {
3081 ir_mode *mode = get_irn_mode(node);
3083 if (mode_is_float(mode)) {
3085 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3086 if (USE_SSE2(env_cg))
3087 return ia32_new_Unknown_xmm(env_cg);
3089 return ia32_new_Unknown_vfp(env_cg);
3091 ir_graph *irg = current_ir_graph;
3092 dbg_info *dbgi = get_irn_dbg_info(node);
3093 ir_node *block = get_irg_start_block(irg);
3094 return new_rd_ia32_vfldz(dbgi, irg, block);
3096 } else if (mode_needs_gp_reg(mode)) {
3097 return ia32_new_Unknown_gp(env_cg);
3099 assert(0 && "unsupported Unknown-Mode");
3106 * Change some phi modes
3108 static ir_node *gen_Phi(ir_node *node) {
3109 ir_node *block = be_transform_node(get_nodes_block(node));
3110 ir_graph *irg = current_ir_graph;
3111 dbg_info *dbgi = get_irn_dbg_info(node);
3112 ir_mode *mode = get_irn_mode(node);
3115 if(mode_needs_gp_reg(mode)) {
3116 /* we shouldn't have any 64bit stuff around anymore */
3117 assert(get_mode_size_bits(mode) <= 32);
3118 /* all integer operations are on 32bit registers now */
3120 } else if(mode_is_float(mode)) {
3121 if (USE_SSE2(env_cg)) {
3128 /* phi nodes allow loops, so we use the old arguments for now
3129 * and fix this later */
3130 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3131 copy_node_attr(node, phi);
3132 be_duplicate_deps(node, phi);
3134 be_set_transformed_node(node, phi);
3135 be_enqueue_preds(node);
3140 /**********************************************************************
3143 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3144 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3145 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3146 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3148 **********************************************************************/
3150 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3152 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3155 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3156 ir_node *val, ir_node *mem);
3159 * Transforms a lowered Load into a "real" one.
3161 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3163 ir_node *block = be_transform_node(get_nodes_block(node));
3164 ir_node *ptr = get_irn_n(node, 0);
3165 ir_node *new_ptr = be_transform_node(ptr);
3166 ir_node *mem = get_irn_n(node, 1);
3167 ir_node *new_mem = be_transform_node(mem);
3168 ir_graph *irg = current_ir_graph;
3169 dbg_info *dbgi = get_irn_dbg_info(node);
3170 ir_mode *mode = get_ia32_ls_mode(node);
3171 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3174 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3176 set_ia32_op_type(new_op, ia32_AddrModeS);
3177 set_ia32_am_flavour(new_op, ia32_am_OB);
3178 set_ia32_am_offs_int(new_op, 0);
3179 set_ia32_am_scale(new_op, 1);
3180 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3181 if (is_ia32_am_sc_sign(node))
3182 set_ia32_am_sc_sign(new_op);
3183 set_ia32_ls_mode(new_op, mode);
3184 if (is_ia32_use_frame(node)) {
3185 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3186 set_ia32_use_frame(new_op);
3189 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3195 * Transforms a lowered Store into a "real" one.
3197 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3199 ir_node *block = be_transform_node(get_nodes_block(node));
3200 ir_node *ptr = get_irn_n(node, 0);
3201 ir_node *new_ptr = be_transform_node(ptr);
3202 ir_node *val = get_irn_n(node, 1);
3203 ir_node *new_val = be_transform_node(val);
3204 ir_node *mem = get_irn_n(node, 2);
3205 ir_node *new_mem = be_transform_node(mem);
3206 ir_graph *irg = current_ir_graph;
3207 dbg_info *dbgi = get_irn_dbg_info(node);
3208 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3209 ir_mode *mode = get_ia32_ls_mode(node);
3212 ia32_am_flavour_t am_flav = ia32_B;
3214 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3216 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3218 add_ia32_am_offs_int(new_op, am_offs);
3221 set_ia32_op_type(new_op, ia32_AddrModeD);
3222 set_ia32_am_flavour(new_op, am_flav);
3223 set_ia32_ls_mode(new_op, mode);
3224 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3225 set_ia32_use_frame(new_op);
3227 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3234 * Transforms an ia32_l_XXX into a "real" XXX node
3236 * @param env The transformation environment
3237 * @return the created ia32 XXX node
3239 #define GEN_LOWERED_OP(op) \
3240 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3241 return gen_binop(node, get_binop_left(node), \
3242 get_binop_right(node), new_rd_ia32_##op,0); \
3245 #define GEN_LOWERED_x87_OP(op) \
3246 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3248 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3249 get_binop_right(node), new_rd_ia32_##op); \
3253 #define GEN_LOWERED_UNOP(op) \
3254 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3255 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3258 #define GEN_LOWERED_SHIFT_OP(op) \
3259 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3260 return gen_shift_binop(node, get_binop_left(node), \
3261 get_binop_right(node), new_rd_ia32_##op); \
3264 #define GEN_LOWERED_LOAD(op) \
3265 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3266 return gen_lowered_Load(node, new_rd_ia32_##op); \
3269 #define GEN_LOWERED_STORE(op) \
3270 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3271 return gen_lowered_Store(node, new_rd_ia32_##op); \
3278 GEN_LOWERED_OP(IMul)
3280 GEN_LOWERED_x87_OP(vfprem)
3281 GEN_LOWERED_x87_OP(vfmul)
3282 GEN_LOWERED_x87_OP(vfsub)
3284 GEN_LOWERED_UNOP(Neg)
3286 GEN_LOWERED_LOAD(vfild)
3287 GEN_LOWERED_LOAD(Load)
3288 // GEN_LOWERED_STORE(vfist) TODO
3289 GEN_LOWERED_STORE(Store)
3291 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3292 ir_node *block = be_transform_node(get_nodes_block(node));
3293 ir_node *left = get_binop_left(node);
3294 ir_node *new_left = be_transform_node(left);
3295 ir_node *right = get_binop_right(node);
3296 ir_node *new_right = be_transform_node(right);
3297 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3298 ir_graph *irg = current_ir_graph;
3299 dbg_info *dbgi = get_irn_dbg_info(node);
3300 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3301 &ia32_fp_cw_regs[REG_FPCW]);
3304 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3305 new_right, new_NoMem(), fpcw);
3306 clear_ia32_commutative(vfdiv);
3307 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3309 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3315 * Transforms a l_MulS into a "real" MulS node.
3317 * @param env The transformation environment
3318 * @return the created ia32 Mul node
3320 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3321 ir_node *block = be_transform_node(get_nodes_block(node));
3322 ir_node *left = get_binop_left(node);
3323 ir_node *new_left = be_transform_node(left);
3324 ir_node *right = get_binop_right(node);
3325 ir_node *new_right = be_transform_node(right);
3326 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3327 ir_graph *irg = current_ir_graph;
3328 dbg_info *dbgi = get_irn_dbg_info(node);
3330 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3331 /* and then skip the result Proj, because all needed Projs are already there. */
3332 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3333 new_right, new_NoMem());
3334 clear_ia32_commutative(muls);
3335 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3337 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3342 GEN_LOWERED_SHIFT_OP(Shl)
3343 GEN_LOWERED_SHIFT_OP(Shr)
3344 GEN_LOWERED_SHIFT_OP(Sar)
3347 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3348 * op1 - target to be shifted
3349 * op2 - contains bits to be shifted into target
3351 * Only op3 can be an immediate.
3353 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3354 ir_node *op2, ir_node *count)
3356 ir_node *block = be_transform_node(get_nodes_block(node));
3357 ir_node *new_op1 = be_transform_node(op1);
3358 ir_node *new_op2 = be_transform_node(op2);
3359 ir_node *new_count = be_transform_node(count);
3360 ir_node *new_op = NULL;
3361 ir_graph *irg = current_ir_graph;
3362 dbg_info *dbgi = get_irn_dbg_info(node);
3363 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3364 ir_node *nomem = new_NoMem();
3368 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3370 /* Check if immediate optimization is on and */
3371 /* if it's an operation with immediate. */
3372 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3374 /* Limit imm_op within range imm8 */
3376 tv = get_ia32_Immop_tarval(imm_op);
3379 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3380 set_ia32_Immop_tarval(imm_op, tv);
3387 /* integer operations */
3389 /* This is ShiftD with const */
3390 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3392 if (is_ia32_l_ShlD(node))
3393 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3394 new_op1, new_op2, noreg, nomem);
3396 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3397 new_op1, new_op2, noreg, nomem);
3398 copy_ia32_Immop_attr(new_op, imm_op);
3401 /* This is a normal ShiftD */
3402 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3403 if (is_ia32_l_ShlD(node))
3404 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3405 new_op1, new_op2, new_count, nomem);
3407 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3408 new_op1, new_op2, new_count, nomem);
3411 /* set AM support */
3412 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3414 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3416 set_ia32_emit_cl(new_op);
3421 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3422 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3423 get_irn_n(node, 1), get_irn_n(node, 2));
3426 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3427 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3428 get_irn_n(node, 1), get_irn_n(node, 2));
3432 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3434 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3435 ir_node *block = be_transform_node(get_nodes_block(node));
3436 ir_node *val = get_irn_n(node, 1);
3437 ir_node *new_val = be_transform_node(val);
3438 ia32_code_gen_t *cg = env_cg;
3439 ir_node *res = NULL;
3440 ir_graph *irg = current_ir_graph;
3442 ir_node *noreg, *new_ptr, *new_mem;
3449 mem = get_irn_n(node, 2);
3450 new_mem = be_transform_node(mem);
3451 ptr = get_irn_n(node, 0);
3452 new_ptr = be_transform_node(ptr);
3453 noreg = ia32_new_NoReg_gp(cg);
3454 dbgi = get_irn_dbg_info(node);
3456 /* Store x87 -> MEM */
3457 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3458 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3459 set_ia32_use_frame(res);
3460 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3461 set_ia32_am_flavour(res, ia32_B);
3462 set_ia32_op_type(res, ia32_AddrModeD);
3464 /* Load MEM -> SSE */
3465 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3466 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3467 set_ia32_use_frame(res);
3468 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3469 set_ia32_am_flavour(res, ia32_B);
3470 set_ia32_op_type(res, ia32_AddrModeS);
3471 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3477 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3479 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3480 ir_node *block = be_transform_node(get_nodes_block(node));
3481 ir_node *val = get_irn_n(node, 1);
3482 ir_node *new_val = be_transform_node(val);
3483 ia32_code_gen_t *cg = env_cg;
3484 ir_graph *irg = current_ir_graph;
3485 ir_node *res = NULL;
3486 ir_entity *fent = get_ia32_frame_ent(node);
3487 ir_mode *lsmode = get_ia32_ls_mode(node);
3489 ir_node *noreg, *new_ptr, *new_mem;
3493 if (! USE_SSE2(cg)) {
3494 /* SSE unit is not used -> skip this node. */
3498 ptr = get_irn_n(node, 0);
3499 new_ptr = be_transform_node(ptr);
3500 mem = get_irn_n(node, 2);
3501 new_mem = be_transform_node(mem);
3502 noreg = ia32_new_NoReg_gp(cg);
3503 dbgi = get_irn_dbg_info(node);
3505 /* Store SSE -> MEM */
3506 if (is_ia32_xLoad(skip_Proj(new_val))) {
3507 ir_node *ld = skip_Proj(new_val);
3509 /* we can vfld the value directly into the fpu */
3510 fent = get_ia32_frame_ent(ld);
3511 ptr = get_irn_n(ld, 0);
3512 offs = get_ia32_am_offs_int(ld);
3514 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3515 set_ia32_frame_ent(res, fent);
3516 set_ia32_use_frame(res);
3517 set_ia32_ls_mode(res, lsmode);
3518 set_ia32_am_flavour(res, ia32_B);
3519 set_ia32_op_type(res, ia32_AddrModeD);
3523 /* Load MEM -> x87 */
3524 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3525 set_ia32_frame_ent(res, fent);
3526 set_ia32_use_frame(res);
3527 add_ia32_am_offs_int(res, offs);
3528 set_ia32_am_flavour(res, ia32_B);
3529 set_ia32_op_type(res, ia32_AddrModeS);
3530 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3535 /*********************************************************
3538 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3539 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3540 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3541 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3543 *********************************************************/
3546 * the BAD transformer.
3548 static ir_node *bad_transform(ir_node *node) {
3549 panic("No transform function for %+F available.\n", node);
3554 * Transform the Projs of an AddSP.
3556 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3557 ir_node *block = be_transform_node(get_nodes_block(node));
3558 ir_node *pred = get_Proj_pred(node);
3559 ir_node *new_pred = be_transform_node(pred);
3560 ir_graph *irg = current_ir_graph;
3561 dbg_info *dbgi = get_irn_dbg_info(node);
3562 long proj = get_Proj_proj(node);
3564 if (proj == pn_be_AddSP_sp) {
3565 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3566 pn_ia32_SubSP_stack);
3567 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3569 } else if(proj == pn_be_AddSP_res) {
3570 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3571 pn_ia32_SubSP_addr);
3572 } else if (proj == pn_be_AddSP_M) {
3573 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3577 return new_rd_Unknown(irg, get_irn_mode(node));
3581 * Transform the Projs of a SubSP.
3583 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3584 ir_node *block = be_transform_node(get_nodes_block(node));
3585 ir_node *pred = get_Proj_pred(node);
3586 ir_node *new_pred = be_transform_node(pred);
3587 ir_graph *irg = current_ir_graph;
3588 dbg_info *dbgi = get_irn_dbg_info(node);
3589 long proj = get_Proj_proj(node);
3591 if (proj == pn_be_SubSP_sp) {
3592 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3593 pn_ia32_AddSP_stack);
3594 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3596 } else if (proj == pn_be_SubSP_M) {
3597 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3601 return new_rd_Unknown(irg, get_irn_mode(node));
3605 * Transform and renumber the Projs from a Load.
3607 static ir_node *gen_Proj_Load(ir_node *node) {
3608 ir_node *block = be_transform_node(get_nodes_block(node));
3609 ir_node *pred = get_Proj_pred(node);
3610 ir_node *new_pred = be_transform_node(pred);
3611 ir_graph *irg = current_ir_graph;
3612 dbg_info *dbgi = get_irn_dbg_info(node);
3613 long proj = get_Proj_proj(node);
3615 /* renumber the proj */
3616 if (is_ia32_Load(new_pred)) {
3617 if (proj == pn_Load_res) {
3618 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3619 } else if (proj == pn_Load_M) {
3620 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3622 } else if (is_ia32_xLoad(new_pred)) {
3623 if (proj == pn_Load_res) {
3624 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3625 } else if (proj == pn_Load_M) {
3626 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3628 } else if (is_ia32_vfld(new_pred)) {
3629 if (proj == pn_Load_res) {
3630 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3631 } else if (proj == pn_Load_M) {
3632 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3637 return new_rd_Unknown(irg, get_irn_mode(node));
3641 * Transform and renumber the Projs from a DivMod like instruction.
3643 static ir_node *gen_Proj_DivMod(ir_node *node) {
3644 ir_node *block = be_transform_node(get_nodes_block(node));
3645 ir_node *pred = get_Proj_pred(node);
3646 ir_node *new_pred = be_transform_node(pred);
3647 ir_graph *irg = current_ir_graph;
3648 dbg_info *dbgi = get_irn_dbg_info(node);
3649 ir_mode *mode = get_irn_mode(node);
3650 long proj = get_Proj_proj(node);
3652 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3654 switch (get_irn_opcode(pred)) {
3658 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3660 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3668 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3670 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3678 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3679 case pn_DivMod_res_div:
3680 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3681 case pn_DivMod_res_mod:
3682 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3692 return new_rd_Unknown(irg, mode);
3696 * Transform and renumber the Projs from a CopyB.
3698 static ir_node *gen_Proj_CopyB(ir_node *node) {
3699 ir_node *block = be_transform_node(get_nodes_block(node));
3700 ir_node *pred = get_Proj_pred(node);
3701 ir_node *new_pred = be_transform_node(pred);
3702 ir_graph *irg = current_ir_graph;
3703 dbg_info *dbgi = get_irn_dbg_info(node);
3704 ir_mode *mode = get_irn_mode(node);
3705 long proj = get_Proj_proj(node);
3708 case pn_CopyB_M_regular:
3709 if (is_ia32_CopyB_i(new_pred)) {
3710 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3711 } else if (is_ia32_CopyB(new_pred)) {
3712 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3720 return new_rd_Unknown(irg, mode);
3724 * Transform and renumber the Projs from a vfdiv.
3726 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3727 ir_node *block = be_transform_node(get_nodes_block(node));
3728 ir_node *pred = get_Proj_pred(node);
3729 ir_node *new_pred = be_transform_node(pred);
3730 ir_graph *irg = current_ir_graph;
3731 dbg_info *dbgi = get_irn_dbg_info(node);
3732 ir_mode *mode = get_irn_mode(node);
3733 long proj = get_Proj_proj(node);
3736 case pn_ia32_l_vfdiv_M:
3737 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3738 case pn_ia32_l_vfdiv_res:
3739 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3744 return new_rd_Unknown(irg, mode);
3748 * Transform and renumber the Projs from a Quot.
3750 static ir_node *gen_Proj_Quot(ir_node *node) {
3751 ir_node *block = be_transform_node(get_nodes_block(node));
3752 ir_node *pred = get_Proj_pred(node);
3753 ir_node *new_pred = be_transform_node(pred);
3754 ir_graph *irg = current_ir_graph;
3755 dbg_info *dbgi = get_irn_dbg_info(node);
3756 ir_mode *mode = get_irn_mode(node);
3757 long proj = get_Proj_proj(node);
3761 if (is_ia32_xDiv(new_pred)) {
3762 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3763 } else if (is_ia32_vfdiv(new_pred)) {
3764 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3768 if (is_ia32_xDiv(new_pred)) {
3769 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3770 } else if (is_ia32_vfdiv(new_pred)) {
3771 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3779 return new_rd_Unknown(irg, mode);
3783 * Transform the Thread Local Storage Proj.
3785 static ir_node *gen_Proj_tls(ir_node *node) {
3786 ir_node *block = be_transform_node(get_nodes_block(node));
3787 ir_graph *irg = current_ir_graph;
3788 dbg_info *dbgi = NULL;
3789 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3795 * Transform the Projs from a be_Call.
3797 static ir_node *gen_Proj_be_Call(ir_node *node) {
3798 ir_node *block = be_transform_node(get_nodes_block(node));
3799 ir_node *call = get_Proj_pred(node);
3800 ir_node *new_call = be_transform_node(call);
3801 ir_graph *irg = current_ir_graph;
3802 dbg_info *dbgi = get_irn_dbg_info(node);
3803 long proj = get_Proj_proj(node);
3804 ir_mode *mode = get_irn_mode(node);
3806 const arch_register_class_t *cls;
3808 /* The following is kinda tricky: If we're using SSE, then we have to
3809 * move the result value of the call in floating point registers to an
3810 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3811 * after the call, we have to make sure to correctly make the
3812 * MemProj and the result Proj use these 2 nodes
3814 if (proj == pn_be_Call_M_regular) {
3815 // get new node for result, are we doing the sse load/store hack?
3816 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3817 ir_node *call_res_new;
3818 ir_node *call_res_pred = NULL;
3820 if (call_res != NULL) {
3821 call_res_new = be_transform_node(call_res);
3822 call_res_pred = get_Proj_pred(call_res_new);
3825 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3826 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3827 pn_be_Call_M_regular);
3829 assert(is_ia32_xLoad(call_res_pred));
3830 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3834 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3836 ir_node *frame = get_irg_frame(irg);
3837 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3839 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3842 /* in case there is no memory output: create one to serialize the copy
3844 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3845 pn_be_Call_M_regular);
3846 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3847 pn_be_Call_first_res);
3849 /* store st(0) onto stack */
3850 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3852 set_ia32_op_type(fstp, ia32_AddrModeD);
3853 set_ia32_use_frame(fstp);
3854 set_ia32_am_flavour(fstp, ia32_am_B);
3856 /* load into SSE register */
3857 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3858 set_ia32_ls_mode(sse_load, mode);
3859 set_ia32_op_type(sse_load, ia32_AddrModeS);
3860 set_ia32_use_frame(sse_load);
3861 set_ia32_am_flavour(sse_load, ia32_am_B);
3863 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3867 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3869 /* get a Proj representing a caller save register */
3870 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3871 assert(is_Proj(p) && "Proj expected.");
3873 /* user of the the proj is the Keep */
3874 p = get_edge_src_irn(get_irn_out_edge_first(p));
3875 assert(be_is_Keep(p) && "Keep expected.");
3881 /* transform call modes */
3882 if (mode_is_data(mode)) {
3883 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3887 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3891 * Transform the Projs from a Cmp.
3893 static ir_node *gen_Proj_Cmp(ir_node *node)
3895 /* normally Cmps are processed when looking at Cond nodes, but this case
3896 * can happen in complicated Psi conditions */
3898 ir_node *cmp = get_Proj_pred(node);
3899 long pnc = get_Proj_proj(node);
3900 ir_node *cmp_left = get_Cmp_left(cmp);
3901 ir_node *cmp_right = get_Cmp_right(cmp);
3902 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3903 dbg_info *dbgi = get_irn_dbg_info(cmp);
3904 ir_node *block = be_transform_node(get_nodes_block(node));
3907 assert(!mode_is_float(cmp_mode));
3909 if(!mode_is_signed(cmp_mode)) {
3910 pnc |= ia32_pn_Cmp_Unsigned;
3913 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3914 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3920 * Transform and potentially renumber Proj nodes.
3922 static ir_node *gen_Proj(ir_node *node) {
3923 ir_graph *irg = current_ir_graph;
3924 dbg_info *dbgi = get_irn_dbg_info(node);
3925 ir_node *pred = get_Proj_pred(node);
3926 long proj = get_Proj_proj(node);
3928 if (is_Store(pred) || be_is_FrameStore(pred)) {
3929 if (proj == pn_Store_M) {
3930 return be_transform_node(pred);
3933 return new_r_Bad(irg);
3935 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3936 return gen_Proj_Load(node);
3937 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3938 return gen_Proj_DivMod(node);
3939 } else if (is_CopyB(pred)) {
3940 return gen_Proj_CopyB(node);
3941 } else if (is_Quot(pred)) {
3942 return gen_Proj_Quot(node);
3943 } else if (is_ia32_l_vfdiv(pred)) {
3944 return gen_Proj_l_vfdiv(node);
3945 } else if (be_is_SubSP(pred)) {
3946 return gen_Proj_be_SubSP(node);
3947 } else if (be_is_AddSP(pred)) {
3948 return gen_Proj_be_AddSP(node);
3949 } else if (be_is_Call(pred)) {
3950 return gen_Proj_be_Call(node);
3951 } else if (is_Cmp(pred)) {
3952 return gen_Proj_Cmp(node);
3953 } else if (get_irn_op(pred) == op_Start) {
3954 if (proj == pn_Start_X_initial_exec) {
3955 ir_node *block = get_nodes_block(pred);
3958 /* we exchange the ProjX with a jump */
3959 block = be_transform_node(block);
3960 jump = new_rd_Jmp(dbgi, irg, block);
3963 if (node == be_get_old_anchor(anchor_tls)) {
3964 return gen_Proj_tls(node);
3967 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
3971 ir_node *new_pred = be_transform_node(pred);
3972 ir_node *block = be_transform_node(get_nodes_block(node));
3973 ir_mode *mode = get_irn_mode(node);
3974 if (mode_needs_gp_reg(mode)) {
3975 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3976 get_Proj_proj(node));
3977 #ifdef DEBUG_libfirm
3978 new_proj->node_nr = node->node_nr;
3984 return be_duplicate_node(node);
3988 * Enters all transform functions into the generic pointer
3990 static void register_transformers(void)
3994 /* first clear the generic function pointer for all ops */
3995 clear_irp_opcodes_generic_func();
3997 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3998 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4034 /* transform ops from intrinsic lowering */
4054 /* GEN(ia32_l_vfist); TODO */
4056 GEN(ia32_l_X87toSSE);
4057 GEN(ia32_l_SSEtoX87);
4062 /* we should never see these nodes */
4077 /* handle generic backend nodes */
4088 /* set the register for all Unknown nodes */
4091 op_Mulh = get_op_Mulh();
4100 * Pre-transform all unknown and noreg nodes.
4102 static void ia32_pretransform_node(void *arch_cg) {
4103 ia32_code_gen_t *cg = arch_cg;
4105 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4106 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4107 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4108 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4109 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4110 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4114 void add_missing_keep_walker(ir_node *node, void *data)
4117 unsigned found_projs = 0;
4118 const ir_edge_t *edge;
4119 ir_mode *mode = get_irn_mode(node);
4124 if(!is_ia32_irn(node))
4127 n_outs = get_ia32_n_res(node);
4130 if(is_ia32_SwitchJmp(node))
4133 assert(n_outs < (int) sizeof(unsigned) * 8);
4134 foreach_out_edge(node, edge) {
4135 ir_node *proj = get_edge_src_irn(edge);
4136 int pn = get_Proj_proj(proj);
4138 assert(pn < n_outs);
4139 found_projs |= 1 << pn;
4143 /* are keeps missing? */
4145 for(i = 0; i < n_outs; ++i) {
4148 const arch_register_req_t *req;
4149 const arch_register_class_t *class;
4151 if(found_projs & (1 << i)) {
4155 req = get_ia32_out_req(node, i);
4161 block = get_nodes_block(node);
4162 in[0] = new_r_Proj(current_ir_graph, block, node,
4163 arch_register_class_mode(class), i);
4164 if(last_keep != NULL) {
4165 be_Keep_add_node(last_keep, class, in[0]);
4167 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4173 * Adds missing keeps to nodes
4176 void add_missing_keeps(ia32_code_gen_t *cg)
4178 ir_graph *irg = be_get_birg_irg(cg->birg);
4179 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4182 /* do the transformation */
4183 void ia32_transform_graph(ia32_code_gen_t *cg) {
4184 register_transformers();
4186 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4187 edges_verify(cg->irg);
4188 add_missing_keeps(cg);
4189 edges_verify(cg->irg);
4192 void ia32_init_transform(void)
4194 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");