2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
563 * Construct a standard binary operation, set AM and immediate if required.
565 * @param op1 The first operand
566 * @param op2 The second operand
567 * @param func The node constructor function
568 * @return The constructed ia32 node.
570 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
571 construct_binop_float_func *func)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_node *new_node = NULL;
577 dbg_info *dbgi = get_irn_dbg_info(node);
578 ir_graph *irg = current_ir_graph;
579 ir_mode *mode = get_irn_mode(node);
580 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
581 ir_node *nomem = new_NoMem();
582 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
583 &ia32_fp_cw_regs[REG_FPCW]);
585 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
587 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
588 if (is_op_commutative(get_irn_op(node))) {
589 set_ia32_commutative(new_node);
592 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
598 * Construct a shift/rotate binary operation, sets AM and immediate if required.
600 * @param op1 The first operand
601 * @param op2 The second operand
602 * @param func The node constructor function
603 * @return The constructed ia32 node.
605 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
606 construct_binop_func *func)
608 ir_node *block = be_transform_node(get_nodes_block(node));
609 ir_node *new_op1 = be_transform_node(op1);
611 ir_node *new_op = NULL;
612 dbg_info *dbgi = get_irn_dbg_info(node);
613 ir_graph *irg = current_ir_graph;
614 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
615 ir_node *nomem = new_NoMem();
617 assert(! mode_is_float(get_irn_mode(node))
618 && "Shift/Rotate with float not supported");
620 new_op2 = create_immediate_or_transform(op2, 'N');
622 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
625 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
627 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
629 set_ia32_emit_cl(new_op);
636 * Construct a standard unary operation, set AM and immediate if required.
638 * @param op The operand
639 * @param func The node constructor function
640 * @return The constructed ia32 node.
642 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
644 ir_node *block = be_transform_node(get_nodes_block(node));
645 ir_node *new_op = be_transform_node(op);
646 ir_node *new_node = NULL;
647 ir_graph *irg = current_ir_graph;
648 dbg_info *dbgi = get_irn_dbg_info(node);
649 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
650 ir_node *nomem = new_NoMem();
652 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
653 DB((dbg, LEVEL_1, "INT unop ..."));
654 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
656 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
662 * Creates an ia32 Add.
664 * @return the created ia32 Add node
666 static ir_node *gen_Add(ir_node *node) {
667 ir_node *block = be_transform_node(get_nodes_block(node));
668 ir_node *op1 = get_Add_left(node);
669 ir_node *new_op1 = be_transform_node(op1);
670 ir_node *op2 = get_Add_right(node);
671 ir_node *new_op2 = be_transform_node(op2);
672 ir_node *new_op = NULL;
673 ir_graph *irg = current_ir_graph;
674 dbg_info *dbgi = get_irn_dbg_info(node);
675 ir_mode *mode = get_irn_mode(node);
676 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
677 ir_node *nomem = new_NoMem();
678 ir_node *expr_op, *imm_op;
680 /* Check if immediate optimization is on and */
681 /* if it's an operation with immediate. */
682 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
683 expr_op = get_expr_op(new_op1, new_op2);
685 assert((expr_op || imm_op) && "invalid operands");
687 if (mode_is_float(mode)) {
689 if (USE_SSE2(env_cg))
690 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
692 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
697 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
698 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
700 /* No expr_op means, that we have two const - one symconst and */
701 /* one tarval or another symconst - because this case is not */
702 /* covered by constant folding */
703 /* We need to check for: */
704 /* 1) symconst + const -> becomes a LEA */
705 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
706 /* linker doesn't support two symconsts */
708 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
709 /* this is the 2nd case */
710 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
711 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
712 set_ia32_am_flavour(new_op, ia32_am_B);
713 set_ia32_op_type(new_op, ia32_AddrModeS);
715 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
716 } else if (tp1 == ia32_ImmSymConst) {
717 tarval *tv = get_ia32_Immop_tarval(new_op2);
718 long offs = get_tarval_long(tv);
720 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
721 add_irn_dep(new_op, get_irg_frame(irg));
722 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
725 add_ia32_am_offs_int(new_op, offs);
726 set_ia32_am_flavour(new_op, ia32_am_OB);
727 set_ia32_op_type(new_op, ia32_AddrModeS);
728 } else if (tp2 == ia32_ImmSymConst) {
729 tarval *tv = get_ia32_Immop_tarval(new_op1);
730 long offs = get_tarval_long(tv);
732 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
733 add_irn_dep(new_op, get_irg_frame(irg));
734 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
736 add_ia32_am_offs_int(new_op, offs);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
738 set_ia32_am_flavour(new_op, ia32_am_OB);
739 set_ia32_op_type(new_op, ia32_AddrModeS);
741 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
742 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
743 tarval *restv = tarval_add(tv1, tv2);
745 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
747 new_op = new_rd_ia32_Const(dbgi, irg, block);
748 set_ia32_Const_tarval(new_op, restv);
749 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
752 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
755 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
756 tarval_classification_t class_tv, class_negtv;
757 tarval *tv = get_ia32_Immop_tarval(imm_op);
759 /* optimize tarvals */
760 class_tv = classify_tarval(tv);
761 class_negtv = classify_tarval(tarval_neg(tv));
763 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
764 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
765 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
766 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
769 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
770 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
771 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
777 /* This is a normal add */
778 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
781 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
782 set_ia32_commutative(new_op);
784 fold_immediate(new_op, 2, 3);
786 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
792 * Creates an ia32 Mul.
794 * @return the created ia32 Mul node
796 static ir_node *gen_Mul(ir_node *node) {
797 ir_node *op1 = get_Mul_left(node);
798 ir_node *op2 = get_Mul_right(node);
799 ir_mode *mode = get_irn_mode(node);
801 if (mode_is_float(mode)) {
803 if (USE_SSE2(env_cg))
804 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
806 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
810 for the lower 32bit of the result it doesn't matter whether we use
811 signed or unsigned multiplication so we use IMul as it has fewer
814 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
818 * Creates an ia32 Mulh.
819 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
820 * this result while Mul returns the lower 32 bit.
822 * @return the created ia32 Mulh node
824 static ir_node *gen_Mulh(ir_node *node) {
825 ir_node *block = be_transform_node(get_nodes_block(node));
826 ir_node *op1 = get_irn_n(node, 0);
827 ir_node *new_op1 = be_transform_node(op1);
828 ir_node *op2 = get_irn_n(node, 1);
829 ir_node *new_op2 = be_transform_node(op2);
830 ir_graph *irg = current_ir_graph;
831 dbg_info *dbgi = get_irn_dbg_info(node);
832 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
833 ir_mode *mode = get_irn_mode(node);
834 ir_node *proj_EAX, *proj_EDX, *res;
837 assert(!mode_is_float(mode) && "Mulh with float not supported");
838 if (mode_is_signed(mode)) {
839 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
841 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
844 set_ia32_commutative(res);
845 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
847 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
848 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
852 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
860 * Creates an ia32 And.
862 * @return The created ia32 And node
864 static ir_node *gen_And(ir_node *node) {
865 ir_node *op1 = get_And_left(node);
866 ir_node *op2 = get_And_right(node);
868 assert (! mode_is_float(get_irn_mode(node)));
869 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
875 * Creates an ia32 Or.
877 * @return The created ia32 Or node
879 static ir_node *gen_Or(ir_node *node) {
880 ir_node *op1 = get_Or_left(node);
881 ir_node *op2 = get_Or_right(node);
883 assert (! mode_is_float(get_irn_mode(node)));
884 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
890 * Creates an ia32 Eor.
892 * @return The created ia32 Eor node
894 static ir_node *gen_Eor(ir_node *node) {
895 ir_node *op1 = get_Eor_left(node);
896 ir_node *op2 = get_Eor_right(node);
898 assert(! mode_is_float(get_irn_mode(node)));
899 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
905 * Creates an ia32 Max.
907 * @return the created ia32 Max node
909 static ir_node *gen_Max(ir_node *node) {
910 ir_node *block = be_transform_node(get_nodes_block(node));
911 ir_node *op1 = get_irn_n(node, 0);
912 ir_node *new_op1 = be_transform_node(op1);
913 ir_node *op2 = get_irn_n(node, 1);
914 ir_node *new_op2 = be_transform_node(op2);
915 ir_graph *irg = current_ir_graph;
916 ir_mode *mode = get_irn_mode(node);
917 dbg_info *dbgi = get_irn_dbg_info(node);
918 ir_mode *op_mode = get_irn_mode(op1);
921 assert(get_mode_size_bits(mode) == 32);
923 if (mode_is_float(mode)) {
925 if (USE_SSE2(env_cg)) {
926 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
928 panic("Can't create Max node");
931 long pnc = pn_Cmp_Gt;
932 if (! mode_is_signed(op_mode)) {
933 pnc |= ia32_pn_Cmp_Unsigned;
935 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
936 new_op1, new_op2, pnc);
938 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
944 * Creates an ia32 Min.
946 * @return the created ia32 Min node
948 static ir_node *gen_Min(ir_node *node) {
949 ir_node *block = be_transform_node(get_nodes_block(node));
950 ir_node *op1 = get_irn_n(node, 0);
951 ir_node *new_op1 = be_transform_node(op1);
952 ir_node *op2 = get_irn_n(node, 1);
953 ir_node *new_op2 = be_transform_node(op2);
954 ir_graph *irg = current_ir_graph;
955 ir_mode *mode = get_irn_mode(node);
956 dbg_info *dbgi = get_irn_dbg_info(node);
957 ir_mode *op_mode = get_irn_mode(op1);
960 assert(get_mode_size_bits(mode) == 32);
962 if (mode_is_float(mode)) {
964 if (USE_SSE2(env_cg)) {
965 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
967 panic("can't create Min node");
970 long pnc = pn_Cmp_Lt;
971 if (! mode_is_signed(op_mode)) {
972 pnc |= ia32_pn_Cmp_Unsigned;
974 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
975 new_op1, new_op2, pnc);
977 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
984 * Creates an ia32 Sub.
986 * @return The created ia32 Sub node
988 static ir_node *gen_Sub(ir_node *node) {
989 ir_node *block = be_transform_node(get_nodes_block(node));
990 ir_node *op1 = get_Sub_left(node);
991 ir_node *new_op1 = be_transform_node(op1);
992 ir_node *op2 = get_Sub_right(node);
993 ir_node *new_op2 = be_transform_node(op2);
994 ir_node *new_op = NULL;
995 ir_graph *irg = current_ir_graph;
996 dbg_info *dbgi = get_irn_dbg_info(node);
997 ir_mode *mode = get_irn_mode(node);
998 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
999 ir_node *nomem = new_NoMem();
1000 ir_node *expr_op, *imm_op;
1002 /* Check if immediate optimization is on and */
1003 /* if it's an operation with immediate. */
1004 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1005 expr_op = get_expr_op(new_op1, new_op2);
1007 assert((expr_op || imm_op) && "invalid operands");
1009 if (mode_is_float(mode)) {
1011 if (USE_SSE2(env_cg))
1012 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1014 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1019 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1020 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1022 /* No expr_op means, that we have two const - one symconst and */
1023 /* one tarval or another symconst - because this case is not */
1024 /* covered by constant folding */
1025 /* We need to check for: */
1026 /* 1) symconst - const -> becomes a LEA */
1027 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1028 /* linker doesn't support two symconsts */
1029 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1030 /* this is the 2nd case */
1031 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1032 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1033 set_ia32_am_sc_sign(new_op);
1034 set_ia32_am_flavour(new_op, ia32_am_B);
1036 DBG_OPT_LEA3(op1, op2, node, new_op);
1037 } else if (tp1 == ia32_ImmSymConst) {
1038 tarval *tv = get_ia32_Immop_tarval(new_op2);
1039 long offs = get_tarval_long(tv);
1041 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1042 add_irn_dep(new_op, get_irg_frame(irg));
1043 DBG_OPT_LEA3(op1, op2, node, new_op);
1045 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1046 add_ia32_am_offs_int(new_op, -offs);
1047 set_ia32_am_flavour(new_op, ia32_am_OB);
1048 set_ia32_op_type(new_op, ia32_AddrModeS);
1049 } else if (tp2 == ia32_ImmSymConst) {
1050 tarval *tv = get_ia32_Immop_tarval(new_op1);
1051 long offs = get_tarval_long(tv);
1053 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1054 add_irn_dep(new_op, get_irg_frame(irg));
1055 DBG_OPT_LEA3(op1, op2, node, new_op);
1057 add_ia32_am_offs_int(new_op, offs);
1058 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1059 set_ia32_am_sc_sign(new_op);
1060 set_ia32_am_flavour(new_op, ia32_am_OB);
1061 set_ia32_op_type(new_op, ia32_AddrModeS);
1063 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1064 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1065 tarval *restv = tarval_sub(tv1, tv2);
1067 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1069 new_op = new_rd_ia32_Const(dbgi, irg, block);
1070 set_ia32_Const_tarval(new_op, restv);
1071 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1074 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1076 } else if (imm_op) {
1077 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1078 tarval_classification_t class_tv, class_negtv;
1079 tarval *tv = get_ia32_Immop_tarval(imm_op);
1081 /* optimize tarvals */
1082 class_tv = classify_tarval(tv);
1083 class_negtv = classify_tarval(tarval_neg(tv));
1085 if (class_tv == TV_CLASSIFY_ONE) {
1086 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1087 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1088 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1090 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1091 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1092 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1093 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1099 /* This is a normal sub */
1100 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1102 /* set AM support */
1103 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1105 fold_immediate(new_op, 2, 3);
1107 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1115 * Generates an ia32 DivMod with additional infrastructure for the
1116 * register allocator if needed.
1118 * @param dividend -no comment- :)
1119 * @param divisor -no comment- :)
1120 * @param dm_flav flavour_Div/Mod/DivMod
1121 * @return The created ia32 DivMod node
1123 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1124 ir_node *divisor, ia32_op_flavour_t dm_flav)
1126 ir_node *block = be_transform_node(get_nodes_block(node));
1127 ir_node *new_dividend = be_transform_node(dividend);
1128 ir_node *new_divisor = be_transform_node(divisor);
1129 ir_graph *irg = current_ir_graph;
1130 dbg_info *dbgi = get_irn_dbg_info(node);
1131 ir_mode *mode = get_irn_mode(node);
1132 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1133 ir_node *res, *proj_div, *proj_mod;
1134 ir_node *sign_extension;
1135 ir_node *in_keep[2];
1136 ir_node *mem, *new_mem;
1137 ir_node *projs[pn_DivMod_max];
1140 ia32_collect_Projs(node, projs, pn_DivMod_max);
1142 proj_div = proj_mod = NULL;
1146 mem = get_Div_mem(node);
1147 mode = get_Div_resmode(node);
1148 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1149 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1152 mem = get_Mod_mem(node);
1153 mode = get_Mod_resmode(node);
1154 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1155 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1157 case flavour_DivMod:
1158 mem = get_DivMod_mem(node);
1159 mode = get_DivMod_resmode(node);
1160 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1161 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1162 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1165 panic("invalid divmod flavour!");
1167 new_mem = be_transform_node(mem);
1169 if (mode_is_signed(mode)) {
1170 /* in signed mode, we need to sign extend the dividend */
1171 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1173 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1174 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1176 add_irn_dep(sign_extension, get_irg_frame(irg));
1179 if (mode_is_signed(mode)) {
1180 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1181 sign_extension, new_divisor, new_mem, dm_flav);
1183 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1184 sign_extension, new_divisor, new_mem, dm_flav);
1187 set_ia32_exc_label(res, has_exc);
1188 set_irn_pinned(res, get_irn_pinned(node));
1190 /* Matze: code can't handle this at the moment... */
1192 /* set AM support */
1193 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1196 /* check, which Proj-Keep, we need to add */
1198 if (proj_div == NULL) {
1199 /* We have only mod result: add div res Proj-Keep */
1200 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1203 if (proj_mod == NULL) {
1204 /* We have only div result: add mod res Proj-Keep */
1205 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1209 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1211 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1218 * Wrapper for generate_DivMod. Sets flavour_Mod.
1221 static ir_node *gen_Mod(ir_node *node) {
1222 return generate_DivMod(node, get_Mod_left(node),
1223 get_Mod_right(node), flavour_Mod);
1227 * Wrapper for generate_DivMod. Sets flavour_Div.
1230 static ir_node *gen_Div(ir_node *node) {
1231 return generate_DivMod(node, get_Div_left(node),
1232 get_Div_right(node), flavour_Div);
1236 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1238 static ir_node *gen_DivMod(ir_node *node) {
1239 return generate_DivMod(node, get_DivMod_left(node),
1240 get_DivMod_right(node), flavour_DivMod);
1246 * Creates an ia32 floating Div.
1248 * @return The created ia32 xDiv node
1250 static ir_node *gen_Quot(ir_node *node) {
1251 ir_node *block = be_transform_node(get_nodes_block(node));
1252 ir_node *op1 = get_Quot_left(node);
1253 ir_node *new_op1 = be_transform_node(op1);
1254 ir_node *op2 = get_Quot_right(node);
1255 ir_node *new_op2 = be_transform_node(op2);
1256 ir_graph *irg = current_ir_graph;
1257 dbg_info *dbgi = get_irn_dbg_info(node);
1258 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1259 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1263 if (USE_SSE2(env_cg)) {
1264 ir_mode *mode = get_irn_mode(op1);
1265 if (is_ia32_xConst(new_op2)) {
1266 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1267 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1268 copy_ia32_Immop_attr(new_op, new_op2);
1270 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1271 // Matze: disabled for now, spillslot coalescer fails
1272 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1274 set_ia32_ls_mode(new_op, mode);
1276 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1277 &ia32_fp_cw_regs[REG_FPCW]);
1278 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1279 new_op2, nomem, fpcw);
1280 // Matze: disabled for now (spillslot coalescer fails)
1281 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1283 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1289 * Creates an ia32 Shl.
1291 * @return The created ia32 Shl node
1293 static ir_node *gen_Shl(ir_node *node) {
1294 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1301 * Creates an ia32 Shr.
1303 * @return The created ia32 Shr node
1305 static ir_node *gen_Shr(ir_node *node) {
1306 return gen_shift_binop(node, get_Shr_left(node),
1307 get_Shr_right(node), new_rd_ia32_Shr);
1313 * Creates an ia32 Sar.
1315 * @return The created ia32 Shrs node
1317 static ir_node *gen_Shrs(ir_node *node) {
1318 ir_node *left = get_Shrs_left(node);
1319 ir_node *right = get_Shrs_right(node);
1320 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1321 tarval *tv = get_Const_tarval(right);
1322 long val = get_tarval_long(tv);
1324 /* this is a sign extension */
1325 ir_graph *irg = current_ir_graph;
1326 dbg_info *dbgi = get_irn_dbg_info(node);
1327 ir_node *block = be_transform_node(get_nodes_block(node));
1329 ir_node *new_op = be_transform_node(op);
1331 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1335 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1341 * Creates an ia32 RotL.
1343 * @param op1 The first operator
1344 * @param op2 The second operator
1345 * @return The created ia32 RotL node
1347 static ir_node *gen_RotL(ir_node *node,
1348 ir_node *op1, ir_node *op2) {
1349 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1355 * Creates an ia32 RotR.
1356 * NOTE: There is no RotR with immediate because this would always be a RotL
1357 * "imm-mode_size_bits" which can be pre-calculated.
1359 * @param op1 The first operator
1360 * @param op2 The second operator
1361 * @return The created ia32 RotR node
1363 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1365 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1371 * Creates an ia32 RotR or RotL (depending on the found pattern).
1373 * @return The created ia32 RotL or RotR node
1375 static ir_node *gen_Rot(ir_node *node) {
1376 ir_node *rotate = NULL;
1377 ir_node *op1 = get_Rot_left(node);
1378 ir_node *op2 = get_Rot_right(node);
1380 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1381 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1382 that means we can create a RotR instead of an Add and a RotL */
1384 if (get_irn_op(op2) == op_Add) {
1386 ir_node *left = get_Add_left(add);
1387 ir_node *right = get_Add_right(add);
1388 if (is_Const(right)) {
1389 tarval *tv = get_Const_tarval(right);
1390 ir_mode *mode = get_irn_mode(node);
1391 long bits = get_mode_size_bits(mode);
1393 if (get_irn_op(left) == op_Minus &&
1394 tarval_is_long(tv) &&
1395 get_tarval_long(tv) == bits)
1397 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1398 rotate = gen_RotR(node, op1, get_Minus_op(left));
1403 if (rotate == NULL) {
1404 rotate = gen_RotL(node, op1, op2);
1413 * Transforms a Minus node.
1415 * @param op The Minus operand
1416 * @return The created ia32 Minus node
1418 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1419 ir_node *block = be_transform_node(get_nodes_block(node));
1420 ir_graph *irg = current_ir_graph;
1421 dbg_info *dbgi = get_irn_dbg_info(node);
1422 ir_mode *mode = get_irn_mode(node);
1427 if (mode_is_float(mode)) {
1428 ir_node *new_op = be_transform_node(op);
1430 if (USE_SSE2(env_cg)) {
1431 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1432 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1433 ir_node *nomem = new_rd_NoMem(irg);
1435 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1437 size = get_mode_size_bits(mode);
1438 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1440 set_ia32_am_sc(res, ent);
1441 set_ia32_op_type(res, ia32_AddrModeS);
1442 set_ia32_ls_mode(res, mode);
1444 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1447 res = gen_unop(node, op, new_rd_ia32_Neg);
1450 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1456 * Transforms a Minus node.
1458 * @return The created ia32 Minus node
1460 static ir_node *gen_Minus(ir_node *node) {
1461 return gen_Minus_ex(node, get_Minus_op(node));
1466 * Transforms a Not node.
1468 * @return The created ia32 Not node
1470 static ir_node *gen_Not(ir_node *node) {
1471 ir_node *op = get_Not_op(node);
1473 assert (! mode_is_float(get_irn_mode(node)));
1474 return gen_unop(node, op, new_rd_ia32_Not);
1480 * Transforms an Abs node.
1482 * @return The created ia32 Abs node
1484 static ir_node *gen_Abs(ir_node *node) {
1485 ir_node *block = be_transform_node(get_nodes_block(node));
1486 ir_node *op = get_Abs_op(node);
1487 ir_node *new_op = be_transform_node(op);
1488 ir_graph *irg = current_ir_graph;
1489 dbg_info *dbgi = get_irn_dbg_info(node);
1490 ir_mode *mode = get_irn_mode(node);
1491 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1492 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1493 ir_node *nomem = new_NoMem();
1498 if (mode_is_float(mode)) {
1500 if (USE_SSE2(env_cg)) {
1501 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1503 size = get_mode_size_bits(mode);
1504 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1506 set_ia32_am_sc(res, ent);
1508 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1510 set_ia32_op_type(res, ia32_AddrModeS);
1511 set_ia32_ls_mode(res, mode);
1514 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1515 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1519 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1520 SET_IA32_ORIG_NODE(sign_extension,
1521 ia32_get_old_node_name(env_cg, node));
1523 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1524 sign_extension, nomem);
1525 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1527 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1528 sign_extension, nomem);
1529 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1538 * Transforms a Load.
1540 * @return the created ia32 Load node
1542 static ir_node *gen_Load(ir_node *node) {
1543 ir_node *block = be_transform_node(get_nodes_block(node));
1544 ir_node *ptr = get_Load_ptr(node);
1545 ir_node *new_ptr = be_transform_node(ptr);
1546 ir_node *mem = get_Load_mem(node);
1547 ir_node *new_mem = be_transform_node(mem);
1548 ir_graph *irg = current_ir_graph;
1549 dbg_info *dbgi = get_irn_dbg_info(node);
1550 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1551 ir_mode *mode = get_Load_mode(node);
1553 ir_node *lptr = new_ptr;
1556 ir_node *projs[pn_Load_max];
1557 ia32_am_flavour_t am_flav = ia32_am_B;
1559 ia32_collect_Projs(node, projs, pn_Load_max);
1561 /* address might be a constant (symconst or absolute address) */
1562 if (is_ia32_Const(new_ptr)) {
1567 if (mode_is_float(mode)) {
1569 if (USE_SSE2(env_cg)) {
1570 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1571 res_mode = mode_xmm;
1573 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1574 res_mode = mode_vfp;
1577 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1582 check for special case: the loaded value might not be used
1584 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1585 /* add a result proj and a Keep to produce a pseudo use */
1586 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1588 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1591 /* base is a constant address */
1593 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1594 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1595 am_flav = ia32_am_N;
1597 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1598 long offs = get_tarval_long(tv);
1600 add_ia32_am_offs_int(new_op, offs);
1601 am_flav = ia32_am_O;
1605 set_irn_pinned(new_op, get_irn_pinned(node));
1606 set_ia32_op_type(new_op, ia32_AddrModeS);
1607 set_ia32_am_flavour(new_op, am_flav);
1608 set_ia32_ls_mode(new_op, mode);
1610 /* make sure we are scheduled behind the initial IncSP/Barrier
1611 * to avoid spills being placed before it
1613 if (block == get_irg_start_block(irg)) {
1614 add_irn_dep(new_op, get_irg_frame(irg));
1617 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1618 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1626 * Transforms a Store.
1628 * @return the created ia32 Store node
1630 static ir_node *gen_Store(ir_node *node) {
1631 ir_node *block = be_transform_node(get_nodes_block(node));
1632 ir_node *ptr = get_Store_ptr(node);
1633 ir_node *new_ptr = be_transform_node(ptr);
1634 ir_node *val = get_Store_value(node);
1636 ir_node *mem = get_Store_mem(node);
1637 ir_node *new_mem = be_transform_node(mem);
1638 ir_graph *irg = current_ir_graph;
1639 dbg_info *dbgi = get_irn_dbg_info(node);
1640 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1641 ir_node *sptr = new_ptr;
1642 ir_mode *mode = get_irn_mode(val);
1645 ia32_am_flavour_t am_flav = ia32_am_B;
1647 /* address might be a constant (symconst or absolute address) */
1648 if (is_ia32_Const(new_ptr)) {
1653 if (mode_is_float(mode)) {
1656 new_val = be_transform_node(val);
1657 if (USE_SSE2(env_cg)) {
1658 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1661 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1665 new_val = create_immediate_or_transform(val, 0);
1667 if (get_mode_size_bits(mode) == 8) {
1668 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1671 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1676 /* base is an constant address */
1678 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1679 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1680 am_flav = ia32_am_N;
1682 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1683 long offs = get_tarval_long(tv);
1685 add_ia32_am_offs_int(new_op, offs);
1686 am_flav = ia32_am_O;
1690 set_irn_pinned(new_op, get_irn_pinned(node));
1691 set_ia32_op_type(new_op, ia32_AddrModeD);
1692 set_ia32_am_flavour(new_op, am_flav);
1693 set_ia32_ls_mode(new_op, mode);
1695 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1696 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1701 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1703 ir_node *cmp_a = get_Cmp_left(node);
1705 ir_node *cmp_b = get_Cmp_right(node);
1715 if(!is_Const(cmp_b))
1718 tv = get_Const_tarval(cmp_b);
1719 if(!tarval_is_null(tv))
1723 if(is_And(cmp_a) && (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg)) {
1724 and_left = get_And_left(cmp_a);
1725 and_right = get_And_right(cmp_a);
1727 new_cmp_a = be_transform_node(and_left);
1728 new_cmp_b = create_immediate_or_transform(and_right, 0);
1730 new_cmp_a = be_transform_node(cmp_a);
1731 new_cmp_b = be_transform_node(cmp_a);
1734 dbgi = get_irn_dbg_info(node);
1735 noreg = ia32_new_NoReg_gp(env_cg);
1736 nomem = new_NoMem();
1738 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1739 new_cmp_a, new_cmp_b, nomem, pnc);
1740 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1741 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1746 static ir_node *create_Switch(ir_node *node)
1748 ir_graph *irg = current_ir_graph;
1749 dbg_info *dbgi = get_irn_dbg_info(node);
1750 ir_node *block = be_transform_node(get_nodes_block(node));
1751 ir_node *sel = get_Cond_selector(node);
1752 ir_node *new_sel = be_transform_node(sel);
1754 int switch_min = INT_MAX;
1755 const ir_edge_t *edge;
1757 /* determine the smallest switch case value */
1758 foreach_out_edge(node, edge) {
1759 ir_node *proj = get_edge_src_irn(edge);
1760 int pn = get_Proj_proj(proj);
1765 if (switch_min != 0) {
1766 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1768 /* if smallest switch case is not 0 we need an additional sub */
1769 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1770 add_ia32_am_offs_int(new_sel, -switch_min);
1771 set_ia32_am_flavour(new_sel, ia32_am_OB);
1772 set_ia32_op_type(new_sel, ia32_AddrModeS);
1774 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1777 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1778 set_ia32_pncode(res, get_Cond_defaultProj(node));
1780 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1786 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1788 * @return The transformed node.
1790 static ir_node *gen_Cond(ir_node *node) {
1791 ir_node *block = be_transform_node(get_nodes_block(node));
1792 ir_graph *irg = current_ir_graph;
1793 dbg_info *dbgi = get_irn_dbg_info(node);
1794 ir_node *sel = get_Cond_selector(node);
1795 ir_mode *sel_mode = get_irn_mode(sel);
1796 ir_node *res = NULL;
1797 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1804 ir_node *nomem = new_NoMem();
1807 if (sel_mode != mode_b) {
1808 return create_Switch(node);
1811 cmp = get_Proj_pred(sel);
1812 cmp_a = get_Cmp_left(cmp);
1813 cmp_b = get_Cmp_right(cmp);
1814 cmp_mode = get_irn_mode(cmp_a);
1815 pnc = get_Proj_proj(sel);
1816 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1817 pnc |= ia32_pn_Cmp_Unsigned;
1820 if(mode_needs_gp_reg(cmp_mode)) {
1821 res = try_create_TestJmp(block, cmp, pnc);
1826 new_cmp_a = be_transform_node(cmp_a);
1827 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1829 if (mode_is_float(cmp_mode)) {
1831 if (USE_SSE2(env_cg)) {
1832 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1834 set_ia32_commutative(res);
1835 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1836 set_ia32_ls_mode(res, cmp_mode);
1839 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1840 set_ia32_commutative(res);
1841 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1842 pn_ia32_vfCondJmp_temp_reg_eax);
1843 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1847 assert(get_mode_size_bits(cmp_mode) == 32);
1848 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1849 new_cmp_a, new_cmp_b, nomem, pnc);
1850 set_ia32_commutative(res);
1851 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1854 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1862 * Transforms a CopyB node.
1864 * @return The transformed node.
1866 static ir_node *gen_CopyB(ir_node *node) {
1867 ir_node *block = be_transform_node(get_nodes_block(node));
1868 ir_node *src = get_CopyB_src(node);
1869 ir_node *new_src = be_transform_node(src);
1870 ir_node *dst = get_CopyB_dst(node);
1871 ir_node *new_dst = be_transform_node(dst);
1872 ir_node *mem = get_CopyB_mem(node);
1873 ir_node *new_mem = be_transform_node(mem);
1874 ir_node *res = NULL;
1875 ir_graph *irg = current_ir_graph;
1876 dbg_info *dbgi = get_irn_dbg_info(node);
1877 int size = get_type_size_bytes(get_CopyB_type(node));
1878 ir_mode *dst_mode = get_irn_mode(dst);
1879 ir_mode *src_mode = get_irn_mode(src);
1883 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1884 /* then we need the size explicitly in ECX. */
1885 if (size >= 32 * 4) {
1886 rem = size & 0x3; /* size % 4 */
1889 res = new_rd_ia32_Const(dbgi, irg, block);
1890 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1891 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1893 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1894 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1896 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1897 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1898 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1899 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1900 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1903 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1904 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1906 /* ok: now attach Proj's because movsd will destroy esi and edi */
1907 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1908 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1909 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1912 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1918 ir_node *gen_be_Copy(ir_node *node)
1920 ir_node *result = be_duplicate_node(node);
1921 ir_mode *mode = get_irn_mode(result);
1923 if (mode_needs_gp_reg(mode)) {
1924 set_irn_mode(result, mode_Iu);
1933 * Transforms a Mux node into CMov.
1935 * @return The transformed node.
1937 static ir_node *gen_Mux(ir_node *node) {
1938 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1939 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1941 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1947 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1948 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1949 ir_node *psi_default);
1952 * Transforms a Psi node into CMov.
1954 * @return The transformed node.
1956 static ir_node *gen_Psi(ir_node *node) {
1957 ir_node *block = be_transform_node(get_nodes_block(node));
1958 ir_node *psi_true = get_Psi_val(node, 0);
1959 ir_node *psi_default = get_Psi_default(node);
1960 ia32_code_gen_t *cg = env_cg;
1961 ir_graph *irg = current_ir_graph;
1962 dbg_info *dbgi = get_irn_dbg_info(node);
1963 ir_node *cond = get_Psi_cond(node, 0);
1964 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1965 ir_node *nomem = new_NoMem();
1967 ir_node *cmp, *cmp_a, *cmp_b;
1968 ir_node *new_cmp_a, *new_cmp_b;
1972 assert(get_Psi_n_conds(node) == 1);
1973 assert(get_irn_mode(cond) == mode_b);
1975 if(is_And(cond) || is_Or(cond)) {
1976 ir_node *new_cond = be_transform_node(cond);
1977 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
1978 arch_set_irn_register(env_cg->arch_env, zero,
1979 &ia32_gp_regs[REG_GP_NOREG]);
1981 /* we have to compare the result against zero */
1982 new_cmp_a = new_cond;
1987 cmp = get_Proj_pred(cond);
1988 cmp_a = get_Cmp_left(cmp);
1989 cmp_b = get_Cmp_right(cmp);
1990 cmp_mode = get_irn_mode(cmp_a);
1991 pnc = get_Proj_proj(cond);
1993 new_cmp_a = be_transform_node(cmp_a);
1994 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1996 if (!mode_is_signed(cmp_mode)) {
1997 pnc |= ia32_pn_Cmp_Unsigned;
2001 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2002 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2003 new_cmp_a, new_cmp_b, nomem, pnc);
2004 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2005 pnc = get_negated_pnc(pnc, cmp_mode);
2006 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2007 new_cmp_a, new_cmp_b, nomem, pnc);
2009 ir_node *new_psi_true = be_transform_node(psi_true);
2010 ir_node *new_psi_default = be_transform_node(psi_default);
2011 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2012 new_psi_true, new_psi_default, pnc);
2014 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2020 * Following conversion rules apply:
2024 * 1) n bit -> m bit n > m (downscale)
2026 * 2) n bit -> m bit n == m (sign change)
2028 * 3) n bit -> m bit n < m (upscale)
2029 * a) source is signed: movsx
2030 * b) source is unsigned: and with lower bits sets
2034 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2038 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2042 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2043 * x87 is mode_E internally, conversions happen only at load and store
2044 * in non-strict semantic
2048 * Create a conversion from x87 state register to general purpose.
2050 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2051 ir_node *block = be_transform_node(get_nodes_block(node));
2052 ir_node *op = get_Conv_op(node);
2053 ir_node *new_op = be_transform_node(op);
2054 ia32_code_gen_t *cg = env_cg;
2055 ir_graph *irg = current_ir_graph;
2056 dbg_info *dbgi = get_irn_dbg_info(node);
2057 ir_node *noreg = ia32_new_NoReg_gp(cg);
2058 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2059 ir_node *fist, *load;
2062 fist = new_rd_ia32_vfist(dbgi, irg, block,
2063 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2065 set_irn_pinned(fist, op_pin_state_floats);
2066 set_ia32_use_frame(fist);
2067 set_ia32_op_type(fist, ia32_AddrModeD);
2068 set_ia32_am_flavour(fist, ia32_am_B);
2069 set_ia32_ls_mode(fist, mode_Iu);
2070 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2073 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2075 set_irn_pinned(load, op_pin_state_floats);
2076 set_ia32_use_frame(load);
2077 set_ia32_op_type(load, ia32_AddrModeS);
2078 set_ia32_am_flavour(load, ia32_am_B);
2079 set_ia32_ls_mode(load, mode_Iu);
2080 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2082 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2086 * Create a conversion from general purpose to x87 register
2088 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2089 ir_node *block = be_transform_node(get_nodes_block(node));
2090 ir_node *op = get_Conv_op(node);
2091 ir_node *new_op = be_transform_node(op);
2092 ir_graph *irg = current_ir_graph;
2093 dbg_info *dbgi = get_irn_dbg_info(node);
2094 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2095 ir_node *nomem = new_NoMem();
2096 ir_node *fild, *store;
2099 /* first convert to 32 bit if necessary */
2100 src_bits = get_mode_size_bits(src_mode);
2101 if (src_bits == 8) {
2102 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2103 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2104 set_ia32_ls_mode(new_op, src_mode);
2105 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2106 } else if (src_bits < 32) {
2107 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2108 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2109 set_ia32_ls_mode(new_op, src_mode);
2110 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2114 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2116 set_ia32_use_frame(store);
2117 set_ia32_op_type(store, ia32_AddrModeD);
2118 set_ia32_am_flavour(store, ia32_am_OB);
2119 set_ia32_ls_mode(store, mode_Iu);
2122 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2124 set_ia32_use_frame(fild);
2125 set_ia32_op_type(fild, ia32_AddrModeS);
2126 set_ia32_am_flavour(fild, ia32_am_OB);
2127 set_ia32_ls_mode(fild, mode_Iu);
2129 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2132 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2135 ir_node *block = get_nodes_block(node);
2136 ir_graph *irg = current_ir_graph;
2137 dbg_info *dbgi = get_irn_dbg_info(node);
2138 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2139 ir_node *nomem = new_NoMem();
2140 int src_bits = get_mode_size_bits(src_mode);
2141 int tgt_bits = get_mode_size_bits(tgt_mode);
2142 ir_node *frame = get_irg_frame(irg);
2143 ir_mode *smaller_mode;
2144 ir_node *store, *load;
2147 if(src_bits <= tgt_bits)
2148 smaller_mode = src_mode;
2150 smaller_mode = tgt_mode;
2152 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2154 set_ia32_use_frame(store);
2155 set_ia32_op_type(store, ia32_AddrModeD);
2156 set_ia32_am_flavour(store, ia32_am_OB);
2158 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2160 set_ia32_use_frame(load);
2161 set_ia32_op_type(load, ia32_AddrModeS);
2162 set_ia32_am_flavour(load, ia32_am_OB);
2164 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2169 * Transforms a Conv node.
2171 * @return The created ia32 Conv node
2173 static ir_node *gen_Conv(ir_node *node) {
2174 ir_node *block = be_transform_node(get_nodes_block(node));
2175 ir_node *op = get_Conv_op(node);
2176 ir_node *new_op = be_transform_node(op);
2177 ir_graph *irg = current_ir_graph;
2178 dbg_info *dbgi = get_irn_dbg_info(node);
2179 ir_mode *src_mode = get_irn_mode(op);
2180 ir_mode *tgt_mode = get_irn_mode(node);
2181 int src_bits = get_mode_size_bits(src_mode);
2182 int tgt_bits = get_mode_size_bits(tgt_mode);
2183 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2184 ir_node *nomem = new_rd_NoMem(irg);
2187 if (src_mode == tgt_mode) {
2188 if (get_Conv_strict(node)) {
2189 if (USE_SSE2(env_cg)) {
2190 /* when we are in SSE mode, we can kill all strict no-op conversion */
2194 /* this should be optimized already, but who knows... */
2195 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2196 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2201 if (mode_is_float(src_mode)) {
2202 /* we convert from float ... */
2203 if (mode_is_float(tgt_mode)) {
2204 if(src_mode == mode_E && tgt_mode == mode_D
2205 && !get_Conv_strict(node)) {
2206 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2211 if (USE_SSE2(env_cg)) {
2212 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2213 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2214 set_ia32_ls_mode(res, tgt_mode);
2216 // Matze: TODO what about strict convs?
2217 if(get_Conv_strict(node)) {
2218 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2219 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2222 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2227 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2228 if (USE_SSE2(env_cg)) {
2229 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2230 set_ia32_ls_mode(res, src_mode);
2232 return gen_x87_fp_to_gp(node);
2236 /* we convert from int ... */
2237 if (mode_is_float(tgt_mode)) {
2240 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2241 if (USE_SSE2(env_cg)) {
2242 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2243 set_ia32_ls_mode(res, tgt_mode);
2244 if(src_bits == 32) {
2245 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2248 return gen_x87_gp_to_fp(node, src_mode);
2252 ir_mode *smaller_mode;
2255 if (src_bits == tgt_bits) {
2256 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2260 if (src_bits < tgt_bits) {
2261 smaller_mode = src_mode;
2262 smaller_bits = src_bits;
2264 smaller_mode = tgt_mode;
2265 smaller_bits = tgt_bits;
2268 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2269 if (smaller_bits == 8) {
2270 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2271 set_ia32_ls_mode(res, smaller_mode);
2273 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2274 set_ia32_ls_mode(res, smaller_mode);
2276 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2280 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2286 int check_immediate_constraint(long val, char immediate_constraint_type)
2288 switch (immediate_constraint_type) {
2292 return val >= 0 && val <= 32;
2294 return val >= 0 && val <= 63;
2296 return val >= -128 && val <= 127;
2298 return val == 0xff || val == 0xffff;
2300 return val >= 0 && val <= 3;
2302 return val >= 0 && val <= 255;
2304 return val >= 0 && val <= 127;
2308 panic("Invalid immediate constraint found");
2313 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2316 tarval *offset = NULL;
2317 int offset_sign = 0;
2319 ir_entity *symconst_ent = NULL;
2320 int symconst_sign = 0;
2322 ir_node *cnst = NULL;
2323 ir_node *symconst = NULL;
2329 mode = get_irn_mode(node);
2330 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2331 !mode_is_reference(mode)) {
2335 if(is_Minus(node)) {
2337 node = get_Minus_op(node);
2340 if(is_Const(node)) {
2343 offset_sign = minus;
2344 } else if(is_SymConst(node)) {
2347 symconst_sign = minus;
2348 } else if(is_Add(node)) {
2349 ir_node *left = get_Add_left(node);
2350 ir_node *right = get_Add_right(node);
2351 if(is_Const(left) && is_SymConst(right)) {
2354 symconst_sign = minus;
2355 offset_sign = minus;
2356 } else if(is_SymConst(left) && is_Const(right)) {
2359 symconst_sign = minus;
2360 offset_sign = minus;
2362 } else if(is_Sub(node)) {
2363 ir_node *left = get_Sub_left(node);
2364 ir_node *right = get_Sub_right(node);
2365 if(is_Const(left) && is_SymConst(right)) {
2368 symconst_sign = !minus;
2369 offset_sign = minus;
2370 } else if(is_SymConst(left) && is_Const(right)) {
2373 symconst_sign = minus;
2374 offset_sign = !minus;
2381 offset = get_Const_tarval(cnst);
2382 if(tarval_is_long(offset)) {
2383 val = get_tarval_long(offset);
2384 } else if(tarval_is_null(offset)) {
2387 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2392 if(!check_immediate_constraint(val, immediate_constraint_type))
2395 if(symconst != NULL) {
2396 if(immediate_constraint_type != 0) {
2397 /* we need full 32bits for symconsts */
2401 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2403 symconst_ent = get_SymConst_entity(symconst);
2405 if(cnst == NULL && symconst == NULL)
2408 if(offset_sign && offset != NULL) {
2409 offset = tarval_neg(offset);
2412 irg = current_ir_graph;
2413 dbgi = get_irn_dbg_info(node);
2414 block = get_irg_start_block(irg);
2415 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2417 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2419 /* make sure we don't schedule stuff before the barrier */
2420 add_irn_dep(res, get_irg_frame(irg));
2426 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2428 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2429 if (new_node == NULL) {
2430 new_node = be_transform_node(node);
2435 typedef struct constraint_t constraint_t;
2436 struct constraint_t {
2439 const arch_register_req_t **out_reqs;
2441 const arch_register_req_t *req;
2442 unsigned immediate_possible;
2443 char immediate_type;
2446 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2448 int immediate_possible = 0;
2449 char immediate_type = 0;
2450 unsigned limited = 0;
2451 const arch_register_class_t *cls = NULL;
2453 struct obstack *obst;
2454 arch_register_req_t *req;
2455 unsigned *limited_ptr;
2459 /* TODO: replace all the asserts with nice error messages */
2461 printf("Constraint: %s\n", c);
2471 assert(cls == NULL ||
2472 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2473 cls = &ia32_reg_classes[CLASS_ia32_gp];
2474 limited |= 1 << REG_EAX;
2477 assert(cls == NULL ||
2478 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2479 cls = &ia32_reg_classes[CLASS_ia32_gp];
2480 limited |= 1 << REG_EBX;
2483 assert(cls == NULL ||
2484 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2485 cls = &ia32_reg_classes[CLASS_ia32_gp];
2486 limited |= 1 << REG_ECX;
2489 assert(cls == NULL ||
2490 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2491 cls = &ia32_reg_classes[CLASS_ia32_gp];
2492 limited |= 1 << REG_EDX;
2495 assert(cls == NULL ||
2496 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2497 cls = &ia32_reg_classes[CLASS_ia32_gp];
2498 limited |= 1 << REG_EDI;
2501 assert(cls == NULL ||
2502 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2503 cls = &ia32_reg_classes[CLASS_ia32_gp];
2504 limited |= 1 << REG_ESI;
2507 case 'q': /* q means lower part of the regs only, this makes no
2508 * difference to Q for us (we only assigne whole registers) */
2509 assert(cls == NULL ||
2510 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2511 cls = &ia32_reg_classes[CLASS_ia32_gp];
2512 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2516 assert(cls == NULL ||
2517 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2518 cls = &ia32_reg_classes[CLASS_ia32_gp];
2519 limited |= 1 << REG_EAX | 1 << REG_EDX;
2522 assert(cls == NULL ||
2523 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2524 cls = &ia32_reg_classes[CLASS_ia32_gp];
2525 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2526 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2533 assert(cls == NULL);
2534 cls = &ia32_reg_classes[CLASS_ia32_gp];
2540 /* TODO: mark values so the x87 simulator knows about t and u */
2541 assert(cls == NULL);
2542 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2547 assert(cls == NULL);
2548 /* TODO: check that sse2 is supported */
2549 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2559 assert(!immediate_possible);
2560 immediate_possible = 1;
2561 immediate_type = *c;
2565 assert(!immediate_possible);
2566 immediate_possible = 1;
2570 assert(!immediate_possible && cls == NULL);
2571 immediate_possible = 1;
2572 cls = &ia32_reg_classes[CLASS_ia32_gp];
2585 assert(constraint->is_in && "can only specify same constraint "
2588 sscanf(c, "%d%n", &same_as, &p);
2595 case 'E': /* no float consts yet */
2596 case 'F': /* no float consts yet */
2597 case 's': /* makes no sense on x86 */
2598 case 'X': /* we can't support that in firm */
2602 case '<': /* no autodecrement on x86 */
2603 case '>': /* no autoincrement on x86 */
2604 case 'C': /* sse constant not supported yet */
2605 case 'G': /* 80387 constant not supported yet */
2606 case 'y': /* we don't support mmx registers yet */
2607 case 'Z': /* not available in 32 bit mode */
2608 case 'e': /* not available in 32 bit mode */
2609 assert(0 && "asm constraint not supported");
2612 assert(0 && "unknown asm constraint found");
2619 const arch_register_req_t *other_constr;
2621 assert(cls == NULL && "same as and register constraint not supported");
2622 assert(!immediate_possible && "same as and immediate constraint not "
2624 assert(same_as < constraint->n_outs && "wrong constraint number in "
2625 "same_as constraint");
2627 other_constr = constraint->out_reqs[same_as];
2629 req = obstack_alloc(obst, sizeof(req[0]));
2630 req->cls = other_constr->cls;
2631 req->type = arch_register_req_type_should_be_same;
2632 req->limited = NULL;
2633 req->other_same = pos;
2634 req->other_different = -1;
2636 /* switch constraints. This is because in firm we have same_as
2637 * constraints on the output constraints while in the gcc asm syntax
2638 * they are specified on the input constraints */
2639 constraint->req = other_constr;
2640 constraint->out_reqs[same_as] = req;
2641 constraint->immediate_possible = 0;
2645 if(immediate_possible && cls == NULL) {
2646 cls = &ia32_reg_classes[CLASS_ia32_gp];
2648 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2649 assert(cls != NULL);
2651 if(immediate_possible) {
2652 assert(constraint->is_in
2653 && "imeediates make no sense for output constraints");
2655 /* todo: check types (no float input on 'r' constrainted in and such... */
2657 irg = current_ir_graph;
2658 obst = get_irg_obstack(irg);
2661 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2662 limited_ptr = (unsigned*) (req+1);
2664 req = obstack_alloc(obst, sizeof(req[0]));
2666 memset(req, 0, sizeof(req[0]));
2669 req->type = arch_register_req_type_limited;
2670 *limited_ptr = limited;
2671 req->limited = limited_ptr;
2673 req->type = arch_register_req_type_normal;
2677 constraint->req = req;
2678 constraint->immediate_possible = immediate_possible;
2679 constraint->immediate_type = immediate_type;
2683 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2690 panic("Clobbers not supported yet");
2693 ir_node *gen_ASM(ir_node *node)
2696 ir_graph *irg = current_ir_graph;
2697 ir_node *block = be_transform_node(get_nodes_block(node));
2698 dbg_info *dbgi = get_irn_dbg_info(node);
2705 ia32_asm_attr_t *attr;
2706 const arch_register_req_t **out_reqs;
2707 const arch_register_req_t **in_reqs;
2708 struct obstack *obst;
2709 constraint_t parsed_constraint;
2711 /* assembler could contain float statements */
2714 /* transform inputs */
2715 arity = get_irn_arity(node);
2716 in = alloca(arity * sizeof(in[0]));
2717 memset(in, 0, arity * sizeof(in[0]));
2719 n_outs = get_ASM_n_output_constraints(node);
2720 n_clobbers = get_ASM_n_clobbers(node);
2721 out_arity = n_outs + n_clobbers;
2723 /* construct register constraints */
2724 obst = get_irg_obstack(irg);
2725 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2726 parsed_constraint.out_reqs = out_reqs;
2727 parsed_constraint.n_outs = n_outs;
2728 parsed_constraint.is_in = 0;
2729 for(i = 0; i < out_arity; ++i) {
2733 const ir_asm_constraint *constraint;
2734 constraint = & get_ASM_output_constraints(node) [i];
2735 c = get_id_str(constraint->constraint);
2736 parse_asm_constraint(i, &parsed_constraint, c);
2738 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2739 c = get_id_str(glob_id);
2740 parse_clobber(node, i, &parsed_constraint, c);
2742 out_reqs[i] = parsed_constraint.req;
2745 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2746 parsed_constraint.is_in = 1;
2747 for(i = 0; i < arity; ++i) {
2748 const ir_asm_constraint *constraint;
2752 constraint = & get_ASM_input_constraints(node) [i];
2753 constr_id = constraint->constraint;
2754 c = get_id_str(constr_id);
2755 parse_asm_constraint(i, &parsed_constraint, c);
2756 in_reqs[i] = parsed_constraint.req;
2758 if(parsed_constraint.immediate_possible) {
2759 ir_node *pred = get_irn_n(node, i);
2760 char imm_type = parsed_constraint.immediate_type;
2761 ir_node *immediate = try_create_Immediate(pred, imm_type);
2763 if(immediate != NULL) {
2769 /* transform inputs */
2770 for(i = 0; i < arity; ++i) {
2772 ir_node *transformed;
2777 pred = get_irn_n(node, i);
2778 transformed = be_transform_node(pred);
2779 in[i] = transformed;
2782 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2784 generic_attr = get_irn_generic_attr(res);
2785 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2786 attr->asm_text = get_ASM_text(node);
2787 set_ia32_out_req_all(res, out_reqs);
2788 set_ia32_in_req_all(res, in_reqs);
2790 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2795 /********************************************
2798 * | |__ ___ _ __ ___ __| | ___ ___
2799 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2800 * | |_) | __/ | | | (_) | (_| | __/\__ \
2801 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2803 ********************************************/
2805 static ir_node *gen_be_StackParam(ir_node *node) {
2806 ir_node *block = be_transform_node(get_nodes_block(node));
2807 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2808 ir_node *new_ptr = be_transform_node(ptr);
2809 ir_node *new_op = NULL;
2810 ir_graph *irg = current_ir_graph;
2811 dbg_info *dbgi = get_irn_dbg_info(node);
2812 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2813 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2814 ir_mode *load_mode = get_irn_mode(node);
2815 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2819 if (mode_is_float(load_mode)) {
2821 if (USE_SSE2(env_cg)) {
2822 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2823 pn_res = pn_ia32_xLoad_res;
2824 proj_mode = mode_xmm;
2826 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2827 pn_res = pn_ia32_vfld_res;
2828 proj_mode = mode_vfp;
2831 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2832 proj_mode = mode_Iu;
2833 pn_res = pn_ia32_Load_res;
2836 set_irn_pinned(new_op, op_pin_state_floats);
2837 set_ia32_frame_ent(new_op, ent);
2838 set_ia32_use_frame(new_op);
2840 set_ia32_op_type(new_op, ia32_AddrModeS);
2841 set_ia32_am_flavour(new_op, ia32_am_B);
2842 set_ia32_ls_mode(new_op, load_mode);
2843 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2845 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2847 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2851 * Transforms a FrameAddr into an ia32 Add.
2853 static ir_node *gen_be_FrameAddr(ir_node *node) {
2854 ir_node *block = be_transform_node(get_nodes_block(node));
2855 ir_node *op = be_get_FrameAddr_frame(node);
2856 ir_node *new_op = be_transform_node(op);
2857 ir_graph *irg = current_ir_graph;
2858 dbg_info *dbgi = get_irn_dbg_info(node);
2859 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2862 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2863 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2864 set_ia32_use_frame(res);
2865 set_ia32_am_flavour(res, ia32_am_OB);
2867 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2873 * Transforms a FrameLoad into an ia32 Load.
2875 static ir_node *gen_be_FrameLoad(ir_node *node) {
2876 ir_node *block = be_transform_node(get_nodes_block(node));
2877 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2878 ir_node *new_mem = be_transform_node(mem);
2879 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2880 ir_node *new_ptr = be_transform_node(ptr);
2881 ir_node *new_op = NULL;
2882 ir_graph *irg = current_ir_graph;
2883 dbg_info *dbgi = get_irn_dbg_info(node);
2884 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2885 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2886 ir_mode *mode = get_type_mode(get_entity_type(ent));
2887 ir_node *projs[pn_Load_max];
2889 ia32_collect_Projs(node, projs, pn_Load_max);
2891 if (mode_is_float(mode)) {
2893 if (USE_SSE2(env_cg)) {
2894 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2897 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2901 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2904 set_irn_pinned(new_op, op_pin_state_floats);
2905 set_ia32_frame_ent(new_op, ent);
2906 set_ia32_use_frame(new_op);
2908 set_ia32_op_type(new_op, ia32_AddrModeS);
2909 set_ia32_am_flavour(new_op, ia32_am_B);
2910 set_ia32_ls_mode(new_op, mode);
2911 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2913 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2920 * Transforms a FrameStore into an ia32 Store.
2922 static ir_node *gen_be_FrameStore(ir_node *node) {
2923 ir_node *block = be_transform_node(get_nodes_block(node));
2924 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2925 ir_node *new_mem = be_transform_node(mem);
2926 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2927 ir_node *new_ptr = be_transform_node(ptr);
2928 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2929 ir_node *new_val = be_transform_node(val);
2930 ir_node *new_op = NULL;
2931 ir_graph *irg = current_ir_graph;
2932 dbg_info *dbgi = get_irn_dbg_info(node);
2933 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2934 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2935 ir_mode *mode = get_irn_mode(val);
2937 if (mode_is_float(mode)) {
2939 if (USE_SSE2(env_cg)) {
2940 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2942 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2944 } else if (get_mode_size_bits(mode) == 8) {
2945 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2947 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2950 set_ia32_frame_ent(new_op, ent);
2951 set_ia32_use_frame(new_op);
2953 set_ia32_op_type(new_op, ia32_AddrModeD);
2954 set_ia32_am_flavour(new_op, ia32_am_B);
2955 set_ia32_ls_mode(new_op, mode);
2957 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2963 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2965 static ir_node *gen_be_Return(ir_node *node) {
2966 ir_graph *irg = current_ir_graph;
2967 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2968 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2969 ir_entity *ent = get_irg_entity(irg);
2970 ir_type *tp = get_entity_type(ent);
2975 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2976 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2979 int pn_ret_val, pn_ret_mem, arity, i;
2981 assert(ret_val != NULL);
2982 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2983 return be_duplicate_node(node);
2986 res_type = get_method_res_type(tp, 0);
2988 if (! is_Primitive_type(res_type)) {
2989 return be_duplicate_node(node);
2992 mode = get_type_mode(res_type);
2993 if (! mode_is_float(mode)) {
2994 return be_duplicate_node(node);
2997 assert(get_method_n_ress(tp) == 1);
2999 pn_ret_val = get_Proj_proj(ret_val);
3000 pn_ret_mem = get_Proj_proj(ret_mem);
3002 /* get the Barrier */
3003 barrier = get_Proj_pred(ret_val);
3005 /* get result input of the Barrier */
3006 ret_val = get_irn_n(barrier, pn_ret_val);
3007 new_ret_val = be_transform_node(ret_val);
3009 /* get memory input of the Barrier */
3010 ret_mem = get_irn_n(barrier, pn_ret_mem);
3011 new_ret_mem = be_transform_node(ret_mem);
3013 frame = get_irg_frame(irg);
3015 dbgi = get_irn_dbg_info(barrier);
3016 block = be_transform_node(get_nodes_block(barrier));
3018 noreg = ia32_new_NoReg_gp(env_cg);
3020 /* store xmm0 onto stack */
3021 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3022 set_ia32_ls_mode(sse_store, mode);
3023 set_ia32_op_type(sse_store, ia32_AddrModeD);
3024 set_ia32_use_frame(sse_store);
3025 set_ia32_am_flavour(sse_store, ia32_am_B);
3028 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3029 set_ia32_ls_mode(fld, mode);
3030 set_ia32_op_type(fld, ia32_AddrModeS);
3031 set_ia32_use_frame(fld);
3032 set_ia32_am_flavour(fld, ia32_am_B);
3034 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3035 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3036 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3038 /* create a new barrier */
3039 arity = get_irn_arity(barrier);
3040 in = alloca(arity * sizeof(in[0]));
3041 for (i = 0; i < arity; ++i) {
3044 if (i == pn_ret_val) {
3046 } else if (i == pn_ret_mem) {
3049 ir_node *in = get_irn_n(barrier, i);
3050 new_in = be_transform_node(in);
3055 new_barrier = new_ir_node(dbgi, irg, block,
3056 get_irn_op(barrier), get_irn_mode(barrier),
3058 copy_node_attr(barrier, new_barrier);
3059 be_duplicate_deps(barrier, new_barrier);
3060 be_set_transformed_node(barrier, new_barrier);
3061 mark_irn_visited(barrier);
3063 /* transform normally */
3064 return be_duplicate_node(node);
3068 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3070 static ir_node *gen_be_AddSP(ir_node *node) {
3071 ir_node *block = be_transform_node(get_nodes_block(node));
3072 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3074 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3075 ir_node *new_sp = be_transform_node(sp);
3076 ir_graph *irg = current_ir_graph;
3077 dbg_info *dbgi = get_irn_dbg_info(node);
3078 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3079 ir_node *nomem = new_NoMem();
3082 new_sz = create_immediate_or_transform(sz, 0);
3084 /* ia32 stack grows in reverse direction, make a SubSP */
3085 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3087 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3088 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3094 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3096 static ir_node *gen_be_SubSP(ir_node *node) {
3097 ir_node *block = be_transform_node(get_nodes_block(node));
3098 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3100 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3101 ir_node *new_sp = be_transform_node(sp);
3102 ir_graph *irg = current_ir_graph;
3103 dbg_info *dbgi = get_irn_dbg_info(node);
3104 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3105 ir_node *nomem = new_NoMem();
3108 new_sz = create_immediate_or_transform(sz, 0);
3110 /* ia32 stack grows in reverse direction, make an AddSP */
3111 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3112 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3113 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3119 * This function just sets the register for the Unknown node
3120 * as this is not done during register allocation because Unknown
3121 * is an "ignore" node.
3123 static ir_node *gen_Unknown(ir_node *node) {
3124 ir_mode *mode = get_irn_mode(node);
3126 if (mode_is_float(mode)) {
3127 if (USE_SSE2(env_cg))
3128 return ia32_new_Unknown_xmm(env_cg);
3130 return ia32_new_Unknown_vfp(env_cg);
3131 } else if (mode_needs_gp_reg(mode)) {
3132 return ia32_new_Unknown_gp(env_cg);
3134 assert(0 && "unsupported Unknown-Mode");
3141 * Change some phi modes
3143 static ir_node *gen_Phi(ir_node *node) {
3144 ir_node *block = be_transform_node(get_nodes_block(node));
3145 ir_graph *irg = current_ir_graph;
3146 dbg_info *dbgi = get_irn_dbg_info(node);
3147 ir_mode *mode = get_irn_mode(node);
3150 if(mode_needs_gp_reg(mode)) {
3151 /* we shouldn't have any 64bit stuff around anymore */
3152 assert(get_mode_size_bits(mode) <= 32);
3153 /* all integer operations are on 32bit registers now */
3155 } else if(mode_is_float(mode)) {
3156 if (USE_SSE2(env_cg)) {
3163 /* phi nodes allow loops, so we use the old arguments for now
3164 * and fix this later */
3165 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3166 copy_node_attr(node, phi);
3167 be_duplicate_deps(node, phi);
3169 be_set_transformed_node(node, phi);
3170 be_enqueue_preds(node);
3175 /**********************************************************************
3178 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3179 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3180 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3181 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3183 **********************************************************************/
3185 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3187 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3190 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3191 ir_node *val, ir_node *mem);
3194 * Transforms a lowered Load into a "real" one.
3196 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3197 ir_node *block = be_transform_node(get_nodes_block(node));
3198 ir_node *ptr = get_irn_n(node, 0);
3199 ir_node *new_ptr = be_transform_node(ptr);
3200 ir_node *mem = get_irn_n(node, 1);
3201 ir_node *new_mem = be_transform_node(mem);
3202 ir_graph *irg = current_ir_graph;
3203 dbg_info *dbgi = get_irn_dbg_info(node);
3204 ir_mode *mode = get_ia32_ls_mode(node);
3205 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3209 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3210 lowering we have x87 nodes, so we need to enforce simulation.
3212 if (mode_is_float(mode)) {
3214 if (fp_unit == fp_x87)
3218 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3220 set_ia32_op_type(new_op, ia32_AddrModeS);
3221 set_ia32_am_flavour(new_op, ia32_am_OB);
3222 set_ia32_am_offs_int(new_op, 0);
3223 set_ia32_am_scale(new_op, 1);
3224 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3225 if (is_ia32_am_sc_sign(node))
3226 set_ia32_am_sc_sign(new_op);
3227 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3228 if (is_ia32_use_frame(node)) {
3229 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3230 set_ia32_use_frame(new_op);
3233 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3239 * Transforms a lowered Store into a "real" one.
3241 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3242 ir_node *block = be_transform_node(get_nodes_block(node));
3243 ir_node *ptr = get_irn_n(node, 0);
3244 ir_node *new_ptr = be_transform_node(ptr);
3245 ir_node *val = get_irn_n(node, 1);
3246 ir_node *new_val = be_transform_node(val);
3247 ir_node *mem = get_irn_n(node, 2);
3248 ir_node *new_mem = be_transform_node(mem);
3249 ir_graph *irg = current_ir_graph;
3250 dbg_info *dbgi = get_irn_dbg_info(node);
3251 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3252 ir_mode *mode = get_ia32_ls_mode(node);
3255 ia32_am_flavour_t am_flav = ia32_B;
3258 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3259 lowering we have x87 nodes, so we need to enforce simulation.
3261 if (mode_is_float(mode)) {
3263 if (fp_unit == fp_x87)
3267 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3269 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3271 add_ia32_am_offs_int(new_op, am_offs);
3274 set_ia32_op_type(new_op, ia32_AddrModeD);
3275 set_ia32_am_flavour(new_op, am_flav);
3276 set_ia32_ls_mode(new_op, mode);
3277 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3278 set_ia32_use_frame(new_op);
3280 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3287 * Transforms an ia32_l_XXX into a "real" XXX node
3289 * @param env The transformation environment
3290 * @return the created ia32 XXX node
3292 #define GEN_LOWERED_OP(op) \
3293 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3294 ir_mode *mode = get_irn_mode(node); \
3295 if (mode_is_float(mode)) \
3297 return gen_binop(node, get_binop_left(node), \
3298 get_binop_right(node), new_rd_ia32_##op,0); \
3301 #define GEN_LOWERED_x87_OP(op) \
3302 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3304 FORCE_x87(env_cg); \
3305 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3306 get_binop_right(node), new_rd_ia32_##op); \
3310 #define GEN_LOWERED_UNOP(op) \
3311 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3312 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3315 #define GEN_LOWERED_SHIFT_OP(op) \
3316 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3317 return gen_shift_binop(node, get_binop_left(node), \
3318 get_binop_right(node), new_rd_ia32_##op); \
3321 #define GEN_LOWERED_LOAD(op, fp_unit) \
3322 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3323 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3326 #define GEN_LOWERED_STORE(op, fp_unit) \
3327 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3328 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3335 GEN_LOWERED_OP(IMul)
3337 GEN_LOWERED_x87_OP(vfprem)
3338 GEN_LOWERED_x87_OP(vfmul)
3339 GEN_LOWERED_x87_OP(vfsub)
3341 GEN_LOWERED_UNOP(Neg)
3343 GEN_LOWERED_LOAD(vfild, fp_x87)
3344 GEN_LOWERED_LOAD(Load, fp_none)
3345 /*GEN_LOWERED_STORE(vfist, fp_x87)
3348 GEN_LOWERED_STORE(Store, fp_none)
3350 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3351 ir_node *block = be_transform_node(get_nodes_block(node));
3352 ir_node *left = get_binop_left(node);
3353 ir_node *new_left = be_transform_node(left);
3354 ir_node *right = get_binop_right(node);
3355 ir_node *new_right = be_transform_node(right);
3356 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3357 ir_graph *irg = current_ir_graph;
3358 dbg_info *dbgi = get_irn_dbg_info(node);
3359 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3360 &ia32_fp_cw_regs[REG_FPCW]);
3363 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3364 new_right, new_NoMem(), fpcw);
3365 clear_ia32_commutative(vfdiv);
3366 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3368 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3376 * Transforms a l_MulS into a "real" MulS node.
3378 * @param env The transformation environment
3379 * @return the created ia32 Mul node
3381 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3382 ir_node *block = be_transform_node(get_nodes_block(node));
3383 ir_node *left = get_binop_left(node);
3384 ir_node *new_left = be_transform_node(left);
3385 ir_node *right = get_binop_right(node);
3386 ir_node *new_right = be_transform_node(right);
3387 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3388 ir_graph *irg = current_ir_graph;
3389 dbg_info *dbgi = get_irn_dbg_info(node);
3392 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3393 /* and then skip the result Proj, because all needed Projs are already there. */
3394 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3395 new_right, new_NoMem());
3396 clear_ia32_commutative(muls);
3397 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3399 /* check if EAX and EDX proj exist, add missing one */
3400 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3401 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3402 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3404 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3409 GEN_LOWERED_SHIFT_OP(Shl)
3410 GEN_LOWERED_SHIFT_OP(Shr)
3411 GEN_LOWERED_SHIFT_OP(Sar)
3414 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3415 * op1 - target to be shifted
3416 * op2 - contains bits to be shifted into target
3418 * Only op3 can be an immediate.
3420 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3421 ir_node *op2, ir_node *count)
3423 ir_node *block = be_transform_node(get_nodes_block(node));
3424 ir_node *new_op1 = be_transform_node(op1);
3425 ir_node *new_op2 = be_transform_node(op2);
3426 ir_node *new_count = be_transform_node(count);
3427 ir_node *new_op = NULL;
3428 ir_graph *irg = current_ir_graph;
3429 dbg_info *dbgi = get_irn_dbg_info(node);
3430 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3431 ir_node *nomem = new_NoMem();
3435 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3437 /* Check if immediate optimization is on and */
3438 /* if it's an operation with immediate. */
3439 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3441 /* Limit imm_op within range imm8 */
3443 tv = get_ia32_Immop_tarval(imm_op);
3446 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3447 set_ia32_Immop_tarval(imm_op, tv);
3454 /* integer operations */
3456 /* This is ShiftD with const */
3457 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3459 if (is_ia32_l_ShlD(node))
3460 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3461 new_op1, new_op2, noreg, nomem);
3463 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3464 new_op1, new_op2, noreg, nomem);
3465 copy_ia32_Immop_attr(new_op, imm_op);
3468 /* This is a normal ShiftD */
3469 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3470 if (is_ia32_l_ShlD(node))
3471 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3472 new_op1, new_op2, new_count, nomem);
3474 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3475 new_op1, new_op2, new_count, nomem);
3478 /* set AM support */
3479 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3481 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3483 set_ia32_emit_cl(new_op);
3488 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3489 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3490 get_irn_n(node, 1), get_irn_n(node, 2));
3493 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3494 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3495 get_irn_n(node, 1), get_irn_n(node, 2));
3499 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3501 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3502 ir_node *block = be_transform_node(get_nodes_block(node));
3503 ir_node *val = get_irn_n(node, 1);
3504 ir_node *new_val = be_transform_node(val);
3505 ia32_code_gen_t *cg = env_cg;
3506 ir_node *res = NULL;
3507 ir_graph *irg = current_ir_graph;
3509 ir_node *noreg, *new_ptr, *new_mem;
3516 mem = get_irn_n(node, 2);
3517 new_mem = be_transform_node(mem);
3518 ptr = get_irn_n(node, 0);
3519 new_ptr = be_transform_node(ptr);
3520 noreg = ia32_new_NoReg_gp(cg);
3521 dbgi = get_irn_dbg_info(node);
3523 /* Store x87 -> MEM */
3524 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3525 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3526 set_ia32_use_frame(res);
3527 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3528 set_ia32_am_flavour(res, ia32_B);
3529 set_ia32_op_type(res, ia32_AddrModeD);
3531 /* Load MEM -> SSE */
3532 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3533 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3534 set_ia32_use_frame(res);
3535 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3536 set_ia32_am_flavour(res, ia32_B);
3537 set_ia32_op_type(res, ia32_AddrModeS);
3538 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3544 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3546 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3547 ir_node *block = be_transform_node(get_nodes_block(node));
3548 ir_node *val = get_irn_n(node, 1);
3549 ir_node *new_val = be_transform_node(val);
3550 ia32_code_gen_t *cg = env_cg;
3551 ir_graph *irg = current_ir_graph;
3552 ir_node *res = NULL;
3553 ir_entity *fent = get_ia32_frame_ent(node);
3554 ir_mode *lsmode = get_ia32_ls_mode(node);
3556 ir_node *noreg, *new_ptr, *new_mem;
3560 if (! USE_SSE2(cg)) {
3561 /* SSE unit is not used -> skip this node. */
3565 ptr = get_irn_n(node, 0);
3566 new_ptr = be_transform_node(ptr);
3567 mem = get_irn_n(node, 2);
3568 new_mem = be_transform_node(mem);
3569 noreg = ia32_new_NoReg_gp(cg);
3570 dbgi = get_irn_dbg_info(node);
3572 /* Store SSE -> MEM */
3573 if (is_ia32_xLoad(skip_Proj(new_val))) {
3574 ir_node *ld = skip_Proj(new_val);
3576 /* we can vfld the value directly into the fpu */
3577 fent = get_ia32_frame_ent(ld);
3578 ptr = get_irn_n(ld, 0);
3579 offs = get_ia32_am_offs_int(ld);
3581 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3582 set_ia32_frame_ent(res, fent);
3583 set_ia32_use_frame(res);
3584 set_ia32_ls_mode(res, lsmode);
3585 set_ia32_am_flavour(res, ia32_B);
3586 set_ia32_op_type(res, ia32_AddrModeD);
3590 /* Load MEM -> x87 */
3591 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3592 set_ia32_frame_ent(res, fent);
3593 set_ia32_use_frame(res);
3594 add_ia32_am_offs_int(res, offs);
3595 set_ia32_am_flavour(res, ia32_B);
3596 set_ia32_op_type(res, ia32_AddrModeS);
3597 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3602 /*********************************************************
3605 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3606 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3607 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3608 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3610 *********************************************************/
3613 * the BAD transformer.
3615 static ir_node *bad_transform(ir_node *node) {
3616 panic("No transform function for %+F available.\n", node);
3621 * Transform the Projs of an AddSP.
3623 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3624 ir_node *block = be_transform_node(get_nodes_block(node));
3625 ir_node *pred = get_Proj_pred(node);
3626 ir_node *new_pred = be_transform_node(pred);
3627 ir_graph *irg = current_ir_graph;
3628 dbg_info *dbgi = get_irn_dbg_info(node);
3629 long proj = get_Proj_proj(node);
3631 if (proj == pn_be_AddSP_res) {
3632 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3633 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3635 } else if (proj == pn_be_AddSP_M) {
3636 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3640 return new_rd_Unknown(irg, get_irn_mode(node));
3644 * Transform the Projs of a SubSP.
3646 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3647 ir_node *block = be_transform_node(get_nodes_block(node));
3648 ir_node *pred = get_Proj_pred(node);
3649 ir_node *new_pred = be_transform_node(pred);
3650 ir_graph *irg = current_ir_graph;
3651 dbg_info *dbgi = get_irn_dbg_info(node);
3652 long proj = get_Proj_proj(node);
3654 if (proj == pn_be_SubSP_res) {
3655 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3656 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3658 } else if (proj == pn_be_SubSP_M) {
3659 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3663 return new_rd_Unknown(irg, get_irn_mode(node));
3667 * Transform and renumber the Projs from a Load.
3669 static ir_node *gen_Proj_Load(ir_node *node) {
3670 ir_node *block = be_transform_node(get_nodes_block(node));
3671 ir_node *pred = get_Proj_pred(node);
3672 ir_node *new_pred = be_transform_node(pred);
3673 ir_graph *irg = current_ir_graph;
3674 dbg_info *dbgi = get_irn_dbg_info(node);
3675 long proj = get_Proj_proj(node);
3677 /* renumber the proj */
3678 if (is_ia32_Load(new_pred)) {
3679 if (proj == pn_Load_res) {
3680 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3681 } else if (proj == pn_Load_M) {
3682 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3684 } else if (is_ia32_xLoad(new_pred)) {
3685 if (proj == pn_Load_res) {
3686 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3687 } else if (proj == pn_Load_M) {
3688 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3690 } else if (is_ia32_vfld(new_pred)) {
3691 if (proj == pn_Load_res) {
3692 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3693 } else if (proj == pn_Load_M) {
3694 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3699 return new_rd_Unknown(irg, get_irn_mode(node));
3703 * Transform and renumber the Projs from a DivMod like instruction.
3705 static ir_node *gen_Proj_DivMod(ir_node *node) {
3706 ir_node *block = be_transform_node(get_nodes_block(node));
3707 ir_node *pred = get_Proj_pred(node);
3708 ir_node *new_pred = be_transform_node(pred);
3709 ir_graph *irg = current_ir_graph;
3710 dbg_info *dbgi = get_irn_dbg_info(node);
3711 ir_mode *mode = get_irn_mode(node);
3712 long proj = get_Proj_proj(node);
3714 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3716 switch (get_irn_opcode(pred)) {
3720 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3722 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3730 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3732 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3741 case pn_DivMod_res_div:
3742 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3743 case pn_DivMod_res_mod:
3744 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3754 return new_rd_Unknown(irg, mode);
3758 * Transform and renumber the Projs from a CopyB.
3760 static ir_node *gen_Proj_CopyB(ir_node *node) {
3761 ir_node *block = be_transform_node(get_nodes_block(node));
3762 ir_node *pred = get_Proj_pred(node);
3763 ir_node *new_pred = be_transform_node(pred);
3764 ir_graph *irg = current_ir_graph;
3765 dbg_info *dbgi = get_irn_dbg_info(node);
3766 ir_mode *mode = get_irn_mode(node);
3767 long proj = get_Proj_proj(node);
3770 case pn_CopyB_M_regular:
3771 if (is_ia32_CopyB_i(new_pred)) {
3772 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3773 } else if (is_ia32_CopyB(new_pred)) {
3774 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3782 return new_rd_Unknown(irg, mode);
3786 * Transform and renumber the Projs from a vfdiv.
3788 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3789 ir_node *block = be_transform_node(get_nodes_block(node));
3790 ir_node *pred = get_Proj_pred(node);
3791 ir_node *new_pred = be_transform_node(pred);
3792 ir_graph *irg = current_ir_graph;
3793 dbg_info *dbgi = get_irn_dbg_info(node);
3794 ir_mode *mode = get_irn_mode(node);
3795 long proj = get_Proj_proj(node);
3798 case pn_ia32_l_vfdiv_M:
3799 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3800 case pn_ia32_l_vfdiv_res:
3801 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3806 return new_rd_Unknown(irg, mode);
3810 * Transform and renumber the Projs from a Quot.
3812 static ir_node *gen_Proj_Quot(ir_node *node) {
3813 ir_node *block = be_transform_node(get_nodes_block(node));
3814 ir_node *pred = get_Proj_pred(node);
3815 ir_node *new_pred = be_transform_node(pred);
3816 ir_graph *irg = current_ir_graph;
3817 dbg_info *dbgi = get_irn_dbg_info(node);
3818 ir_mode *mode = get_irn_mode(node);
3819 long proj = get_Proj_proj(node);
3823 if (is_ia32_xDiv(new_pred)) {
3824 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3825 } else if (is_ia32_vfdiv(new_pred)) {
3826 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3830 if (is_ia32_xDiv(new_pred)) {
3831 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3832 } else if (is_ia32_vfdiv(new_pred)) {
3833 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3841 return new_rd_Unknown(irg, mode);
3845 * Transform the Thread Local Storage Proj.
3847 static ir_node *gen_Proj_tls(ir_node *node) {
3848 ir_node *block = be_transform_node(get_nodes_block(node));
3849 ir_graph *irg = current_ir_graph;
3850 dbg_info *dbgi = NULL;
3851 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3857 * Transform the Projs from a be_Call.
3859 static ir_node *gen_Proj_be_Call(ir_node *node) {
3860 ir_node *block = be_transform_node(get_nodes_block(node));
3861 ir_node *call = get_Proj_pred(node);
3862 ir_node *new_call = be_transform_node(call);
3863 ir_graph *irg = current_ir_graph;
3864 dbg_info *dbgi = get_irn_dbg_info(node);
3865 long proj = get_Proj_proj(node);
3866 ir_mode *mode = get_irn_mode(node);
3868 const arch_register_class_t *cls;
3870 /* The following is kinda tricky: If we're using SSE, then we have to
3871 * move the result value of the call in floating point registers to an
3872 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3873 * after the call, we have to make sure to correctly make the
3874 * MemProj and the result Proj use these 2 nodes
3876 if (proj == pn_be_Call_M_regular) {
3877 // get new node for result, are we doing the sse load/store hack?
3878 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3879 ir_node *call_res_new;
3880 ir_node *call_res_pred = NULL;
3882 if (call_res != NULL) {
3883 call_res_new = be_transform_node(call_res);
3884 call_res_pred = get_Proj_pred(call_res_new);
3887 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3888 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3890 assert(is_ia32_xLoad(call_res_pred));
3891 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3894 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3896 ir_node *frame = get_irg_frame(irg);
3897 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3899 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3901 const arch_register_class_t *cls;
3903 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3904 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3906 /* store st(0) onto stack */
3907 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3909 set_ia32_ls_mode(fstp, mode);
3910 set_ia32_op_type(fstp, ia32_AddrModeD);
3911 set_ia32_use_frame(fstp);
3912 set_ia32_am_flavour(fstp, ia32_am_B);
3914 /* load into SSE register */
3915 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3916 set_ia32_ls_mode(sse_load, mode);
3917 set_ia32_op_type(sse_load, ia32_AddrModeS);
3918 set_ia32_use_frame(sse_load);
3919 set_ia32_am_flavour(sse_load, ia32_am_B);
3921 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3923 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3925 /* get a Proj representing a caller save register */
3926 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3927 assert(is_Proj(p) && "Proj expected.");
3929 /* user of the the proj is the Keep */
3930 p = get_edge_src_irn(get_irn_out_edge_first(p));
3931 assert(be_is_Keep(p) && "Keep expected.");
3933 /* keep the result */
3934 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3935 keepin[0] = sse_load;
3936 be_new_Keep(cls, irg, block, 1, keepin);
3941 /* transform call modes */
3942 if (mode_is_data(mode)) {
3943 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3947 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3951 * Transform the Projs from a Cmp.
3953 static ir_node *gen_Proj_Cmp(ir_node *node)
3955 /* normally Cmps are processed when looking at Cond nodes, but this case
3956 * can happen in complicated Psi conditions */
3958 ir_graph *irg = current_ir_graph;
3959 dbg_info *dbgi = get_irn_dbg_info(node);
3960 ir_node *block = be_transform_node(get_nodes_block(node));
3961 ir_node *cmp = get_Proj_pred(node);
3962 long pnc = get_Proj_proj(node);
3963 ir_node *cmp_left = get_Cmp_left(cmp);
3964 ir_node *cmp_right = get_Cmp_right(cmp);
3965 ir_node *new_cmp_left;
3966 ir_node *new_cmp_right;
3967 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3968 ir_node *nomem = new_rd_NoMem(irg);
3969 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3972 assert(!mode_is_float(cmp_mode));
3974 /* (a != b) -> (a ^ b) */
3975 if(pnc == pn_Cmp_Lg) {
3976 if(is_Const_0(cmp_left)) {
3977 new_op = be_transform_node(cmp_right);
3978 } else if(is_Const_0(cmp_right)) {
3979 new_op = be_transform_node(cmp_left);
3981 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
3987 * (a == b) -> !(a ^ b)
3988 * (a < 0) -> (a & 0x80000000) oder a >> 31
3989 * (a >= 0) -> (a >> 31) ^ 1
3992 if(!mode_is_signed(cmp_mode)) {
3993 pnc |= ia32_pn_Cmp_Unsigned;
3996 new_cmp_left = be_transform_node(cmp_left);
3997 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
3999 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4000 new_cmp_right, nomem, pnc);
4001 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4007 * Transform and potentially renumber Proj nodes.
4009 static ir_node *gen_Proj(ir_node *node) {
4010 ir_graph *irg = current_ir_graph;
4011 dbg_info *dbgi = get_irn_dbg_info(node);
4012 ir_node *pred = get_Proj_pred(node);
4013 long proj = get_Proj_proj(node);
4015 if (is_Store(pred) || be_is_FrameStore(pred)) {
4016 if (proj == pn_Store_M) {
4017 return be_transform_node(pred);
4020 return new_r_Bad(irg);
4022 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4023 return gen_Proj_Load(node);
4024 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4025 return gen_Proj_DivMod(node);
4026 } else if (is_CopyB(pred)) {
4027 return gen_Proj_CopyB(node);
4028 } else if (is_Quot(pred)) {
4029 return gen_Proj_Quot(node);
4030 } else if (is_ia32_l_vfdiv(pred)) {
4031 return gen_Proj_l_vfdiv(node);
4032 } else if (be_is_SubSP(pred)) {
4033 return gen_Proj_be_SubSP(node);
4034 } else if (be_is_AddSP(pred)) {
4035 return gen_Proj_be_AddSP(node);
4036 } else if (be_is_Call(pred)) {
4037 return gen_Proj_be_Call(node);
4038 } else if (is_Cmp(pred)) {
4039 return gen_Proj_Cmp(node);
4040 } else if (get_irn_op(pred) == op_Start) {
4041 if (proj == pn_Start_X_initial_exec) {
4042 ir_node *block = get_nodes_block(pred);
4045 /* we exchange the ProjX with a jump */
4046 block = be_transform_node(block);
4047 jump = new_rd_Jmp(dbgi, irg, block);
4050 if (node == be_get_old_anchor(anchor_tls)) {
4051 return gen_Proj_tls(node);
4054 ir_node *new_pred = be_transform_node(pred);
4055 ir_node *block = be_transform_node(get_nodes_block(node));
4056 ir_mode *mode = get_irn_mode(node);
4057 if (mode_needs_gp_reg(mode)) {
4058 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4059 get_Proj_proj(node));
4060 #ifdef DEBUG_libfirm
4061 new_proj->node_nr = node->node_nr;
4067 return be_duplicate_node(node);
4071 * Enters all transform functions into the generic pointer
4073 static void register_transformers(void) {
4074 ir_op *op_Max, *op_Min, *op_Mulh;
4076 /* first clear the generic function pointer for all ops */
4077 clear_irp_opcodes_generic_func();
4079 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4080 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4117 /* transform ops from intrinsic lowering */
4137 /* GEN(ia32_l_vfist); TODO */
4139 GEN(ia32_l_X87toSSE);
4140 GEN(ia32_l_SSEtoX87);
4145 /* we should never see these nodes */
4160 /* handle generic backend nodes */
4171 /* set the register for all Unknown nodes */
4174 op_Max = get_op_Max();
4177 op_Min = get_op_Min();
4180 op_Mulh = get_op_Mulh();
4189 * Pre-transform all unknown and noreg nodes.
4191 static void ia32_pretransform_node(void *arch_cg) {
4192 ia32_code_gen_t *cg = arch_cg;
4194 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4195 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4196 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4197 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4198 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4199 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4202 /* do the transformation */
4203 void ia32_transform_graph(ia32_code_gen_t *cg) {
4204 register_transformers();
4206 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4209 void ia32_init_transform(void)
4211 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");