2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
91 extern ir_op *get_op_Mulh(void);
93 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
94 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
95 ir_node *op2, ir_node *mem);
97 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
98 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
99 ir_node *op2, ir_node *mem, ir_node *fpcw);
101 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
105 /****************************************************************************************************
107 * | | | | / _| | | (_)
108 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
109 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
110 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
111 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
113 ****************************************************************************************************/
115 static ir_node *try_create_Immediate(ir_node *node,
116 char immediate_constraint_type);
118 static ir_node *create_immediate_or_transform(ir_node *node,
119 char immediate_constraint_type);
122 * Return true if a mode can be stored in the GP register set
124 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
125 if(mode == mode_fpcw)
127 return mode_is_int(mode) || mode_is_character(mode)
128 || mode_is_reference(mode) || mode == mode_b;
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
563 * Construct a standard binary operation, set AM and immediate if required.
565 * @param op1 The first operand
566 * @param op2 The second operand
567 * @param func The node constructor function
568 * @return The constructed ia32 node.
570 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
571 construct_binop_float_func *func)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_node *new_node = NULL;
577 dbg_info *dbgi = get_irn_dbg_info(node);
578 ir_graph *irg = current_ir_graph;
579 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
580 ir_node *nomem = new_NoMem();
581 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
582 &ia32_fp_cw_regs[REG_FPCW]);
584 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
586 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
587 if (is_op_commutative(get_irn_op(node))) {
588 set_ia32_commutative(new_node);
591 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
597 * Construct a shift/rotate binary operation, sets AM and immediate if required.
599 * @param op1 The first operand
600 * @param op2 The second operand
601 * @param func The node constructor function
602 * @return The constructed ia32 node.
604 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
605 construct_binop_func *func)
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *new_op1 = be_transform_node(op1);
610 ir_node *new_op = NULL;
611 dbg_info *dbgi = get_irn_dbg_info(node);
612 ir_graph *irg = current_ir_graph;
613 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
614 ir_node *nomem = new_NoMem();
616 assert(! mode_is_float(get_irn_mode(node))
617 && "Shift/Rotate with float not supported");
619 new_op2 = create_immediate_or_transform(op2, 'N');
621 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
624 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
626 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
628 set_ia32_emit_cl(new_op);
635 * Construct a standard unary operation, set AM and immediate if required.
637 * @param op The operand
638 * @param func The node constructor function
639 * @return The constructed ia32 node.
641 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
643 ir_node *block = be_transform_node(get_nodes_block(node));
644 ir_node *new_op = be_transform_node(op);
645 ir_node *new_node = NULL;
646 ir_graph *irg = current_ir_graph;
647 dbg_info *dbgi = get_irn_dbg_info(node);
648 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
649 ir_node *nomem = new_NoMem();
651 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
652 DB((dbg, LEVEL_1, "INT unop ..."));
653 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
661 * Creates an ia32 Add.
663 * @return the created ia32 Add node
665 static ir_node *gen_Add(ir_node *node) {
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *op1 = get_Add_left(node);
668 ir_node *new_op1 = be_transform_node(op1);
669 ir_node *op2 = get_Add_right(node);
670 ir_node *new_op2 = be_transform_node(op2);
671 ir_node *new_op = NULL;
672 ir_graph *irg = current_ir_graph;
673 dbg_info *dbgi = get_irn_dbg_info(node);
674 ir_mode *mode = get_irn_mode(node);
675 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
676 ir_node *nomem = new_NoMem();
677 ir_node *expr_op, *imm_op;
679 /* Check if immediate optimization is on and */
680 /* if it's an operation with immediate. */
681 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
682 expr_op = get_expr_op(new_op1, new_op2);
684 assert((expr_op || imm_op) && "invalid operands");
686 if (mode_is_float(mode)) {
688 if (USE_SSE2(env_cg))
689 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
691 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
696 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
697 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
699 /* No expr_op means, that we have two const - one symconst and */
700 /* one tarval or another symconst - because this case is not */
701 /* covered by constant folding */
702 /* We need to check for: */
703 /* 1) symconst + const -> becomes a LEA */
704 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
705 /* linker doesn't support two symconsts */
707 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
708 /* this is the 2nd case */
709 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
710 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
711 set_ia32_am_flavour(new_op, ia32_am_B);
712 set_ia32_op_type(new_op, ia32_AddrModeS);
714 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
715 } else if (tp1 == ia32_ImmSymConst) {
716 tarval *tv = get_ia32_Immop_tarval(new_op2);
717 long offs = get_tarval_long(tv);
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
720 add_irn_dep(new_op, get_irg_frame(irg));
721 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
723 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
724 add_ia32_am_offs_int(new_op, offs);
725 set_ia32_am_flavour(new_op, ia32_am_OB);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
727 } else if (tp2 == ia32_ImmSymConst) {
728 tarval *tv = get_ia32_Immop_tarval(new_op1);
729 long offs = get_tarval_long(tv);
731 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
732 add_irn_dep(new_op, get_irg_frame(irg));
733 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
735 add_ia32_am_offs_int(new_op, offs);
736 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
737 set_ia32_am_flavour(new_op, ia32_am_OB);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
741 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
742 tarval *restv = tarval_add(tv1, tv2);
744 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
746 new_op = new_rd_ia32_Const(dbgi, irg, block);
747 set_ia32_Const_tarval(new_op, restv);
748 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
754 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
755 tarval_classification_t class_tv, class_negtv;
756 tarval *tv = get_ia32_Immop_tarval(imm_op);
758 /* optimize tarvals */
759 class_tv = classify_tarval(tv);
760 class_negtv = classify_tarval(tarval_neg(tv));
762 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
763 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
764 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
767 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
768 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
769 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
770 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
776 /* This is a normal add */
777 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
780 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
781 set_ia32_commutative(new_op);
783 fold_immediate(new_op, 2, 3);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
791 * Creates an ia32 Mul.
793 * @return the created ia32 Mul node
795 static ir_node *gen_Mul(ir_node *node) {
796 ir_node *op1 = get_Mul_left(node);
797 ir_node *op2 = get_Mul_right(node);
798 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode)) {
802 if (USE_SSE2(env_cg))
803 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
805 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
809 for the lower 32bit of the result it doesn't matter whether we use
810 signed or unsigned multiplication so we use IMul as it has fewer
813 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
817 * Creates an ia32 Mulh.
818 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
819 * this result while Mul returns the lower 32 bit.
821 * @return the created ia32 Mulh node
823 static ir_node *gen_Mulh(ir_node *node) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *op1 = get_irn_n(node, 0);
826 ir_node *new_op1 = be_transform_node(op1);
827 ir_node *op2 = get_irn_n(node, 1);
828 ir_node *new_op2 = be_transform_node(op2);
829 ir_graph *irg = current_ir_graph;
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
832 ir_mode *mode = get_irn_mode(node);
833 ir_node *proj_EDX, *res;
835 assert(!mode_is_float(mode) && "Mulh with float not supported");
836 if (mode_is_signed(mode)) {
837 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
838 new_op2, new_NoMem());
840 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
844 set_ia32_commutative(res);
845 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
847 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
855 * Creates an ia32 And.
857 * @return The created ia32 And node
859 static ir_node *gen_And(ir_node *node) {
860 ir_node *op1 = get_And_left(node);
861 ir_node *op2 = get_And_right(node);
863 assert (! mode_is_float(get_irn_mode(node)));
864 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
870 * Creates an ia32 Or.
872 * @return The created ia32 Or node
874 static ir_node *gen_Or(ir_node *node) {
875 ir_node *op1 = get_Or_left(node);
876 ir_node *op2 = get_Or_right(node);
878 assert (! mode_is_float(get_irn_mode(node)));
879 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
885 * Creates an ia32 Eor.
887 * @return The created ia32 Eor node
889 static ir_node *gen_Eor(ir_node *node) {
890 ir_node *op1 = get_Eor_left(node);
891 ir_node *op2 = get_Eor_right(node);
893 assert(! mode_is_float(get_irn_mode(node)));
894 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
899 * Creates an ia32 Sub.
901 * @return The created ia32 Sub node
903 static ir_node *gen_Sub(ir_node *node) {
904 ir_node *block = be_transform_node(get_nodes_block(node));
905 ir_node *op1 = get_Sub_left(node);
906 ir_node *new_op1 = be_transform_node(op1);
907 ir_node *op2 = get_Sub_right(node);
908 ir_node *new_op2 = be_transform_node(op2);
909 ir_node *new_op = NULL;
910 ir_graph *irg = current_ir_graph;
911 dbg_info *dbgi = get_irn_dbg_info(node);
912 ir_mode *mode = get_irn_mode(node);
913 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
914 ir_node *nomem = new_NoMem();
915 ir_node *expr_op, *imm_op;
917 /* Check if immediate optimization is on and */
918 /* if it's an operation with immediate. */
919 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
920 expr_op = get_expr_op(new_op1, new_op2);
922 assert((expr_op || imm_op) && "invalid operands");
924 if (mode_is_float(mode)) {
926 if (USE_SSE2(env_cg))
927 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
929 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
934 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
935 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
937 /* No expr_op means, that we have two const - one symconst and */
938 /* one tarval or another symconst - because this case is not */
939 /* covered by constant folding */
940 /* We need to check for: */
941 /* 1) symconst - const -> becomes a LEA */
942 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
943 /* linker doesn't support two symconsts */
944 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
945 /* this is the 2nd case */
946 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
947 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
948 set_ia32_am_sc_sign(new_op);
949 set_ia32_am_flavour(new_op, ia32_am_B);
951 DBG_OPT_LEA3(op1, op2, node, new_op);
952 } else if (tp1 == ia32_ImmSymConst) {
953 tarval *tv = get_ia32_Immop_tarval(new_op2);
954 long offs = get_tarval_long(tv);
956 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
957 add_irn_dep(new_op, get_irg_frame(irg));
958 DBG_OPT_LEA3(op1, op2, node, new_op);
960 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
961 add_ia32_am_offs_int(new_op, -offs);
962 set_ia32_am_flavour(new_op, ia32_am_OB);
963 set_ia32_op_type(new_op, ia32_AddrModeS);
964 } else if (tp2 == ia32_ImmSymConst) {
965 tarval *tv = get_ia32_Immop_tarval(new_op1);
966 long offs = get_tarval_long(tv);
968 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
969 add_irn_dep(new_op, get_irg_frame(irg));
970 DBG_OPT_LEA3(op1, op2, node, new_op);
972 add_ia32_am_offs_int(new_op, offs);
973 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
974 set_ia32_am_sc_sign(new_op);
975 set_ia32_am_flavour(new_op, ia32_am_OB);
976 set_ia32_op_type(new_op, ia32_AddrModeS);
978 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
979 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
980 tarval *restv = tarval_sub(tv1, tv2);
982 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
984 new_op = new_rd_ia32_Const(dbgi, irg, block);
985 set_ia32_Const_tarval(new_op, restv);
986 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
989 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
992 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
993 tarval_classification_t class_tv, class_negtv;
994 tarval *tv = get_ia32_Immop_tarval(imm_op);
996 /* optimize tarvals */
997 class_tv = classify_tarval(tv);
998 class_negtv = classify_tarval(tarval_neg(tv));
1000 if (class_tv == TV_CLASSIFY_ONE) {
1001 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1002 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1003 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1005 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1006 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1007 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1008 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1014 /* This is a normal sub */
1015 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1017 /* set AM support */
1018 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1020 fold_immediate(new_op, 2, 3);
1022 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1030 * Generates an ia32 DivMod with additional infrastructure for the
1031 * register allocator if needed.
1033 * @param dividend -no comment- :)
1034 * @param divisor -no comment- :)
1035 * @param dm_flav flavour_Div/Mod/DivMod
1036 * @return The created ia32 DivMod node
1038 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1039 ir_node *divisor, ia32_op_flavour_t dm_flav)
1041 ir_node *block = be_transform_node(get_nodes_block(node));
1042 ir_node *new_dividend = be_transform_node(dividend);
1043 ir_node *new_divisor = be_transform_node(divisor);
1044 ir_graph *irg = current_ir_graph;
1045 dbg_info *dbgi = get_irn_dbg_info(node);
1046 ir_mode *mode = get_irn_mode(node);
1047 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1048 ir_node *res, *proj_div, *proj_mod;
1049 ir_node *sign_extension;
1050 ir_node *mem, *new_mem;
1051 ir_node *projs[pn_DivMod_max];
1054 ia32_collect_Projs(node, projs, pn_DivMod_max);
1056 proj_div = proj_mod = NULL;
1060 mem = get_Div_mem(node);
1061 mode = get_Div_resmode(node);
1062 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1063 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1066 mem = get_Mod_mem(node);
1067 mode = get_Mod_resmode(node);
1068 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1069 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1071 case flavour_DivMod:
1072 mem = get_DivMod_mem(node);
1073 mode = get_DivMod_resmode(node);
1074 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1075 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1076 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1079 panic("invalid divmod flavour!");
1081 new_mem = be_transform_node(mem);
1083 if (mode_is_signed(mode)) {
1084 /* in signed mode, we need to sign extend the dividend */
1085 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1087 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1088 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1090 add_irn_dep(sign_extension, get_irg_frame(irg));
1093 if (mode_is_signed(mode)) {
1094 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1095 sign_extension, new_divisor, new_mem, dm_flav);
1097 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1098 sign_extension, new_divisor, new_mem, dm_flav);
1101 set_ia32_exc_label(res, has_exc);
1102 set_irn_pinned(res, get_irn_pinned(node));
1103 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1105 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1112 * Wrapper for generate_DivMod. Sets flavour_Mod.
1115 static ir_node *gen_Mod(ir_node *node) {
1116 return generate_DivMod(node, get_Mod_left(node),
1117 get_Mod_right(node), flavour_Mod);
1121 * Wrapper for generate_DivMod. Sets flavour_Div.
1124 static ir_node *gen_Div(ir_node *node) {
1125 return generate_DivMod(node, get_Div_left(node),
1126 get_Div_right(node), flavour_Div);
1130 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1132 static ir_node *gen_DivMod(ir_node *node) {
1133 return generate_DivMod(node, get_DivMod_left(node),
1134 get_DivMod_right(node), flavour_DivMod);
1140 * Creates an ia32 floating Div.
1142 * @return The created ia32 xDiv node
1144 static ir_node *gen_Quot(ir_node *node) {
1145 ir_node *block = be_transform_node(get_nodes_block(node));
1146 ir_node *op1 = get_Quot_left(node);
1147 ir_node *new_op1 = be_transform_node(op1);
1148 ir_node *op2 = get_Quot_right(node);
1149 ir_node *new_op2 = be_transform_node(op2);
1150 ir_graph *irg = current_ir_graph;
1151 dbg_info *dbgi = get_irn_dbg_info(node);
1152 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1153 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1157 if (USE_SSE2(env_cg)) {
1158 ir_mode *mode = get_irn_mode(op1);
1159 if (is_ia32_xConst(new_op2)) {
1160 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1161 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1162 copy_ia32_Immop_attr(new_op, new_op2);
1164 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1165 // Matze: disabled for now, spillslot coalescer fails
1166 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1168 set_ia32_ls_mode(new_op, mode);
1170 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1171 &ia32_fp_cw_regs[REG_FPCW]);
1172 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1173 new_op2, nomem, fpcw);
1174 // Matze: disabled for now (spillslot coalescer fails)
1175 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1183 * Creates an ia32 Shl.
1185 * @return The created ia32 Shl node
1187 static ir_node *gen_Shl(ir_node *node) {
1188 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1195 * Creates an ia32 Shr.
1197 * @return The created ia32 Shr node
1199 static ir_node *gen_Shr(ir_node *node) {
1200 return gen_shift_binop(node, get_Shr_left(node),
1201 get_Shr_right(node), new_rd_ia32_Shr);
1207 * Creates an ia32 Sar.
1209 * @return The created ia32 Shrs node
1211 static ir_node *gen_Shrs(ir_node *node) {
1212 ir_node *left = get_Shrs_left(node);
1213 ir_node *right = get_Shrs_right(node);
1214 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1215 tarval *tv = get_Const_tarval(right);
1216 long val = get_tarval_long(tv);
1218 /* this is a sign extension */
1219 ir_graph *irg = current_ir_graph;
1220 dbg_info *dbgi = get_irn_dbg_info(node);
1221 ir_node *block = be_transform_node(get_nodes_block(node));
1223 ir_node *new_op = be_transform_node(op);
1225 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1229 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1235 * Creates an ia32 RotL.
1237 * @param op1 The first operator
1238 * @param op2 The second operator
1239 * @return The created ia32 RotL node
1241 static ir_node *gen_RotL(ir_node *node,
1242 ir_node *op1, ir_node *op2) {
1243 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1249 * Creates an ia32 RotR.
1250 * NOTE: There is no RotR with immediate because this would always be a RotL
1251 * "imm-mode_size_bits" which can be pre-calculated.
1253 * @param op1 The first operator
1254 * @param op2 The second operator
1255 * @return The created ia32 RotR node
1257 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1259 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1265 * Creates an ia32 RotR or RotL (depending on the found pattern).
1267 * @return The created ia32 RotL or RotR node
1269 static ir_node *gen_Rot(ir_node *node) {
1270 ir_node *rotate = NULL;
1271 ir_node *op1 = get_Rot_left(node);
1272 ir_node *op2 = get_Rot_right(node);
1274 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1275 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1276 that means we can create a RotR instead of an Add and a RotL */
1278 if (get_irn_op(op2) == op_Add) {
1280 ir_node *left = get_Add_left(add);
1281 ir_node *right = get_Add_right(add);
1282 if (is_Const(right)) {
1283 tarval *tv = get_Const_tarval(right);
1284 ir_mode *mode = get_irn_mode(node);
1285 long bits = get_mode_size_bits(mode);
1287 if (get_irn_op(left) == op_Minus &&
1288 tarval_is_long(tv) &&
1289 get_tarval_long(tv) == bits)
1291 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1292 rotate = gen_RotR(node, op1, get_Minus_op(left));
1297 if (rotate == NULL) {
1298 rotate = gen_RotL(node, op1, op2);
1307 * Transforms a Minus node.
1309 * @param op The Minus operand
1310 * @return The created ia32 Minus node
1312 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1313 ir_node *block = be_transform_node(get_nodes_block(node));
1314 ir_graph *irg = current_ir_graph;
1315 dbg_info *dbgi = get_irn_dbg_info(node);
1316 ir_mode *mode = get_irn_mode(node);
1321 if (mode_is_float(mode)) {
1322 ir_node *new_op = be_transform_node(op);
1324 if (USE_SSE2(env_cg)) {
1325 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1326 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1327 ir_node *nomem = new_rd_NoMem(irg);
1329 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1331 size = get_mode_size_bits(mode);
1332 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1334 set_ia32_am_sc(res, ent);
1335 set_ia32_op_type(res, ia32_AddrModeS);
1336 set_ia32_ls_mode(res, mode);
1338 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1341 res = gen_unop(node, op, new_rd_ia32_Neg);
1344 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1350 * Transforms a Minus node.
1352 * @return The created ia32 Minus node
1354 static ir_node *gen_Minus(ir_node *node) {
1355 return gen_Minus_ex(node, get_Minus_op(node));
1358 static ir_node *gen_bin_Not(ir_node *node)
1360 ir_graph *irg = current_ir_graph;
1361 dbg_info *dbgi = get_irn_dbg_info(node);
1362 ir_node *block = be_transform_node(get_nodes_block(node));
1363 ir_node *op = get_Not_op(node);
1364 ir_node *new_op = be_transform_node(op);
1365 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1366 ir_node *nomem = new_NoMem();
1367 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1368 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1370 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1374 * Transforms a Not node.
1376 * @return The created ia32 Not node
1378 static ir_node *gen_Not(ir_node *node) {
1379 ir_node *op = get_Not_op(node);
1380 ir_mode *mode = get_irn_mode(node);
1382 if(mode == mode_b) {
1383 return gen_bin_Not(node);
1386 assert (! mode_is_float(get_irn_mode(node)));
1387 return gen_unop(node, op, new_rd_ia32_Not);
1393 * Transforms an Abs node.
1395 * @return The created ia32 Abs node
1397 static ir_node *gen_Abs(ir_node *node) {
1398 ir_node *block = be_transform_node(get_nodes_block(node));
1399 ir_node *op = get_Abs_op(node);
1400 ir_node *new_op = be_transform_node(op);
1401 ir_graph *irg = current_ir_graph;
1402 dbg_info *dbgi = get_irn_dbg_info(node);
1403 ir_mode *mode = get_irn_mode(node);
1404 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1405 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1406 ir_node *nomem = new_NoMem();
1411 if (mode_is_float(mode)) {
1413 if (USE_SSE2(env_cg)) {
1414 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1416 size = get_mode_size_bits(mode);
1417 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1419 set_ia32_am_sc(res, ent);
1421 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1423 set_ia32_op_type(res, ia32_AddrModeS);
1424 set_ia32_ls_mode(res, mode);
1427 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1428 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1432 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1433 SET_IA32_ORIG_NODE(sign_extension,
1434 ia32_get_old_node_name(env_cg, node));
1436 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1437 sign_extension, nomem);
1438 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1440 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1441 sign_extension, nomem);
1442 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1451 * Transforms a Load.
1453 * @return the created ia32 Load node
1455 static ir_node *gen_Load(ir_node *node) {
1456 ir_node *block = be_transform_node(get_nodes_block(node));
1457 ir_node *ptr = get_Load_ptr(node);
1458 ir_node *new_ptr = be_transform_node(ptr);
1459 ir_node *mem = get_Load_mem(node);
1460 ir_node *new_mem = be_transform_node(mem);
1461 ir_graph *irg = current_ir_graph;
1462 dbg_info *dbgi = get_irn_dbg_info(node);
1463 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1464 ir_mode *mode = get_Load_mode(node);
1466 ir_node *lptr = new_ptr;
1469 ia32_am_flavour_t am_flav = ia32_am_B;
1471 /* address might be a constant (symconst or absolute address) */
1472 if (is_ia32_Const(new_ptr)) {
1477 if (mode_is_float(mode)) {
1479 if (USE_SSE2(env_cg)) {
1480 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1481 res_mode = mode_xmm;
1483 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1484 res_mode = mode_vfp;
1487 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1491 /* base is a constant address */
1493 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1494 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1495 am_flav = ia32_am_N;
1497 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1498 long offs = get_tarval_long(tv);
1500 add_ia32_am_offs_int(new_op, offs);
1501 am_flav = ia32_am_O;
1505 set_irn_pinned(new_op, get_irn_pinned(node));
1506 set_ia32_op_type(new_op, ia32_AddrModeS);
1507 set_ia32_am_flavour(new_op, am_flav);
1508 set_ia32_ls_mode(new_op, mode);
1510 /* make sure we are scheduled behind the initial IncSP/Barrier
1511 * to avoid spills being placed before it
1513 if (block == get_irg_start_block(irg)) {
1514 add_irn_dep(new_op, get_irg_frame(irg));
1517 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1518 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1526 * Transforms a Store.
1528 * @return the created ia32 Store node
1530 static ir_node *gen_Store(ir_node *node) {
1531 ir_node *block = be_transform_node(get_nodes_block(node));
1532 ir_node *ptr = get_Store_ptr(node);
1533 ir_node *new_ptr = be_transform_node(ptr);
1534 ir_node *val = get_Store_value(node);
1536 ir_node *mem = get_Store_mem(node);
1537 ir_node *new_mem = be_transform_node(mem);
1538 ir_graph *irg = current_ir_graph;
1539 dbg_info *dbgi = get_irn_dbg_info(node);
1540 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1541 ir_node *sptr = new_ptr;
1542 ir_mode *mode = get_irn_mode(val);
1545 ia32_am_flavour_t am_flav = ia32_am_B;
1547 /* address might be a constant (symconst or absolute address) */
1548 if (is_ia32_Const(new_ptr)) {
1553 if (mode_is_float(mode)) {
1556 new_val = be_transform_node(val);
1557 if (USE_SSE2(env_cg)) {
1558 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1561 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1565 new_val = create_immediate_or_transform(val, 0);
1567 if (get_mode_size_bits(mode) == 8) {
1568 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1571 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1576 /* base is an constant address */
1578 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1579 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1580 am_flav = ia32_am_N;
1582 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1583 long offs = get_tarval_long(tv);
1585 add_ia32_am_offs_int(new_op, offs);
1586 am_flav = ia32_am_O;
1590 set_irn_pinned(new_op, get_irn_pinned(node));
1591 set_ia32_op_type(new_op, ia32_AddrModeD);
1592 set_ia32_am_flavour(new_op, am_flav);
1593 set_ia32_ls_mode(new_op, mode);
1595 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1596 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1601 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1602 ir_node *cmp_left, ir_node *cmp_right)
1604 ir_node *new_cmp_left;
1605 ir_node *new_cmp_right;
1611 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1613 if(cmp_right != NULL && !is_Const_0(cmp_right))
1616 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1617 and_left = get_And_left(cmp_left);
1618 and_right = get_And_right(cmp_left);
1620 new_cmp_left = be_transform_node(and_left);
1621 new_cmp_right = create_immediate_or_transform(and_right, 0);
1623 new_cmp_left = be_transform_node(cmp_left);
1624 new_cmp_right = be_transform_node(cmp_left);
1627 noreg = ia32_new_NoReg_gp(env_cg);
1628 nomem = new_NoMem();
1630 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1631 new_cmp_left, new_cmp_right, nomem, pnc);
1632 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1637 static ir_node *create_Switch(ir_node *node)
1639 ir_graph *irg = current_ir_graph;
1640 dbg_info *dbgi = get_irn_dbg_info(node);
1641 ir_node *block = be_transform_node(get_nodes_block(node));
1642 ir_node *sel = get_Cond_selector(node);
1643 ir_node *new_sel = be_transform_node(sel);
1645 int switch_min = INT_MAX;
1646 const ir_edge_t *edge;
1648 /* determine the smallest switch case value */
1649 foreach_out_edge(node, edge) {
1650 ir_node *proj = get_edge_src_irn(edge);
1651 int pn = get_Proj_proj(proj);
1656 if (switch_min != 0) {
1657 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1659 /* if smallest switch case is not 0 we need an additional sub */
1660 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1661 add_ia32_am_offs_int(new_sel, -switch_min);
1662 set_ia32_am_flavour(new_sel, ia32_am_OB);
1663 set_ia32_op_type(new_sel, ia32_AddrModeS);
1665 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1668 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1669 set_ia32_pncode(res, get_Cond_defaultProj(node));
1671 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1677 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1679 * @return The transformed node.
1681 static ir_node *gen_Cond(ir_node *node) {
1682 ir_node *block = be_transform_node(get_nodes_block(node));
1683 ir_graph *irg = current_ir_graph;
1684 dbg_info *dbgi = get_irn_dbg_info(node);
1685 ir_node *sel = get_Cond_selector(node);
1686 ir_mode *sel_mode = get_irn_mode(sel);
1687 ir_node *res = NULL;
1688 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1695 ir_node *nomem = new_NoMem();
1698 if (sel_mode != mode_b) {
1699 return create_Switch(node);
1702 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1703 /* it's some mode_b value not a direct comparison -> create a testjmp */
1704 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1705 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1709 cmp = get_Proj_pred(sel);
1710 cmp_a = get_Cmp_left(cmp);
1711 cmp_b = get_Cmp_right(cmp);
1712 cmp_mode = get_irn_mode(cmp_a);
1713 pnc = get_Proj_proj(sel);
1714 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1715 pnc |= ia32_pn_Cmp_Unsigned;
1718 if(mode_needs_gp_reg(cmp_mode)) {
1719 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1721 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1726 new_cmp_a = be_transform_node(cmp_a);
1727 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1729 if (mode_is_float(cmp_mode)) {
1731 if (USE_SSE2(env_cg)) {
1732 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1734 set_ia32_commutative(res);
1735 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1736 set_ia32_ls_mode(res, cmp_mode);
1738 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1739 set_ia32_commutative(res);
1742 assert(get_mode_size_bits(cmp_mode) == 32);
1743 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1744 new_cmp_a, new_cmp_b, nomem, pnc);
1745 set_ia32_commutative(res);
1746 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1749 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1757 * Transforms a CopyB node.
1759 * @return The transformed node.
1761 static ir_node *gen_CopyB(ir_node *node) {
1762 ir_node *block = be_transform_node(get_nodes_block(node));
1763 ir_node *src = get_CopyB_src(node);
1764 ir_node *new_src = be_transform_node(src);
1765 ir_node *dst = get_CopyB_dst(node);
1766 ir_node *new_dst = be_transform_node(dst);
1767 ir_node *mem = get_CopyB_mem(node);
1768 ir_node *new_mem = be_transform_node(mem);
1769 ir_node *res = NULL;
1770 ir_graph *irg = current_ir_graph;
1771 dbg_info *dbgi = get_irn_dbg_info(node);
1772 int size = get_type_size_bytes(get_CopyB_type(node));
1775 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1776 /* then we need the size explicitly in ECX. */
1777 if (size >= 32 * 4) {
1778 rem = size & 0x3; /* size % 4 */
1781 res = new_rd_ia32_Const(dbgi, irg, block);
1782 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1783 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1785 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1786 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1788 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1789 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1792 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1798 ir_node *gen_be_Copy(ir_node *node)
1800 ir_node *result = be_duplicate_node(node);
1801 ir_mode *mode = get_irn_mode(result);
1803 if (mode_needs_gp_reg(mode)) {
1804 set_irn_mode(result, mode_Iu);
1811 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1812 dbg_info *dbgi, ir_node *block)
1814 ir_graph *irg = current_ir_graph;
1815 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1816 ir_node *nomem = new_rd_NoMem(irg);
1817 ir_node *new_cmp_left;
1818 ir_node *new_cmp_right;
1821 /* can we use a test instruction? */
1822 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1823 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1824 if(is_And(cmp_left) &&
1825 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1826 ir_node *and_left = get_And_left(cmp_left);
1827 ir_node *and_right = get_And_right(cmp_left);
1829 new_cmp_left = be_transform_node(and_left);
1830 new_cmp_right = create_immediate_or_transform(and_right, 0);
1832 new_cmp_left = be_transform_node(cmp_left);
1833 new_cmp_right = be_transform_node(cmp_left);
1836 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1837 new_cmp_left, new_cmp_right, nomem, pnc);
1838 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1843 new_cmp_left = be_transform_node(cmp_left);
1844 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1845 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1846 new_cmp_left, new_cmp_right, nomem, pnc);
1851 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1852 ir_node *val_true, ir_node *val_false,
1853 dbg_info *dbgi, ir_node *block)
1855 ir_graph *irg = current_ir_graph;
1856 ir_node *new_val_true = be_transform_node(val_true);
1857 ir_node *new_val_false = be_transform_node(val_false);
1858 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1859 ir_node *nomem = new_NoMem();
1860 ir_node *new_cmp_left;
1861 ir_node *new_cmp_right;
1864 /* cmovs with unknowns are pointless... */
1865 if(is_Unknown(val_true)) {
1866 #ifdef DEBUG_libfirm
1867 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1869 return new_val_false;
1871 if(is_Unknown(val_false)) {
1872 #ifdef DEBUG_libfirm
1873 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1875 return new_val_true;
1878 /* can we use a test instruction? */
1879 if(is_Const_0(cmp_right)) {
1880 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1881 if(is_And(cmp_left) &&
1882 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1883 ir_node *and_left = get_And_left(cmp_left);
1884 ir_node *and_right = get_And_right(cmp_left);
1886 new_cmp_left = be_transform_node(and_left);
1887 new_cmp_right = create_immediate_or_transform(and_right, 0);
1889 new_cmp_left = be_transform_node(cmp_left);
1890 new_cmp_right = be_transform_node(cmp_left);
1893 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1894 new_cmp_left, new_cmp_right, nomem,
1895 new_val_true, new_val_false, pnc);
1896 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1901 new_cmp_left = be_transform_node(cmp_left);
1902 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1904 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1905 new_cmp_right, nomem, new_val_true, new_val_false,
1907 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1914 * Transforms a Psi node into CMov.
1916 * @return The transformed node.
1918 static ir_node *gen_Psi(ir_node *node) {
1919 ir_node *psi_true = get_Psi_val(node, 0);
1920 ir_node *psi_default = get_Psi_default(node);
1921 ia32_code_gen_t *cg = env_cg;
1922 ir_node *cond = get_Psi_cond(node, 0);
1923 ir_node *block = be_transform_node(get_nodes_block(node));
1924 dbg_info *dbgi = get_irn_dbg_info(node);
1931 assert(get_Psi_n_conds(node) == 1);
1932 assert(get_irn_mode(cond) == mode_b);
1934 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1935 /* a mode_b value, we have to compare it against 0 */
1937 cmp_right = new_Const_long(mode_Iu, 0);
1941 ir_node *cmp = get_Proj_pred(cond);
1943 cmp_left = get_Cmp_left(cmp);
1944 cmp_right = get_Cmp_right(cmp);
1945 cmp_mode = get_irn_mode(cmp_left);
1946 pnc = get_Proj_proj(cond);
1948 assert(!mode_is_float(cmp_mode));
1950 if (!mode_is_signed(cmp_mode)) {
1951 pnc |= ia32_pn_Cmp_Unsigned;
1955 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1956 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1957 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1958 pnc = get_negated_pnc(pnc, cmp_mode);
1959 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1961 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1964 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1970 * Following conversion rules apply:
1974 * 1) n bit -> m bit n > m (downscale)
1976 * 2) n bit -> m bit n == m (sign change)
1978 * 3) n bit -> m bit n < m (upscale)
1979 * a) source is signed: movsx
1980 * b) source is unsigned: and with lower bits sets
1984 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1988 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1992 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1993 * x87 is mode_E internally, conversions happen only at load and store
1994 * in non-strict semantic
1998 * Create a conversion from x87 state register to general purpose.
2000 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2001 ir_node *block = be_transform_node(get_nodes_block(node));
2002 ir_node *op = get_Conv_op(node);
2003 ir_node *new_op = be_transform_node(op);
2004 ia32_code_gen_t *cg = env_cg;
2005 ir_graph *irg = current_ir_graph;
2006 dbg_info *dbgi = get_irn_dbg_info(node);
2007 ir_node *noreg = ia32_new_NoReg_gp(cg);
2008 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2009 ir_node *fist, *load;
2012 fist = new_rd_ia32_vfist(dbgi, irg, block,
2013 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2015 set_irn_pinned(fist, op_pin_state_floats);
2016 set_ia32_use_frame(fist);
2017 set_ia32_op_type(fist, ia32_AddrModeD);
2018 set_ia32_am_flavour(fist, ia32_am_B);
2019 set_ia32_ls_mode(fist, mode_Iu);
2020 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2023 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2025 set_irn_pinned(load, op_pin_state_floats);
2026 set_ia32_use_frame(load);
2027 set_ia32_op_type(load, ia32_AddrModeS);
2028 set_ia32_am_flavour(load, ia32_am_B);
2029 set_ia32_ls_mode(load, mode_Iu);
2030 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2032 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2036 * Create a conversion from general purpose to x87 register
2038 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2039 ir_node *block = be_transform_node(get_nodes_block(node));
2040 ir_node *op = get_Conv_op(node);
2041 ir_node *new_op = be_transform_node(op);
2042 ir_graph *irg = current_ir_graph;
2043 dbg_info *dbgi = get_irn_dbg_info(node);
2044 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2045 ir_node *nomem = new_NoMem();
2046 ir_node *fild, *store;
2049 /* first convert to 32 bit if necessary */
2050 src_bits = get_mode_size_bits(src_mode);
2051 if (src_bits == 8) {
2052 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2053 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2054 set_ia32_ls_mode(new_op, src_mode);
2055 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2056 } else if (src_bits < 32) {
2057 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2058 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2059 set_ia32_ls_mode(new_op, src_mode);
2060 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2064 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2066 set_ia32_use_frame(store);
2067 set_ia32_op_type(store, ia32_AddrModeD);
2068 set_ia32_am_flavour(store, ia32_am_OB);
2069 set_ia32_ls_mode(store, mode_Iu);
2072 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2074 set_ia32_use_frame(fild);
2075 set_ia32_op_type(fild, ia32_AddrModeS);
2076 set_ia32_am_flavour(fild, ia32_am_OB);
2077 set_ia32_ls_mode(fild, mode_Iu);
2079 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2082 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2085 ir_node *block = get_nodes_block(node);
2086 ir_graph *irg = current_ir_graph;
2087 dbg_info *dbgi = get_irn_dbg_info(node);
2088 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2089 ir_node *nomem = new_NoMem();
2090 int src_bits = get_mode_size_bits(src_mode);
2091 int tgt_bits = get_mode_size_bits(tgt_mode);
2092 ir_node *frame = get_irg_frame(irg);
2093 ir_mode *smaller_mode;
2094 ir_node *store, *load;
2097 if(src_bits <= tgt_bits)
2098 smaller_mode = src_mode;
2100 smaller_mode = tgt_mode;
2102 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2104 set_ia32_use_frame(store);
2105 set_ia32_op_type(store, ia32_AddrModeD);
2106 set_ia32_am_flavour(store, ia32_am_OB);
2108 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2110 set_ia32_use_frame(load);
2111 set_ia32_op_type(load, ia32_AddrModeS);
2112 set_ia32_am_flavour(load, ia32_am_OB);
2114 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2119 * Transforms a Conv node.
2121 * @return The created ia32 Conv node
2123 static ir_node *gen_Conv(ir_node *node) {
2124 ir_node *block = be_transform_node(get_nodes_block(node));
2125 ir_node *op = get_Conv_op(node);
2126 ir_node *new_op = be_transform_node(op);
2127 ir_graph *irg = current_ir_graph;
2128 dbg_info *dbgi = get_irn_dbg_info(node);
2129 ir_mode *src_mode = get_irn_mode(op);
2130 ir_mode *tgt_mode = get_irn_mode(node);
2131 int src_bits = get_mode_size_bits(src_mode);
2132 int tgt_bits = get_mode_size_bits(tgt_mode);
2133 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2134 ir_node *nomem = new_rd_NoMem(irg);
2137 if (src_mode == mode_b) {
2138 assert(mode_is_int(tgt_mode));
2139 /* nothing to do, we already model bools as 0/1 ints */
2143 if (src_mode == tgt_mode) {
2144 if (get_Conv_strict(node)) {
2145 if (USE_SSE2(env_cg)) {
2146 /* when we are in SSE mode, we can kill all strict no-op conversion */
2150 /* this should be optimized already, but who knows... */
2151 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2152 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2157 if (mode_is_float(src_mode)) {
2158 /* we convert from float ... */
2159 if (mode_is_float(tgt_mode)) {
2160 if(src_mode == mode_E && tgt_mode == mode_D
2161 && !get_Conv_strict(node)) {
2162 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2167 if (USE_SSE2(env_cg)) {
2168 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2169 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2170 set_ia32_ls_mode(res, tgt_mode);
2172 // Matze: TODO what about strict convs?
2173 if(get_Conv_strict(node)) {
2174 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2175 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2178 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2183 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2184 if (USE_SSE2(env_cg)) {
2185 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2186 set_ia32_ls_mode(res, src_mode);
2188 return gen_x87_fp_to_gp(node);
2192 /* we convert from int ... */
2193 if (mode_is_float(tgt_mode)) {
2196 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2197 if (USE_SSE2(env_cg)) {
2198 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2199 set_ia32_ls_mode(res, tgt_mode);
2200 if(src_bits == 32) {
2201 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2204 return gen_x87_gp_to_fp(node, src_mode);
2206 } else if(tgt_mode == mode_b) {
2209 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2211 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2216 ir_mode *smaller_mode;
2219 if (src_bits == tgt_bits) {
2220 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2221 src_mode, tgt_mode));
2225 if (src_bits < tgt_bits) {
2226 smaller_mode = src_mode;
2227 smaller_bits = src_bits;
2229 smaller_mode = tgt_mode;
2230 smaller_bits = tgt_bits;
2233 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2234 if (smaller_bits == 8) {
2235 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2236 set_ia32_ls_mode(res, smaller_mode);
2238 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2239 set_ia32_ls_mode(res, smaller_mode);
2241 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2245 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2251 int check_immediate_constraint(long val, char immediate_constraint_type)
2253 switch (immediate_constraint_type) {
2257 return val >= 0 && val <= 32;
2259 return val >= 0 && val <= 63;
2261 return val >= -128 && val <= 127;
2263 return val == 0xff || val == 0xffff;
2265 return val >= 0 && val <= 3;
2267 return val >= 0 && val <= 255;
2269 return val >= 0 && val <= 127;
2273 panic("Invalid immediate constraint found");
2278 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2281 tarval *offset = NULL;
2282 int offset_sign = 0;
2284 ir_entity *symconst_ent = NULL;
2285 int symconst_sign = 0;
2287 ir_node *cnst = NULL;
2288 ir_node *symconst = NULL;
2294 mode = get_irn_mode(node);
2295 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2296 !mode_is_reference(mode)) {
2300 if(is_Minus(node)) {
2302 node = get_Minus_op(node);
2305 if(is_Const(node)) {
2308 offset_sign = minus;
2309 } else if(is_SymConst(node)) {
2312 symconst_sign = minus;
2313 } else if(is_Add(node)) {
2314 ir_node *left = get_Add_left(node);
2315 ir_node *right = get_Add_right(node);
2316 if(is_Const(left) && is_SymConst(right)) {
2319 symconst_sign = minus;
2320 offset_sign = minus;
2321 } else if(is_SymConst(left) && is_Const(right)) {
2324 symconst_sign = minus;
2325 offset_sign = minus;
2327 } else if(is_Sub(node)) {
2328 ir_node *left = get_Sub_left(node);
2329 ir_node *right = get_Sub_right(node);
2330 if(is_Const(left) && is_SymConst(right)) {
2333 symconst_sign = !minus;
2334 offset_sign = minus;
2335 } else if(is_SymConst(left) && is_Const(right)) {
2338 symconst_sign = minus;
2339 offset_sign = !minus;
2346 offset = get_Const_tarval(cnst);
2347 if(tarval_is_long(offset)) {
2348 val = get_tarval_long(offset);
2349 } else if(tarval_is_null(offset)) {
2352 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2357 if(!check_immediate_constraint(val, immediate_constraint_type))
2360 if(symconst != NULL) {
2361 if(immediate_constraint_type != 0) {
2362 /* we need full 32bits for symconsts */
2366 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2368 symconst_ent = get_SymConst_entity(symconst);
2370 if(cnst == NULL && symconst == NULL)
2373 if(offset_sign && offset != NULL) {
2374 offset = tarval_neg(offset);
2377 irg = current_ir_graph;
2378 dbgi = get_irn_dbg_info(node);
2379 block = get_irg_start_block(irg);
2380 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2382 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2384 /* make sure we don't schedule stuff before the barrier */
2385 add_irn_dep(res, get_irg_frame(irg));
2391 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2393 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2394 if (new_node == NULL) {
2395 new_node = be_transform_node(node);
2400 typedef struct constraint_t constraint_t;
2401 struct constraint_t {
2404 const arch_register_req_t **out_reqs;
2406 const arch_register_req_t *req;
2407 unsigned immediate_possible;
2408 char immediate_type;
2411 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2413 int immediate_possible = 0;
2414 char immediate_type = 0;
2415 unsigned limited = 0;
2416 const arch_register_class_t *cls = NULL;
2418 struct obstack *obst;
2419 arch_register_req_t *req;
2420 unsigned *limited_ptr;
2424 /* TODO: replace all the asserts with nice error messages */
2426 printf("Constraint: %s\n", c);
2436 assert(cls == NULL ||
2437 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2438 cls = &ia32_reg_classes[CLASS_ia32_gp];
2439 limited |= 1 << REG_EAX;
2442 assert(cls == NULL ||
2443 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2444 cls = &ia32_reg_classes[CLASS_ia32_gp];
2445 limited |= 1 << REG_EBX;
2448 assert(cls == NULL ||
2449 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2450 cls = &ia32_reg_classes[CLASS_ia32_gp];
2451 limited |= 1 << REG_ECX;
2454 assert(cls == NULL ||
2455 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2456 cls = &ia32_reg_classes[CLASS_ia32_gp];
2457 limited |= 1 << REG_EDX;
2460 assert(cls == NULL ||
2461 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2462 cls = &ia32_reg_classes[CLASS_ia32_gp];
2463 limited |= 1 << REG_EDI;
2466 assert(cls == NULL ||
2467 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2468 cls = &ia32_reg_classes[CLASS_ia32_gp];
2469 limited |= 1 << REG_ESI;
2472 case 'q': /* q means lower part of the regs only, this makes no
2473 * difference to Q for us (we only assigne whole registers) */
2474 assert(cls == NULL ||
2475 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2476 cls = &ia32_reg_classes[CLASS_ia32_gp];
2477 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2481 assert(cls == NULL ||
2482 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2483 cls = &ia32_reg_classes[CLASS_ia32_gp];
2484 limited |= 1 << REG_EAX | 1 << REG_EDX;
2487 assert(cls == NULL ||
2488 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2489 cls = &ia32_reg_classes[CLASS_ia32_gp];
2490 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2491 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2498 assert(cls == NULL);
2499 cls = &ia32_reg_classes[CLASS_ia32_gp];
2505 /* TODO: mark values so the x87 simulator knows about t and u */
2506 assert(cls == NULL);
2507 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2512 assert(cls == NULL);
2513 /* TODO: check that sse2 is supported */
2514 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2524 assert(!immediate_possible);
2525 immediate_possible = 1;
2526 immediate_type = *c;
2530 assert(!immediate_possible);
2531 immediate_possible = 1;
2535 assert(!immediate_possible && cls == NULL);
2536 immediate_possible = 1;
2537 cls = &ia32_reg_classes[CLASS_ia32_gp];
2550 assert(constraint->is_in && "can only specify same constraint "
2553 sscanf(c, "%d%n", &same_as, &p);
2560 case 'E': /* no float consts yet */
2561 case 'F': /* no float consts yet */
2562 case 's': /* makes no sense on x86 */
2563 case 'X': /* we can't support that in firm */
2567 case '<': /* no autodecrement on x86 */
2568 case '>': /* no autoincrement on x86 */
2569 case 'C': /* sse constant not supported yet */
2570 case 'G': /* 80387 constant not supported yet */
2571 case 'y': /* we don't support mmx registers yet */
2572 case 'Z': /* not available in 32 bit mode */
2573 case 'e': /* not available in 32 bit mode */
2574 assert(0 && "asm constraint not supported");
2577 assert(0 && "unknown asm constraint found");
2584 const arch_register_req_t *other_constr;
2586 assert(cls == NULL && "same as and register constraint not supported");
2587 assert(!immediate_possible && "same as and immediate constraint not "
2589 assert(same_as < constraint->n_outs && "wrong constraint number in "
2590 "same_as constraint");
2592 other_constr = constraint->out_reqs[same_as];
2594 req = obstack_alloc(obst, sizeof(req[0]));
2595 req->cls = other_constr->cls;
2596 req->type = arch_register_req_type_should_be_same;
2597 req->limited = NULL;
2598 req->other_same = pos;
2599 req->other_different = -1;
2601 /* switch constraints. This is because in firm we have same_as
2602 * constraints on the output constraints while in the gcc asm syntax
2603 * they are specified on the input constraints */
2604 constraint->req = other_constr;
2605 constraint->out_reqs[same_as] = req;
2606 constraint->immediate_possible = 0;
2610 if(immediate_possible && cls == NULL) {
2611 cls = &ia32_reg_classes[CLASS_ia32_gp];
2613 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2614 assert(cls != NULL);
2616 if(immediate_possible) {
2617 assert(constraint->is_in
2618 && "imeediates make no sense for output constraints");
2620 /* todo: check types (no float input on 'r' constrainted in and such... */
2622 irg = current_ir_graph;
2623 obst = get_irg_obstack(irg);
2626 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2627 limited_ptr = (unsigned*) (req+1);
2629 req = obstack_alloc(obst, sizeof(req[0]));
2631 memset(req, 0, sizeof(req[0]));
2634 req->type = arch_register_req_type_limited;
2635 *limited_ptr = limited;
2636 req->limited = limited_ptr;
2638 req->type = arch_register_req_type_normal;
2642 constraint->req = req;
2643 constraint->immediate_possible = immediate_possible;
2644 constraint->immediate_type = immediate_type;
2648 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2655 panic("Clobbers not supported yet");
2658 ir_node *gen_ASM(ir_node *node)
2661 ir_graph *irg = current_ir_graph;
2662 ir_node *block = be_transform_node(get_nodes_block(node));
2663 dbg_info *dbgi = get_irn_dbg_info(node);
2670 ia32_asm_attr_t *attr;
2671 const arch_register_req_t **out_reqs;
2672 const arch_register_req_t **in_reqs;
2673 struct obstack *obst;
2674 constraint_t parsed_constraint;
2676 /* assembler could contain float statements */
2679 /* transform inputs */
2680 arity = get_irn_arity(node);
2681 in = alloca(arity * sizeof(in[0]));
2682 memset(in, 0, arity * sizeof(in[0]));
2684 n_outs = get_ASM_n_output_constraints(node);
2685 n_clobbers = get_ASM_n_clobbers(node);
2686 out_arity = n_outs + n_clobbers;
2688 /* construct register constraints */
2689 obst = get_irg_obstack(irg);
2690 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2691 parsed_constraint.out_reqs = out_reqs;
2692 parsed_constraint.n_outs = n_outs;
2693 parsed_constraint.is_in = 0;
2694 for(i = 0; i < out_arity; ++i) {
2698 const ir_asm_constraint *constraint;
2699 constraint = & get_ASM_output_constraints(node) [i];
2700 c = get_id_str(constraint->constraint);
2701 parse_asm_constraint(i, &parsed_constraint, c);
2703 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2704 c = get_id_str(glob_id);
2705 parse_clobber(node, i, &parsed_constraint, c);
2707 out_reqs[i] = parsed_constraint.req;
2710 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2711 parsed_constraint.is_in = 1;
2712 for(i = 0; i < arity; ++i) {
2713 const ir_asm_constraint *constraint;
2717 constraint = & get_ASM_input_constraints(node) [i];
2718 constr_id = constraint->constraint;
2719 c = get_id_str(constr_id);
2720 parse_asm_constraint(i, &parsed_constraint, c);
2721 in_reqs[i] = parsed_constraint.req;
2723 if(parsed_constraint.immediate_possible) {
2724 ir_node *pred = get_irn_n(node, i);
2725 char imm_type = parsed_constraint.immediate_type;
2726 ir_node *immediate = try_create_Immediate(pred, imm_type);
2728 if(immediate != NULL) {
2734 /* transform inputs */
2735 for(i = 0; i < arity; ++i) {
2737 ir_node *transformed;
2742 pred = get_irn_n(node, i);
2743 transformed = be_transform_node(pred);
2744 in[i] = transformed;
2747 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2749 generic_attr = get_irn_generic_attr(res);
2750 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2751 attr->asm_text = get_ASM_text(node);
2752 set_ia32_out_req_all(res, out_reqs);
2753 set_ia32_in_req_all(res, in_reqs);
2755 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2760 /********************************************
2763 * | |__ ___ _ __ ___ __| | ___ ___
2764 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2765 * | |_) | __/ | | | (_) | (_| | __/\__ \
2766 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2768 ********************************************/
2770 static ir_node *gen_be_StackParam(ir_node *node) {
2771 ir_node *block = be_transform_node(get_nodes_block(node));
2772 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2773 ir_node *new_ptr = be_transform_node(ptr);
2774 ir_node *new_op = NULL;
2775 ir_graph *irg = current_ir_graph;
2776 dbg_info *dbgi = get_irn_dbg_info(node);
2777 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2778 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2779 ir_mode *load_mode = get_irn_mode(node);
2780 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2784 if (mode_is_float(load_mode)) {
2786 if (USE_SSE2(env_cg)) {
2787 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2788 pn_res = pn_ia32_xLoad_res;
2789 proj_mode = mode_xmm;
2791 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2792 pn_res = pn_ia32_vfld_res;
2793 proj_mode = mode_vfp;
2796 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2797 proj_mode = mode_Iu;
2798 pn_res = pn_ia32_Load_res;
2801 set_irn_pinned(new_op, op_pin_state_floats);
2802 set_ia32_frame_ent(new_op, ent);
2803 set_ia32_use_frame(new_op);
2805 set_ia32_op_type(new_op, ia32_AddrModeS);
2806 set_ia32_am_flavour(new_op, ia32_am_B);
2807 set_ia32_ls_mode(new_op, load_mode);
2808 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2810 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2812 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2816 * Transforms a FrameAddr into an ia32 Add.
2818 static ir_node *gen_be_FrameAddr(ir_node *node) {
2819 ir_node *block = be_transform_node(get_nodes_block(node));
2820 ir_node *op = be_get_FrameAddr_frame(node);
2821 ir_node *new_op = be_transform_node(op);
2822 ir_graph *irg = current_ir_graph;
2823 dbg_info *dbgi = get_irn_dbg_info(node);
2824 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2827 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2828 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2829 set_ia32_use_frame(res);
2830 set_ia32_am_flavour(res, ia32_am_OB);
2832 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2838 * Transforms a FrameLoad into an ia32 Load.
2840 static ir_node *gen_be_FrameLoad(ir_node *node) {
2841 ir_node *block = be_transform_node(get_nodes_block(node));
2842 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2843 ir_node *new_mem = be_transform_node(mem);
2844 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2845 ir_node *new_ptr = be_transform_node(ptr);
2846 ir_node *new_op = NULL;
2847 ir_graph *irg = current_ir_graph;
2848 dbg_info *dbgi = get_irn_dbg_info(node);
2849 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2850 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2851 ir_mode *mode = get_type_mode(get_entity_type(ent));
2852 ir_node *projs[pn_Load_max];
2854 ia32_collect_Projs(node, projs, pn_Load_max);
2856 if (mode_is_float(mode)) {
2858 if (USE_SSE2(env_cg)) {
2859 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2862 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2866 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2869 set_irn_pinned(new_op, op_pin_state_floats);
2870 set_ia32_frame_ent(new_op, ent);
2871 set_ia32_use_frame(new_op);
2873 set_ia32_op_type(new_op, ia32_AddrModeS);
2874 set_ia32_am_flavour(new_op, ia32_am_B);
2875 set_ia32_ls_mode(new_op, mode);
2876 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2878 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2885 * Transforms a FrameStore into an ia32 Store.
2887 static ir_node *gen_be_FrameStore(ir_node *node) {
2888 ir_node *block = be_transform_node(get_nodes_block(node));
2889 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2890 ir_node *new_mem = be_transform_node(mem);
2891 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2892 ir_node *new_ptr = be_transform_node(ptr);
2893 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2894 ir_node *new_val = be_transform_node(val);
2895 ir_node *new_op = NULL;
2896 ir_graph *irg = current_ir_graph;
2897 dbg_info *dbgi = get_irn_dbg_info(node);
2898 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2899 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2900 ir_mode *mode = get_irn_mode(val);
2902 if (mode_is_float(mode)) {
2904 if (USE_SSE2(env_cg)) {
2905 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2907 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2909 } else if (get_mode_size_bits(mode) == 8) {
2910 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2912 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2915 set_ia32_frame_ent(new_op, ent);
2916 set_ia32_use_frame(new_op);
2918 set_ia32_op_type(new_op, ia32_AddrModeD);
2919 set_ia32_am_flavour(new_op, ia32_am_B);
2920 set_ia32_ls_mode(new_op, mode);
2922 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2928 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2930 static ir_node *gen_be_Return(ir_node *node) {
2931 ir_graph *irg = current_ir_graph;
2932 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2933 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2934 ir_entity *ent = get_irg_entity(irg);
2935 ir_type *tp = get_entity_type(ent);
2940 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2941 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2944 int pn_ret_val, pn_ret_mem, arity, i;
2946 assert(ret_val != NULL);
2947 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2948 return be_duplicate_node(node);
2951 res_type = get_method_res_type(tp, 0);
2953 if (! is_Primitive_type(res_type)) {
2954 return be_duplicate_node(node);
2957 mode = get_type_mode(res_type);
2958 if (! mode_is_float(mode)) {
2959 return be_duplicate_node(node);
2962 assert(get_method_n_ress(tp) == 1);
2964 pn_ret_val = get_Proj_proj(ret_val);
2965 pn_ret_mem = get_Proj_proj(ret_mem);
2967 /* get the Barrier */
2968 barrier = get_Proj_pred(ret_val);
2970 /* get result input of the Barrier */
2971 ret_val = get_irn_n(barrier, pn_ret_val);
2972 new_ret_val = be_transform_node(ret_val);
2974 /* get memory input of the Barrier */
2975 ret_mem = get_irn_n(barrier, pn_ret_mem);
2976 new_ret_mem = be_transform_node(ret_mem);
2978 frame = get_irg_frame(irg);
2980 dbgi = get_irn_dbg_info(barrier);
2981 block = be_transform_node(get_nodes_block(barrier));
2983 noreg = ia32_new_NoReg_gp(env_cg);
2985 /* store xmm0 onto stack */
2986 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
2987 set_ia32_ls_mode(sse_store, mode);
2988 set_ia32_op_type(sse_store, ia32_AddrModeD);
2989 set_ia32_use_frame(sse_store);
2990 set_ia32_am_flavour(sse_store, ia32_am_B);
2993 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
2994 set_ia32_ls_mode(fld, mode);
2995 set_ia32_op_type(fld, ia32_AddrModeS);
2996 set_ia32_use_frame(fld);
2997 set_ia32_am_flavour(fld, ia32_am_B);
2999 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3000 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3001 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3003 /* create a new barrier */
3004 arity = get_irn_arity(barrier);
3005 in = alloca(arity * sizeof(in[0]));
3006 for (i = 0; i < arity; ++i) {
3009 if (i == pn_ret_val) {
3011 } else if (i == pn_ret_mem) {
3014 ir_node *in = get_irn_n(barrier, i);
3015 new_in = be_transform_node(in);
3020 new_barrier = new_ir_node(dbgi, irg, block,
3021 get_irn_op(barrier), get_irn_mode(barrier),
3023 copy_node_attr(barrier, new_barrier);
3024 be_duplicate_deps(barrier, new_barrier);
3025 be_set_transformed_node(barrier, new_barrier);
3026 mark_irn_visited(barrier);
3028 /* transform normally */
3029 return be_duplicate_node(node);
3033 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3035 static ir_node *gen_be_AddSP(ir_node *node) {
3036 ir_node *block = be_transform_node(get_nodes_block(node));
3037 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3039 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3040 ir_node *new_sp = be_transform_node(sp);
3041 ir_graph *irg = current_ir_graph;
3042 dbg_info *dbgi = get_irn_dbg_info(node);
3043 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3044 ir_node *nomem = new_NoMem();
3047 new_sz = create_immediate_or_transform(sz, 0);
3049 /* ia32 stack grows in reverse direction, make a SubSP */
3050 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3052 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3053 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3059 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3061 static ir_node *gen_be_SubSP(ir_node *node) {
3062 ir_node *block = be_transform_node(get_nodes_block(node));
3063 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3065 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3066 ir_node *new_sp = be_transform_node(sp);
3067 ir_graph *irg = current_ir_graph;
3068 dbg_info *dbgi = get_irn_dbg_info(node);
3069 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3070 ir_node *nomem = new_NoMem();
3073 new_sz = create_immediate_or_transform(sz, 0);
3075 /* ia32 stack grows in reverse direction, make an AddSP */
3076 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3077 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3078 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3084 * This function just sets the register for the Unknown node
3085 * as this is not done during register allocation because Unknown
3086 * is an "ignore" node.
3088 static ir_node *gen_Unknown(ir_node *node) {
3089 ir_mode *mode = get_irn_mode(node);
3091 if (mode_is_float(mode)) {
3093 if (USE_SSE2(env_cg))
3094 return ia32_new_Unknown_xmm(env_cg);
3096 return ia32_new_Unknown_vfp(env_cg);
3097 } else if (mode_needs_gp_reg(mode)) {
3098 return ia32_new_Unknown_gp(env_cg);
3100 assert(0 && "unsupported Unknown-Mode");
3107 * Change some phi modes
3109 static ir_node *gen_Phi(ir_node *node) {
3110 ir_node *block = be_transform_node(get_nodes_block(node));
3111 ir_graph *irg = current_ir_graph;
3112 dbg_info *dbgi = get_irn_dbg_info(node);
3113 ir_mode *mode = get_irn_mode(node);
3116 if(mode_needs_gp_reg(mode)) {
3117 /* we shouldn't have any 64bit stuff around anymore */
3118 assert(get_mode_size_bits(mode) <= 32);
3119 /* all integer operations are on 32bit registers now */
3121 } else if(mode_is_float(mode)) {
3122 if (USE_SSE2(env_cg)) {
3129 /* phi nodes allow loops, so we use the old arguments for now
3130 * and fix this later */
3131 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3132 copy_node_attr(node, phi);
3133 be_duplicate_deps(node, phi);
3135 be_set_transformed_node(node, phi);
3136 be_enqueue_preds(node);
3141 /**********************************************************************
3144 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3145 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3146 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3147 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3149 **********************************************************************/
3151 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3153 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3156 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3157 ir_node *val, ir_node *mem);
3160 * Transforms a lowered Load into a "real" one.
3162 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3163 ir_node *block = be_transform_node(get_nodes_block(node));
3164 ir_node *ptr = get_irn_n(node, 0);
3165 ir_node *new_ptr = be_transform_node(ptr);
3166 ir_node *mem = get_irn_n(node, 1);
3167 ir_node *new_mem = be_transform_node(mem);
3168 ir_graph *irg = current_ir_graph;
3169 dbg_info *dbgi = get_irn_dbg_info(node);
3170 ir_mode *mode = get_ia32_ls_mode(node);
3171 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3175 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3176 lowering we have x87 nodes, so we need to enforce simulation.
3178 if (mode_is_float(mode)) {
3180 if (fp_unit == fp_x87)
3184 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3186 set_ia32_op_type(new_op, ia32_AddrModeS);
3187 set_ia32_am_flavour(new_op, ia32_am_OB);
3188 set_ia32_am_offs_int(new_op, 0);
3189 set_ia32_am_scale(new_op, 1);
3190 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3191 if (is_ia32_am_sc_sign(node))
3192 set_ia32_am_sc_sign(new_op);
3193 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3194 if (is_ia32_use_frame(node)) {
3195 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3196 set_ia32_use_frame(new_op);
3199 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3205 * Transforms a lowered Store into a "real" one.
3207 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3208 ir_node *block = be_transform_node(get_nodes_block(node));
3209 ir_node *ptr = get_irn_n(node, 0);
3210 ir_node *new_ptr = be_transform_node(ptr);
3211 ir_node *val = get_irn_n(node, 1);
3212 ir_node *new_val = be_transform_node(val);
3213 ir_node *mem = get_irn_n(node, 2);
3214 ir_node *new_mem = be_transform_node(mem);
3215 ir_graph *irg = current_ir_graph;
3216 dbg_info *dbgi = get_irn_dbg_info(node);
3217 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3218 ir_mode *mode = get_ia32_ls_mode(node);
3221 ia32_am_flavour_t am_flav = ia32_B;
3224 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3225 lowering we have x87 nodes, so we need to enforce simulation.
3227 if (mode_is_float(mode)) {
3229 if (fp_unit == fp_x87)
3233 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3235 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3237 add_ia32_am_offs_int(new_op, am_offs);
3240 set_ia32_op_type(new_op, ia32_AddrModeD);
3241 set_ia32_am_flavour(new_op, am_flav);
3242 set_ia32_ls_mode(new_op, mode);
3243 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3244 set_ia32_use_frame(new_op);
3246 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3253 * Transforms an ia32_l_XXX into a "real" XXX node
3255 * @param env The transformation environment
3256 * @return the created ia32 XXX node
3258 #define GEN_LOWERED_OP(op) \
3259 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3260 ir_mode *mode = get_irn_mode(node); \
3261 if (mode_is_float(mode)) \
3263 return gen_binop(node, get_binop_left(node), \
3264 get_binop_right(node), new_rd_ia32_##op,0); \
3267 #define GEN_LOWERED_x87_OP(op) \
3268 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3270 FORCE_x87(env_cg); \
3271 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3272 get_binop_right(node), new_rd_ia32_##op); \
3276 #define GEN_LOWERED_UNOP(op) \
3277 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3278 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3281 #define GEN_LOWERED_SHIFT_OP(op) \
3282 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3283 return gen_shift_binop(node, get_binop_left(node), \
3284 get_binop_right(node), new_rd_ia32_##op); \
3287 #define GEN_LOWERED_LOAD(op, fp_unit) \
3288 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3289 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3292 #define GEN_LOWERED_STORE(op, fp_unit) \
3293 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3294 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3301 GEN_LOWERED_OP(IMul)
3303 GEN_LOWERED_x87_OP(vfprem)
3304 GEN_LOWERED_x87_OP(vfmul)
3305 GEN_LOWERED_x87_OP(vfsub)
3307 GEN_LOWERED_UNOP(Neg)
3309 GEN_LOWERED_LOAD(vfild, fp_x87)
3310 GEN_LOWERED_LOAD(Load, fp_none)
3311 /*GEN_LOWERED_STORE(vfist, fp_x87)
3314 GEN_LOWERED_STORE(Store, fp_none)
3316 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3317 ir_node *block = be_transform_node(get_nodes_block(node));
3318 ir_node *left = get_binop_left(node);
3319 ir_node *new_left = be_transform_node(left);
3320 ir_node *right = get_binop_right(node);
3321 ir_node *new_right = be_transform_node(right);
3322 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3323 ir_graph *irg = current_ir_graph;
3324 dbg_info *dbgi = get_irn_dbg_info(node);
3325 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3326 &ia32_fp_cw_regs[REG_FPCW]);
3329 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3330 new_right, new_NoMem(), fpcw);
3331 clear_ia32_commutative(vfdiv);
3332 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3334 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3342 * Transforms a l_MulS into a "real" MulS node.
3344 * @param env The transformation environment
3345 * @return the created ia32 Mul node
3347 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3348 ir_node *block = be_transform_node(get_nodes_block(node));
3349 ir_node *left = get_binop_left(node);
3350 ir_node *new_left = be_transform_node(left);
3351 ir_node *right = get_binop_right(node);
3352 ir_node *new_right = be_transform_node(right);
3353 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3354 ir_graph *irg = current_ir_graph;
3355 dbg_info *dbgi = get_irn_dbg_info(node);
3357 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3358 /* and then skip the result Proj, because all needed Projs are already there. */
3359 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3360 new_right, new_NoMem());
3361 clear_ia32_commutative(muls);
3362 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3364 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3369 GEN_LOWERED_SHIFT_OP(Shl)
3370 GEN_LOWERED_SHIFT_OP(Shr)
3371 GEN_LOWERED_SHIFT_OP(Sar)
3374 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3375 * op1 - target to be shifted
3376 * op2 - contains bits to be shifted into target
3378 * Only op3 can be an immediate.
3380 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3381 ir_node *op2, ir_node *count)
3383 ir_node *block = be_transform_node(get_nodes_block(node));
3384 ir_node *new_op1 = be_transform_node(op1);
3385 ir_node *new_op2 = be_transform_node(op2);
3386 ir_node *new_count = be_transform_node(count);
3387 ir_node *new_op = NULL;
3388 ir_graph *irg = current_ir_graph;
3389 dbg_info *dbgi = get_irn_dbg_info(node);
3390 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3391 ir_node *nomem = new_NoMem();
3395 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3397 /* Check if immediate optimization is on and */
3398 /* if it's an operation with immediate. */
3399 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3401 /* Limit imm_op within range imm8 */
3403 tv = get_ia32_Immop_tarval(imm_op);
3406 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3407 set_ia32_Immop_tarval(imm_op, tv);
3414 /* integer operations */
3416 /* This is ShiftD with const */
3417 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3419 if (is_ia32_l_ShlD(node))
3420 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3421 new_op1, new_op2, noreg, nomem);
3423 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3424 new_op1, new_op2, noreg, nomem);
3425 copy_ia32_Immop_attr(new_op, imm_op);
3428 /* This is a normal ShiftD */
3429 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3430 if (is_ia32_l_ShlD(node))
3431 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3432 new_op1, new_op2, new_count, nomem);
3434 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3435 new_op1, new_op2, new_count, nomem);
3438 /* set AM support */
3439 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3441 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3443 set_ia32_emit_cl(new_op);
3448 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3449 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3450 get_irn_n(node, 1), get_irn_n(node, 2));
3453 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3454 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3455 get_irn_n(node, 1), get_irn_n(node, 2));
3459 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3461 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3462 ir_node *block = be_transform_node(get_nodes_block(node));
3463 ir_node *val = get_irn_n(node, 1);
3464 ir_node *new_val = be_transform_node(val);
3465 ia32_code_gen_t *cg = env_cg;
3466 ir_node *res = NULL;
3467 ir_graph *irg = current_ir_graph;
3469 ir_node *noreg, *new_ptr, *new_mem;
3476 mem = get_irn_n(node, 2);
3477 new_mem = be_transform_node(mem);
3478 ptr = get_irn_n(node, 0);
3479 new_ptr = be_transform_node(ptr);
3480 noreg = ia32_new_NoReg_gp(cg);
3481 dbgi = get_irn_dbg_info(node);
3483 /* Store x87 -> MEM */
3484 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3485 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3486 set_ia32_use_frame(res);
3487 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3488 set_ia32_am_flavour(res, ia32_B);
3489 set_ia32_op_type(res, ia32_AddrModeD);
3491 /* Load MEM -> SSE */
3492 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3493 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3494 set_ia32_use_frame(res);
3495 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3496 set_ia32_am_flavour(res, ia32_B);
3497 set_ia32_op_type(res, ia32_AddrModeS);
3498 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3504 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3506 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3507 ir_node *block = be_transform_node(get_nodes_block(node));
3508 ir_node *val = get_irn_n(node, 1);
3509 ir_node *new_val = be_transform_node(val);
3510 ia32_code_gen_t *cg = env_cg;
3511 ir_graph *irg = current_ir_graph;
3512 ir_node *res = NULL;
3513 ir_entity *fent = get_ia32_frame_ent(node);
3514 ir_mode *lsmode = get_ia32_ls_mode(node);
3516 ir_node *noreg, *new_ptr, *new_mem;
3520 if (! USE_SSE2(cg)) {
3521 /* SSE unit is not used -> skip this node. */
3525 ptr = get_irn_n(node, 0);
3526 new_ptr = be_transform_node(ptr);
3527 mem = get_irn_n(node, 2);
3528 new_mem = be_transform_node(mem);
3529 noreg = ia32_new_NoReg_gp(cg);
3530 dbgi = get_irn_dbg_info(node);
3532 /* Store SSE -> MEM */
3533 if (is_ia32_xLoad(skip_Proj(new_val))) {
3534 ir_node *ld = skip_Proj(new_val);
3536 /* we can vfld the value directly into the fpu */
3537 fent = get_ia32_frame_ent(ld);
3538 ptr = get_irn_n(ld, 0);
3539 offs = get_ia32_am_offs_int(ld);
3541 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3542 set_ia32_frame_ent(res, fent);
3543 set_ia32_use_frame(res);
3544 set_ia32_ls_mode(res, lsmode);
3545 set_ia32_am_flavour(res, ia32_B);
3546 set_ia32_op_type(res, ia32_AddrModeD);
3550 /* Load MEM -> x87 */
3551 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3552 set_ia32_frame_ent(res, fent);
3553 set_ia32_use_frame(res);
3554 add_ia32_am_offs_int(res, offs);
3555 set_ia32_am_flavour(res, ia32_B);
3556 set_ia32_op_type(res, ia32_AddrModeS);
3557 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3562 /*********************************************************
3565 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3566 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3567 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3568 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3570 *********************************************************/
3573 * the BAD transformer.
3575 static ir_node *bad_transform(ir_node *node) {
3576 panic("No transform function for %+F available.\n", node);
3581 * Transform the Projs of an AddSP.
3583 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3584 ir_node *block = be_transform_node(get_nodes_block(node));
3585 ir_node *pred = get_Proj_pred(node);
3586 ir_node *new_pred = be_transform_node(pred);
3587 ir_graph *irg = current_ir_graph;
3588 dbg_info *dbgi = get_irn_dbg_info(node);
3589 long proj = get_Proj_proj(node);
3591 if (proj == pn_be_AddSP_res) {
3592 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3593 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3595 } else if (proj == pn_be_AddSP_M) {
3596 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3600 return new_rd_Unknown(irg, get_irn_mode(node));
3604 * Transform the Projs of a SubSP.
3606 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3607 ir_node *block = be_transform_node(get_nodes_block(node));
3608 ir_node *pred = get_Proj_pred(node);
3609 ir_node *new_pred = be_transform_node(pred);
3610 ir_graph *irg = current_ir_graph;
3611 dbg_info *dbgi = get_irn_dbg_info(node);
3612 long proj = get_Proj_proj(node);
3614 if (proj == pn_be_SubSP_res) {
3615 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3616 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3618 } else if (proj == pn_be_SubSP_M) {
3619 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3623 return new_rd_Unknown(irg, get_irn_mode(node));
3627 * Transform and renumber the Projs from a Load.
3629 static ir_node *gen_Proj_Load(ir_node *node) {
3630 ir_node *block = be_transform_node(get_nodes_block(node));
3631 ir_node *pred = get_Proj_pred(node);
3632 ir_node *new_pred = be_transform_node(pred);
3633 ir_graph *irg = current_ir_graph;
3634 dbg_info *dbgi = get_irn_dbg_info(node);
3635 long proj = get_Proj_proj(node);
3637 /* renumber the proj */
3638 if (is_ia32_Load(new_pred)) {
3639 if (proj == pn_Load_res) {
3640 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3641 } else if (proj == pn_Load_M) {
3642 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3644 } else if (is_ia32_xLoad(new_pred)) {
3645 if (proj == pn_Load_res) {
3646 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3647 } else if (proj == pn_Load_M) {
3648 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3650 } else if (is_ia32_vfld(new_pred)) {
3651 if (proj == pn_Load_res) {
3652 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3653 } else if (proj == pn_Load_M) {
3654 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3659 return new_rd_Unknown(irg, get_irn_mode(node));
3663 * Transform and renumber the Projs from a DivMod like instruction.
3665 static ir_node *gen_Proj_DivMod(ir_node *node) {
3666 ir_node *block = be_transform_node(get_nodes_block(node));
3667 ir_node *pred = get_Proj_pred(node);
3668 ir_node *new_pred = be_transform_node(pred);
3669 ir_graph *irg = current_ir_graph;
3670 dbg_info *dbgi = get_irn_dbg_info(node);
3671 ir_mode *mode = get_irn_mode(node);
3672 long proj = get_Proj_proj(node);
3674 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3676 switch (get_irn_opcode(pred)) {
3680 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3682 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3690 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3692 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3700 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3701 case pn_DivMod_res_div:
3702 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3703 case pn_DivMod_res_mod:
3704 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3714 return new_rd_Unknown(irg, mode);
3718 * Transform and renumber the Projs from a CopyB.
3720 static ir_node *gen_Proj_CopyB(ir_node *node) {
3721 ir_node *block = be_transform_node(get_nodes_block(node));
3722 ir_node *pred = get_Proj_pred(node);
3723 ir_node *new_pred = be_transform_node(pred);
3724 ir_graph *irg = current_ir_graph;
3725 dbg_info *dbgi = get_irn_dbg_info(node);
3726 ir_mode *mode = get_irn_mode(node);
3727 long proj = get_Proj_proj(node);
3730 case pn_CopyB_M_regular:
3731 if (is_ia32_CopyB_i(new_pred)) {
3732 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3733 } else if (is_ia32_CopyB(new_pred)) {
3734 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3742 return new_rd_Unknown(irg, mode);
3746 * Transform and renumber the Projs from a vfdiv.
3748 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3749 ir_node *block = be_transform_node(get_nodes_block(node));
3750 ir_node *pred = get_Proj_pred(node);
3751 ir_node *new_pred = be_transform_node(pred);
3752 ir_graph *irg = current_ir_graph;
3753 dbg_info *dbgi = get_irn_dbg_info(node);
3754 ir_mode *mode = get_irn_mode(node);
3755 long proj = get_Proj_proj(node);
3758 case pn_ia32_l_vfdiv_M:
3759 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3760 case pn_ia32_l_vfdiv_res:
3761 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3766 return new_rd_Unknown(irg, mode);
3770 * Transform and renumber the Projs from a Quot.
3772 static ir_node *gen_Proj_Quot(ir_node *node) {
3773 ir_node *block = be_transform_node(get_nodes_block(node));
3774 ir_node *pred = get_Proj_pred(node);
3775 ir_node *new_pred = be_transform_node(pred);
3776 ir_graph *irg = current_ir_graph;
3777 dbg_info *dbgi = get_irn_dbg_info(node);
3778 ir_mode *mode = get_irn_mode(node);
3779 long proj = get_Proj_proj(node);
3783 if (is_ia32_xDiv(new_pred)) {
3784 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3785 } else if (is_ia32_vfdiv(new_pred)) {
3786 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3790 if (is_ia32_xDiv(new_pred)) {
3791 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3792 } else if (is_ia32_vfdiv(new_pred)) {
3793 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3801 return new_rd_Unknown(irg, mode);
3805 * Transform the Thread Local Storage Proj.
3807 static ir_node *gen_Proj_tls(ir_node *node) {
3808 ir_node *block = be_transform_node(get_nodes_block(node));
3809 ir_graph *irg = current_ir_graph;
3810 dbg_info *dbgi = NULL;
3811 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3817 * Transform the Projs from a be_Call.
3819 static ir_node *gen_Proj_be_Call(ir_node *node) {
3820 ir_node *block = be_transform_node(get_nodes_block(node));
3821 ir_node *call = get_Proj_pred(node);
3822 ir_node *new_call = be_transform_node(call);
3823 ir_graph *irg = current_ir_graph;
3824 dbg_info *dbgi = get_irn_dbg_info(node);
3825 long proj = get_Proj_proj(node);
3826 ir_mode *mode = get_irn_mode(node);
3828 const arch_register_class_t *cls;
3830 /* The following is kinda tricky: If we're using SSE, then we have to
3831 * move the result value of the call in floating point registers to an
3832 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3833 * after the call, we have to make sure to correctly make the
3834 * MemProj and the result Proj use these 2 nodes
3836 if (proj == pn_be_Call_M_regular) {
3837 // get new node for result, are we doing the sse load/store hack?
3838 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3839 ir_node *call_res_new;
3840 ir_node *call_res_pred = NULL;
3842 if (call_res != NULL) {
3843 call_res_new = be_transform_node(call_res);
3844 call_res_pred = get_Proj_pred(call_res_new);
3847 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3848 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3850 assert(is_ia32_xLoad(call_res_pred));
3851 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3854 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3856 ir_node *frame = get_irg_frame(irg);
3857 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3859 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3861 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3862 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3864 /* store st(0) onto stack */
3865 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3867 set_ia32_ls_mode(fstp, mode);
3868 set_ia32_op_type(fstp, ia32_AddrModeD);
3869 set_ia32_use_frame(fstp);
3870 set_ia32_am_flavour(fstp, ia32_am_B);
3872 /* load into SSE register */
3873 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3874 set_ia32_ls_mode(sse_load, mode);
3875 set_ia32_op_type(sse_load, ia32_AddrModeS);
3876 set_ia32_use_frame(sse_load);
3877 set_ia32_am_flavour(sse_load, ia32_am_B);
3879 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3881 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3883 /* get a Proj representing a caller save register */
3884 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3885 assert(is_Proj(p) && "Proj expected.");
3887 /* user of the the proj is the Keep */
3888 p = get_edge_src_irn(get_irn_out_edge_first(p));
3889 assert(be_is_Keep(p) && "Keep expected.");
3894 /* transform call modes */
3895 if (mode_is_data(mode)) {
3896 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3900 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3904 * Transform the Projs from a Cmp.
3906 static ir_node *gen_Proj_Cmp(ir_node *node)
3908 /* normally Cmps are processed when looking at Cond nodes, but this case
3909 * can happen in complicated Psi conditions */
3911 ir_node *cmp = get_Proj_pred(node);
3912 long pnc = get_Proj_proj(node);
3913 ir_node *cmp_left = get_Cmp_left(cmp);
3914 ir_node *cmp_right = get_Cmp_right(cmp);
3915 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3916 dbg_info *dbgi = get_irn_dbg_info(cmp);
3917 ir_node *block = be_transform_node(get_nodes_block(node));
3920 assert(!mode_is_float(cmp_mode));
3922 if(!mode_is_signed(cmp_mode)) {
3923 pnc |= ia32_pn_Cmp_Unsigned;
3926 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3927 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3933 * Transform and potentially renumber Proj nodes.
3935 static ir_node *gen_Proj(ir_node *node) {
3936 ir_graph *irg = current_ir_graph;
3937 dbg_info *dbgi = get_irn_dbg_info(node);
3938 ir_node *pred = get_Proj_pred(node);
3939 long proj = get_Proj_proj(node);
3941 if (is_Store(pred) || be_is_FrameStore(pred)) {
3942 if (proj == pn_Store_M) {
3943 return be_transform_node(pred);
3946 return new_r_Bad(irg);
3948 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3949 return gen_Proj_Load(node);
3950 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3951 return gen_Proj_DivMod(node);
3952 } else if (is_CopyB(pred)) {
3953 return gen_Proj_CopyB(node);
3954 } else if (is_Quot(pred)) {
3955 return gen_Proj_Quot(node);
3956 } else if (is_ia32_l_vfdiv(pred)) {
3957 return gen_Proj_l_vfdiv(node);
3958 } else if (be_is_SubSP(pred)) {
3959 return gen_Proj_be_SubSP(node);
3960 } else if (be_is_AddSP(pred)) {
3961 return gen_Proj_be_AddSP(node);
3962 } else if (be_is_Call(pred)) {
3963 return gen_Proj_be_Call(node);
3964 } else if (is_Cmp(pred)) {
3965 return gen_Proj_Cmp(node);
3966 } else if (get_irn_op(pred) == op_Start) {
3967 if (proj == pn_Start_X_initial_exec) {
3968 ir_node *block = get_nodes_block(pred);
3971 /* we exchange the ProjX with a jump */
3972 block = be_transform_node(block);
3973 jump = new_rd_Jmp(dbgi, irg, block);
3976 if (node == be_get_old_anchor(anchor_tls)) {
3977 return gen_Proj_tls(node);
3980 ir_node *new_pred = be_transform_node(pred);
3981 ir_node *block = be_transform_node(get_nodes_block(node));
3982 ir_mode *mode = get_irn_mode(node);
3983 if (mode_needs_gp_reg(mode)) {
3984 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3985 get_Proj_proj(node));
3986 #ifdef DEBUG_libfirm
3987 new_proj->node_nr = node->node_nr;
3993 return be_duplicate_node(node);
3997 * Enters all transform functions into the generic pointer
3999 static void register_transformers(void)
4003 /* first clear the generic function pointer for all ops */
4004 clear_irp_opcodes_generic_func();
4006 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4007 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4043 /* transform ops from intrinsic lowering */
4063 /* GEN(ia32_l_vfist); TODO */
4065 GEN(ia32_l_X87toSSE);
4066 GEN(ia32_l_SSEtoX87);
4071 /* we should never see these nodes */
4086 /* handle generic backend nodes */
4097 /* set the register for all Unknown nodes */
4100 op_Mulh = get_op_Mulh();
4109 * Pre-transform all unknown and noreg nodes.
4111 static void ia32_pretransform_node(void *arch_cg) {
4112 ia32_code_gen_t *cg = arch_cg;
4114 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4115 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4116 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4117 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4118 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4119 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4123 void add_missing_keep_walker(ir_node *node, void *data)
4126 unsigned found_projs = 0;
4127 const ir_edge_t *edge;
4128 ir_mode *mode = get_irn_mode(node);
4133 if(!is_ia32_irn(node))
4136 n_outs = get_ia32_n_res(node);
4139 if(is_ia32_SwitchJmp(node))
4142 assert(n_outs < (int) sizeof(unsigned) * 8);
4143 foreach_out_edge(node, edge) {
4144 ir_node *proj = get_edge_src_irn(edge);
4145 int pn = get_Proj_proj(proj);
4147 assert(pn < n_outs);
4148 found_projs |= 1 << pn;
4152 /* are keeps missing? */
4154 for(i = 0; i < n_outs; ++i) {
4157 const arch_register_req_t *req;
4158 const arch_register_class_t *class;
4160 if(found_projs & (1 << i)) {
4164 req = get_ia32_out_req(node, i);
4170 block = get_nodes_block(node);
4171 in[0] = new_r_Proj(current_ir_graph, block, node,
4172 arch_register_class_mode(class), i);
4173 if(last_keep != NULL) {
4174 be_Keep_add_node(last_keep, class, in[0]);
4176 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4182 * Adds missing keeps to nodes
4185 void add_missing_keeps(ia32_code_gen_t *cg)
4187 ir_graph *irg = be_get_birg_irg(cg->birg);
4188 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4191 /* do the transformation */
4192 void ia32_transform_graph(ia32_code_gen_t *cg) {
4193 register_transformers();
4195 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4196 edges_verify(cg->irg);
4197 add_missing_keeps(cg);
4198 edges_verify(cg->irg);
4201 void ia32_init_transform(void)
4203 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");