2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 if(get_mode_size_bits(mode) > 32)
150 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
154 * creates a unique ident by adding a number to a tag
156 * @param tag the tag string, must contain a %d if a number
159 static ident *unique_id(const char *tag)
161 static unsigned id = 0;
164 snprintf(str, sizeof(str), tag, ++id);
165 return new_id_from_str(str);
169 * Get a primitive type for a mode.
171 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
173 pmap_entry *e = pmap_find(types, mode);
178 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
179 res = new_type_primitive(new_id_from_str(buf), mode);
180 set_type_alignment_bytes(res, 16);
181 pmap_insert(types, mode, res);
189 * Get an atomic entity that is initialized with a tarval
191 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
193 tarval *tv = get_Const_tarval(cnst);
194 pmap_entry *e = pmap_find(isa->tv_ent, tv);
199 ir_mode *mode = get_irn_mode(cnst);
200 ir_type *tp = get_Const_type(cnst);
201 if (tp == firm_unknown_type)
202 tp = get_prim_type(isa->types, mode);
204 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
206 set_entity_ld_ident(res, get_entity_ident(res));
207 set_entity_visibility(res, visibility_local);
208 set_entity_variability(res, variability_constant);
209 set_entity_allocation(res, allocation_static);
211 /* we create a new entity here: It's initialization must resist on the
213 rem = current_ir_graph;
214 current_ir_graph = get_const_code_irg();
215 set_atomic_ent_value(res, new_Const_type(tv, tp));
216 current_ir_graph = rem;
218 pmap_insert(isa->tv_ent, tv, res);
226 static int is_Const_0(ir_node *node) {
227 return is_Const(node) && is_Const_null(node);
230 static int is_Const_1(ir_node *node) {
231 return is_Const(node) && is_Const_one(node);
234 static int is_Const_Minus_1(ir_node *node) {
235 return is_Const(node) && is_Const_all_one(node);
239 * Transforms a Const.
241 static ir_node *gen_Const(ir_node *node) {
242 ir_graph *irg = current_ir_graph;
243 ir_node *old_block = get_nodes_block(node);
244 ir_node *block = be_transform_node(old_block);
245 dbg_info *dbgi = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
248 if (mode_is_float(mode)) {
250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
251 ir_node *nomem = new_NoMem();
255 if (USE_SSE2(env_cg)) {
256 if (is_Const_null(node)) {
257 load = new_rd_ia32_xZero(dbgi, irg, block);
258 set_ia32_ls_mode(load, mode);
261 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
263 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
265 set_ia32_op_type(load, ia32_AddrModeS);
266 set_ia32_am_sc(load, floatent);
267 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
268 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
271 if (is_Const_null(node)) {
272 load = new_rd_ia32_vfldz(dbgi, irg, block);
274 } else if (is_Const_one(node)) {
275 load = new_rd_ia32_vfld1(dbgi, irg, block);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
286 set_ia32_ls_mode(load, mode);
289 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
291 /* Const Nodes before the initial IncSP are a bad idea, because
292 * they could be spilled and we have no SP ready at that point yet.
293 * So add a dependency to the initial frame pointer calculation to
294 * avoid that situation.
296 if (get_irg_start_block(irg) == block) {
297 add_irn_dep(load, get_irg_frame(irg));
300 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
304 tarval *tv = get_Const_tarval(node);
307 tv = tarval_convert_to(tv, mode_Iu);
309 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
311 panic("couldn't convert constant tarval (%+F)", node);
313 val = get_tarval_long(tv);
315 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
316 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
319 get_ia32_flags(cnst) | arch_irn_flags_modify_flags);
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(cnst, get_irg_frame(irg));
332 * Transforms a SymConst.
334 static ir_node *gen_SymConst(ir_node *node) {
335 ir_graph *irg = current_ir_graph;
336 ir_node *old_block = get_nodes_block(node);
337 ir_node *block = be_transform_node(old_block);
338 dbg_info *dbgi = get_irn_dbg_info(node);
339 ir_mode *mode = get_irn_mode(node);
342 if (mode_is_float(mode)) {
343 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
344 ir_node *nomem = new_NoMem();
346 if (USE_SSE2(env_cg))
347 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
349 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
350 set_ia32_am_sc(cnst, get_SymConst_entity(node));
351 set_ia32_use_frame(cnst);
355 if(get_SymConst_kind(node) != symconst_addr_ent) {
356 panic("backend only support symconst_addr_ent (at %+F)", node);
358 entity = get_SymConst_entity(node);
359 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
362 /* Const Nodes before the initial IncSP are a bad idea, because
363 * they could be spilled and we have no SP ready at that point yet
365 if (get_irg_start_block(irg) == block) {
366 add_irn_dep(cnst, get_irg_frame(irg));
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
375 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
376 static const struct {
378 const char *ent_name;
379 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
387 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
389 static ir_entity *ent_cache[ia32_known_const_max];
391 const char *tp_name, *ent_name, *cnst_str;
399 ent_name = names[kct].ent_name;
400 if (! ent_cache[kct]) {
401 tp_name = names[kct].tp_name;
402 cnst_str = names[kct].cnst_str;
404 switch (names[kct].mode) {
405 case 0: mode = mode_Iu; break;
406 case 1: mode = mode_Lu; break;
407 default: mode = mode_F; break;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, names[kct].align);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
458 load = get_Proj_pred(node);
459 pn = get_Proj_proj(node);
460 if(!is_Load(load) || pn != pn_Load_res)
462 if(get_nodes_block(load) != block)
464 /* we only use address mode if we're the only user of the load */
465 if(get_irn_n_edges(node) > 1)
468 mode = get_irn_mode(node);
469 if(!mode_needs_gp_reg(mode))
471 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
474 /* don't do AM if other node inputs depend on the load (via mem-proj) */
475 if(other != NULL && get_nodes_block(other) == block
476 && heights_reachable_in_block(heights, other, load))
482 typedef struct ia32_address_mode_t ia32_address_mode_t;
483 struct ia32_address_mode_t {
487 ia32_op_type_t op_type;
494 static void build_address(ia32_address_mode_t *am, ir_node *node)
496 ia32_address_t *addr = &am->addr;
497 ir_node *load = get_Proj_pred(node);
498 ir_node *ptr = get_Load_ptr(load);
499 ir_node *mem = get_Load_mem(load);
500 ir_node *new_mem = be_transform_node(mem);
504 am->ls_mode = get_Load_mode(load);
505 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
507 /* construct load address */
508 ia32_create_address_mode(addr, ptr, 0);
513 base = ia32_new_NoReg_gp(env_cg);
515 base = be_transform_node(base);
519 index = ia32_new_NoReg_gp(env_cg);
521 index = be_transform_node(index);
529 static void set_address(ir_node *node, ia32_address_t *addr)
531 set_ia32_am_scale(node, addr->scale);
532 set_ia32_am_sc(node, addr->symconst_ent);
533 set_ia32_am_offs_int(node, addr->offset);
534 if(addr->symconst_sign)
535 set_ia32_am_sc_sign(node);
537 set_ia32_use_frame(node);
538 set_ia32_frame_ent(node, addr->frame_entity);
541 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
543 set_address(node, &am->addr);
545 set_ia32_op_type(node, am->op_type);
546 set_ia32_ls_mode(node, am->ls_mode);
548 set_ia32_commutative(node);
552 match_commutative = 1 << 0,
553 match_am_and_immediates = 1 << 1,
554 match_no_am = 1 << 2,
555 match_8_16_bit_am = 1 << 3,
556 match_no_immediate = 1 << 4
559 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
560 ir_node *op1, ir_node *op2, match_flags_t flags)
562 ia32_address_t *addr = &am->addr;
563 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
568 int use_am_and_immediates;
571 memset(am, 0, sizeof(am[0]));
573 commutative = (flags & match_commutative) != 0;
574 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
575 use_am = ! (flags & match_no_am);
576 use_immediate = !(flags & match_no_immediate);
579 assert(!commutative || op1 != NULL);
581 if(!(flags & match_8_16_bit_am)
583 && get_mode_size_bits(get_irn_mode(op1)) < 32)
586 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
587 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
588 build_address(am, op2);
589 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
591 am->op_type = ia32_AddrModeS;
592 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
593 use_am && use_source_address_mode(block, op1, op2)) {
594 build_address(am, op1);
595 if(new_op2 != NULL) {
598 new_op1 = be_transform_node(op2);
602 am->op_type = ia32_AddrModeS;
604 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
606 new_op2 = be_transform_node(op2);
607 am->op_type = ia32_Normal;
609 if(addr->base == NULL)
610 addr->base = noreg_gp;
611 if(addr->index == NULL)
612 addr->index = noreg_gp;
613 if(addr->mem == NULL)
614 addr->mem = new_NoMem();
616 am->new_op1 = new_op1;
617 am->new_op2 = new_op2;
618 am->commutative = commutative;
621 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
623 ir_graph *irg = current_ir_graph;
627 if(am->mem_proj == NULL)
630 /* we have to create a mode_T so the old MemProj can attach to us */
631 mode = get_irn_mode(node);
632 load = get_Proj_pred(am->mem_proj);
634 mark_irn_visited(load);
635 be_set_transformed_node(load, node);
638 set_irn_mode(node, mode_T);
639 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
646 * Construct a standard binary operation, set AM and immediate if required.
648 * @param op1 The first operand
649 * @param op2 The second operand
650 * @param func The node constructor function
651 * @return The constructed ia32 node.
653 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
654 construct_binop_func *func, int commutative)
656 ir_node *src_block = get_nodes_block(node);
657 ir_node *block = be_transform_node(src_block);
658 ir_graph *irg = current_ir_graph;
659 dbg_info *dbgi = get_irn_dbg_info(node);
661 ia32_address_mode_t am;
662 ia32_address_t *addr = &am.addr;
663 match_flags_t flags = 0;
666 flags |= match_commutative;
668 match_arguments(&am, src_block, op1, op2, flags);
670 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
671 am.new_op1, am.new_op2);
672 set_am_attributes(new_node, &am);
673 /* we can't use source address mode anymore when using immediates */
674 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
675 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
676 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
678 new_node = fix_mem_proj(new_node, &am);
684 * Construct a standard binary operation, set AM and immediate if required.
686 * @param op1 The first operand
687 * @param op2 The second operand
688 * @param func The node constructor function
689 * @return The constructed ia32 node.
691 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
692 construct_binop_func *func)
694 ir_node *block = be_transform_node(get_nodes_block(node));
695 ir_node *new_op1 = be_transform_node(op1);
696 ir_node *new_op2 = be_transform_node(op2);
697 ir_node *new_node = NULL;
698 dbg_info *dbgi = get_irn_dbg_info(node);
699 ir_graph *irg = current_ir_graph;
700 ir_mode *mode = get_irn_mode(node);
701 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
702 ir_node *nomem = new_NoMem();
704 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
706 if (is_op_commutative(get_irn_op(node))) {
707 set_ia32_commutative(new_node);
709 set_ia32_ls_mode(new_node, mode);
711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
716 static ir_node *get_fpcw(void)
719 if(initial_fpcw != NULL)
722 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
723 &ia32_fp_cw_regs[REG_FPCW]);
724 initial_fpcw = be_transform_node(fpcw);
730 * Construct a standard binary operation, set AM and immediate if required.
732 * @param op1 The first operand
733 * @param op2 The second operand
734 * @param func The node constructor function
735 * @return The constructed ia32 node.
737 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
738 construct_binop_float_func *func)
740 ir_node *block = be_transform_node(get_nodes_block(node));
741 ir_node *new_op1 = be_transform_node(op1);
742 ir_node *new_op2 = be_transform_node(op2);
743 ir_node *new_node = NULL;
744 dbg_info *dbgi = get_irn_dbg_info(node);
745 ir_graph *irg = current_ir_graph;
746 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
747 ir_node *nomem = new_NoMem();
749 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
751 if (is_op_commutative(get_irn_op(node))) {
752 set_ia32_commutative(new_node);
755 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
761 * Construct a shift/rotate binary operation, sets AM and immediate if required.
763 * @param op1 The first operand
764 * @param op2 The second operand
765 * @param func The node constructor function
766 * @return The constructed ia32 node.
768 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
769 construct_shift_func *func)
771 dbg_info *dbgi = get_irn_dbg_info(node);
772 ir_graph *irg = current_ir_graph;
773 ir_node *block = get_nodes_block(node);
774 ir_node *new_block = be_transform_node(block);
775 ir_node *new_op1 = be_transform_node(op1);
776 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
779 assert(! mode_is_float(get_irn_mode(node))
780 && "Shift/Rotate with float not supported");
782 res = func(dbgi, irg, new_block, new_op1, new_op2);
783 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
785 /* lowered shift instruction may have a dependency operand, handle it here */
786 if (get_irn_arity(node) == 3) {
787 /* we have a dependency */
788 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
789 add_irn_dep(res, new_dep);
797 * Construct a standard unary operation, set AM and immediate if required.
799 * @param op The operand
800 * @param func The node constructor function
801 * @return The constructed ia32 node.
803 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
805 ir_node *block = be_transform_node(get_nodes_block(node));
806 ir_node *new_op = be_transform_node(op);
807 ir_node *new_node = NULL;
808 ir_graph *irg = current_ir_graph;
809 dbg_info *dbgi = get_irn_dbg_info(node);
811 new_node = func(dbgi, irg, block, new_op);
813 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
818 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
819 ia32_address_t *addr)
821 ir_graph *irg = current_ir_graph;
822 ir_node *base = addr->base;
823 ir_node *index = addr->index;
827 base = ia32_new_NoReg_gp(env_cg);
829 base = be_transform_node(base);
833 index = ia32_new_NoReg_gp(env_cg);
835 index = be_transform_node(index);
838 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
839 set_address(res, addr);
844 static int am_has_immediates(const ia32_address_t *addr)
846 return addr->offset != 0 || addr->symconst_ent != NULL
847 || addr->frame_entity || addr->use_frame;
851 * Creates an ia32 Add.
853 * @return the created ia32 Add node
855 static ir_node *gen_Add(ir_node *node) {
856 ir_node *block = be_transform_node(get_nodes_block(node));
857 ir_node *op1 = get_Add_left(node);
858 ir_node *op2 = get_Add_right(node);
861 ir_graph *irg = current_ir_graph;
862 dbg_info *dbgi = get_irn_dbg_info(node);
863 ir_mode *mode = get_irn_mode(node);
864 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
865 ir_node *src_block = get_nodes_block(node);
866 ir_node *add_immediate_op;
868 ia32_address_mode_t am;
870 if (mode_is_float(mode)) {
871 if (USE_SSE2(env_cg))
872 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
874 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
879 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
880 * 1. Add with immediate -> Lea
881 * 2. Add with possible source address mode -> Add
882 * 3. Otherwise -> Lea
884 memset(&addr, 0, sizeof(addr));
885 ia32_create_address_mode(&addr, node, 1);
886 add_immediate_op = NULL;
888 if(addr.base == NULL && addr.index == NULL) {
889 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
890 addr.symconst_sign, addr.offset);
891 add_irn_dep(new_op, get_irg_frame(irg));
892 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
895 /* add with immediate? */
896 if(addr.index == NULL) {
897 add_immediate_op = addr.base;
898 } else if(addr.base == NULL && addr.scale == 0) {
899 add_immediate_op = addr.index;
902 if(add_immediate_op != NULL) {
903 if(!am_has_immediates(&addr)) {
905 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
908 return be_transform_node(add_immediate_op);
911 new_op = create_lea_from_address(dbgi, block, &addr);
912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
916 /* test if we can use source address mode */
917 memset(&am, 0, sizeof(am));
919 if(use_source_address_mode(src_block, op2, op1)) {
920 build_address(&am, op2);
921 new_op1 = be_transform_node(op1);
922 } else if(use_source_address_mode(src_block, op1, op2)) {
923 build_address(&am, op1);
924 new_op1 = be_transform_node(op2);
926 /* construct an Add with source address mode */
927 if(new_op1 != NULL) {
928 ia32_address_t *am_addr = &am.addr;
929 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
930 am_addr->mem, new_op1, noreg);
931 set_address(new_op, am_addr);
932 set_ia32_op_type(new_op, ia32_AddrModeS);
933 set_ia32_ls_mode(new_op, am.ls_mode);
934 set_ia32_commutative(new_op);
935 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
937 new_op = fix_mem_proj(new_op, &am);
942 /* otherwise construct a lea */
943 new_op = create_lea_from_address(dbgi, block, &addr);
944 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
949 * Creates an ia32 Mul.
951 * @return the created ia32 Mul node
953 static ir_node *gen_Mul(ir_node *node) {
954 ir_node *op1 = get_Mul_left(node);
955 ir_node *op2 = get_Mul_right(node);
956 ir_mode *mode = get_irn_mode(node);
958 if (mode_is_float(mode)) {
959 if (USE_SSE2(env_cg))
960 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
962 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
966 for the lower 32bit of the result it doesn't matter whether we use
967 signed or unsigned multiplication so we use IMul as it has fewer
970 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
974 * Creates an ia32 Mulh.
975 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
976 * this result while Mul returns the lower 32 bit.
978 * @return the created ia32 Mulh node
980 static ir_node *gen_Mulh(ir_node *node) {
981 ir_node *block = be_transform_node(get_nodes_block(node));
982 ir_node *op1 = get_irn_n(node, 0);
983 ir_node *new_op1 = be_transform_node(op1);
984 ir_node *op2 = get_irn_n(node, 1);
985 ir_node *new_op2 = be_transform_node(op2);
986 ir_graph *irg = current_ir_graph;
987 dbg_info *dbgi = get_irn_dbg_info(node);
988 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
989 ir_mode *mode = get_irn_mode(node);
990 ir_node *proj_EDX, *res;
992 assert(!mode_is_float(mode) && "Mulh with float not supported");
993 if (mode_is_signed(mode)) {
994 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
997 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1001 set_ia32_commutative(res);
1003 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1011 * Creates an ia32 And.
1013 * @return The created ia32 And node
1015 static ir_node *gen_And(ir_node *node) {
1016 ir_node *op1 = get_And_left(node);
1017 ir_node *op2 = get_And_right(node);
1018 assert(! mode_is_float(get_irn_mode(node)));
1020 /* is it a zero extension? */
1021 if (is_Const(op2)) {
1022 tarval *tv = get_Const_tarval(op2);
1023 long v = get_tarval_long(tv);
1025 if (v == 0xFF || v == 0xFFFF) {
1026 dbg_info *dbgi = get_irn_dbg_info(node);
1027 ir_node *block = get_nodes_block(node);
1034 assert(v == 0xFFFF);
1037 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1043 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1049 * Creates an ia32 Or.
1051 * @return The created ia32 Or node
1053 static ir_node *gen_Or(ir_node *node) {
1054 ir_node *op1 = get_Or_left(node);
1055 ir_node *op2 = get_Or_right(node);
1057 assert (! mode_is_float(get_irn_mode(node)));
1058 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1064 * Creates an ia32 Eor.
1066 * @return The created ia32 Eor node
1068 static ir_node *gen_Eor(ir_node *node) {
1069 ir_node *op1 = get_Eor_left(node);
1070 ir_node *op2 = get_Eor_right(node);
1072 assert(! mode_is_float(get_irn_mode(node)));
1073 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1078 * Creates an ia32 Sub.
1080 * @return The created ia32 Sub node
1082 static ir_node *gen_Sub(ir_node *node) {
1083 ir_node *op1 = get_Sub_left(node);
1084 ir_node *op2 = get_Sub_right(node);
1085 ir_mode *mode = get_irn_mode(node);
1087 if (mode_is_float(mode)) {
1088 if (USE_SSE2(env_cg))
1089 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1091 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1095 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1099 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1105 * Generates an ia32 DivMod with additional infrastructure for the
1106 * register allocator if needed.
1108 * @param dividend -no comment- :)
1109 * @param divisor -no comment- :)
1110 * @param dm_flav flavour_Div/Mod/DivMod
1111 * @return The created ia32 DivMod node
1113 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1114 ir_node *divisor, ia32_op_flavour_t dm_flav)
1116 ir_node *block = be_transform_node(get_nodes_block(node));
1117 ir_node *new_dividend = be_transform_node(dividend);
1118 ir_node *new_divisor = be_transform_node(divisor);
1119 ir_graph *irg = current_ir_graph;
1120 dbg_info *dbgi = get_irn_dbg_info(node);
1121 ir_mode *mode = get_irn_mode(node);
1122 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1123 ir_node *res, *proj_div, *proj_mod;
1124 ir_node *sign_extension;
1125 ir_node *mem, *new_mem;
1128 proj_div = proj_mod = NULL;
1132 mem = get_Div_mem(node);
1133 mode = get_Div_resmode(node);
1134 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1135 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1138 mem = get_Mod_mem(node);
1139 mode = get_Mod_resmode(node);
1140 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1141 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1143 case flavour_DivMod:
1144 mem = get_DivMod_mem(node);
1145 mode = get_DivMod_resmode(node);
1146 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1147 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1148 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1151 panic("invalid divmod flavour!");
1153 new_mem = be_transform_node(mem);
1155 if (mode_is_signed(mode)) {
1156 /* in signed mode, we need to sign extend the dividend */
1157 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1158 add_irn_dep(produceval, get_irg_frame(irg));
1159 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1162 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1163 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1164 add_irn_dep(sign_extension, get_irg_frame(irg));
1167 if (mode_is_signed(mode)) {
1168 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1169 new_dividend, sign_extension, new_divisor, dm_flav);
1171 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1172 sign_extension, new_divisor, dm_flav);
1175 set_ia32_exc_label(res, has_exc);
1176 set_irn_pinned(res, get_irn_pinned(node));
1178 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1185 * Wrapper for generate_DivMod. Sets flavour_Mod.
1188 static ir_node *gen_Mod(ir_node *node) {
1189 return generate_DivMod(node, get_Mod_left(node),
1190 get_Mod_right(node), flavour_Mod);
1194 * Wrapper for generate_DivMod. Sets flavour_Div.
1197 static ir_node *gen_Div(ir_node *node) {
1198 return generate_DivMod(node, get_Div_left(node),
1199 get_Div_right(node), flavour_Div);
1203 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1205 static ir_node *gen_DivMod(ir_node *node) {
1206 return generate_DivMod(node, get_DivMod_left(node),
1207 get_DivMod_right(node), flavour_DivMod);
1213 * Creates an ia32 floating Div.
1215 * @return The created ia32 xDiv node
1217 static ir_node *gen_Quot(ir_node *node) {
1218 ir_node *block = be_transform_node(get_nodes_block(node));
1219 ir_node *op1 = get_Quot_left(node);
1220 ir_node *new_op1 = be_transform_node(op1);
1221 ir_node *op2 = get_Quot_right(node);
1222 ir_node *new_op2 = be_transform_node(op2);
1223 ir_graph *irg = current_ir_graph;
1224 dbg_info *dbgi = get_irn_dbg_info(node);
1225 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1226 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1229 if (USE_SSE2(env_cg)) {
1230 ir_mode *mode = get_irn_mode(op1);
1231 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1233 set_ia32_ls_mode(new_op, mode);
1235 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1236 new_op2, get_fpcw());
1238 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1244 * Creates an ia32 Shl.
1246 * @return The created ia32 Shl node
1248 static ir_node *gen_Shl(ir_node *node) {
1249 ir_node *right = get_Shl_right(node);
1251 /* test whether we can build a lea */
1252 if(is_Const(right)) {
1253 tarval *tv = get_Const_tarval(right);
1254 if(tarval_is_long(tv)) {
1255 long val = get_tarval_long(tv);
1256 if(val >= 0 && val <= 3) {
1257 ir_graph *irg = current_ir_graph;
1258 dbg_info *dbgi = get_irn_dbg_info(node);
1259 ir_node *block = be_transform_node(get_nodes_block(node));
1260 ir_node *base = ia32_new_NoReg_gp(env_cg);
1261 ir_node *index = be_transform_node(get_Shl_left(node));
1262 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1263 set_ia32_am_scale(res, val);
1264 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1270 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1277 * Creates an ia32 Shr.
1279 * @return The created ia32 Shr node
1281 static ir_node *gen_Shr(ir_node *node) {
1282 return gen_shift_binop(node, get_Shr_left(node),
1283 get_Shr_right(node), new_rd_ia32_Shr);
1289 * Creates an ia32 Sar.
1291 * @return The created ia32 Shrs node
1293 static ir_node *gen_Shrs(ir_node *node) {
1294 ir_node *left = get_Shrs_left(node);
1295 ir_node *right = get_Shrs_right(node);
1296 ir_mode *mode = get_irn_mode(node);
1297 if(is_Const(right) && mode == mode_Is) {
1298 tarval *tv = get_Const_tarval(right);
1299 long val = get_tarval_long(tv);
1301 /* this is a sign extension */
1302 ir_graph *irg = current_ir_graph;
1303 dbg_info *dbgi = get_irn_dbg_info(node);
1304 ir_node *block = be_transform_node(get_nodes_block(node));
1306 ir_node *new_op = be_transform_node(op);
1307 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1308 add_irn_dep(pval, get_irg_frame(irg));
1310 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1314 /* 8 or 16 bit sign extension? */
1315 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1316 ir_node *shl_left = get_Shl_left(left);
1317 ir_node *shl_right = get_Shl_right(left);
1318 if(is_Const(shl_right)) {
1319 tarval *tv1 = get_Const_tarval(right);
1320 tarval *tv2 = get_Const_tarval(shl_right);
1321 if(tv1 == tv2 && tarval_is_long(tv1)) {
1322 long val = get_tarval_long(tv1);
1323 if(val == 16 || val == 24) {
1324 dbg_info *dbgi = get_irn_dbg_info(node);
1325 ir_node *block = get_nodes_block(node);
1335 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1344 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1350 * Creates an ia32 RotL.
1352 * @param op1 The first operator
1353 * @param op2 The second operator
1354 * @return The created ia32 RotL node
1356 static ir_node *gen_RotL(ir_node *node,
1357 ir_node *op1, ir_node *op2) {
1358 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1364 * Creates an ia32 RotR.
1365 * NOTE: There is no RotR with immediate because this would always be a RotL
1366 * "imm-mode_size_bits" which can be pre-calculated.
1368 * @param op1 The first operator
1369 * @param op2 The second operator
1370 * @return The created ia32 RotR node
1372 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1374 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1380 * Creates an ia32 RotR or RotL (depending on the found pattern).
1382 * @return The created ia32 RotL or RotR node
1384 static ir_node *gen_Rot(ir_node *node) {
1385 ir_node *rotate = NULL;
1386 ir_node *op1 = get_Rot_left(node);
1387 ir_node *op2 = get_Rot_right(node);
1389 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1390 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1391 that means we can create a RotR instead of an Add and a RotL */
1393 if (get_irn_op(op2) == op_Add) {
1395 ir_node *left = get_Add_left(add);
1396 ir_node *right = get_Add_right(add);
1397 if (is_Const(right)) {
1398 tarval *tv = get_Const_tarval(right);
1399 ir_mode *mode = get_irn_mode(node);
1400 long bits = get_mode_size_bits(mode);
1402 if (get_irn_op(left) == op_Minus &&
1403 tarval_is_long(tv) &&
1404 get_tarval_long(tv) == bits)
1406 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1407 rotate = gen_RotR(node, op1, get_Minus_op(left));
1412 if (rotate == NULL) {
1413 rotate = gen_RotL(node, op1, op2);
1422 * Transforms a Minus node.
1424 * @param op The Minus operand
1425 * @return The created ia32 Minus node
1427 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1428 ir_node *block = be_transform_node(get_nodes_block(node));
1429 ir_graph *irg = current_ir_graph;
1430 dbg_info *dbgi = get_irn_dbg_info(node);
1431 ir_mode *mode = get_irn_mode(node);
1436 if (mode_is_float(mode)) {
1437 ir_node *new_op = be_transform_node(op);
1438 if (USE_SSE2(env_cg)) {
1439 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1440 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1441 ir_node *nomem = new_rd_NoMem(irg);
1443 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1446 size = get_mode_size_bits(mode);
1447 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1449 set_ia32_am_sc(res, ent);
1450 set_ia32_op_type(res, ia32_AddrModeS);
1451 set_ia32_ls_mode(res, mode);
1453 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1456 res = gen_unop(node, op, new_rd_ia32_Neg);
1459 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1465 * Transforms a Minus node.
1467 * @return The created ia32 Minus node
1469 static ir_node *gen_Minus(ir_node *node) {
1470 return gen_Minus_ex(node, get_Minus_op(node));
1473 static ir_node *create_Immediate_from_int(int val)
1475 ir_graph *irg = current_ir_graph;
1476 ir_node *start_block = get_irg_start_block(irg);
1477 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1478 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1483 static ir_node *gen_bin_Not(ir_node *node)
1485 ir_graph *irg = current_ir_graph;
1486 dbg_info *dbgi = get_irn_dbg_info(node);
1487 ir_node *block = be_transform_node(get_nodes_block(node));
1488 ir_node *op = get_Not_op(node);
1489 ir_node *new_op = be_transform_node(op);
1490 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1491 ir_node *nomem = new_NoMem();
1492 ir_node *one = create_Immediate_from_int(1);
1494 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1498 * Transforms a Not node.
1500 * @return The created ia32 Not node
1502 static ir_node *gen_Not(ir_node *node) {
1503 ir_node *op = get_Not_op(node);
1504 ir_mode *mode = get_irn_mode(node);
1506 if(mode == mode_b) {
1507 return gen_bin_Not(node);
1510 assert (! mode_is_float(get_irn_mode(node)));
1511 return gen_unop(node, op, new_rd_ia32_Not);
1517 * Transforms an Abs node.
1519 * @return The created ia32 Abs node
1521 static ir_node *gen_Abs(ir_node *node) {
1522 ir_node *block = be_transform_node(get_nodes_block(node));
1523 ir_node *op = get_Abs_op(node);
1524 ir_node *new_op = be_transform_node(op);
1525 ir_graph *irg = current_ir_graph;
1526 dbg_info *dbgi = get_irn_dbg_info(node);
1527 ir_mode *mode = get_irn_mode(node);
1528 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1529 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1530 ir_node *nomem = new_NoMem();
1535 if (mode_is_float(mode)) {
1536 if (USE_SSE2(env_cg)) {
1537 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1539 size = get_mode_size_bits(mode);
1540 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1542 set_ia32_am_sc(res, ent);
1544 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1546 set_ia32_op_type(res, ia32_AddrModeS);
1547 set_ia32_ls_mode(res, mode);
1550 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1551 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1555 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1556 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1559 add_irn_dep(pval, get_irg_frame(irg));
1560 SET_IA32_ORIG_NODE(sign_extension,
1561 ia32_get_old_node_name(env_cg, node));
1563 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1565 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1567 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1569 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1576 * Transforms a Load.
1578 * @return the created ia32 Load node
1580 static ir_node *gen_Load(ir_node *node) {
1581 ir_node *old_block = get_nodes_block(node);
1582 ir_node *block = be_transform_node(old_block);
1583 ir_node *ptr = get_Load_ptr(node);
1584 ir_node *mem = get_Load_mem(node);
1585 ir_node *new_mem = be_transform_node(mem);
1588 ir_graph *irg = current_ir_graph;
1589 dbg_info *dbgi = get_irn_dbg_info(node);
1590 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1591 ir_mode *mode = get_Load_mode(node);
1594 ia32_address_t addr;
1596 /* construct load address */
1597 memset(&addr, 0, sizeof(addr));
1598 ia32_create_address_mode(&addr, ptr, 0);
1605 base = be_transform_node(base);
1611 index = be_transform_node(index);
1614 if (mode_is_float(mode)) {
1615 if (USE_SSE2(env_cg)) {
1616 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1618 res_mode = mode_xmm;
1620 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1622 res_mode = mode_vfp;
1628 /* create a conv node with address mode for smaller modes */
1629 if(get_mode_size_bits(mode) < 32) {
1630 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1631 new_mem, noreg, mode);
1633 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1638 set_irn_pinned(new_op, get_irn_pinned(node));
1639 set_ia32_op_type(new_op, ia32_AddrModeS);
1640 set_ia32_ls_mode(new_op, mode);
1641 set_address(new_op, &addr);
1643 /* make sure we are scheduled behind the initial IncSP/Barrier
1644 * to avoid spills being placed before it
1646 if (block == get_irg_start_block(irg)) {
1647 add_irn_dep(new_op, get_irg_frame(irg));
1650 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1651 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1656 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1657 ir_node *ptr, ir_mode *mode, ir_node *other)
1664 /* we only use address mode if we're the only user of the load */
1665 if(get_irn_n_edges(node) > 1)
1668 load = get_Proj_pred(node);
1671 if(get_nodes_block(load) != block)
1674 /* Store should be attached to the load */
1675 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1677 /* store should have the same pointer as the load */
1678 if(get_Load_ptr(load) != ptr)
1681 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1682 if(other != NULL && get_nodes_block(other) == block
1683 && heights_reachable_in_block(heights, other, load))
1686 assert(get_Load_mode(load) == mode);
1691 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1692 ir_node *mem, ir_node *ptr, ir_mode *mode,
1693 construct_binop_dest_func *func,
1694 construct_binop_dest_func *func8bit,
1697 ir_node *src_block = get_nodes_block(node);
1699 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1700 ir_graph *irg = current_ir_graph;
1704 ia32_address_mode_t am;
1705 ia32_address_t *addr = &am.addr;
1706 memset(&am, 0, sizeof(am));
1708 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1709 build_address(&am, op1);
1710 new_op = create_immediate_or_transform(op2, 0);
1711 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1712 build_address(&am, op2);
1713 new_op = create_immediate_or_transform(op1, 0);
1718 if(addr->base == NULL)
1719 addr->base = noreg_gp;
1720 if(addr->index == NULL)
1721 addr->index = noreg_gp;
1722 if(addr->mem == NULL)
1723 addr->mem = new_NoMem();
1725 dbgi = get_irn_dbg_info(node);
1726 block = be_transform_node(src_block);
1727 if(get_mode_size_bits(mode) == 8) {
1728 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1731 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1734 set_address(new_node, addr);
1735 set_ia32_op_type(new_node, ia32_AddrModeD);
1736 set_ia32_ls_mode(new_node, mode);
1737 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1742 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1743 ir_node *ptr, ir_mode *mode,
1744 construct_unop_dest_func *func)
1746 ir_node *src_block = get_nodes_block(node);
1748 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1749 ir_graph *irg = current_ir_graph;
1752 ia32_address_mode_t am;
1753 ia32_address_t *addr = &am.addr;
1754 memset(&am, 0, sizeof(am));
1756 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1759 build_address(&am, op);
1761 if(addr->base == NULL)
1762 addr->base = noreg_gp;
1763 if(addr->index == NULL)
1764 addr->index = noreg_gp;
1765 if(addr->mem == NULL)
1766 addr->mem = new_NoMem();
1768 dbgi = get_irn_dbg_info(node);
1769 block = be_transform_node(src_block);
1770 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1771 set_address(new_node, addr);
1772 set_ia32_op_type(new_node, ia32_AddrModeD);
1773 set_ia32_ls_mode(new_node, mode);
1774 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1779 static ir_node *try_create_dest_am(ir_node *node) {
1780 ir_node *val = get_Store_value(node);
1781 ir_node *mem = get_Store_mem(node);
1782 ir_node *ptr = get_Store_ptr(node);
1783 ir_mode *mode = get_irn_mode(val);
1788 /* handle only GP modes for now... */
1789 if(!mode_needs_gp_reg(mode))
1792 /* store must be the only user of the val node */
1793 if(get_irn_n_edges(val) > 1)
1796 switch(get_irn_opcode(val)) {
1798 op1 = get_Add_left(val);
1799 op2 = get_Add_right(val);
1800 if(is_Const_1(op2)) {
1801 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1802 new_rd_ia32_IncMem);
1804 } else if(is_Const_Minus_1(op2)) {
1805 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1806 new_rd_ia32_DecMem);
1809 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1810 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1813 op1 = get_Sub_left(val);
1814 op2 = get_Sub_right(val);
1816 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1819 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1820 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1823 op1 = get_And_left(val);
1824 op2 = get_And_right(val);
1825 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1826 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1829 op1 = get_Or_left(val);
1830 op2 = get_Or_right(val);
1831 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1832 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1835 op1 = get_Eor_left(val);
1836 op2 = get_Eor_right(val);
1837 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1838 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1841 op1 = get_Shl_left(val);
1842 op2 = get_Shl_right(val);
1843 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1844 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1847 op1 = get_Shr_left(val);
1848 op2 = get_Shr_right(val);
1849 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1850 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1853 op1 = get_Shrs_left(val);
1854 op2 = get_Shrs_right(val);
1855 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1856 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1859 op1 = get_Rot_left(val);
1860 op2 = get_Rot_right(val);
1861 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1862 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1864 /* TODO: match ROR patterns... */
1866 op1 = get_Minus_op(val);
1867 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1870 /* should be lowered already */
1871 assert(mode != mode_b);
1872 op1 = get_Not_op(val);
1873 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1883 * Transforms a Store.
1885 * @return the created ia32 Store node
1887 static ir_node *gen_Store(ir_node *node) {
1888 ir_node *block = be_transform_node(get_nodes_block(node));
1889 ir_node *ptr = get_Store_ptr(node);
1892 ir_node *val = get_Store_value(node);
1894 ir_node *mem = get_Store_mem(node);
1895 ir_node *new_mem = be_transform_node(mem);
1896 ir_graph *irg = current_ir_graph;
1897 dbg_info *dbgi = get_irn_dbg_info(node);
1898 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1899 ir_mode *mode = get_irn_mode(val);
1901 ia32_address_t addr;
1903 /* check for destination address mode */
1904 new_op = try_create_dest_am(node);
1908 /* construct store address */
1909 memset(&addr, 0, sizeof(addr));
1910 ia32_create_address_mode(&addr, ptr, 0);
1917 base = be_transform_node(base);
1923 index = be_transform_node(index);
1926 if (mode_is_float(mode)) {
1927 new_val = be_transform_node(val);
1928 if (USE_SSE2(env_cg)) {
1929 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1932 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1936 new_val = create_immediate_or_transform(val, 0);
1940 if (get_mode_size_bits(mode) == 8) {
1941 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1944 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1949 set_irn_pinned(new_op, get_irn_pinned(node));
1950 set_ia32_op_type(new_op, ia32_AddrModeD);
1951 set_ia32_ls_mode(new_op, mode);
1953 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1954 set_address(new_op, &addr);
1955 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1960 static ir_node *create_Switch(ir_node *node)
1962 ir_graph *irg = current_ir_graph;
1963 dbg_info *dbgi = get_irn_dbg_info(node);
1964 ir_node *block = be_transform_node(get_nodes_block(node));
1965 ir_node *sel = get_Cond_selector(node);
1966 ir_node *new_sel = be_transform_node(sel);
1968 int switch_min = INT_MAX;
1969 const ir_edge_t *edge;
1971 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1973 /* determine the smallest switch case value */
1974 foreach_out_edge(node, edge) {
1975 ir_node *proj = get_edge_src_irn(edge);
1976 int pn = get_Proj_proj(proj);
1981 if (switch_min != 0) {
1982 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1984 /* if smallest switch case is not 0 we need an additional sub */
1985 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1986 add_ia32_am_offs_int(new_sel, -switch_min);
1987 set_ia32_op_type(new_sel, ia32_AddrModeS);
1989 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1992 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1993 set_ia32_pncode(res, get_Cond_defaultProj(node));
1995 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2000 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2002 ir_graph *irg = current_ir_graph;
2010 /* we have a Cmp as input */
2012 ir_node *pred = get_Proj_pred(node);
2014 flags = be_transform_node(pred);
2015 *pnc_out = get_Proj_proj(node);
2020 /* a mode_b value, we have to compare it against 0 */
2021 dbgi = get_irn_dbg_info(node);
2022 new_block = be_transform_node(get_nodes_block(node));
2023 new_op = be_transform_node(node);
2024 noreg = ia32_new_NoReg_gp(env_cg);
2025 nomem = new_NoMem();
2026 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2027 new_op, new_op, 0, 0);
2028 *pnc_out = pn_Cmp_Lg;
2032 static ir_node *gen_Cond(ir_node *node) {
2033 ir_node *block = get_nodes_block(node);
2034 ir_node *new_block = be_transform_node(block);
2035 ir_graph *irg = current_ir_graph;
2036 dbg_info *dbgi = get_irn_dbg_info(node);
2037 ir_node *sel = get_Cond_selector(node);
2038 ir_mode *sel_mode = get_irn_mode(sel);
2040 ir_node *flags = NULL;
2043 if (sel_mode != mode_b) {
2044 return create_Switch(node);
2047 /* we get flags from a cmp */
2048 flags = get_flags_node(sel, &pnc);
2050 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2051 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2059 * Transforms a CopyB node.
2061 * @return The transformed node.
2063 static ir_node *gen_CopyB(ir_node *node) {
2064 ir_node *block = be_transform_node(get_nodes_block(node));
2065 ir_node *src = get_CopyB_src(node);
2066 ir_node *new_src = be_transform_node(src);
2067 ir_node *dst = get_CopyB_dst(node);
2068 ir_node *new_dst = be_transform_node(dst);
2069 ir_node *mem = get_CopyB_mem(node);
2070 ir_node *new_mem = be_transform_node(mem);
2071 ir_node *res = NULL;
2072 ir_graph *irg = current_ir_graph;
2073 dbg_info *dbgi = get_irn_dbg_info(node);
2074 int size = get_type_size_bytes(get_CopyB_type(node));
2077 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2078 /* then we need the size explicitly in ECX. */
2079 if (size >= 32 * 4) {
2080 rem = size & 0x3; /* size % 4 */
2083 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2085 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2087 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2089 add_irn_dep(res, get_irg_frame(irg));
2091 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2092 /* we misuse the pncode field for the copyb size */
2093 set_ia32_pncode(res, rem);
2095 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2096 set_ia32_pncode(res, size);
2099 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2104 static ir_node *gen_be_Copy(ir_node *node)
2106 ir_node *result = be_duplicate_node(node);
2107 ir_mode *mode = get_irn_mode(result);
2109 if (mode_needs_gp_reg(mode)) {
2110 set_irn_mode(result, mode_Iu);
2117 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2118 * to fold an and into a test node
2120 static int can_fold_test_and(ir_node *node)
2122 const ir_edge_t *edge;
2124 /** we can only have eq and lg projs */
2125 foreach_out_edge(node, edge) {
2126 ir_node *proj = get_edge_src_irn(edge);
2127 pn_Cmp pnc = get_Proj_proj(proj);
2128 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2135 static ir_node *try_create_Test(ir_node *node)
2137 ir_graph *irg = current_ir_graph;
2138 dbg_info *dbgi = get_irn_dbg_info(node);
2139 ir_node *block = get_nodes_block(node);
2140 ir_node *new_block = be_transform_node(block);
2141 ir_node *cmp_left = get_Cmp_left(node);
2142 ir_node *cmp_right = get_Cmp_right(node);
2147 ia32_address_mode_t am;
2148 ia32_address_t *addr = &am.addr;
2151 /* can we use a test instruction? */
2152 if(!is_Const_0(cmp_right))
2155 if(is_And(cmp_left) && can_fold_test_and(node)) {
2156 ir_node *and_left = get_And_left(cmp_left);
2157 ir_node *and_right = get_And_right(cmp_left);
2159 mode = get_irn_mode(and_left);
2163 mode = get_irn_mode(cmp_left);
2168 assert(get_mode_size_bits(mode) <= 32);
2170 match_arguments(&am, block, left, right, match_commutative |
2171 match_8_16_bit_am | match_am_and_immediates);
2173 cmp_unsigned = !mode_is_signed(mode);
2174 if(get_mode_size_bits(mode) == 8) {
2175 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2176 addr->index, addr->mem, am.new_op1,
2177 am.new_op2, am.flipped, cmp_unsigned);
2179 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2180 addr->mem, am.new_op1, am.new_op2, am.flipped,
2183 set_am_attributes(res, &am);
2184 assert(mode != NULL);
2185 set_ia32_ls_mode(res, mode);
2187 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2189 res = fix_mem_proj(res, &am);
2193 static ir_node *create_Fucom(ir_node *node)
2195 ir_graph *irg = current_ir_graph;
2196 dbg_info *dbgi = get_irn_dbg_info(node);
2197 ir_node *block = get_nodes_block(node);
2198 ir_node *new_block = be_transform_node(block);
2199 ir_node *left = get_Cmp_left(node);
2200 ir_node *new_left = be_transform_node(left);
2201 ir_node *right = get_Cmp_right(node);
2202 ir_node *new_right = be_transform_node(right);
2205 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right,
2207 set_ia32_commutative(res);
2209 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2211 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2212 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2217 static ir_node *create_Ucomi(ir_node *node)
2219 ir_graph *irg = current_ir_graph;
2220 dbg_info *dbgi = get_irn_dbg_info(node);
2221 ir_node *block = get_nodes_block(node);
2222 ir_node *new_block = be_transform_node(block);
2223 ir_node *left = get_Cmp_left(node);
2224 ir_node *new_left = be_transform_node(left);
2225 ir_node *right = get_Cmp_right(node);
2226 ir_node *new_right = be_transform_node(right);
2227 ir_mode *mode = get_irn_mode(left);
2228 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2229 ir_node *nomem = new_NoMem();
2232 res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
2234 set_ia32_commutative(res);
2235 set_ia32_ls_mode(res, mode);
2237 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2242 static ir_node *gen_Cmp(ir_node *node)
2244 ir_graph *irg = current_ir_graph;
2245 dbg_info *dbgi = get_irn_dbg_info(node);
2246 ir_node *block = get_nodes_block(node);
2247 ir_node *new_block = be_transform_node(block);
2248 ir_node *left = get_Cmp_left(node);
2249 ir_node *right = get_Cmp_right(node);
2250 ir_mode *cmp_mode = get_irn_mode(left);
2252 ia32_address_mode_t am;
2253 ia32_address_t *addr = &am.addr;
2256 if(mode_is_float(cmp_mode)) {
2257 if (USE_SSE2(env_cg)) {
2258 return create_Ucomi(node);
2260 return create_Fucom(node);
2264 assert(mode_needs_gp_reg(cmp_mode));
2266 /* we prefer the Test instruction where possible except cases where
2267 * we can use SourceAM */
2268 if(!use_source_address_mode(block, left, right) &&
2269 !use_source_address_mode(block, right, left)) {
2270 res = try_create_Test(node);
2275 match_arguments(&am, block, left, right,
2276 match_commutative | match_8_16_bit_am |
2277 match_am_and_immediates);
2279 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2280 if(get_mode_size_bits(cmp_mode) == 8) {
2281 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2282 addr->mem, am.new_op1, am.new_op2,
2283 am.flipped, cmp_unsigned);
2285 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2286 addr->mem, am.new_op1, am.new_op2, am.flipped,
2289 set_am_attributes(res, &am);
2290 assert(cmp_mode != NULL);
2291 set_ia32_ls_mode(res, cmp_mode);
2293 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2295 res = fix_mem_proj(res, &am);
2300 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2302 ir_graph *irg = current_ir_graph;
2303 dbg_info *dbgi = get_irn_dbg_info(node);
2304 ir_node *block = get_nodes_block(node);
2305 ir_node *new_block = be_transform_node(block);
2306 ir_node *val_true = get_Psi_val(node, 0);
2307 ir_node *new_val_true = be_transform_node(val_true);
2308 ir_node *val_false = get_Psi_default(node);
2309 ir_node *new_val_false = be_transform_node(val_false);
2310 ir_mode *mode = get_irn_mode(node);
2311 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2312 ir_node *nomem = new_NoMem();
2315 assert(mode_needs_gp_reg(mode));
2317 res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
2318 new_val_false, new_val_true, new_flags, pnc);
2319 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2326 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2327 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2329 ir_graph *irg = current_ir_graph;
2330 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2331 ir_node *nomem = new_NoMem();
2334 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2335 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2336 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2337 nomem, res, mode_Bu);
2338 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2344 * Transforms a Psi node into CMov.
2346 * @return The transformed node.
2348 static ir_node *gen_Psi(ir_node *node)
2350 dbg_info *dbgi = get_irn_dbg_info(node);
2351 ir_node *block = get_nodes_block(node);
2352 ir_node *new_block = be_transform_node(block);
2353 ir_node *psi_true = get_Psi_val(node, 0);
2354 ir_node *psi_default = get_Psi_default(node);
2355 ir_node *cond = get_Psi_cond(node, 0);
2356 ir_node *flags = NULL;
2361 assert(get_Psi_n_conds(node) == 1);
2362 assert(get_irn_mode(cond) == mode_b);
2363 assert(mode_needs_gp_reg(get_irn_mode(node)));
2365 flags = get_flags_node(cond, &pnc);
2367 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2368 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2369 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2370 pnc = get_negated_pnc(pnc, cmp_mode);
2371 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2373 res = create_CMov(node, flags, pnc);
2380 * Create a conversion from x87 state register to general purpose.
2382 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2383 ir_node *block = be_transform_node(get_nodes_block(node));
2384 ir_node *op = get_Conv_op(node);
2385 ir_node *new_op = be_transform_node(op);
2386 ia32_code_gen_t *cg = env_cg;
2387 ir_graph *irg = current_ir_graph;
2388 dbg_info *dbgi = get_irn_dbg_info(node);
2389 ir_node *noreg = ia32_new_NoReg_gp(cg);
2390 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2391 ir_mode *mode = get_irn_mode(node);
2392 ir_node *fist, *load;
2395 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2396 new_NoMem(), new_op, trunc_mode);
2398 set_irn_pinned(fist, op_pin_state_floats);
2399 set_ia32_use_frame(fist);
2400 set_ia32_op_type(fist, ia32_AddrModeD);
2402 assert(get_mode_size_bits(mode) <= 32);
2403 /* exception we can only store signed 32 bit integers, so for unsigned
2404 we store a 64bit (signed) integer and load the lower bits */
2405 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2406 set_ia32_ls_mode(fist, mode_Ls);
2408 set_ia32_ls_mode(fist, mode_Is);
2410 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2413 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2415 set_irn_pinned(load, op_pin_state_floats);
2416 set_ia32_use_frame(load);
2417 set_ia32_op_type(load, ia32_AddrModeS);
2418 set_ia32_ls_mode(load, mode_Is);
2419 if(get_ia32_ls_mode(fist) == mode_Ls) {
2420 ia32_attr_t *attr = get_ia32_attr(load);
2421 attr->data.need_64bit_stackent = 1;
2423 ia32_attr_t *attr = get_ia32_attr(load);
2424 attr->data.need_32bit_stackent = 1;
2426 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2428 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2432 * Creates a x87 strict Conv by placing a Sore and a Load
2434 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2436 ir_node *block = get_nodes_block(node);
2437 ir_graph *irg = current_ir_graph;
2438 dbg_info *dbgi = get_irn_dbg_info(node);
2439 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2440 ir_node *nomem = new_NoMem();
2441 ir_node *frame = get_irg_frame(irg);
2442 ir_node *store, *load;
2445 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2447 set_ia32_use_frame(store);
2448 set_ia32_op_type(store, ia32_AddrModeD);
2449 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2451 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2453 set_ia32_use_frame(load);
2454 set_ia32_op_type(load, ia32_AddrModeS);
2455 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2457 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2462 * Create a conversion from general purpose to x87 register
2464 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2465 ir_node *src_block = get_nodes_block(node);
2466 ir_node *block = be_transform_node(src_block);
2467 ir_graph *irg = current_ir_graph;
2468 dbg_info *dbgi = get_irn_dbg_info(node);
2469 ir_node *op = get_Conv_op(node);
2474 ir_mode *store_mode;
2480 /* fild can use source AM if the operand is a signed 32bit integer */
2481 if (src_mode == mode_Is) {
2482 ia32_address_mode_t am;
2484 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2485 if (am.op_type == ia32_AddrModeS) {
2486 ia32_address_t *addr = &am.addr;
2488 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2489 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2491 set_am_attributes(fild, &am);
2492 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2494 fix_mem_proj(fild, &am);
2498 new_op = am.new_op2;
2500 new_op = be_transform_node(op);
2503 noreg = ia32_new_NoReg_gp(env_cg);
2504 nomem = new_NoMem();
2505 mode = get_irn_mode(op);
2507 /* first convert to 32 bit signed if necessary */
2508 src_bits = get_mode_size_bits(src_mode);
2509 if (src_bits == 8) {
2510 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2512 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2514 } else if (src_bits < 32) {
2515 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2517 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2521 assert(get_mode_size_bits(mode) == 32);
2524 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2527 set_ia32_use_frame(store);
2528 set_ia32_op_type(store, ia32_AddrModeD);
2529 set_ia32_ls_mode(store, mode_Iu);
2531 /* exception for 32bit unsigned, do a 64bit spill+load */
2532 if(!mode_is_signed(mode)) {
2535 ir_node *zero_const = create_Immediate_from_int(0);
2537 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2538 get_irg_frame(irg), noreg, nomem,
2541 set_ia32_use_frame(zero_store);
2542 set_ia32_op_type(zero_store, ia32_AddrModeD);
2543 add_ia32_am_offs_int(zero_store, 4);
2544 set_ia32_ls_mode(zero_store, mode_Iu);
2549 store = new_rd_Sync(dbgi, irg, block, 2, in);
2550 store_mode = mode_Ls;
2552 store_mode = mode_Is;
2556 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2558 set_ia32_use_frame(fild);
2559 set_ia32_op_type(fild, ia32_AddrModeS);
2560 set_ia32_ls_mode(fild, store_mode);
2562 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2568 * Crete a conversion from one integer mode into another one
2570 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2571 dbg_info *dbgi, ir_node *block, ir_node *op,
2574 ir_graph *irg = current_ir_graph;
2575 int src_bits = get_mode_size_bits(src_mode);
2576 int tgt_bits = get_mode_size_bits(tgt_mode);
2577 ir_node *new_block = be_transform_node(block);
2578 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2581 ir_mode *smaller_mode;
2583 ia32_address_mode_t am;
2584 ia32_address_t *addr = &am.addr;
2586 if (src_bits < tgt_bits) {
2587 smaller_mode = src_mode;
2588 smaller_bits = src_bits;
2590 smaller_mode = tgt_mode;
2591 smaller_bits = tgt_bits;
2594 memset(&am, 0, sizeof(am));
2595 if(use_source_address_mode(block, op, NULL)) {
2596 build_address(&am, op);
2598 am.op_type = ia32_AddrModeS;
2600 new_op = be_transform_node(op);
2601 am.op_type = ia32_Normal;
2603 if(addr->base == NULL)
2605 if(addr->index == NULL)
2606 addr->index = noreg;
2607 if(addr->mem == NULL)
2608 addr->mem = new_NoMem();
2610 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2611 if (smaller_bits == 8) {
2612 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2613 addr->index, addr->mem, new_op,
2616 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2617 addr->index, addr->mem, new_op,
2621 set_am_attributes(res, &am);
2622 set_ia32_ls_mode(res, smaller_mode);
2623 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2624 res = fix_mem_proj(res, &am);
2630 * Transforms a Conv node.
2632 * @return The created ia32 Conv node
2634 static ir_node *gen_Conv(ir_node *node) {
2635 ir_node *block = get_nodes_block(node);
2636 ir_node *new_block = be_transform_node(block);
2637 ir_node *op = get_Conv_op(node);
2638 ir_node *new_op = NULL;
2639 ir_graph *irg = current_ir_graph;
2640 dbg_info *dbgi = get_irn_dbg_info(node);
2641 ir_mode *src_mode = get_irn_mode(op);
2642 ir_mode *tgt_mode = get_irn_mode(node);
2643 int src_bits = get_mode_size_bits(src_mode);
2644 int tgt_bits = get_mode_size_bits(tgt_mode);
2645 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2646 ir_node *nomem = new_rd_NoMem(irg);
2647 ir_node *res = NULL;
2649 if (src_mode == mode_b) {
2650 assert(mode_is_int(tgt_mode));
2651 /* nothing to do, we already model bools as 0/1 ints */
2652 return be_transform_node(op);
2655 if (src_mode == tgt_mode) {
2656 if (get_Conv_strict(node)) {
2657 if (USE_SSE2(env_cg)) {
2658 /* when we are in SSE mode, we can kill all strict no-op conversion */
2659 return be_transform_node(op);
2662 /* this should be optimized already, but who knows... */
2663 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2664 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2665 return be_transform_node(op);
2669 if (mode_is_float(src_mode)) {
2670 new_op = be_transform_node(op);
2671 /* we convert from float ... */
2672 if (mode_is_float(tgt_mode)) {
2673 if(src_mode == mode_E && tgt_mode == mode_D
2674 && !get_Conv_strict(node)) {
2675 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2680 if (USE_SSE2(env_cg)) {
2681 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2682 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2684 set_ia32_ls_mode(res, tgt_mode);
2686 if(get_Conv_strict(node)) {
2687 res = gen_x87_strict_conv(tgt_mode, new_op);
2688 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2691 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2696 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2697 if (USE_SSE2(env_cg)) {
2698 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2700 set_ia32_ls_mode(res, src_mode);
2702 return gen_x87_fp_to_gp(node);
2706 /* we convert from int ... */
2707 if (mode_is_float(tgt_mode)) {
2709 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2710 if (USE_SSE2(env_cg)) {
2711 new_op = be_transform_node(op);
2712 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2714 set_ia32_ls_mode(res, tgt_mode);
2716 res = gen_x87_gp_to_fp(node, src_mode);
2717 if(get_Conv_strict(node)) {
2718 res = gen_x87_strict_conv(tgt_mode, res);
2719 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2720 ia32_get_old_node_name(env_cg, node));
2724 } else if(tgt_mode == mode_b) {
2725 /* mode_b lowering already took care that we only have 0/1 values */
2726 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2727 src_mode, tgt_mode));
2728 return be_transform_node(op);
2731 if (src_bits == tgt_bits) {
2732 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2733 src_mode, tgt_mode));
2734 return be_transform_node(op);
2737 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2745 static int check_immediate_constraint(long val, char immediate_constraint_type)
2747 switch (immediate_constraint_type) {
2751 return val >= 0 && val <= 32;
2753 return val >= 0 && val <= 63;
2755 return val >= -128 && val <= 127;
2757 return val == 0xff || val == 0xffff;
2759 return val >= 0 && val <= 3;
2761 return val >= 0 && val <= 255;
2763 return val >= 0 && val <= 127;
2767 panic("Invalid immediate constraint found");
2771 static ir_node *try_create_Immediate(ir_node *node,
2772 char immediate_constraint_type)
2775 tarval *offset = NULL;
2776 int offset_sign = 0;
2778 ir_entity *symconst_ent = NULL;
2779 int symconst_sign = 0;
2781 ir_node *cnst = NULL;
2782 ir_node *symconst = NULL;
2788 mode = get_irn_mode(node);
2789 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2793 if(is_Minus(node)) {
2795 node = get_Minus_op(node);
2798 if(is_Const(node)) {
2801 offset_sign = minus;
2802 } else if(is_SymConst(node)) {
2805 symconst_sign = minus;
2806 } else if(is_Add(node)) {
2807 ir_node *left = get_Add_left(node);
2808 ir_node *right = get_Add_right(node);
2809 if(is_Const(left) && is_SymConst(right)) {
2812 symconst_sign = minus;
2813 offset_sign = minus;
2814 } else if(is_SymConst(left) && is_Const(right)) {
2817 symconst_sign = minus;
2818 offset_sign = minus;
2820 } else if(is_Sub(node)) {
2821 ir_node *left = get_Sub_left(node);
2822 ir_node *right = get_Sub_right(node);
2823 if(is_Const(left) && is_SymConst(right)) {
2826 symconst_sign = !minus;
2827 offset_sign = minus;
2828 } else if(is_SymConst(left) && is_Const(right)) {
2831 symconst_sign = minus;
2832 offset_sign = !minus;
2839 offset = get_Const_tarval(cnst);
2840 if(tarval_is_long(offset)) {
2841 val = get_tarval_long(offset);
2843 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2848 if(!check_immediate_constraint(val, immediate_constraint_type))
2851 if(symconst != NULL) {
2852 if(immediate_constraint_type != 0) {
2853 /* we need full 32bits for symconsts */
2857 /* unfortunately the assembler/linker doesn't support -symconst */
2861 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2863 symconst_ent = get_SymConst_entity(symconst);
2865 if(cnst == NULL && symconst == NULL)
2868 if(offset_sign && offset != NULL) {
2869 offset = tarval_neg(offset);
2872 irg = current_ir_graph;
2873 dbgi = get_irn_dbg_info(node);
2874 block = get_irg_start_block(irg);
2875 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2876 symconst_sign, val);
2877 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2882 static ir_node *create_immediate_or_transform(ir_node *node,
2883 char immediate_constraint_type)
2885 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2886 if (new_node == NULL) {
2887 new_node = be_transform_node(node);
2892 typedef struct constraint_t constraint_t;
2893 struct constraint_t {
2896 const arch_register_req_t **out_reqs;
2898 const arch_register_req_t *req;
2899 unsigned immediate_possible;
2900 char immediate_type;
2903 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2905 int immediate_possible = 0;
2906 char immediate_type = 0;
2907 unsigned limited = 0;
2908 const arch_register_class_t *cls = NULL;
2909 ir_graph *irg = current_ir_graph;
2910 struct obstack *obst = get_irg_obstack(irg);
2911 arch_register_req_t *req;
2912 unsigned *limited_ptr;
2916 /* TODO: replace all the asserts with nice error messages */
2918 printf("Constraint: %s\n", c);
2928 assert(cls == NULL ||
2929 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2930 cls = &ia32_reg_classes[CLASS_ia32_gp];
2931 limited |= 1 << REG_EAX;
2934 assert(cls == NULL ||
2935 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2936 cls = &ia32_reg_classes[CLASS_ia32_gp];
2937 limited |= 1 << REG_EBX;
2940 assert(cls == NULL ||
2941 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2942 cls = &ia32_reg_classes[CLASS_ia32_gp];
2943 limited |= 1 << REG_ECX;
2946 assert(cls == NULL ||
2947 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2948 cls = &ia32_reg_classes[CLASS_ia32_gp];
2949 limited |= 1 << REG_EDX;
2952 assert(cls == NULL ||
2953 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2954 cls = &ia32_reg_classes[CLASS_ia32_gp];
2955 limited |= 1 << REG_EDI;
2958 assert(cls == NULL ||
2959 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2960 cls = &ia32_reg_classes[CLASS_ia32_gp];
2961 limited |= 1 << REG_ESI;
2964 case 'q': /* q means lower part of the regs only, this makes no
2965 * difference to Q for us (we only assigne whole registers) */
2966 assert(cls == NULL ||
2967 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2968 cls = &ia32_reg_classes[CLASS_ia32_gp];
2969 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2973 assert(cls == NULL ||
2974 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2975 cls = &ia32_reg_classes[CLASS_ia32_gp];
2976 limited |= 1 << REG_EAX | 1 << REG_EDX;
2979 assert(cls == NULL ||
2980 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2981 cls = &ia32_reg_classes[CLASS_ia32_gp];
2982 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2983 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2990 assert(cls == NULL);
2991 cls = &ia32_reg_classes[CLASS_ia32_gp];
2997 /* TODO: mark values so the x87 simulator knows about t and u */
2998 assert(cls == NULL);
2999 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3004 assert(cls == NULL);
3005 /* TODO: check that sse2 is supported */
3006 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3016 assert(!immediate_possible);
3017 immediate_possible = 1;
3018 immediate_type = *c;
3022 assert(!immediate_possible);
3023 immediate_possible = 1;
3027 assert(!immediate_possible && cls == NULL);
3028 immediate_possible = 1;
3029 cls = &ia32_reg_classes[CLASS_ia32_gp];
3042 assert(constraint->is_in && "can only specify same constraint "
3045 sscanf(c, "%d%n", &same_as, &p);
3052 case 'E': /* no float consts yet */
3053 case 'F': /* no float consts yet */
3054 case 's': /* makes no sense on x86 */
3055 case 'X': /* we can't support that in firm */
3059 case '<': /* no autodecrement on x86 */
3060 case '>': /* no autoincrement on x86 */
3061 case 'C': /* sse constant not supported yet */
3062 case 'G': /* 80387 constant not supported yet */
3063 case 'y': /* we don't support mmx registers yet */
3064 case 'Z': /* not available in 32 bit mode */
3065 case 'e': /* not available in 32 bit mode */
3066 assert(0 && "asm constraint not supported");
3069 assert(0 && "unknown asm constraint found");
3076 const arch_register_req_t *other_constr;
3078 assert(cls == NULL && "same as and register constraint not supported");
3079 assert(!immediate_possible && "same as and immediate constraint not "
3081 assert(same_as < constraint->n_outs && "wrong constraint number in "
3082 "same_as constraint");
3084 other_constr = constraint->out_reqs[same_as];
3086 req = obstack_alloc(obst, sizeof(req[0]));
3087 req->cls = other_constr->cls;
3088 req->type = arch_register_req_type_should_be_same;
3089 req->limited = NULL;
3090 req->other_same = pos;
3091 req->other_different = -1;
3093 /* switch constraints. This is because in firm we have same_as
3094 * constraints on the output constraints while in the gcc asm syntax
3095 * they are specified on the input constraints */
3096 constraint->req = other_constr;
3097 constraint->out_reqs[same_as] = req;
3098 constraint->immediate_possible = 0;
3102 if(immediate_possible && cls == NULL) {
3103 cls = &ia32_reg_classes[CLASS_ia32_gp];
3105 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3106 assert(cls != NULL);
3108 if(immediate_possible) {
3109 assert(constraint->is_in
3110 && "imeediates make no sense for output constraints");
3112 /* todo: check types (no float input on 'r' constrained in and such... */
3115 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3116 limited_ptr = (unsigned*) (req+1);
3118 req = obstack_alloc(obst, sizeof(req[0]));
3120 memset(req, 0, sizeof(req[0]));
3123 req->type = arch_register_req_type_limited;
3124 *limited_ptr = limited;
3125 req->limited = limited_ptr;
3127 req->type = arch_register_req_type_normal;
3131 constraint->req = req;
3132 constraint->immediate_possible = immediate_possible;
3133 constraint->immediate_type = immediate_type;
3136 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3143 panic("Clobbers not supported yet");
3147 * generates code for a ASM node
3149 static ir_node *gen_ASM(ir_node *node)
3152 ir_graph *irg = current_ir_graph;
3153 ir_node *block = be_transform_node(get_nodes_block(node));
3154 dbg_info *dbgi = get_irn_dbg_info(node);
3161 ia32_asm_attr_t *attr;
3162 const arch_register_req_t **out_reqs;
3163 const arch_register_req_t **in_reqs;
3164 struct obstack *obst;
3165 constraint_t parsed_constraint;
3167 /* transform inputs */
3168 arity = get_irn_arity(node);
3169 in = alloca(arity * sizeof(in[0]));
3170 memset(in, 0, arity * sizeof(in[0]));
3172 n_outs = get_ASM_n_output_constraints(node);
3173 n_clobbers = get_ASM_n_clobbers(node);
3174 out_arity = n_outs + n_clobbers;
3176 /* construct register constraints */
3177 obst = get_irg_obstack(irg);
3178 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3179 parsed_constraint.out_reqs = out_reqs;
3180 parsed_constraint.n_outs = n_outs;
3181 parsed_constraint.is_in = 0;
3182 for(i = 0; i < out_arity; ++i) {
3186 const ir_asm_constraint *constraint;
3187 constraint = & get_ASM_output_constraints(node) [i];
3188 c = get_id_str(constraint->constraint);
3189 parse_asm_constraint(i, &parsed_constraint, c);
3191 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3192 c = get_id_str(glob_id);
3193 parse_clobber(node, i, &parsed_constraint, c);
3195 out_reqs[i] = parsed_constraint.req;
3198 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3199 parsed_constraint.is_in = 1;
3200 for(i = 0; i < arity; ++i) {
3201 const ir_asm_constraint *constraint;
3205 constraint = & get_ASM_input_constraints(node) [i];
3206 constr_id = constraint->constraint;
3207 c = get_id_str(constr_id);
3208 parse_asm_constraint(i, &parsed_constraint, c);
3209 in_reqs[i] = parsed_constraint.req;
3211 if(parsed_constraint.immediate_possible) {
3212 ir_node *pred = get_irn_n(node, i);
3213 char imm_type = parsed_constraint.immediate_type;
3214 ir_node *immediate = try_create_Immediate(pred, imm_type);
3216 if(immediate != NULL) {
3222 /* transform inputs */
3223 for(i = 0; i < arity; ++i) {
3225 ir_node *transformed;
3230 pred = get_irn_n(node, i);
3231 transformed = be_transform_node(pred);
3232 in[i] = transformed;
3235 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3237 generic_attr = get_irn_generic_attr(res);
3238 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3239 attr->asm_text = get_ASM_text(node);
3240 set_ia32_out_req_all(res, out_reqs);
3241 set_ia32_in_req_all(res, in_reqs);
3243 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3248 /********************************************
3251 * | |__ ___ _ __ ___ __| | ___ ___
3252 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3253 * | |_) | __/ | | | (_) | (_| | __/\__ \
3254 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3256 ********************************************/
3259 * Transforms a FrameAddr into an ia32 Add.
3261 static ir_node *gen_be_FrameAddr(ir_node *node) {
3262 ir_node *block = be_transform_node(get_nodes_block(node));
3263 ir_node *op = be_get_FrameAddr_frame(node);
3264 ir_node *new_op = be_transform_node(op);
3265 ir_graph *irg = current_ir_graph;
3266 dbg_info *dbgi = get_irn_dbg_info(node);
3267 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3270 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3271 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3272 set_ia32_use_frame(res);
3274 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3280 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3282 static ir_node *gen_be_Return(ir_node *node) {
3283 ir_graph *irg = current_ir_graph;
3284 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3285 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3286 ir_entity *ent = get_irg_entity(irg);
3287 ir_type *tp = get_entity_type(ent);
3292 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3293 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3296 int pn_ret_val, pn_ret_mem, arity, i;
3298 assert(ret_val != NULL);
3299 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3300 return be_duplicate_node(node);
3303 res_type = get_method_res_type(tp, 0);
3305 if (! is_Primitive_type(res_type)) {
3306 return be_duplicate_node(node);
3309 mode = get_type_mode(res_type);
3310 if (! mode_is_float(mode)) {
3311 return be_duplicate_node(node);
3314 assert(get_method_n_ress(tp) == 1);
3316 pn_ret_val = get_Proj_proj(ret_val);
3317 pn_ret_mem = get_Proj_proj(ret_mem);
3319 /* get the Barrier */
3320 barrier = get_Proj_pred(ret_val);
3322 /* get result input of the Barrier */
3323 ret_val = get_irn_n(barrier, pn_ret_val);
3324 new_ret_val = be_transform_node(ret_val);
3326 /* get memory input of the Barrier */
3327 ret_mem = get_irn_n(barrier, pn_ret_mem);
3328 new_ret_mem = be_transform_node(ret_mem);
3330 frame = get_irg_frame(irg);
3332 dbgi = get_irn_dbg_info(barrier);
3333 block = be_transform_node(get_nodes_block(barrier));
3335 noreg = ia32_new_NoReg_gp(env_cg);
3337 /* store xmm0 onto stack */
3338 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3339 new_ret_mem, new_ret_val);
3340 set_ia32_ls_mode(sse_store, mode);
3341 set_ia32_op_type(sse_store, ia32_AddrModeD);
3342 set_ia32_use_frame(sse_store);
3344 /* load into x87 register */
3345 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3346 set_ia32_op_type(fld, ia32_AddrModeS);
3347 set_ia32_use_frame(fld);
3349 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3350 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3352 /* create a new barrier */
3353 arity = get_irn_arity(barrier);
3354 in = alloca(arity * sizeof(in[0]));
3355 for (i = 0; i < arity; ++i) {
3358 if (i == pn_ret_val) {
3360 } else if (i == pn_ret_mem) {
3363 ir_node *in = get_irn_n(barrier, i);
3364 new_in = be_transform_node(in);
3369 new_barrier = new_ir_node(dbgi, irg, block,
3370 get_irn_op(barrier), get_irn_mode(barrier),
3372 copy_node_attr(barrier, new_barrier);
3373 be_duplicate_deps(barrier, new_barrier);
3374 be_set_transformed_node(barrier, new_barrier);
3375 mark_irn_visited(barrier);
3377 /* transform normally */
3378 return be_duplicate_node(node);
3382 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3384 static ir_node *gen_be_AddSP(ir_node *node) {
3385 ir_node *block = be_transform_node(get_nodes_block(node));
3386 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3388 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3389 ir_node *new_sp = be_transform_node(sp);
3390 ir_graph *irg = current_ir_graph;
3391 dbg_info *dbgi = get_irn_dbg_info(node);
3392 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3393 ir_node *nomem = new_NoMem();
3396 new_sz = create_immediate_or_transform(sz, 0);
3398 /* ia32 stack grows in reverse direction, make a SubSP */
3399 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3401 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3407 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3409 static ir_node *gen_be_SubSP(ir_node *node) {
3410 ir_node *block = be_transform_node(get_nodes_block(node));
3411 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3413 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3414 ir_node *new_sp = be_transform_node(sp);
3415 ir_graph *irg = current_ir_graph;
3416 dbg_info *dbgi = get_irn_dbg_info(node);
3417 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3418 ir_node *nomem = new_NoMem();
3421 new_sz = create_immediate_or_transform(sz, 0);
3423 /* ia32 stack grows in reverse direction, make an AddSP */
3424 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3426 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3432 * This function just sets the register for the Unknown node
3433 * as this is not done during register allocation because Unknown
3434 * is an "ignore" node.
3436 static ir_node *gen_Unknown(ir_node *node) {
3437 ir_mode *mode = get_irn_mode(node);
3439 if (mode_is_float(mode)) {
3440 if (USE_SSE2(env_cg)) {
3441 return ia32_new_Unknown_xmm(env_cg);
3443 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3444 ir_graph *irg = current_ir_graph;
3445 dbg_info *dbgi = get_irn_dbg_info(node);
3446 ir_node *block = get_irg_start_block(irg);
3447 return new_rd_ia32_vfldz(dbgi, irg, block);
3449 } else if (mode_needs_gp_reg(mode)) {
3450 return ia32_new_Unknown_gp(env_cg);
3452 assert(0 && "unsupported Unknown-Mode");
3459 * Change some phi modes
3461 static ir_node *gen_Phi(ir_node *node) {
3462 ir_node *block = be_transform_node(get_nodes_block(node));
3463 ir_graph *irg = current_ir_graph;
3464 dbg_info *dbgi = get_irn_dbg_info(node);
3465 ir_mode *mode = get_irn_mode(node);
3468 if(mode_needs_gp_reg(mode)) {
3469 /* we shouldn't have any 64bit stuff around anymore */
3470 assert(get_mode_size_bits(mode) <= 32);
3471 /* all integer operations are on 32bit registers now */
3473 } else if(mode_is_float(mode)) {
3474 if (USE_SSE2(env_cg)) {
3481 /* phi nodes allow loops, so we use the old arguments for now
3482 * and fix this later */
3483 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3484 get_irn_in(node) + 1);
3485 copy_node_attr(node, phi);
3486 be_duplicate_deps(node, phi);
3488 be_set_transformed_node(node, phi);
3489 be_enqueue_preds(node);
3497 static ir_node *gen_IJmp(ir_node *node) {
3498 /* TODO: support AM */
3499 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3503 /**********************************************************************
3506 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3507 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3508 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3509 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3511 **********************************************************************/
3513 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3515 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3518 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3519 ir_node *val, ir_node *mem);
3522 * Transforms a lowered Load into a "real" one.
3524 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3526 ir_node *block = be_transform_node(get_nodes_block(node));
3527 ir_node *ptr = get_irn_n(node, 0);
3528 ir_node *new_ptr = be_transform_node(ptr);
3529 ir_node *mem = get_irn_n(node, 1);
3530 ir_node *new_mem = be_transform_node(mem);
3531 ir_graph *irg = current_ir_graph;
3532 dbg_info *dbgi = get_irn_dbg_info(node);
3533 ir_mode *mode = get_ia32_ls_mode(node);
3534 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3537 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3539 set_ia32_op_type(new_op, ia32_AddrModeS);
3540 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3541 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3542 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3543 if (is_ia32_am_sc_sign(node))
3544 set_ia32_am_sc_sign(new_op);
3545 set_ia32_ls_mode(new_op, mode);
3546 if (is_ia32_use_frame(node)) {
3547 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3548 set_ia32_use_frame(new_op);
3551 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3557 * Transforms a lowered Store into a "real" one.
3559 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3561 ir_node *block = be_transform_node(get_nodes_block(node));
3562 ir_node *ptr = get_irn_n(node, 0);
3563 ir_node *new_ptr = be_transform_node(ptr);
3564 ir_node *val = get_irn_n(node, 1);
3565 ir_node *new_val = be_transform_node(val);
3566 ir_node *mem = get_irn_n(node, 2);
3567 ir_node *new_mem = be_transform_node(mem);
3568 ir_graph *irg = current_ir_graph;
3569 dbg_info *dbgi = get_irn_dbg_info(node);
3570 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3571 ir_mode *mode = get_ia32_ls_mode(node);
3575 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3577 am_offs = get_ia32_am_offs_int(node);
3578 add_ia32_am_offs_int(new_op, am_offs);
3580 set_ia32_op_type(new_op, ia32_AddrModeD);
3581 set_ia32_ls_mode(new_op, mode);
3582 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3583 set_ia32_use_frame(new_op);
3585 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3592 * Transforms an ia32_l_XXX into a "real" XXX node
3594 * @param node The node to transform
3595 * @return the created ia32 XXX node
3597 #define GEN_LOWERED_OP(op) \
3598 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3599 return gen_binop(node, get_binop_left(node), \
3600 get_binop_right(node), new_rd_ia32_##op,0); \
3603 #define GEN_LOWERED_x87_OP(op) \
3604 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3606 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3607 get_binop_right(node), new_rd_ia32_##op); \
3611 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3612 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3613 return gen_shift_binop(node, get_irn_n(node, 0), \
3614 get_irn_n(node, 1), new_rd_ia32_##op); \
3617 GEN_LOWERED_x87_OP(vfprem)
3618 GEN_LOWERED_x87_OP(vfmul)
3619 GEN_LOWERED_x87_OP(vfsub)
3620 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3621 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3622 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3623 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3625 static ir_node *gen_ia32_l_Add(ir_node *node) {
3626 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3627 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3628 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3630 if(is_Proj(lowered)) {
3631 lowered = get_Proj_pred(lowered);
3633 assert(is_ia32_Add(lowered));
3634 set_irn_mode(lowered, mode_T);
3640 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3641 ir_node *src_block = get_nodes_block(node);
3642 ir_node *block = be_transform_node(src_block);
3643 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3644 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3645 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3646 ir_node *new_flags = be_transform_node(flags);
3647 ir_graph *irg = current_ir_graph;
3648 dbg_info *dbgi = get_irn_dbg_info(node);
3650 ia32_address_mode_t am;
3651 ia32_address_t *addr = &am.addr;
3653 match_arguments(&am, src_block, op1, op2, match_commutative);
3655 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3656 addr->mem, am.new_op1, am.new_op2, new_flags);
3657 set_am_attributes(new_node, &am);
3658 /* we can't use source address mode anymore when using immediates */
3659 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3660 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3663 new_node = fix_mem_proj(new_node, &am);
3669 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3671 * @param node The node to transform
3672 * @return the created ia32 Neg node
3674 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3675 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3679 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3681 * @param node The node to transform
3682 * @return the created ia32 vfild node
3684 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3685 return gen_lowered_Load(node, new_rd_ia32_vfild);
3689 * Transforms an ia32_l_Load into a "real" ia32_Load node
3691 * @param node The node to transform
3692 * @return the created ia32 Load node
3694 static ir_node *gen_ia32_l_Load(ir_node *node) {
3695 return gen_lowered_Load(node, new_rd_ia32_Load);
3699 * Transforms an ia32_l_Store into a "real" ia32_Store node
3701 * @param node The node to transform
3702 * @return the created ia32 Store node
3704 static ir_node *gen_ia32_l_Store(ir_node *node) {
3705 return gen_lowered_Store(node, new_rd_ia32_Store);
3709 * Transforms a l_vfist into a "real" vfist node.
3711 * @param node The node to transform
3712 * @return the created ia32 vfist node
3714 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3715 ir_node *block = be_transform_node(get_nodes_block(node));
3716 ir_node *ptr = get_irn_n(node, 0);
3717 ir_node *new_ptr = be_transform_node(ptr);
3718 ir_node *val = get_irn_n(node, 1);
3719 ir_node *new_val = be_transform_node(val);
3720 ir_node *mem = get_irn_n(node, 2);
3721 ir_node *new_mem = be_transform_node(mem);
3722 ir_graph *irg = current_ir_graph;
3723 dbg_info *dbgi = get_irn_dbg_info(node);
3724 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3725 ir_mode *mode = get_ia32_ls_mode(node);
3726 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3730 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3731 new_val, trunc_mode);
3733 am_offs = get_ia32_am_offs_int(node);
3734 add_ia32_am_offs_int(new_op, am_offs);
3736 set_ia32_op_type(new_op, ia32_AddrModeD);
3737 set_ia32_ls_mode(new_op, mode);
3738 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3739 set_ia32_use_frame(new_op);
3741 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3747 * Transforms a l_vfdiv into a "real" vfdiv node.
3749 * @param env The transformation environment
3750 * @return the created ia32 vfdiv node
3752 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3753 ir_node *block = be_transform_node(get_nodes_block(node));
3754 ir_node *left = get_binop_left(node);
3755 ir_node *new_left = be_transform_node(left);
3756 ir_node *right = get_binop_right(node);
3757 ir_node *new_right = be_transform_node(right);
3758 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3759 ir_graph *irg = current_ir_graph;
3760 dbg_info *dbgi = get_irn_dbg_info(node);
3761 ir_node *fpcw = get_fpcw();
3764 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3765 new_left, new_right, fpcw);
3766 clear_ia32_commutative(vfdiv);
3768 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3774 * Transforms a l_MulS into a "real" MulS node.
3776 * @param env The transformation environment
3777 * @return the created ia32 Mul node
3779 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3780 ir_node *block = be_transform_node(get_nodes_block(node));
3781 ir_node *left = get_binop_left(node);
3782 ir_node *new_left = be_transform_node(left);
3783 ir_node *right = get_binop_right(node);
3784 ir_node *new_right = be_transform_node(right);
3785 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3786 ir_graph *irg = current_ir_graph;
3787 dbg_info *dbgi = get_irn_dbg_info(node);
3789 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3790 /* and then skip the result Proj, because all needed Projs are already there. */
3791 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3792 new_left, new_right);
3793 clear_ia32_commutative(muls);
3795 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3801 * Transforms a l_IMulS into a "real" IMul1OPS node.
3803 * @param env The transformation environment
3804 * @return the created ia32 IMul1OP node
3806 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3807 ir_node *block = be_transform_node(get_nodes_block(node));
3808 ir_node *left = get_binop_left(node);
3809 ir_node *new_left = be_transform_node(left);
3810 ir_node *right = get_binop_right(node);
3811 ir_node *new_right = be_transform_node(right);
3812 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3813 ir_graph *irg = current_ir_graph;
3814 dbg_info *dbgi = get_irn_dbg_info(node);
3816 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3817 /* and then skip the result Proj, because all needed Projs are already there. */
3818 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3819 new_NoMem(), new_left, new_right);
3820 clear_ia32_commutative(muls);
3822 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3827 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3829 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3830 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3831 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3832 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3833 ir_node *block = be_transform_node(get_nodes_block(node));
3834 dbg_info *dbgi = get_irn_dbg_info(node);
3835 ir_graph *irg = current_ir_graph;
3836 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3837 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3842 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3843 * op1 - target to be shifted
3844 * op2 - contains bits to be shifted into target
3846 * Only op3 can be an immediate.
3848 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3849 ir_node *op2, ir_node *count)
3851 ir_node *block = be_transform_node(get_nodes_block(node));
3852 ir_node *new_op = NULL;
3853 ir_graph *irg = current_ir_graph;
3854 dbg_info *dbgi = get_irn_dbg_info(node);
3855 ir_node *new_op1 = be_transform_node(op1);
3856 ir_node *new_op2 = be_transform_node(op2);
3857 ir_node *new_count = create_immediate_or_transform(count, 'I');
3859 /* TODO proper AM support */
3861 if (is_ia32_l_ShlD(node))
3862 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3864 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3866 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3871 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3872 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3873 get_irn_n(node, 1), get_irn_n(node, 2));
3876 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3877 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3878 get_irn_n(node, 1), get_irn_n(node, 2));
3882 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3884 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3885 ir_node *block = be_transform_node(get_nodes_block(node));
3886 ir_node *val = get_irn_n(node, 1);
3887 ir_node *new_val = be_transform_node(val);
3888 ia32_code_gen_t *cg = env_cg;
3889 ir_node *res = NULL;
3890 ir_graph *irg = current_ir_graph;
3892 ir_node *noreg, *new_ptr, *new_mem;
3899 mem = get_irn_n(node, 2);
3900 new_mem = be_transform_node(mem);
3901 ptr = get_irn_n(node, 0);
3902 new_ptr = be_transform_node(ptr);
3903 noreg = ia32_new_NoReg_gp(cg);
3904 dbgi = get_irn_dbg_info(node);
3906 /* Store x87 -> MEM */
3907 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3908 get_ia32_ls_mode(node));
3909 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3910 set_ia32_use_frame(res);
3911 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3912 set_ia32_op_type(res, ia32_AddrModeD);
3914 /* Load MEM -> SSE */
3915 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3916 get_ia32_ls_mode(node));
3917 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3918 set_ia32_use_frame(res);
3919 set_ia32_op_type(res, ia32_AddrModeS);
3920 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3926 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3928 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3929 ir_node *block = be_transform_node(get_nodes_block(node));
3930 ir_node *val = get_irn_n(node, 1);
3931 ir_node *new_val = be_transform_node(val);
3932 ia32_code_gen_t *cg = env_cg;
3933 ir_graph *irg = current_ir_graph;
3934 ir_node *res = NULL;
3935 ir_entity *fent = get_ia32_frame_ent(node);
3936 ir_mode *lsmode = get_ia32_ls_mode(node);
3938 ir_node *noreg, *new_ptr, *new_mem;
3942 if (! USE_SSE2(cg)) {
3943 /* SSE unit is not used -> skip this node. */
3947 ptr = get_irn_n(node, 0);
3948 new_ptr = be_transform_node(ptr);
3949 mem = get_irn_n(node, 2);
3950 new_mem = be_transform_node(mem);
3951 noreg = ia32_new_NoReg_gp(cg);
3952 dbgi = get_irn_dbg_info(node);
3954 /* Store SSE -> MEM */
3955 if (is_ia32_xLoad(skip_Proj(new_val))) {
3956 ir_node *ld = skip_Proj(new_val);
3958 /* we can vfld the value directly into the fpu */
3959 fent = get_ia32_frame_ent(ld);
3960 ptr = get_irn_n(ld, 0);
3961 offs = get_ia32_am_offs_int(ld);
3963 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3965 set_ia32_frame_ent(res, fent);
3966 set_ia32_use_frame(res);
3967 set_ia32_ls_mode(res, lsmode);
3968 set_ia32_op_type(res, ia32_AddrModeD);
3972 /* Load MEM -> x87 */
3973 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3974 set_ia32_frame_ent(res, fent);
3975 set_ia32_use_frame(res);
3976 add_ia32_am_offs_int(res, offs);
3977 set_ia32_op_type(res, ia32_AddrModeS);
3978 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3983 /*********************************************************
3986 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3987 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3988 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3989 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3991 *********************************************************/
3994 * the BAD transformer.
3996 static ir_node *bad_transform(ir_node *node) {
3997 panic("No transform function for %+F available.\n", node);
4002 * Transform the Projs of an AddSP.
4004 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4005 ir_node *block = be_transform_node(get_nodes_block(node));
4006 ir_node *pred = get_Proj_pred(node);
4007 ir_node *new_pred = be_transform_node(pred);
4008 ir_graph *irg = current_ir_graph;
4009 dbg_info *dbgi = get_irn_dbg_info(node);
4010 long proj = get_Proj_proj(node);
4012 if (proj == pn_be_AddSP_sp) {
4013 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4014 pn_ia32_SubSP_stack);
4015 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4017 } else if(proj == pn_be_AddSP_res) {
4018 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4019 pn_ia32_SubSP_addr);
4020 } else if (proj == pn_be_AddSP_M) {
4021 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4025 return new_rd_Unknown(irg, get_irn_mode(node));
4029 * Transform the Projs of a SubSP.
4031 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4032 ir_node *block = be_transform_node(get_nodes_block(node));
4033 ir_node *pred = get_Proj_pred(node);
4034 ir_node *new_pred = be_transform_node(pred);
4035 ir_graph *irg = current_ir_graph;
4036 dbg_info *dbgi = get_irn_dbg_info(node);
4037 long proj = get_Proj_proj(node);
4039 if (proj == pn_be_SubSP_sp) {
4040 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4041 pn_ia32_AddSP_stack);
4042 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4044 } else if (proj == pn_be_SubSP_M) {
4045 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4049 return new_rd_Unknown(irg, get_irn_mode(node));
4053 * Transform and renumber the Projs from a Load.
4055 static ir_node *gen_Proj_Load(ir_node *node) {
4057 ir_node *block = be_transform_node(get_nodes_block(node));
4058 ir_node *pred = get_Proj_pred(node);
4059 ir_graph *irg = current_ir_graph;
4060 dbg_info *dbgi = get_irn_dbg_info(node);
4061 long proj = get_Proj_proj(node);
4064 /* loads might be part of source address mode matches, so we don't
4065 transform the ProjMs yet (with the exception of loads whose result is
4068 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4071 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4073 /* this is needed, because sometimes we have loops that are only
4074 reachable through the ProjM */
4075 be_enqueue_preds(node);
4076 /* do it in 2 steps, to silence firm verifier */
4077 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4078 set_Proj_proj(res, pn_ia32_Load_M);
4082 /* renumber the proj */
4083 new_pred = be_transform_node(pred);
4084 if (is_ia32_Load(new_pred)) {
4085 if (proj == pn_Load_res) {
4086 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4088 } else if (proj == pn_Load_M) {
4089 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4092 } else if(is_ia32_Conv_I2I(new_pred)) {
4093 set_irn_mode(new_pred, mode_T);
4094 if (proj == pn_Load_res) {
4095 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4096 } else if (proj == pn_Load_M) {
4097 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4099 } else if (is_ia32_xLoad(new_pred)) {
4100 if (proj == pn_Load_res) {
4101 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4103 } else if (proj == pn_Load_M) {
4104 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4107 } else if (is_ia32_vfld(new_pred)) {
4108 if (proj == pn_Load_res) {
4109 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4111 } else if (proj == pn_Load_M) {
4112 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4116 /* can happen for ProJMs when source address mode happened for the
4119 /* however it should not be the result proj, as that would mean the
4120 load had multiple users and should not have been used for
4122 if(proj != pn_Load_M) {
4123 panic("internal error: transformed node not a Load");
4125 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4129 return new_rd_Unknown(irg, get_irn_mode(node));
4133 * Transform and renumber the Projs from a DivMod like instruction.
4135 static ir_node *gen_Proj_DivMod(ir_node *node) {
4136 ir_node *block = be_transform_node(get_nodes_block(node));
4137 ir_node *pred = get_Proj_pred(node);
4138 ir_node *new_pred = be_transform_node(pred);
4139 ir_graph *irg = current_ir_graph;
4140 dbg_info *dbgi = get_irn_dbg_info(node);
4141 ir_mode *mode = get_irn_mode(node);
4142 long proj = get_Proj_proj(node);
4144 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4146 switch (get_irn_opcode(pred)) {
4150 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4152 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4160 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4162 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4170 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4171 case pn_DivMod_res_div:
4172 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4173 case pn_DivMod_res_mod:
4174 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4184 return new_rd_Unknown(irg, mode);
4188 * Transform and renumber the Projs from a CopyB.
4190 static ir_node *gen_Proj_CopyB(ir_node *node) {
4191 ir_node *block = be_transform_node(get_nodes_block(node));
4192 ir_node *pred = get_Proj_pred(node);
4193 ir_node *new_pred = be_transform_node(pred);
4194 ir_graph *irg = current_ir_graph;
4195 dbg_info *dbgi = get_irn_dbg_info(node);
4196 ir_mode *mode = get_irn_mode(node);
4197 long proj = get_Proj_proj(node);
4200 case pn_CopyB_M_regular:
4201 if (is_ia32_CopyB_i(new_pred)) {
4202 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4203 } else if (is_ia32_CopyB(new_pred)) {
4204 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4212 return new_rd_Unknown(irg, mode);
4216 * Transform and renumber the Projs from a vfdiv.
4218 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4219 ir_node *block = be_transform_node(get_nodes_block(node));
4220 ir_node *pred = get_Proj_pred(node);
4221 ir_node *new_pred = be_transform_node(pred);
4222 ir_graph *irg = current_ir_graph;
4223 dbg_info *dbgi = get_irn_dbg_info(node);
4224 ir_mode *mode = get_irn_mode(node);
4225 long proj = get_Proj_proj(node);
4228 case pn_ia32_l_vfdiv_M:
4229 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4230 case pn_ia32_l_vfdiv_res:
4231 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4236 return new_rd_Unknown(irg, mode);
4240 * Transform and renumber the Projs from a Quot.
4242 static ir_node *gen_Proj_Quot(ir_node *node) {
4243 ir_node *block = be_transform_node(get_nodes_block(node));
4244 ir_node *pred = get_Proj_pred(node);
4245 ir_node *new_pred = be_transform_node(pred);
4246 ir_graph *irg = current_ir_graph;
4247 dbg_info *dbgi = get_irn_dbg_info(node);
4248 ir_mode *mode = get_irn_mode(node);
4249 long proj = get_Proj_proj(node);
4253 if (is_ia32_xDiv(new_pred)) {
4254 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4255 } else if (is_ia32_vfdiv(new_pred)) {
4256 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4260 if (is_ia32_xDiv(new_pred)) {
4261 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4262 } else if (is_ia32_vfdiv(new_pred)) {
4263 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4271 return new_rd_Unknown(irg, mode);
4275 * Transform the Thread Local Storage Proj.
4277 static ir_node *gen_Proj_tls(ir_node *node) {
4278 ir_node *block = be_transform_node(get_nodes_block(node));
4279 ir_graph *irg = current_ir_graph;
4280 dbg_info *dbgi = NULL;
4281 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4286 static ir_node *gen_be_Call(ir_node *node) {
4287 ir_node *res = be_duplicate_node(node);
4288 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4293 static ir_node *gen_be_IncSP(ir_node *node) {
4294 ir_node *res = be_duplicate_node(node);
4295 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4301 * Transform the Projs from a be_Call.
4303 static ir_node *gen_Proj_be_Call(ir_node *node) {
4304 ir_node *block = be_transform_node(get_nodes_block(node));
4305 ir_node *call = get_Proj_pred(node);
4306 ir_node *new_call = be_transform_node(call);
4307 ir_graph *irg = current_ir_graph;
4308 dbg_info *dbgi = get_irn_dbg_info(node);
4309 ir_type *method_type = be_Call_get_type(call);
4310 int n_res = get_method_n_ress(method_type);
4311 long proj = get_Proj_proj(node);
4312 ir_mode *mode = get_irn_mode(node);
4314 const arch_register_class_t *cls;
4316 /* The following is kinda tricky: If we're using SSE, then we have to
4317 * move the result value of the call in floating point registers to an
4318 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4319 * after the call, we have to make sure to correctly make the
4320 * MemProj and the result Proj use these 2 nodes
4322 if (proj == pn_be_Call_M_regular) {
4323 // get new node for result, are we doing the sse load/store hack?
4324 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4325 ir_node *call_res_new;
4326 ir_node *call_res_pred = NULL;
4328 if (call_res != NULL) {
4329 call_res_new = be_transform_node(call_res);
4330 call_res_pred = get_Proj_pred(call_res_new);
4333 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4334 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4335 pn_be_Call_M_regular);
4337 assert(is_ia32_xLoad(call_res_pred));
4338 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4342 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4343 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4344 && USE_SSE2(env_cg)) {
4346 ir_node *frame = get_irg_frame(irg);
4347 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4349 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4352 /* in case there is no memory output: create one to serialize the copy
4354 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4355 pn_be_Call_M_regular);
4356 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4357 pn_be_Call_first_res);
4359 /* store st(0) onto stack */
4360 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4362 set_ia32_op_type(fstp, ia32_AddrModeD);
4363 set_ia32_use_frame(fstp);
4365 /* load into SSE register */
4366 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4368 set_ia32_op_type(sse_load, ia32_AddrModeS);
4369 set_ia32_use_frame(sse_load);
4371 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4377 /* transform call modes */
4378 if (mode_is_data(mode)) {
4379 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4383 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4387 * Transform the Projs from a Cmp.
4389 static ir_node *gen_Proj_Cmp(ir_node *node)
4391 /* normally Cmps are processed when looking at Cond nodes, but this case
4392 * can happen in complicated Psi conditions */
4393 dbg_info *dbgi = get_irn_dbg_info(node);
4394 ir_node *block = get_nodes_block(node);
4395 ir_node *new_block = be_transform_node(block);
4396 ir_node *cmp = get_Proj_pred(node);
4397 ir_node *new_cmp = be_transform_node(cmp);
4398 long pnc = get_Proj_proj(node);
4401 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4407 * Transform and potentially renumber Proj nodes.
4409 static ir_node *gen_Proj(ir_node *node) {
4410 ir_graph *irg = current_ir_graph;
4411 dbg_info *dbgi = get_irn_dbg_info(node);
4412 ir_node *pred = get_Proj_pred(node);
4413 long proj = get_Proj_proj(node);
4415 if (is_Store(pred)) {
4416 if (proj == pn_Store_M) {
4417 return be_transform_node(pred);
4420 return new_r_Bad(irg);
4422 } else if (is_Load(pred)) {
4423 return gen_Proj_Load(node);
4424 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4425 return gen_Proj_DivMod(node);
4426 } else if (is_CopyB(pred)) {
4427 return gen_Proj_CopyB(node);
4428 } else if (is_Quot(pred)) {
4429 return gen_Proj_Quot(node);
4430 } else if (is_ia32_l_vfdiv(pred)) {
4431 return gen_Proj_l_vfdiv(node);
4432 } else if (be_is_SubSP(pred)) {
4433 return gen_Proj_be_SubSP(node);
4434 } else if (be_is_AddSP(pred)) {
4435 return gen_Proj_be_AddSP(node);
4436 } else if (be_is_Call(pred)) {
4437 return gen_Proj_be_Call(node);
4438 } else if (is_Cmp(pred)) {
4439 return gen_Proj_Cmp(node);
4440 } else if (get_irn_op(pred) == op_Start) {
4441 if (proj == pn_Start_X_initial_exec) {
4442 ir_node *block = get_nodes_block(pred);
4445 /* we exchange the ProjX with a jump */
4446 block = be_transform_node(block);
4447 jump = new_rd_Jmp(dbgi, irg, block);
4450 if (node == be_get_old_anchor(anchor_tls)) {
4451 return gen_Proj_tls(node);
4454 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4458 ir_node *new_pred = be_transform_node(pred);
4459 ir_node *block = be_transform_node(get_nodes_block(node));
4460 ir_mode *mode = get_irn_mode(node);
4461 if (mode_needs_gp_reg(mode)) {
4462 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4463 get_Proj_proj(node));
4464 #ifdef DEBUG_libfirm
4465 new_proj->node_nr = node->node_nr;
4471 return be_duplicate_node(node);
4475 * Enters all transform functions into the generic pointer
4477 static void register_transformers(void)
4481 /* first clear the generic function pointer for all ops */
4482 clear_irp_opcodes_generic_func();
4484 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4485 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4523 /* transform ops from intrinsic lowering */
4544 GEN(ia32_l_X87toSSE);
4545 GEN(ia32_l_SSEtoX87);
4551 /* we should never see these nodes */
4566 /* handle generic backend nodes */
4575 op_Mulh = get_op_Mulh();
4584 * Pre-transform all unknown and noreg nodes.
4586 static void ia32_pretransform_node(void *arch_cg) {
4587 ia32_code_gen_t *cg = arch_cg;
4589 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4590 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4591 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4592 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4593 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4594 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4599 * Walker, checks if all ia32 nodes producing more than one result have
4600 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4602 static void add_missing_keep_walker(ir_node *node, void *data)
4605 unsigned found_projs = 0;
4606 const ir_edge_t *edge;
4607 ir_mode *mode = get_irn_mode(node);
4612 if(!is_ia32_irn(node))
4615 n_outs = get_ia32_n_res(node);
4618 if(is_ia32_SwitchJmp(node))
4621 assert(n_outs < (int) sizeof(unsigned) * 8);
4622 foreach_out_edge(node, edge) {
4623 ir_node *proj = get_edge_src_irn(edge);
4624 int pn = get_Proj_proj(proj);
4626 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4627 found_projs |= 1 << pn;
4631 /* are keeps missing? */
4633 for(i = 0; i < n_outs; ++i) {
4636 const arch_register_req_t *req;
4637 const arch_register_class_t *class;
4639 if(found_projs & (1 << i)) {
4643 req = get_ia32_out_req(node, i);
4648 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4652 block = get_nodes_block(node);
4653 in[0] = new_r_Proj(current_ir_graph, block, node,
4654 arch_register_class_mode(class), i);
4655 if(last_keep != NULL) {
4656 be_Keep_add_node(last_keep, class, in[0]);
4658 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4659 if(sched_is_scheduled(node)) {
4660 sched_add_after(node, last_keep);
4667 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4670 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4672 ir_graph *irg = be_get_birg_irg(cg->birg);
4673 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4676 /* do the transformation */
4677 void ia32_transform_graph(ia32_code_gen_t *cg) {
4678 ir_graph *irg = cg->irg;
4680 register_transformers();
4682 initial_fpcw = NULL;
4684 heights = heights_new(irg);
4685 calculate_non_address_mode_nodes(irg);
4687 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4689 free_non_address_mode_nodes();
4690 heights_free(heights);
4694 void ia32_init_transform(void)
4696 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");