2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
42 #include "bearch_ia32_t.h"
43 #include "ia32_nodes_attr.h"
44 #include "ia32_transform.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "ia32_util.h"
51 #include "gen_ia32_regalloc_if.h"
53 #define SFP_SIGN "0x80000000"
54 #define DFP_SIGN "0x8000000000000000"
55 #define SFP_ABS "0x7FFFFFFF"
56 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
58 #define TP_SFP_SIGN "ia32_sfp_sign"
59 #define TP_DFP_SIGN "ia32_dfp_sign"
60 #define TP_SFP_ABS "ia32_sfp_abs"
61 #define TP_DFP_ABS "ia32_dfp_abs"
63 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
64 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
65 #define ENT_SFP_ABS "IA32_SFP_ABS"
66 #define ENT_DFP_ABS "IA32_DFP_ABS"
68 typedef struct ia32_transform_env_t {
69 ir_graph *irg; /**< The irg, the node should be created in */
70 ia32_code_gen_t *cg; /**< The code generator */
71 int visited; /**< visited count that indicates whether a
72 node is already transformed */
73 pdeq *worklist; /**< worklist of nodes that still need to be
75 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
76 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
77 } ia32_transform_env_t;
79 extern ir_op *get_op_Mulh(void);
81 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
82 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
83 ir_node *op2, ir_node *mem);
85 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
86 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
89 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
91 /****************************************************************************************************
93 * | | | | / _| | | (_)
94 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
95 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
96 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
97 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
99 ****************************************************************************************************/
101 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
102 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
103 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
106 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
108 set_irn_link(old_node, new_node);
111 static INLINE ir_node *get_new_node(ir_node *old_node)
113 assert(irn_visited(old_node));
114 return (ir_node*) get_irn_link(old_node);
118 * Returns 1 if irn is a Const representing 0, 0 otherwise
120 static INLINE int is_ia32_Const_0(ir_node *irn) {
121 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
122 && tarval_is_null(get_ia32_Immop_tarval(irn));
126 * Returns 1 if irn is a Const representing 1, 0 otherwise
128 static INLINE int is_ia32_Const_1(ir_node *irn) {
129 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
130 && tarval_is_one(get_ia32_Immop_tarval(irn));
134 * Collects all Projs of a node into the node array. Index is the projnum.
135 * BEWARE: The caller has to assure the appropriate array size!
137 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
138 const ir_edge_t *edge;
139 assert(get_irn_mode(irn) == mode_T && "need mode_T");
141 memset(projs, 0, size * sizeof(projs[0]));
143 foreach_out_edge(irn, edge) {
144 ir_node *proj = get_edge_src_irn(edge);
145 int proj_proj = get_Proj_proj(proj);
146 assert(proj_proj < size);
147 projs[proj_proj] = proj;
152 * Renumbers the proj having pn_old in the array tp pn_new
153 * and removes the proj from the array.
155 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
156 fprintf(stderr, "Warning: renumber_Proj used!\n");
158 set_Proj_proj(projs[pn_old], pn_new);
159 projs[pn_old] = NULL;
164 * creates a unique ident by adding a number to a tag
166 * @param tag the tag string, must contain a %d if a number
169 static ident *unique_id(const char *tag)
171 static unsigned id = 0;
174 snprintf(str, sizeof(str), tag, ++id);
175 return new_id_from_str(str);
179 * Get a primitive type for a mode.
181 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
183 pmap_entry *e = pmap_find(types, mode);
188 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
189 res = new_type_primitive(new_id_from_str(buf), mode);
190 pmap_insert(types, mode, res);
198 * Get an entity that is initialized with a tarval
200 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
202 tarval *tv = get_Const_tarval(cnst);
203 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
208 ir_mode *mode = get_irn_mode(cnst);
209 ir_type *tp = get_Const_type(cnst);
210 if (tp == firm_unknown_type)
211 tp = get_prim_type(cg->isa->types, mode);
213 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
215 set_entity_ld_ident(res, get_entity_ident(res));
216 set_entity_visibility(res, visibility_local);
217 set_entity_variability(res, variability_constant);
218 set_entity_allocation(res, allocation_static);
220 /* we create a new entity here: It's initialization must resist on the
222 rem = current_ir_graph;
223 current_ir_graph = get_const_code_irg();
224 set_atomic_ent_value(res, new_Const_type(tv, tp));
225 current_ir_graph = rem;
227 pmap_insert(cg->isa->tv_ent, tv, res);
235 * Transforms a Const.
237 * @param mod the debug module
238 * @param block the block the new node should belong to
239 * @param node the ir Const node
240 * @param mode mode of the Const
241 * @return the created ia32 Const node
243 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
244 ir_graph *irg = env->irg;
245 dbg_info *dbg = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
247 ir_node *block = transform_node(env, get_nodes_block(node));
249 if (mode_is_float(mode)) {
252 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
253 ir_node *nomem = new_NoMem();
257 if (! USE_SSE2(env->cg)) {
258 cnst_classify_t clss = classify_Const(node);
260 if (clss == CNST_NULL) {
261 load = new_rd_ia32_vfldz(dbg, irg, block);
263 } else if (clss == CNST_ONE) {
264 load = new_rd_ia32_vfld1(dbg, irg, block);
267 floatent = get_entity_for_tv(env->cg, node);
269 load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem);
270 set_ia32_am_support(load, ia32_am_Source);
271 set_ia32_op_type(load, ia32_AddrModeS);
272 set_ia32_am_flavour(load, ia32_am_N);
273 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
274 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
277 floatent = get_entity_for_tv(env->cg, node);
279 load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem);
280 set_ia32_am_support(load, ia32_am_Source);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_flavour(load, ia32_am_N);
283 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
284 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
287 set_ia32_ls_mode(load, mode);
288 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
290 /* Const Nodes before the initial IncSP are a bad idea, because
291 * they could be spilled and we have no SP ready at that point yet
293 if (get_irg_start_block(irg) == block) {
294 add_irn_dep(load, get_irg_frame(irg));
297 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 ir_node *cnst = new_rd_ia32_Const(dbg, irg, block);
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(cnst, get_irg_frame(irg));
307 set_ia32_Const_attr(cnst, node);
308 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
313 return new_r_Bad(irg);
317 * Transforms a SymConst.
319 * @param mod the debug module
320 * @param block the block the new node should belong to
321 * @param node the ir SymConst node
322 * @param mode mode of the SymConst
323 * @return the created ia32 Const node
325 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
326 ir_graph *irg = env->irg;
327 dbg_info *dbg = get_irn_dbg_info(node);
328 ir_mode *mode = get_irn_mode(node);
329 ir_node *block = transform_node(env, get_nodes_block(node));
332 if (mode_is_float(mode)) {
334 if (USE_SSE2(env->cg))
335 cnst = new_rd_ia32_xConst(dbg, irg, block);
337 cnst = new_rd_ia32_vfConst(dbg, irg, block);
338 set_ia32_ls_mode(cnst, mode);
340 cnst = new_rd_ia32_Const(dbg, irg, block);
343 /* Const Nodes before the initial IncSP are a bad idea, because
344 * they could be spilled and we have no SP ready at that point yet
346 if (get_irg_start_block(irg) == block) {
347 add_irn_dep(cnst, get_irg_frame(irg));
350 set_ia32_Const_attr(cnst, node);
351 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
357 * SSE convert of an integer node into a floating point node.
359 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg,
360 ir_graph *irg, ir_node *block,
361 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
364 ir_node *nomem = new_rd_NoMem(irg);
365 ir_node *old_pred = get_Cmp_left(old_node);
366 ir_mode *in_mode = get_irn_mode(old_pred);
367 int in_bits = get_mode_size_bits(in_mode);
369 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
370 set_ia32_ls_mode(conv, tgt_mode);
372 set_ia32_am_support(conv, ia32_am_Source);
374 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
380 * SSE convert of an float node into a double node.
382 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
383 ir_graph *irg, ir_node *block,
384 ir_node *in, ir_node *old_node)
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
387 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
390 set_ia32_am_support(conv, ia32_am_Source);
391 set_ia32_ls_mode(conv, mode_E);
392 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
398 ident *ia32_gen_fp_known_const(ia32_known_const_t kct) {
399 static const struct {
401 const char *ent_name;
402 const char *cnst_str;
403 } names [ia32_known_const_max] = {
404 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
405 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
406 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
407 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
409 static ir_entity *ent_cache[ia32_known_const_max];
411 const char *tp_name, *ent_name, *cnst_str;
419 ent_name = names[kct].ent_name;
420 if (! ent_cache[kct]) {
421 tp_name = names[kct].tp_name;
422 cnst_str = names[kct].cnst_str;
424 //mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
426 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
427 tp = new_type_primitive(new_id_from_str(tp_name), mode);
428 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
430 set_entity_ld_ident(ent, get_entity_ident(ent));
431 set_entity_visibility(ent, visibility_local);
432 set_entity_variability(ent, variability_constant);
433 set_entity_allocation(ent, allocation_static);
435 /* we create a new entity here: It's initialization must resist on the
437 rem = current_ir_graph;
438 current_ir_graph = get_const_code_irg();
439 cnst = new_Const(mode, tv);
440 current_ir_graph = rem;
442 set_atomic_ent_value(ent, cnst);
444 /* cache the entry */
445 ent_cache[kct] = ent;
448 return get_entity_ident(ent_cache[kct]);
453 * Prints the old node name on cg obst and returns a pointer to it.
455 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
456 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
458 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
459 obstack_1grow(isa->name_obst, 0);
460 return obstack_finish(isa->name_obst);
464 /* determine if one operator is an Imm */
465 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
467 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
468 else return is_ia32_Cnst(op2) ? op2 : NULL;
471 /* determine if one operator is not an Imm */
472 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
473 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
476 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
480 if(! (env->cg->opt & IA32_OPT_IMMOPS))
483 left = get_irn_n(node, in1);
484 right = get_irn_n(node, in2);
485 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
486 /* we can only set right operand to immediate */
487 if(!is_ia32_commutative(node))
489 /* exchange left/right */
490 set_irn_n(node, in1, right);
491 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
492 copy_ia32_Immop_attr(node, left);
493 } else if(is_ia32_Cnst(right)) {
494 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
495 copy_ia32_Immop_attr(node, right);
500 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
504 * Construct a standard binary operation, set AM and immediate if required.
506 * @param env The transformation environment
507 * @param op1 The first operand
508 * @param op2 The second operand
509 * @param func The node constructor function
510 * @return The constructed ia32 node.
512 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
513 ir_node *op1, ir_node *op2,
514 construct_binop_func *func) {
515 ir_node *new_node = NULL;
516 ir_graph *irg = env->irg;
517 dbg_info *dbg = get_irn_dbg_info(node);
518 ir_node *block = transform_node(env, get_nodes_block(node));
519 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
520 ir_node *nomem = new_NoMem();
521 ir_node *new_op1 = transform_node(env, op1);
522 ir_node *new_op2 = transform_node(env, op2);
524 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
525 if(func == new_rd_ia32_IMul) {
526 set_ia32_am_support(new_node, ia32_am_Source);
528 set_ia32_am_support(new_node, ia32_am_Full);
531 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
532 if (is_op_commutative(get_irn_op(node))) {
533 set_ia32_commutative(new_node);
535 fold_immediate(env, new_node, 2, 3);
541 * Construct a standard binary operation, set AM and immediate if required.
543 * @param env The transformation environment
544 * @param op1 The first operand
545 * @param op2 The second operand
546 * @param func The node constructor function
547 * @return The constructed ia32 node.
549 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
550 ir_node *op1, ir_node *op2,
551 construct_binop_func *func)
553 ir_node *new_node = NULL;
554 dbg_info *dbg = get_irn_dbg_info(node);
555 ir_graph *irg = env->irg;
556 ir_mode *mode = get_irn_mode(node);
557 ir_node *block = transform_node(env, get_nodes_block(node));
558 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
559 ir_node *nomem = new_NoMem();
560 ir_node *new_op1 = transform_node(env, op1);
561 ir_node *new_op2 = transform_node(env, op2);
563 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
564 set_ia32_am_support(new_node, ia32_am_Source);
565 if (is_op_commutative(get_irn_op(node))) {
566 set_ia32_commutative(new_node);
568 if (USE_SSE2(env->cg)) {
569 set_ia32_ls_mode(new_node, mode);
572 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
579 * Construct a shift/rotate binary operation, sets AM and immediate if required.
581 * @param env The transformation environment
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
588 ir_node *op1, ir_node *op2,
589 construct_binop_func *func) {
590 ir_node *new_op = NULL;
591 dbg_info *dbg = get_irn_dbg_info(node);
592 ir_graph *irg = env->irg;
593 ir_node *block = transform_node(env, get_nodes_block(node));
594 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
595 ir_node *nomem = new_NoMem();
598 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
599 ir_node *new_op1 = transform_node(env, op1);
600 ir_node *new_op2 = transform_node(env, op2);
603 assert(! mode_is_float(get_irn_mode(node))
604 && "Shift/Rotate with float not supported");
606 /* Check if immediate optimization is on and */
607 /* if it's an operation with immediate. */
608 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
609 expr_op = get_expr_op(new_op1, new_op2);
611 assert((expr_op || imm_op) && "invalid operands");
614 /* We have two consts here: not yet supported */
618 /* Limit imm_op within range imm8 */
620 tv = get_ia32_Immop_tarval(imm_op);
623 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
624 set_ia32_Immop_tarval(imm_op, tv);
631 /* integer operations */
633 /* This is shift/rot with const */
634 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
636 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
637 copy_ia32_Immop_attr(new_op, imm_op);
639 /* This is a normal shift/rot */
640 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
641 new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
645 set_ia32_am_support(new_op, ia32_am_Dest);
647 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
649 set_ia32_emit_cl(new_op);
656 * Construct a standard unary operation, set AM and immediate if required.
658 * @param env The transformation environment
659 * @param op The operand
660 * @param func The node constructor function
661 * @return The constructed ia32 node.
663 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
664 construct_unop_func *func) {
665 ir_node *new_node = NULL;
666 ir_graph *irg = env->irg;
667 dbg_info *dbg = get_irn_dbg_info(node);
668 ir_node *block = transform_node(env, get_nodes_block(node));
669 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
670 ir_node *nomem = new_NoMem();
671 ir_node *new_op = transform_node(env, op);
672 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
674 new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem);
675 DB((mod, LEVEL_1, "INT unop ..."));
676 set_ia32_am_support(new_node, ia32_am_Dest);
678 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
685 * Creates an ia32 Add.
687 * @param env The transformation environment
688 * @return the created ia32 Add node
690 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
691 ir_node *new_op = NULL;
692 ir_graph *irg = env->irg;
693 dbg_info *dbg = get_irn_dbg_info(node);
694 ir_mode *mode = get_irn_mode(node);
695 ir_node *block = transform_node(env, get_nodes_block(node));
696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
697 ir_node *nomem = new_NoMem();
698 ir_node *expr_op, *imm_op;
699 ir_node *op1 = get_Add_left(node);
700 ir_node *op2 = get_Add_right(node);
701 ir_node *new_op1 = transform_node(env, op1);
702 ir_node *new_op2 = transform_node(env, op2);
704 /* Check if immediate optimization is on and */
705 /* if it's an operation with immediate. */
706 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
707 expr_op = get_expr_op(new_op1, new_op2);
709 assert((expr_op || imm_op) && "invalid operands");
711 if (mode_is_float(mode)) {
713 if (USE_SSE2(env->cg))
714 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
716 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
721 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
722 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
724 /* No expr_op means, that we have two const - one symconst and */
725 /* one tarval or another symconst - because this case is not */
726 /* covered by constant folding */
727 /* We need to check for: */
728 /* 1) symconst + const -> becomes a LEA */
729 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
730 /* linker doesn't support two symconsts */
732 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
733 /* this is the 2nd case */
734 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
735 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
736 set_ia32_am_flavour(new_op, ia32_am_OB);
737 set_ia32_am_support(new_op, ia32_am_Source);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 } else if (tp1 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op2);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
746 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
748 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_flavour(new_op, ia32_am_O);
751 set_ia32_am_support(new_op, ia32_am_Source);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
753 } else if (tp2 == ia32_ImmSymConst) {
754 tarval *tv = get_ia32_Immop_tarval(new_op1);
755 long offs = get_tarval_long(tv);
757 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
758 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
760 add_ia32_am_offs_int(new_op, offs);
761 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
762 set_ia32_am_flavour(new_op, ia32_am_O);
763 set_ia32_am_support(new_op, ia32_am_Source);
764 set_ia32_op_type(new_op, ia32_AddrModeS);
766 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
767 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
768 tarval *restv = tarval_add(tv1, tv2);
770 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
772 new_op = new_rd_ia32_Const(dbg, irg, block);
773 set_ia32_Const_tarval(new_op, restv);
774 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
780 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
781 tarval_classification_t class_tv, class_negtv;
782 tarval *tv = get_ia32_Immop_tarval(imm_op);
784 /* optimize tarvals */
785 class_tv = classify_tarval(tv);
786 class_negtv = classify_tarval(tarval_neg(tv));
788 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
789 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
790 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
793 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
794 DB((env->mod, LEVEL_2, "Add(-1) to Dec ... "));
795 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
796 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
802 /* This is a normal add */
803 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
806 set_ia32_am_support(new_op, ia32_am_Full);
807 set_ia32_commutative(new_op);
809 fold_immediate(env, new_op, 2, 3);
811 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
817 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
818 ir_graph *irg = env->irg;
819 dbg_info *dbg = get_irn_dbg_info(node);
820 ir_node *block = transform_node(env, get_nodes_block(node));
821 ir_node *op1 = get_Mul_left(node);
822 ir_node *op2 = get_Mul_right(node);
823 ir_node *new_op1 = transform_node(env, op1);
824 ir_node *new_op2 = transform_node(env, op2);
825 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
826 ir_node *proj_EAX, *proj_EDX, *res;
829 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
830 set_ia32_commutative(res);
831 set_ia32_am_support(res, ia32_am_Source);
833 /* imediates are not supported, so no fold_immediate */
834 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
835 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
839 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
847 * Creates an ia32 Mul.
849 * @param env The transformation environment
850 * @return the created ia32 Mul node
852 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
853 ir_node *op1 = get_Mul_left(node);
854 ir_node *op2 = get_Mul_right(node);
855 ir_mode *mode = get_irn_mode(node);
857 if (mode_is_float(mode)) {
859 if (USE_SSE2(env->cg))
860 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
862 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
865 // for the lower 32bit of the result it doesn't matter whether we use
866 // signed or unsigned multiplication so we use IMul as it has fewer
868 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
872 * Creates an ia32 Mulh.
873 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
874 * this result while Mul returns the lower 32 bit.
876 * @param env The transformation environment
877 * @return the created ia32 Mulh node
879 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
880 ir_graph *irg = env->irg;
881 dbg_info *dbg = get_irn_dbg_info(node);
882 ir_node *block = transform_node(env, get_nodes_block(node));
883 ir_node *op1 = get_irn_n(node, 0);
884 ir_node *op2 = get_irn_n(node, 1);
885 ir_node *new_op1 = transform_node(env, op1);
886 ir_node *new_op2 = transform_node(env, op2);
887 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
888 ir_node *proj_EAX, *proj_EDX, *res;
889 ir_mode *mode = get_irn_mode(node);
892 assert(!mode_is_float(mode) && "Mulh with float not supported");
893 if(mode_is_signed(mode)) {
894 res = new_rd_ia32_IMul1OP(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
896 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
899 set_ia32_commutative(res);
900 set_ia32_am_support(res, ia32_am_Source);
902 set_ia32_am_support(res, ia32_am_Source);
904 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
905 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
909 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
917 * Creates an ia32 And.
919 * @param env The transformation environment
920 * @return The created ia32 And node
922 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
923 ir_node *op1 = get_And_left(node);
924 ir_node *op2 = get_And_right(node);
926 assert (! mode_is_float(get_irn_mode(node)));
927 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
933 * Creates an ia32 Or.
935 * @param env The transformation environment
936 * @return The created ia32 Or node
938 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
939 ir_node *op1 = get_Or_left(node);
940 ir_node *op2 = get_Or_right(node);
942 assert (! mode_is_float(get_irn_mode(node)));
943 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
949 * Creates an ia32 Eor.
951 * @param env The transformation environment
952 * @return The created ia32 Eor node
954 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
955 ir_node *op1 = get_Eor_left(node);
956 ir_node *op2 = get_Eor_right(node);
958 assert(! mode_is_float(get_irn_mode(node)));
959 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
965 * Creates an ia32 Max.
967 * @param env The transformation environment
968 * @return the created ia32 Max node
970 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
971 ir_graph *irg = env->irg;
973 ir_mode *mode = get_irn_mode(node);
974 dbg_info *dbg = get_irn_dbg_info(node);
975 ir_node *block = transform_node(env, get_nodes_block(node));
976 ir_node *op1 = get_irn_n(node, 0);
977 ir_node *op2 = get_irn_n(node, 1);
978 ir_node *new_op1 = transform_node(env, op1);
979 ir_node *new_op2 = transform_node(env, op2);
980 ir_mode *op_mode = get_irn_mode(op1);
982 assert(get_mode_size_bits(mode) == 32);
984 if (mode_is_float(mode)) {
986 if (USE_SSE2(env->cg)) {
987 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
989 panic("Can't create Max node");
992 long pnc = pn_Cmp_Gt;
993 if(!mode_is_signed(op_mode)) {
994 pnc |= ia32_pn_Cmp_Unsigned;
996 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
997 set_ia32_pncode(new_op, pnc);
998 set_ia32_am_support(new_op, ia32_am_None);
1000 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1006 * Creates an ia32 Min.
1008 * @param env The transformation environment
1009 * @return the created ia32 Min node
1011 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1012 ir_graph *irg = env->irg;
1014 ir_mode *mode = get_irn_mode(node);
1015 dbg_info *dbg = get_irn_dbg_info(node);
1016 ir_node *block = transform_node(env, get_nodes_block(node));
1017 ir_node *op1 = get_irn_n(node, 0);
1018 ir_node *op2 = get_irn_n(node, 1);
1019 ir_node *new_op1 = transform_node(env, op1);
1020 ir_node *new_op2 = transform_node(env, op2);
1021 ir_mode *op_mode = get_irn_mode(op1);
1023 assert(get_mode_size_bits(mode) == 32);
1025 if (mode_is_float(mode)) {
1027 if (USE_SSE2(env->cg)) {
1028 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1030 panic("can't create Min node");
1033 long pnc = pn_Cmp_Lt;
1034 if(!mode_is_signed(op_mode)) {
1035 pnc |= ia32_pn_Cmp_Unsigned;
1037 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1038 set_ia32_pncode(new_op, pnc);
1039 set_ia32_am_support(new_op, ia32_am_None);
1041 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1048 * Creates an ia32 Sub.
1050 * @param env The transformation environment
1051 * @return The created ia32 Sub node
1053 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1054 ir_node *new_op = NULL;
1055 ir_graph *irg = env->irg;
1056 dbg_info *dbg = get_irn_dbg_info(node);
1057 ir_mode *mode = get_irn_mode(node);
1058 ir_node *block = transform_node(env, get_nodes_block(node));
1059 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1060 ir_node *nomem = new_NoMem();
1061 ir_node *op1 = get_Sub_left(node);
1062 ir_node *op2 = get_Sub_right(node);
1063 ir_node *new_op1 = transform_node(env, op1);
1064 ir_node *new_op2 = transform_node(env, op2);
1065 ir_node *expr_op, *imm_op;
1067 /* Check if immediate optimization is on and */
1068 /* if it's an operation with immediate. */
1069 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1070 expr_op = get_expr_op(new_op1, new_op2);
1072 assert((expr_op || imm_op) && "invalid operands");
1074 if (mode_is_float(mode)) {
1076 if (USE_SSE2(env->cg))
1077 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1079 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1084 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1085 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1087 /* No expr_op means, that we have two const - one symconst and */
1088 /* one tarval or another symconst - because this case is not */
1089 /* covered by constant folding */
1090 /* We need to check for: */
1091 /* 1) symconst - const -> becomes a LEA */
1092 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1093 /* linker doesn't support two symconsts */
1094 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1095 /* this is the 2nd case */
1096 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
1097 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1098 set_ia32_am_sc_sign(new_op);
1099 set_ia32_am_flavour(new_op, ia32_am_OB);
1101 DBG_OPT_LEA3(op1, op2, node, new_op);
1102 } else if (tp1 == ia32_ImmSymConst) {
1103 tarval *tv = get_ia32_Immop_tarval(new_op2);
1104 long offs = get_tarval_long(tv);
1106 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1107 DBG_OPT_LEA3(op1, op2, node, new_op);
1109 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1110 add_ia32_am_offs_int(new_op, -offs);
1111 set_ia32_am_flavour(new_op, ia32_am_O);
1112 set_ia32_am_support(new_op, ia32_am_Source);
1113 set_ia32_op_type(new_op, ia32_AddrModeS);
1114 } else if (tp2 == ia32_ImmSymConst) {
1115 tarval *tv = get_ia32_Immop_tarval(new_op1);
1116 long offs = get_tarval_long(tv);
1118 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1119 DBG_OPT_LEA3(op1, op2, node, new_op);
1121 add_ia32_am_offs_int(new_op, offs);
1122 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1123 set_ia32_am_sc_sign(new_op);
1124 set_ia32_am_flavour(new_op, ia32_am_O);
1125 set_ia32_am_support(new_op, ia32_am_Source);
1126 set_ia32_op_type(new_op, ia32_AddrModeS);
1128 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1129 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1130 tarval *restv = tarval_sub(tv1, tv2);
1132 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1134 new_op = new_rd_ia32_Const(dbg, irg, block);
1135 set_ia32_Const_tarval(new_op, restv);
1136 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1139 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1141 } else if (imm_op) {
1142 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1143 tarval_classification_t class_tv, class_negtv;
1144 tarval *tv = get_ia32_Immop_tarval(imm_op);
1146 /* optimize tarvals */
1147 class_tv = classify_tarval(tv);
1148 class_negtv = classify_tarval(tarval_neg(tv));
1150 if (class_tv == TV_CLASSIFY_ONE) {
1151 DB((env->mod, LEVEL_2, "Sub(1) to Dec ... "));
1152 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
1153 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1155 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1156 DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... "));
1157 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
1158 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1164 /* This is a normal sub */
1165 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1167 /* set AM support */
1168 set_ia32_am_support(new_op, ia32_am_Full);
1170 fold_immediate(env, new_op, 2, 3);
1172 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1180 * Generates an ia32 DivMod with additional infrastructure for the
1181 * register allocator if needed.
1183 * @param env The transformation environment
1184 * @param dividend -no comment- :)
1185 * @param divisor -no comment- :)
1186 * @param dm_flav flavour_Div/Mod/DivMod
1187 * @return The created ia32 DivMod node
1189 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1190 ir_node *dividend, ir_node *divisor,
1191 ia32_op_flavour_t dm_flav) {
1192 ir_graph *irg = env->irg;
1193 dbg_info *dbg = get_irn_dbg_info(node);
1194 ir_mode *mode = get_irn_mode(node);
1195 ir_node *block = transform_node(env, get_nodes_block(node));
1196 ir_node *res, *proj_div, *proj_mod;
1197 ir_node *edx_node, *cltd;
1198 ir_node *in_keep[1];
1199 ir_node *mem, *new_mem;
1200 ir_node *projs[pn_DivMod_max];
1201 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1202 ir_node *new_dividend = transform_node(env, dividend);
1203 ir_node *new_divisor = transform_node(env, divisor);
1205 ia32_collect_Projs(node, projs, pn_DivMod_max);
1209 mem = get_Div_mem(node);
1210 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1213 mem = get_Mod_mem(node);
1214 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1216 case flavour_DivMod:
1217 mem = get_DivMod_mem(node);
1218 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1219 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1220 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1223 panic("invalid divmod flavour!");
1225 new_mem = transform_node(env, mem);
1227 if (mode_is_signed(mode)) {
1228 /* in signed mode, we need to sign extend the dividend */
1229 cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend);
1230 new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1231 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1233 edx_node = new_rd_ia32_Const(dbg, irg, block);
1234 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1235 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1238 if(mode_is_signed(mode)) {
1239 res = new_rd_ia32_IDiv(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1241 res = new_rd_ia32_Div(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1244 /* Matze: code can't handle this at the moment... */
1246 /* set AM support */
1247 set_ia32_am_support(res, ia32_am_Source);
1250 set_ia32_n_res(res, 2);
1252 /* Only one proj is used -> We must add a second proj and */
1253 /* connect this one to a Keep node to eat up the second */
1254 /* destroyed register. */
1255 /* We also renumber the Firm projs into ia32 projs. */
1257 switch (get_irn_opcode(node)) {
1259 /* add Proj-Keep for mod res */
1260 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1261 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1264 /* add Proj-Keep for div res */
1265 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1266 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1269 /* check, which Proj-Keep, we need to add */
1270 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1271 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1273 if (proj_div && proj_mod) {
1274 /* nothing to be done */
1276 else if (! proj_div && ! proj_mod) {
1277 assert(0 && "Missing DivMod result proj");
1279 else if (! proj_div) {
1280 /* We have only mod result: add div res Proj-Keep */
1281 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1282 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1285 /* We have only div result: add mod res Proj-Keep */
1286 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1287 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1291 assert(0 && "Div, Mod, or DivMod expected.");
1295 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1302 * Wrapper for generate_DivMod. Sets flavour_Mod.
1304 * @param env The transformation environment
1306 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1307 return generate_DivMod(env, node, get_Mod_left(node),
1308 get_Mod_right(node), flavour_Mod);
1312 * Wrapper for generate_DivMod. Sets flavour_Div.
1314 * @param env The transformation environment
1316 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1317 return generate_DivMod(env, node, get_Div_left(node),
1318 get_Div_right(node), flavour_Div);
1322 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1324 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1325 return generate_DivMod(env, node, get_DivMod_left(node),
1326 get_DivMod_right(node), flavour_DivMod);
1332 * Creates an ia32 floating Div.
1334 * @param env The transformation environment
1335 * @return The created ia32 xDiv node
1337 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1338 ir_graph *irg = env->irg;
1339 dbg_info *dbg = get_irn_dbg_info(node);
1340 ir_node *block = transform_node(env, get_nodes_block(node));
1341 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1343 ir_node *nomem = new_rd_NoMem(env->irg);
1344 ir_node *op1 = get_Quot_left(node);
1345 ir_node *op2 = get_Quot_right(node);
1346 ir_node *new_op1 = transform_node(env, op1);
1347 ir_node *new_op2 = transform_node(env, op2);
1350 if (USE_SSE2(env->cg)) {
1351 ir_mode *mode = get_irn_mode(op1);
1352 if (is_ia32_xConst(new_op2)) {
1353 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
1354 set_ia32_am_support(new_op, ia32_am_None);
1355 copy_ia32_Immop_attr(new_op, new_op2);
1357 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1358 // Matze: disabled for now, spillslot coalescer fails
1359 //set_ia32_am_support(new_op, ia32_am_Source);
1361 set_ia32_ls_mode(new_op, mode);
1363 new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1364 // Matze: disabled for now (spillslot coalescer fails)
1365 //set_ia32_am_support(new_op, ia32_am_Source);
1367 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1373 * Creates an ia32 Shl.
1375 * @param env The transformation environment
1376 * @return The created ia32 Shl node
1378 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1379 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1386 * Creates an ia32 Shr.
1388 * @param env The transformation environment
1389 * @return The created ia32 Shr node
1391 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1392 return gen_shift_binop(env, node, get_Shr_left(node),
1393 get_Shr_right(node), new_rd_ia32_Shr);
1399 * Creates an ia32 Sar.
1401 * @param env The transformation environment
1402 * @return The created ia32 Shrs node
1404 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1405 return gen_shift_binop(env, node, get_Shrs_left(node),
1406 get_Shrs_right(node), new_rd_ia32_Sar);
1412 * Creates an ia32 RotL.
1414 * @param env The transformation environment
1415 * @param op1 The first operator
1416 * @param op2 The second operator
1417 * @return The created ia32 RotL node
1419 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1420 ir_node *op1, ir_node *op2) {
1421 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1427 * Creates an ia32 RotR.
1428 * NOTE: There is no RotR with immediate because this would always be a RotL
1429 * "imm-mode_size_bits" which can be pre-calculated.
1431 * @param env The transformation environment
1432 * @param op1 The first operator
1433 * @param op2 The second operator
1434 * @return The created ia32 RotR node
1436 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1438 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1444 * Creates an ia32 RotR or RotL (depending on the found pattern).
1446 * @param env The transformation environment
1447 * @return The created ia32 RotL or RotR node
1449 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1450 ir_node *rotate = NULL;
1451 ir_node *op1 = get_Rot_left(node);
1452 ir_node *op2 = get_Rot_right(node);
1454 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1455 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1456 that means we can create a RotR instead of an Add and a RotL */
1458 if (get_irn_op(op2) == op_Add) {
1460 ir_node *left = get_Add_left(add);
1461 ir_node *right = get_Add_right(add);
1462 if (is_Const(right)) {
1463 tarval *tv = get_Const_tarval(right);
1464 ir_mode *mode = get_irn_mode(node);
1465 long bits = get_mode_size_bits(mode);
1467 if (get_irn_op(left) == op_Minus &&
1468 tarval_is_long(tv) &&
1469 get_tarval_long(tv) == bits)
1471 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1472 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1477 if (rotate == NULL) {
1478 rotate = gen_RotL(env, node, op1, op2);
1487 * Transforms a Minus node.
1489 * @param env The transformation environment
1490 * @param op The Minus operand
1491 * @return The created ia32 Minus node
1493 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1496 ir_graph *irg = env->irg;
1497 dbg_info *dbg = get_irn_dbg_info(node);
1498 ir_node *block = transform_node(env, get_nodes_block(node));
1499 ir_mode *mode = get_irn_mode(node);
1502 if (mode_is_float(mode)) {
1503 ir_node *new_op = transform_node(env, op);
1505 if (USE_SSE2(env->cg)) {
1506 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1507 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1508 ir_node *nomem = new_rd_NoMem(irg);
1510 res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1512 size = get_mode_size_bits(mode);
1513 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1515 set_ia32_am_sc(res, name);
1516 set_ia32_op_type(res, ia32_AddrModeS);
1517 set_ia32_ls_mode(res, mode);
1519 res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
1522 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1525 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1531 * Transforms a Minus node.
1533 * @param env The transformation environment
1534 * @return The created ia32 Minus node
1536 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1537 return gen_Minus_ex(env, node, get_Minus_op(node));
1542 * Transforms a Not node.
1544 * @param env The transformation environment
1545 * @return The created ia32 Not node
1547 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1548 ir_node *op = get_Not_op(node);
1550 assert (! mode_is_float(get_irn_mode(node)));
1551 return gen_unop(env, node, op, new_rd_ia32_Not);
1557 * Transforms an Abs node.
1559 * @param env The transformation environment
1560 * @return The created ia32 Abs node
1562 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1563 ir_node *res, *p_eax, *p_edx;
1564 ir_graph *irg = env->irg;
1565 dbg_info *dbg = get_irn_dbg_info(node);
1566 ir_node *block = transform_node(env, get_nodes_block(node));
1567 ir_mode *mode = get_irn_mode(node);
1568 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1569 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1570 ir_node *nomem = new_NoMem();
1571 ir_node *op = get_Abs_op(node);
1572 ir_node *new_op = transform_node(env, op);
1576 if (mode_is_float(mode)) {
1578 if (USE_SSE2(env->cg)) {
1579 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1581 size = get_mode_size_bits(mode);
1582 name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1584 set_ia32_am_sc(res, name);
1586 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1588 set_ia32_op_type(res, ia32_AddrModeS);
1589 set_ia32_ls_mode(res, mode);
1592 res = new_rd_ia32_vfabs(dbg, irg, block, new_op);
1593 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1597 res = new_rd_ia32_Cltd(dbg, irg, block, new_op);
1598 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1600 p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
1601 p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
1603 res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1604 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1606 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1607 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1616 * Transforms a Load.
1618 * @param env The transformation environment
1619 * @return the created ia32 Load node
1621 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1622 ir_graph *irg = env->irg;
1623 dbg_info *dbg = get_irn_dbg_info(node);
1624 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1625 ir_mode *mode = get_Load_mode(node);
1626 ir_node *block = transform_node(env, get_nodes_block(node));
1627 ir_node *ptr = get_Load_ptr(node);
1628 ir_node *new_ptr = transform_node(env, ptr);
1629 ir_node *lptr = new_ptr;
1630 ir_node *mem = get_Load_mem(node);
1631 ir_node *new_mem = transform_node(env, mem);
1634 ia32_am_flavour_t am_flav = ia32_am_B;
1635 ir_node *projs[pn_Load_max];
1637 ia32_collect_Projs(node, projs, pn_Load_max);
1640 check for special case: the loaded value might not be used (optimized, volatile, ...)
1641 we add a Proj + Keep for volatile loads and ignore all other cases
1643 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1644 /* add a result proj and a Keep to produce a pseudo use */
1645 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1646 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1649 /* address might be a constant (symconst or absolute address) */
1650 if (is_ia32_Const(new_ptr)) {
1655 if (mode_is_float(mode)) {
1657 if (USE_SSE2(env->cg)) {
1658 new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem);
1660 new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem);
1663 new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem);
1666 /* base is a constant address */
1668 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1669 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1670 am_flav = ia32_am_N;
1672 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1673 long offs = get_tarval_long(tv);
1675 add_ia32_am_offs_int(new_op, offs);
1676 am_flav = ia32_am_O;
1680 set_ia32_am_support(new_op, ia32_am_Source);
1681 set_ia32_op_type(new_op, ia32_AddrModeS);
1682 set_ia32_am_flavour(new_op, am_flav);
1683 set_ia32_ls_mode(new_op, mode);
1685 /* make sure we are scheduled behind the intial IncSP/Barrier
1686 * to avoid spills being placed before it
1688 if(block == get_irg_start_block(irg)) {
1689 add_irn_dep(new_op, get_irg_frame(irg));
1692 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1700 * Transforms a Store.
1702 * @param env The transformation environment
1703 * @return the created ia32 Store node
1705 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1706 ir_graph *irg = env->irg;
1707 dbg_info *dbg = get_irn_dbg_info(node);
1708 ir_node *block = transform_node(env, get_nodes_block(node));
1709 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1710 ir_node *ptr = get_Store_ptr(node);
1711 ir_node *new_ptr = transform_node(env, ptr);
1712 ir_node *sptr = new_ptr;
1713 ir_node *val = get_Store_value(node);
1714 ir_node *new_val = transform_node(env, val);
1715 ir_node *mem = get_Store_mem(node);
1716 ir_node *new_mem = transform_node(env, mem);
1717 ir_mode *mode = get_irn_mode(val);
1718 ir_node *sval = new_val;
1721 ia32_am_flavour_t am_flav = ia32_am_B;
1723 if (is_ia32_Const(new_val)) {
1724 assert(!mode_is_float(mode));
1728 /* address might be a constant (symconst or absolute address) */
1729 if (is_ia32_Const(new_ptr)) {
1734 if (mode_is_float(mode)) {
1736 if (USE_SSE2(env->cg)) {
1737 new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
1739 new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
1741 } else if (get_mode_size_bits(mode) == 8) {
1742 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
1744 new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
1747 /* stored const is an immediate value */
1748 if (is_ia32_Const(new_val)) {
1749 assert(!mode_is_float(mode));
1750 copy_ia32_Immop_attr(new_op, new_val);
1753 /* base is an constant address */
1755 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1756 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1757 am_flav = ia32_am_N;
1759 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1760 long offs = get_tarval_long(tv);
1762 add_ia32_am_offs_int(new_op, offs);
1763 am_flav = ia32_am_O;
1767 set_ia32_am_support(new_op, ia32_am_Dest);
1768 set_ia32_op_type(new_op, ia32_AddrModeD);
1769 set_ia32_am_flavour(new_op, am_flav);
1770 set_ia32_ls_mode(new_op, mode);
1772 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1780 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1782 * @param env The transformation environment
1783 * @return The transformed node.
1785 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1786 ir_graph *irg = env->irg;
1787 dbg_info *dbg = get_irn_dbg_info(node);
1788 ir_node *block = transform_node(env, get_nodes_block(node));
1789 ir_node *sel = get_Cond_selector(node);
1790 ir_mode *sel_mode = get_irn_mode(sel);
1791 ir_node *res = NULL;
1792 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1793 ir_node *cnst, *expr;
1795 if (is_Proj(sel) && sel_mode == mode_b) {
1796 ir_node *nomem = new_NoMem();
1797 ir_node *pred = get_Proj_pred(sel);
1798 ir_node *cmp_a = get_Cmp_left(pred);
1799 ir_node *new_cmp_a = transform_node(env, cmp_a);
1800 ir_node *cmp_b = get_Cmp_right(pred);
1801 ir_node *new_cmp_b = transform_node(env, cmp_b);
1802 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1804 int pnc = get_Proj_proj(sel);
1805 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1806 pnc |= ia32_pn_Cmp_Unsigned;
1809 /* check if we can use a CondJmp with immediate */
1810 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1811 expr = get_expr_op(new_cmp_a, new_cmp_b);
1813 if (cnst != NULL && expr != NULL) {
1814 /* immop has to be the right operand, we might need to flip pnc */
1815 if(cnst != new_cmp_b) {
1816 pnc = get_inversed_pnc(pnc);
1819 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1820 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1821 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1823 /* a Cmp A =/!= 0 */
1824 ir_node *op1 = expr;
1825 ir_node *op2 = expr;
1828 /* check, if expr is an only once used And operation */
1829 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1830 op1 = get_irn_n(expr, 2);
1831 op2 = get_irn_n(expr, 3);
1833 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1835 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1836 set_ia32_pncode(res, pnc);
1839 copy_ia32_Immop_attr(res, expr);
1842 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1847 if (mode_is_float(cmp_mode)) {
1849 if (USE_SSE2(env->cg)) {
1850 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1851 set_ia32_ls_mode(res, cmp_mode);
1857 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1859 copy_ia32_Immop_attr(res, cnst);
1862 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1864 if (mode_is_float(cmp_mode)) {
1866 if (USE_SSE2(env->cg)) {
1867 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1868 set_ia32_ls_mode(res, cmp_mode);
1871 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1873 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1877 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1878 set_ia32_commutative(res);
1882 set_ia32_pncode(res, pnc);
1883 // Matze: disabled for now, because the default collect_spills_walker
1884 // is not able to detect the mode of the spilled value
1885 // moreover, the lea optimize phase freely exchanges left/right
1886 // without updating the pnc
1887 //set_ia32_am_support(res, ia32_am_Source);
1890 /* determine the smallest switch case value */
1891 int switch_min = INT_MAX;
1892 const ir_edge_t *edge;
1893 ir_node *new_sel = transform_node(env, sel);
1895 foreach_out_edge(node, edge) {
1896 int pn = get_Proj_proj(get_edge_src_irn(edge));
1897 switch_min = pn < switch_min ? pn : switch_min;
1901 /* if smallest switch case is not 0 we need an additional sub */
1902 res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg);
1903 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1904 add_ia32_am_offs_int(res, -switch_min);
1905 set_ia32_am_flavour(res, ia32_am_OB);
1906 set_ia32_am_support(res, ia32_am_Source);
1907 set_ia32_op_type(res, ia32_AddrModeS);
1910 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T);
1911 set_ia32_pncode(res, get_Cond_defaultProj(node));
1914 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1921 * Transforms a CopyB node.
1923 * @param env The transformation environment
1924 * @return The transformed node.
1926 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1927 ir_node *res = NULL;
1928 ir_graph *irg = env->irg;
1929 dbg_info *dbg = get_irn_dbg_info(node);
1930 ir_node *block = transform_node(env, get_nodes_block(node));
1931 ir_node *src = get_CopyB_src(node);
1932 ir_node *new_src = transform_node(env, src);
1933 ir_node *dst = get_CopyB_dst(node);
1934 ir_node *new_dst = transform_node(env, dst);
1935 ir_node *mem = get_CopyB_mem(node);
1936 ir_node *new_mem = transform_node(env, mem);
1937 int size = get_type_size_bytes(get_CopyB_type(node));
1938 ir_mode *dst_mode = get_irn_mode(dst);
1939 ir_mode *src_mode = get_irn_mode(src);
1943 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1944 /* then we need the size explicitly in ECX. */
1945 if (size >= 32 * 4) {
1946 rem = size & 0x3; /* size % 4 */
1949 res = new_rd_ia32_Const(dbg, irg, block);
1950 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1951 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1953 res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
1954 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1956 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1957 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1958 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1959 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1960 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1963 res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
1964 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1966 /* ok: now attach Proj's because movsd will destroy esi and edi */
1967 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1968 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1969 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1972 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1980 * Transforms a Mux node into CMov.
1982 * @param env The transformation environment
1983 * @return The transformed node.
1985 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1986 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1987 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1989 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1995 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1996 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1997 ir_node *psi_default);
2000 * Transforms a Psi node into CMov.
2002 * @param env The transformation environment
2003 * @return The transformed node.
2005 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2006 ia32_code_gen_t *cg = env->cg;
2007 ir_graph *irg = env->irg;
2008 dbg_info *dbg = get_irn_dbg_info(node);
2009 ir_mode *mode = get_irn_mode(node);
2010 ir_node *block = transform_node(env, get_nodes_block(node));
2011 ir_node *cmp_proj = get_Mux_sel(node);
2012 ir_node *psi_true = get_Psi_val(node, 0);
2013 ir_node *psi_default = get_Psi_default(node);
2014 ir_node *new_psi_true = transform_node(env, psi_true);
2015 ir_node *new_psi_default = transform_node(env, psi_default);
2016 ir_node *noreg = ia32_new_NoReg_gp(cg);
2017 ir_node *nomem = new_rd_NoMem(irg);
2018 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2019 ir_node *new_cmp_a, *new_cmp_b;
2023 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2025 cmp = get_Proj_pred(cmp_proj);
2026 cmp_a = get_Cmp_left(cmp);
2027 cmp_b = get_Cmp_right(cmp);
2028 cmp_mode = get_irn_mode(cmp_a);
2029 new_cmp_a = transform_node(env, cmp_a);
2030 new_cmp_b = transform_node(env, cmp_b);
2032 pnc = get_Proj_proj(cmp_proj);
2033 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2034 pnc |= ia32_pn_Cmp_Unsigned;
2037 if (mode_is_float(mode)) {
2038 /* floating point psi */
2041 /* 1st case: compare operands are float too */
2043 /* psi(cmp(a, b), t, f) can be done as: */
2044 /* tmp = cmp a, b */
2045 /* tmp2 = t and tmp */
2046 /* tmp3 = f and not tmp */
2047 /* res = tmp2 or tmp3 */
2049 /* in case the compare operands are int, we move them into xmm register */
2050 if (! mode_is_float(get_irn_mode(cmp_a))) {
2051 new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E);
2052 new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E);
2054 pnc |= 8; /* transform integer compare to fp compare */
2057 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2058 set_ia32_pncode(new_op, pnc);
2059 set_ia32_am_support(new_op, ia32_am_Source);
2060 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2062 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2063 set_ia32_am_support(and1, ia32_am_None);
2064 set_ia32_commutative(and1);
2065 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2067 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2068 set_ia32_am_support(and2, ia32_am_None);
2069 set_ia32_commutative(and2);
2070 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2072 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
2073 set_ia32_am_support(new_op, ia32_am_None);
2074 set_ia32_commutative(new_op);
2075 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2079 new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2080 set_ia32_pncode(new_op, pnc);
2081 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2086 construct_binop_func *set_func = NULL;
2087 cmov_func_t *cmov_func = NULL;
2089 if (mode_is_float(get_irn_mode(cmp_a))) {
2090 /* 1st case: compare operands are floats */
2095 set_func = new_rd_ia32_xCmpSet;
2096 cmov_func = new_rd_ia32_xCmpCMov;
2100 set_func = new_rd_ia32_vfCmpSet;
2101 cmov_func = new_rd_ia32_vfCmpCMov;
2104 pnc &= ~0x8; /* fp compare -> int compare */
2107 /* 2nd case: compare operand are integer too */
2108 set_func = new_rd_ia32_CmpSet;
2109 cmov_func = new_rd_ia32_CmpCMov;
2112 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2113 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2114 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2115 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2116 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2117 set_ia32_pncode(new_op, pnc);
2119 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2120 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2121 /* we invert condition and set default to 0 */
2122 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2123 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2126 /* otherwise: use CMOVcc */
2127 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2128 set_ia32_pncode(new_op, pnc);
2131 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2134 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2135 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2136 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2137 set_ia32_pncode(new_op, pnc);
2138 set_ia32_am_support(new_op, ia32_am_Source);
2140 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2141 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2142 /* we invert condition and set default to 0 */
2143 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2144 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2145 set_ia32_am_support(new_op, ia32_am_Source);
2148 /* otherwise: use CMOVcc */
2149 new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2150 set_ia32_pncode(new_op, pnc);
2151 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2161 * Following conversion rules apply:
2165 * 1) n bit -> m bit n > m (downscale)
2167 * 2) n bit -> m bit n == m (sign change)
2169 * 3) n bit -> m bit n < m (upscale)
2170 * a) source is signed: movsx
2171 * b) source is unsigned: and with lower bits sets
2175 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2179 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2183 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2184 * x87 is mode_E internally, conversions happen only at load and store
2185 * in non-strict semantic
2189 * Create a conversion from x87 state register to general purpose.
2191 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2192 ia32_code_gen_t *cg = env->cg;
2193 ir_graph *irg = env->irg;
2194 dbg_info *dbg = get_irn_dbg_info(node);
2195 ir_node *block = transform_node(env, get_nodes_block(node));
2196 ir_node *noreg = ia32_new_NoReg_gp(cg);
2197 ir_node *op = get_Conv_op(node);
2198 ir_node *new_op = transform_node(env, op);
2199 ir_node *fist, *load;
2200 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2203 fist = new_rd_ia32_vfist(dbg, irg, block,
2204 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2206 set_ia32_use_frame(fist);
2207 set_ia32_am_support(fist, ia32_am_Dest);
2208 set_ia32_op_type(fist, ia32_AddrModeD);
2209 set_ia32_am_flavour(fist, ia32_am_B);
2210 set_ia32_ls_mode(fist, mode_Iu);
2211 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2214 load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist);
2216 set_ia32_use_frame(load);
2217 set_ia32_am_support(load, ia32_am_Source);
2218 set_ia32_op_type(load, ia32_AddrModeS);
2219 set_ia32_am_flavour(load, ia32_am_B);
2220 set_ia32_ls_mode(load, mode_Iu);
2221 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2223 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2227 * Create a conversion from general purpose to x87 register
2229 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2231 ia32_code_gen_t *cg = env->cg;
2233 ir_graph *irg = env->irg;
2234 dbg_info *dbg = get_irn_dbg_info(node);
2235 ir_mode *mode = get_irn_mode(node);
2236 ir_node *block = transform_node(env, get_nodes_block(node));
2237 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2238 ir_node *nomem = new_NoMem();
2239 ir_node *op = get_Conv_op(node);
2240 ir_node *new_op = transform_node(env, op);
2241 ir_node *fild, *store;
2244 /* first convert to 32 bit if necessary */
2245 src_bits = get_mode_size_bits(src_mode);
2246 if (src_bits == 8) {
2247 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2248 set_ia32_am_support(new_op, ia32_am_Source);
2249 set_ia32_ls_mode(new_op, src_mode);
2250 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2251 } else if (src_bits < 32) {
2252 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2253 set_ia32_am_support(new_op, ia32_am_Source);
2254 set_ia32_ls_mode(new_op, src_mode);
2255 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2259 store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2261 set_ia32_use_frame(store);
2262 set_ia32_am_support(store, ia32_am_Dest);
2263 set_ia32_op_type(store, ia32_AddrModeD);
2264 set_ia32_am_flavour(store, ia32_am_OB);
2265 set_ia32_ls_mode(store, mode_Iu);
2268 fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store);
2270 set_ia32_use_frame(fild);
2271 set_ia32_am_support(fild, ia32_am_Source);
2272 set_ia32_op_type(fild, ia32_AddrModeS);
2273 set_ia32_am_flavour(fild, ia32_am_OB);
2274 set_ia32_ls_mode(fild, mode);
2276 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2280 * Transforms a Conv node.
2282 * @param env The transformation environment
2283 * @return The created ia32 Conv node
2285 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2286 ir_graph *irg = env->irg;
2287 dbg_info *dbg = get_irn_dbg_info(node);
2288 ir_node *op = get_Conv_op(node);
2289 ir_mode *src_mode = get_irn_mode(op);
2290 ir_mode *tgt_mode = get_irn_mode(node);
2291 int src_bits = get_mode_size_bits(src_mode);
2292 int tgt_bits = get_mode_size_bits(tgt_mode);
2293 ir_node *block = transform_node(env, get_nodes_block(node));
2295 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2296 ir_node *nomem = new_rd_NoMem(irg);
2297 ir_node *new_op = transform_node(env, op);
2298 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2300 if (src_mode == tgt_mode) {
2301 /* this should be optimized already, but who knows... */
2302 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2303 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2307 if (mode_is_float(src_mode)) {
2308 /* we convert from float ... */
2309 if (mode_is_float(tgt_mode)) {
2311 if (USE_SSE2(env->cg)) {
2312 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2313 res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2314 set_ia32_ls_mode(res, tgt_mode);
2316 // Matze: TODO what about strict convs?
2317 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2322 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2323 if (USE_SSE2(env->cg)) {
2324 res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2325 set_ia32_ls_mode(res, src_mode);
2327 return gen_x87_fp_to_gp(env, node);
2331 /* we convert from int ... */
2332 if (mode_is_float(tgt_mode)) {
2335 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2336 if (USE_SSE2(env->cg)) {
2337 res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2338 set_ia32_ls_mode(res, tgt_mode);
2339 if(src_bits == 32) {
2340 set_ia32_am_support(res, ia32_am_Source);
2343 return gen_x87_gp_to_fp(env, node, src_mode);
2347 ir_mode *smaller_mode;
2350 if (src_bits == tgt_bits) {
2351 DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2355 if(src_bits < tgt_bits) {
2356 smaller_mode = src_mode;
2357 smaller_bits = src_bits;
2359 smaller_mode = tgt_mode;
2360 smaller_bits = tgt_bits;
2363 // The following is not correct, we can't change the mode,
2364 // maybe others are using the load too
2365 // better move this to a separate phase!
2368 if(is_Proj(new_op)) {
2369 /* load operations do already sign/zero extend, so we have
2370 * nothing left to do */
2371 ir_node *pred = get_Proj_pred(new_op);
2372 if(is_ia32_Load(pred)) {
2373 set_ia32_ls_mode(pred, smaller_mode);
2379 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2380 if (smaller_bits == 8) {
2381 res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2382 set_ia32_ls_mode(res, smaller_mode);
2384 res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2385 set_ia32_ls_mode(res, smaller_mode);
2387 set_ia32_am_support(res, ia32_am_Source);
2391 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2398 /********************************************
2401 * | |__ ___ _ __ ___ __| | ___ ___
2402 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2403 * | |_) | __/ | | | (_) | (_| | __/\__ \
2404 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2406 ********************************************/
2408 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2409 ir_node *new_op = NULL;
2410 ir_graph *irg = env->irg;
2411 dbg_info *dbg = get_irn_dbg_info(node);
2412 ir_node *block = transform_node(env, get_nodes_block(node));
2413 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2414 ir_node *nomem = new_rd_NoMem(env->irg);
2415 ir_node *ptr = get_irn_n(node, 0);
2416 ir_node *new_ptr = transform_node(env, ptr);
2417 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2418 ir_mode *load_mode = get_irn_mode(node);
2422 if (mode_is_float(load_mode)) {
2424 if (USE_SSE2(env->cg)) {
2425 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem);
2426 pn_res = pn_ia32_xLoad_res;
2428 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem);
2429 pn_res = pn_ia32_vfld_res;
2434 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
2435 proj_mode = mode_Iu;
2436 pn_res = pn_ia32_Load_res;
2439 set_ia32_frame_ent(new_op, ent);
2440 set_ia32_use_frame(new_op);
2442 set_ia32_am_support(new_op, ia32_am_Source);
2443 set_ia32_op_type(new_op, ia32_AddrModeS);
2444 set_ia32_am_flavour(new_op, ia32_am_B);
2445 set_ia32_ls_mode(new_op, load_mode);
2446 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2448 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2450 return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res);
2454 * Transforms a FrameAddr into an ia32 Add.
2456 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2457 ir_graph *irg = env->irg;
2458 dbg_info *dbg = get_irn_dbg_info(node);
2459 ir_node *block = transform_node(env, get_nodes_block(node));
2460 ir_node *op = get_irn_n(node, 0);
2461 ir_node *new_op = transform_node(env, op);
2463 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2465 res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg);
2466 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2467 set_ia32_am_support(res, ia32_am_Full);
2468 set_ia32_use_frame(res);
2469 set_ia32_am_flavour(res, ia32_am_OB);
2471 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2477 * Transforms a FrameLoad into an ia32 Load.
2479 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2480 ir_node *new_op = NULL;
2481 ir_graph *irg = env->irg;
2482 dbg_info *dbg = get_irn_dbg_info(node);
2483 ir_node *block = transform_node(env, get_nodes_block(node));
2484 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2485 ir_node *mem = get_irn_n(node, 0);
2486 ir_node *ptr = get_irn_n(node, 1);
2487 ir_node *new_mem = transform_node(env, mem);
2488 ir_node *new_ptr = transform_node(env, ptr);
2489 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2490 ir_mode *mode = get_type_mode(get_entity_type(ent));
2491 ir_node *projs[pn_Load_max];
2493 ia32_collect_Projs(node, projs, pn_Load_max);
2495 if (mode_is_float(mode)) {
2497 if (USE_SSE2(env->cg)) {
2498 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem);
2501 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
2505 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem);
2508 set_ia32_frame_ent(new_op, ent);
2509 set_ia32_use_frame(new_op);
2511 set_ia32_am_support(new_op, ia32_am_Source);
2512 set_ia32_op_type(new_op, ia32_AddrModeS);
2513 set_ia32_am_flavour(new_op, ia32_am_B);
2514 set_ia32_ls_mode(new_op, mode);
2516 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2523 * Transforms a FrameStore into an ia32 Store.
2525 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2526 ir_node *new_op = NULL;
2527 ir_graph *irg = env->irg;
2528 dbg_info *dbg = get_irn_dbg_info(node);
2529 ir_node *block = transform_node(env, get_nodes_block(node));
2530 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2531 ir_node *mem = get_irn_n(node, 0);
2532 ir_node *ptr = get_irn_n(node, 1);
2533 ir_node *val = get_irn_n(node, 2);
2534 ir_node *new_mem = transform_node(env, mem);
2535 ir_node *new_ptr = transform_node(env, ptr);
2536 ir_node *new_val = transform_node(env, val);
2537 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2538 ir_mode *mode = get_irn_mode(val);
2540 if (mode_is_float(mode)) {
2542 if (USE_SSE2(env->cg)) {
2543 new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2546 new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2549 else if (get_mode_size_bits(mode) == 8) {
2550 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2553 new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2556 set_ia32_frame_ent(new_op, ent);
2557 set_ia32_use_frame(new_op);
2559 set_ia32_am_support(new_op, ia32_am_Dest);
2560 set_ia32_op_type(new_op, ia32_AddrModeD);
2561 set_ia32_am_flavour(new_op, ia32_am_B);
2562 set_ia32_ls_mode(new_op, mode);
2564 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2570 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2572 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2573 ir_graph *irg = env->irg;
2576 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2577 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2578 ir_entity *ent = get_irg_entity(irg);
2579 ir_type *tp = get_entity_type(ent);
2582 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2583 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2585 int pn_ret_val, pn_ret_mem, arity, i;
2587 assert(ret_val != NULL);
2588 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2589 return duplicate_node(env, node);
2592 res_type = get_method_res_type(tp, 0);
2594 if (!is_Primitive_type(res_type)) {
2595 return duplicate_node(env, node);
2598 mode = get_type_mode(res_type);
2599 if (!mode_is_float(mode)) {
2600 return duplicate_node(env, node);
2603 assert(get_method_n_ress(tp) == 1);
2605 pn_ret_val = get_Proj_proj(ret_val);
2606 pn_ret_mem = get_Proj_proj(ret_mem);
2608 /* get the Barrier */
2609 barrier = get_Proj_pred(ret_val);
2611 /* get result input of the Barrier */
2612 ret_val = get_irn_n(barrier, pn_ret_val);
2613 new_ret_val = transform_node(env, ret_val);
2615 /* get memory input of the Barrier */
2616 ret_mem = get_irn_n(barrier, pn_ret_mem);
2617 new_ret_mem = transform_node(env, ret_mem);
2619 frame = get_irg_frame(irg);
2621 dbg = get_irn_dbg_info(barrier);
2622 block = transform_node(env, get_nodes_block(barrier));
2624 /* store xmm0 onto stack */
2625 sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, frame, new_ret_val, new_ret_mem);
2626 set_ia32_ls_mode(sse_store, mode);
2627 set_ia32_op_type(sse_store, ia32_AddrModeD);
2628 set_ia32_use_frame(sse_store);
2629 set_ia32_am_flavour(sse_store, ia32_am_B);
2630 set_ia32_am_support(sse_store, ia32_am_Dest);
2633 fld = new_rd_ia32_SetST0(dbg, irg, block, frame, sse_store);
2634 set_ia32_ls_mode(fld, mode);
2635 set_ia32_op_type(fld, ia32_AddrModeS);
2636 set_ia32_use_frame(fld);
2637 set_ia32_am_flavour(fld, ia32_am_B);
2638 set_ia32_am_support(fld, ia32_am_Source);
2640 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2641 fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
2642 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2644 /* create a new barrier */
2645 arity = get_irn_arity(barrier);
2646 in = alloca(arity * sizeof(in[0]));
2647 for(i = 0; i < arity; ++i) {
2649 if(i == pn_ret_val) {
2651 } else if(i == pn_ret_mem) {
2654 ir_node *in = get_irn_n(barrier, i);
2655 new_in = transform_node(env, in);
2660 new_barrier = new_ir_node(dbg, irg, block,
2661 get_irn_op(barrier), get_irn_mode(barrier),
2663 copy_node_attr(barrier, new_barrier);
2664 duplicate_deps(env, barrier, new_barrier);
2665 set_new_node(barrier, new_barrier);
2666 mark_irn_visited(barrier);
2668 /* transform normally */
2669 return duplicate_node(env, node);
2673 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2675 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2677 ir_graph *irg = env->irg;
2678 dbg_info *dbg = get_irn_dbg_info(node);
2679 ir_node *block = transform_node(env, get_nodes_block(node));
2680 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2681 ir_node *new_sz = transform_node(env, sz);
2682 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2683 ir_node *new_sp = transform_node(env, sp);
2684 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2685 ir_node *nomem = new_NoMem();
2687 /* ia32 stack grows in reverse direction, make a SubSP */
2688 new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2689 set_ia32_am_support(new_op, ia32_am_Source);
2690 fold_immediate(env, new_op, 2, 3);
2692 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2698 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2700 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2702 ir_graph *irg = env->irg;
2703 dbg_info *dbg = get_irn_dbg_info(node);
2704 ir_node *block = transform_node(env, get_nodes_block(node));
2705 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2706 ir_node *new_sz = transform_node(env, sz);
2707 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2708 ir_node *new_sp = transform_node(env, sp);
2709 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2710 ir_node *nomem = new_NoMem();
2712 /* ia32 stack grows in reverse direction, make an AddSP */
2713 new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2714 set_ia32_am_support(new_op, ia32_am_Source);
2715 fold_immediate(env, new_op, 2, 3);
2717 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2723 * This function just sets the register for the Unknown node
2724 * as this is not done during register allocation because Unknown
2725 * is an "ignore" node.
2727 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2728 ir_mode *mode = get_irn_mode(node);
2730 if (mode_is_float(mode)) {
2731 if (USE_SSE2(env->cg))
2732 return ia32_new_Unknown_xmm(env->cg);
2734 return ia32_new_Unknown_vfp(env->cg);
2735 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2736 return ia32_new_Unknown_gp(env->cg);
2738 assert(0 && "unsupported Unknown-Mode");
2745 * Change some phi modes
2747 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2748 ir_graph *irg = env->irg;
2749 dbg_info *dbg = get_irn_dbg_info(node);
2750 ir_mode *mode = get_irn_mode(node);
2751 ir_node *block = transform_node(env, get_nodes_block(node));
2755 if(mode_is_int(mode) || mode_is_reference(mode)) {
2756 // we shouldn't have any 64bit stuff around anymore
2757 assert(get_mode_size_bits(mode) <= 32);
2758 // all integer operations are on 32bit registers now
2760 } else if(mode_is_float(mode)) {
2761 assert(mode == mode_D || mode == mode_F);
2762 // all float operations are on mode_E registers
2766 /* phi nodes allow loops, so we use the old arguments for now
2767 * and fix this later */
2768 phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node),
2769 get_irn_in(node) + 1);
2770 copy_node_attr(node, phi);
2771 duplicate_deps(env, node, phi);
2773 set_new_node(node, phi);
2775 /* put the preds in the worklist */
2776 arity = get_irn_arity(node);
2777 for(i = 0; i < arity; ++i) {
2778 ir_node *pred = get_irn_n(node, i);
2779 pdeq_putr(env->worklist, pred);
2785 /**********************************************************************
2788 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2789 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2790 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2791 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2793 **********************************************************************/
2795 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2797 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2800 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2801 ir_node *val, ir_node *mem);
2804 * Transforms a lowered Load into a "real" one.
2806 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2807 ir_graph *irg = env->irg;
2808 dbg_info *dbg = get_irn_dbg_info(node);
2809 ir_node *block = transform_node(env, get_nodes_block(node));
2810 ir_mode *mode = get_ia32_ls_mode(node);
2812 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2813 ir_node *ptr = get_irn_n(node, 0);
2814 ir_node *mem = get_irn_n(node, 1);
2815 ir_node *new_ptr = transform_node(env, ptr);
2816 ir_node *new_mem = transform_node(env, mem);
2819 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2820 lowering we have x87 nodes, so we need to enforce simulation.
2822 if (mode_is_float(mode)) {
2824 if (fp_unit == fp_x87)
2828 new_op = func(dbg, irg, block, new_ptr, noreg, new_mem);
2830 set_ia32_am_support(new_op, ia32_am_Source);
2831 set_ia32_op_type(new_op, ia32_AddrModeS);
2832 set_ia32_am_flavour(new_op, ia32_am_OB);
2833 set_ia32_am_offs_int(new_op, 0);
2834 set_ia32_am_scale(new_op, 1);
2835 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2836 if(is_ia32_am_sc_sign(node))
2837 set_ia32_am_sc_sign(new_op);
2838 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2839 if(is_ia32_use_frame(node)) {
2840 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2841 set_ia32_use_frame(new_op);
2844 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2850 * Transforms a lowered Store into a "real" one.
2852 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2853 ir_graph *irg = env->irg;
2854 dbg_info *dbg = get_irn_dbg_info(node);
2855 ir_node *block = transform_node(env, get_nodes_block(node));
2856 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2857 ir_mode *mode = get_ia32_ls_mode(node);
2860 ia32_am_flavour_t am_flav = ia32_B;
2861 ir_node *ptr = get_irn_n(node, 0);
2862 ir_node *val = get_irn_n(node, 1);
2863 ir_node *mem = get_irn_n(node, 2);
2864 ir_node *new_ptr = transform_node(env, ptr);
2865 ir_node *new_val = transform_node(env, val);
2866 ir_node *new_mem = transform_node(env, mem);
2869 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2870 lowering we have x87 nodes, so we need to enforce simulation.
2872 if (mode_is_float(mode)) {
2874 if (fp_unit == fp_x87)
2878 new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2880 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2882 add_ia32_am_offs_int(new_op, am_offs);
2885 set_ia32_am_support(new_op, ia32_am_Dest);
2886 set_ia32_op_type(new_op, ia32_AddrModeD);
2887 set_ia32_am_flavour(new_op, am_flav);
2888 set_ia32_ls_mode(new_op, mode);
2889 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2890 set_ia32_use_frame(new_op);
2892 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2899 * Transforms an ia32_l_XXX into a "real" XXX node
2901 * @param env The transformation environment
2902 * @return the created ia32 XXX node
2904 #define GEN_LOWERED_OP(op) \
2905 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2906 ir_mode *mode = get_irn_mode(node); \
2907 if (mode_is_float(mode)) \
2909 return gen_binop(env, node, get_binop_left(node), \
2910 get_binop_right(node), new_rd_ia32_##op); \
2913 #define GEN_LOWERED_x87_OP(op) \
2914 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2916 FORCE_x87(env->cg); \
2917 new_op = gen_binop_float(env, node, get_binop_left(node), \
2918 get_binop_right(node), new_rd_ia32_##op); \
2922 #define GEN_LOWERED_UNOP(op) \
2923 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2924 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2927 #define GEN_LOWERED_SHIFT_OP(op) \
2928 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2929 return gen_shift_binop(env, node, get_binop_left(node), \
2930 get_binop_right(node), new_rd_ia32_##op); \
2933 #define GEN_LOWERED_LOAD(op, fp_unit) \
2934 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2935 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2938 #define GEN_LOWERED_STORE(op, fp_unit) \
2939 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2940 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2947 GEN_LOWERED_OP(IMul)
2949 GEN_LOWERED_x87_OP(vfprem)
2950 GEN_LOWERED_x87_OP(vfmul)
2951 GEN_LOWERED_x87_OP(vfsub)
2953 GEN_LOWERED_UNOP(Neg)
2955 GEN_LOWERED_LOAD(vfild, fp_x87)
2956 GEN_LOWERED_LOAD(Load, fp_none)
2957 GEN_LOWERED_STORE(vfist, fp_x87)
2958 GEN_LOWERED_STORE(Store, fp_none)
2960 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2961 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2962 ir_graph *irg = env->irg;
2963 dbg_info *dbg = get_irn_dbg_info(node);
2964 ir_node *block = transform_node(env, get_nodes_block(node));
2965 ir_node *left = get_binop_left(node);
2966 ir_node *right = get_binop_right(node);
2967 ir_node *new_left = transform_node(env, left);
2968 ir_node *new_right = transform_node(env, right);
2971 vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2972 clear_ia32_commutative(vfdiv);
2973 set_ia32_am_support(vfdiv, ia32_am_Source);
2974 fold_immediate(env, vfdiv, 2, 3);
2976 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2984 * Transforms a l_MulS into a "real" MulS node.
2986 * @param env The transformation environment
2987 * @return the created ia32 Mul node
2989 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
2990 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2991 ir_graph *irg = env->irg;
2992 dbg_info *dbg = get_irn_dbg_info(node);
2993 ir_node *block = transform_node(env, get_nodes_block(node));
2994 ir_node *left = get_binop_left(node);
2995 ir_node *right = get_binop_right(node);
2996 ir_node *new_left = transform_node(env, left);
2997 ir_node *new_right = transform_node(env, right);
3000 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3001 /* and then skip the result Proj, because all needed Projs are already there. */
3002 ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3003 clear_ia32_commutative(muls);
3004 set_ia32_am_support(muls, ia32_am_Source);
3005 fold_immediate(env, muls, 2, 3);
3007 /* check if EAX and EDX proj exist, add missing one */
3008 in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX);
3009 in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX);
3010 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3012 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3017 GEN_LOWERED_SHIFT_OP(Shl)
3018 GEN_LOWERED_SHIFT_OP(Shr)
3019 GEN_LOWERED_SHIFT_OP(Sar)
3022 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3023 * op1 - target to be shifted
3024 * op2 - contains bits to be shifted into target
3026 * Only op3 can be an immediate.
3028 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3029 ir_node *op1, ir_node *op2,
3031 ir_node *new_op = NULL;
3032 ir_graph *irg = env->irg;
3033 dbg_info *dbg = get_irn_dbg_info(node);
3034 ir_node *block = transform_node(env, get_nodes_block(node));
3035 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3036 ir_node *nomem = new_NoMem();
3038 ir_node *new_op1 = transform_node(env, op1);
3039 ir_node *new_op2 = transform_node(env, op2);
3040 ir_node *new_count = transform_node(env, count);
3042 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
3044 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3046 /* Check if immediate optimization is on and */
3047 /* if it's an operation with immediate. */
3048 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3050 /* Limit imm_op within range imm8 */
3052 tv = get_ia32_Immop_tarval(imm_op);
3055 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3056 set_ia32_Immop_tarval(imm_op, tv);
3063 /* integer operations */
3065 /* This is ShiftD with const */
3066 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
3068 if (is_ia32_l_ShlD(node))
3069 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3070 new_op1, new_op2, noreg, nomem);
3072 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3073 new_op1, new_op2, noreg, nomem);
3074 copy_ia32_Immop_attr(new_op, imm_op);
3077 /* This is a normal ShiftD */
3078 DB((mod, LEVEL_1, "ShiftD binop ..."));
3079 if (is_ia32_l_ShlD(node))
3080 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3081 new_op1, new_op2, new_count, nomem);
3083 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3084 new_op1, new_op2, new_count, nomem);
3087 /* set AM support */
3088 // Matze: node has unsupported format (6inputs)
3089 //set_ia32_am_support(new_op, ia32_am_Dest);
3091 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3093 set_ia32_emit_cl(new_op);
3098 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3099 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3100 get_irn_n(node, 1), get_irn_n(node, 2));
3103 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3104 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3105 get_irn_n(node, 1), get_irn_n(node, 2));
3109 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3111 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3112 ia32_code_gen_t *cg = env->cg;
3113 ir_node *res = NULL;
3114 ir_graph *irg = env->irg;
3115 dbg_info *dbg = get_irn_dbg_info(node);
3116 ir_node *block = transform_node(env, get_nodes_block(node));
3117 ir_node *ptr = get_irn_n(node, 0);
3118 ir_node *val = get_irn_n(node, 1);
3119 ir_node *new_val = transform_node(env, val);
3120 ir_node *mem = get_irn_n(node, 2);
3121 ir_node *noreg, *new_ptr, *new_mem;
3127 noreg = ia32_new_NoReg_gp(cg);
3128 new_mem = transform_node(env, mem);
3129 new_ptr = transform_node(env, ptr);
3131 /* Store x87 -> MEM */
3132 res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3133 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3134 set_ia32_use_frame(res);
3135 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3136 set_ia32_am_support(res, ia32_am_Dest);
3137 set_ia32_am_flavour(res, ia32_B);
3138 set_ia32_op_type(res, ia32_AddrModeD);
3140 /* Load MEM -> SSE */
3141 res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res);
3142 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3143 set_ia32_use_frame(res);
3144 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3145 set_ia32_am_support(res, ia32_am_Source);
3146 set_ia32_am_flavour(res, ia32_B);
3147 set_ia32_op_type(res, ia32_AddrModeS);
3148 res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res);
3154 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3156 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3157 ia32_code_gen_t *cg = env->cg;
3158 ir_graph *irg = env->irg;
3159 dbg_info *dbg = get_irn_dbg_info(node);
3160 ir_node *block = transform_node(env, get_nodes_block(node));
3161 ir_node *res = NULL;
3162 ir_node *ptr = get_irn_n(node, 0);
3163 ir_node *val = get_irn_n(node, 1);
3164 ir_node *mem = get_irn_n(node, 2);
3165 ir_entity *fent = get_ia32_frame_ent(node);
3166 ir_mode *lsmode = get_ia32_ls_mode(node);
3167 ir_node *new_val = transform_node(env, val);
3168 ir_node *noreg, *new_ptr, *new_mem;
3171 if (!USE_SSE2(cg)) {
3172 /* SSE unit is not used -> skip this node. */
3176 noreg = ia32_new_NoReg_gp(cg);
3177 new_val = transform_node(env, val);
3178 new_ptr = transform_node(env, ptr);
3179 new_mem = transform_node(env, mem);
3181 /* Store SSE -> MEM */
3182 if (is_ia32_xLoad(skip_Proj(new_val))) {
3183 ir_node *ld = skip_Proj(new_val);
3185 /* we can vfld the value directly into the fpu */
3186 fent = get_ia32_frame_ent(ld);
3187 ptr = get_irn_n(ld, 0);
3188 offs = get_ia32_am_offs_int(ld);
3190 res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3191 set_ia32_frame_ent(res, fent);
3192 set_ia32_use_frame(res);
3193 set_ia32_ls_mode(res, lsmode);
3194 set_ia32_am_support(res, ia32_am_Dest);
3195 set_ia32_am_flavour(res, ia32_B);
3196 set_ia32_op_type(res, ia32_AddrModeD);
3200 /* Load MEM -> x87 */
3201 res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
3202 set_ia32_frame_ent(res, fent);
3203 set_ia32_use_frame(res);
3204 set_ia32_ls_mode(res, lsmode);
3205 add_ia32_am_offs_int(res, offs);
3206 set_ia32_am_support(res, ia32_am_Source);
3207 set_ia32_am_flavour(res, ia32_B);
3208 set_ia32_op_type(res, ia32_AddrModeS);
3209 res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res);
3214 /*********************************************************
3217 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3218 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3219 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3220 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3222 *********************************************************/
3225 * the BAD transformer.
3227 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3228 panic("No transform function for %+F available.\n", node);
3232 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3233 /* end has to be duplicated manually because we need a dynamic in array */
3234 ir_graph *irg = env->irg;
3235 dbg_info *dbg = get_irn_dbg_info(node);
3236 ir_node *block = transform_node(env, get_nodes_block(node));
3240 new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL);
3241 copy_node_attr(node, new_end);
3242 duplicate_deps(env, node, new_end);
3244 set_irg_end(irg, new_end);
3245 set_new_node(new_end, new_end);
3247 /* transform preds */
3248 arity = get_irn_arity(node);
3249 for(i = 0; i < arity; ++i) {
3250 ir_node *in = get_irn_n(node, i);
3251 ir_node *new_in = transform_node(env, in);
3253 add_End_keepalive(new_end, new_in);
3259 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3260 ir_graph *irg = env->irg;
3261 dbg_info *dbg = get_irn_dbg_info(node);
3262 ir_node *start_block = env->old_anchors[anchor_start_block];
3267 * We replace the ProjX from the start node with a jump,
3268 * so the startblock has no preds anymore now
3270 if(node == start_block) {
3271 return new_rd_Block(dbg, irg, 0, NULL);
3274 /* we use the old blocks for now, because jumps allow cycles in the graph
3275 * we have to fix this later */
3276 block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node),
3277 get_irn_arity(node), get_irn_in(node) + 1);
3278 copy_node_attr(node, block);
3280 #ifdef DEBUG_libfirm
3281 block->node_nr = node->node_nr;
3283 set_new_node(node, block);
3285 /* put the preds in the worklist */
3286 arity = get_irn_arity(node);
3287 for(i = 0; i < arity; ++i) {
3288 ir_node *in = get_irn_n(node, i);
3289 pdeq_putr(env->worklist, in);
3295 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3296 ir_graph *irg = env->irg;
3297 ir_node *block = transform_node(env, get_nodes_block(node));
3298 dbg_info *dbg = get_irn_dbg_info(node);
3299 ir_node *pred = get_Proj_pred(node);
3300 ir_node *new_pred = transform_node(env, pred);
3301 long proj = get_Proj_proj(node);
3303 if(proj == pn_be_AddSP_res) {
3304 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3305 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3307 } else if(proj == pn_be_AddSP_M) {
3308 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3312 return new_rd_Unknown(irg, get_irn_mode(node));
3315 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3316 ir_graph *irg = env->irg;
3317 ir_node *block = transform_node(env, get_nodes_block(node));
3318 dbg_info *dbg = get_irn_dbg_info(node);
3319 ir_node *pred = get_Proj_pred(node);
3320 ir_node *new_pred = transform_node(env, pred);
3321 long proj = get_Proj_proj(node);
3323 if(proj == pn_be_SubSP_res) {
3324 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3325 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3327 } else if(proj == pn_be_SubSP_M) {
3328 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3332 return new_rd_Unknown(irg, get_irn_mode(node));
3335 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3336 ir_graph *irg = env->irg;
3337 ir_node *block = transform_node(env, get_nodes_block(node));
3338 dbg_info *dbg = get_irn_dbg_info(node);
3339 ir_node *pred = get_Proj_pred(node);
3340 ir_node *new_pred = transform_node(env, pred);
3341 long proj = get_Proj_proj(node);
3343 /* renumber the proj */
3344 if(is_ia32_Load(new_pred)) {
3345 if(proj == pn_Load_res) {
3346 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3347 } else if(proj == pn_Load_M) {
3348 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3350 } else if(is_ia32_xLoad(new_pred)) {
3351 if(proj == pn_Load_res) {
3352 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
3353 } else if(proj == pn_Load_M) {
3354 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3356 } else if(is_ia32_vfld(new_pred)) {
3357 if(proj == pn_Load_res) {
3358 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
3359 } else if(proj == pn_Load_M) {
3360 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3365 return new_rd_Unknown(irg, get_irn_mode(node));
3368 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3369 ir_graph *irg = env->irg;
3370 dbg_info *dbg = get_irn_dbg_info(node);
3371 ir_node *block = transform_node(env, get_nodes_block(node));
3372 ir_mode *mode = get_irn_mode(node);
3374 ir_node *pred = get_Proj_pred(node);
3375 ir_node *new_pred = transform_node(env, pred);
3376 long proj = get_Proj_proj(node);
3378 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3380 switch(get_irn_opcode(pred)) {
3384 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3386 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3394 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3396 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3404 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3405 case pn_DivMod_res_div:
3406 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3407 case pn_DivMod_res_mod:
3408 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3418 return new_rd_Unknown(irg, mode);
3421 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3423 ir_graph *irg = env->irg;
3424 dbg_info *dbg = get_irn_dbg_info(node);
3425 ir_node *block = transform_node(env, get_nodes_block(node));
3426 ir_mode *mode = get_irn_mode(node);
3428 ir_node *pred = get_Proj_pred(node);
3429 ir_node *new_pred = transform_node(env, pred);
3430 long proj = get_Proj_proj(node);
3433 case pn_CopyB_M_regular:
3434 if(is_ia32_CopyB_i(new_pred)) {
3435 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3437 } else if(is_ia32_CopyB(new_pred)) {
3438 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3447 return new_rd_Unknown(irg, mode);
3450 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3452 ir_graph *irg = env->irg;
3453 dbg_info *dbg = get_irn_dbg_info(node);
3454 ir_node *block = transform_node(env, get_nodes_block(node));
3455 ir_mode *mode = get_irn_mode(node);
3457 ir_node *pred = get_Proj_pred(node);
3458 ir_node *new_pred = transform_node(env, pred);
3459 long proj = get_Proj_proj(node);
3462 case pn_ia32_l_vfdiv_M:
3463 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3464 case pn_ia32_l_vfdiv_res:
3465 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
3470 return new_rd_Unknown(irg, mode);
3473 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3475 ir_graph *irg = env->irg;
3476 dbg_info *dbg = get_irn_dbg_info(node);
3477 ir_node *block = transform_node(env, get_nodes_block(node));
3478 ir_mode *mode = get_irn_mode(node);
3480 ir_node *pred = get_Proj_pred(node);
3481 ir_node *new_pred = transform_node(env, pred);
3482 long proj = get_Proj_proj(node);
3486 if(is_ia32_xDiv(new_pred)) {
3487 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3489 } else if(is_ia32_vfdiv(new_pred)) {
3490 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3495 if(is_ia32_xDiv(new_pred)) {
3496 return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
3498 } else if(is_ia32_vfdiv(new_pred)) {
3499 return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
3508 return new_rd_Unknown(irg, mode);
3511 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3512 ir_graph *irg = env->irg;
3513 //dbg_info *dbg = get_irn_dbg_info(node);
3514 dbg_info *dbg = NULL;
3515 ir_node *block = transform_node(env, get_nodes_block(node));
3517 ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu);
3522 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3523 ir_graph *irg = env->irg;
3524 dbg_info *dbg = get_irn_dbg_info(node);
3525 long proj = get_Proj_proj(node);
3526 ir_mode *mode = get_irn_mode(node);
3527 ir_node *block = transform_node(env, get_nodes_block(node));
3529 ir_node *call = get_Proj_pred(node);
3530 ir_node *new_call = transform_node(env, call);
3531 const arch_register_class_t *cls;
3533 /* The following is kinda tricky: If we're using SSE, then we have to
3534 * move the result value of the call in floating point registers to an
3535 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3536 * after the call, we have to make sure to correctly make the
3537 * MemProj and the result Proj use these 2 nodes
3539 if(proj == pn_be_Call_M_regular) {
3540 // get new node for result, are we doing the sse load/store hack?
3541 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3542 ir_node *call_res_new;
3543 ir_node *call_res_pred = NULL;
3545 if(call_res != NULL) {
3546 call_res_new = transform_node(env, call_res);
3547 call_res_pred = get_Proj_pred(call_res_new);
3550 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3551 return new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3553 assert(is_ia32_xLoad(call_res_pred));
3554 return new_rd_Proj(dbg, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3557 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3558 && USE_SSE2(env->cg)) {
3560 ir_node *frame = get_irg_frame(irg);
3561 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3563 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3565 const arch_register_class_t *cls;
3567 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3568 call_mem = new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3570 /* store st(0) onto stack */
3571 fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, call_mem);
3573 set_ia32_ls_mode(fstp, mode);
3574 set_ia32_op_type(fstp, ia32_AddrModeD);
3575 set_ia32_use_frame(fstp);
3576 set_ia32_am_flavour(fstp, ia32_am_B);
3577 set_ia32_am_support(fstp, ia32_am_Dest);
3579 /* load into SSE register */
3580 sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, noreg, fstp);
3581 set_ia32_ls_mode(sse_load, mode);
3582 set_ia32_op_type(sse_load, ia32_AddrModeS);
3583 set_ia32_use_frame(sse_load);
3584 set_ia32_am_flavour(sse_load, ia32_am_B);
3585 set_ia32_am_support(sse_load, ia32_am_Source);
3587 //mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
3588 sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode_E, pn_ia32_xLoad_res);
3590 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3592 /* get a Proj representing a caller save register */
3593 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3594 assert(is_Proj(p) && "Proj expected.");
3596 /* user of the the proj is the Keep */
3597 p = get_edge_src_irn(get_irn_out_edge_first(p));
3598 assert(be_is_Keep(p) && "Keep expected.");
3600 /* keep the result */
3601 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3602 keepin[0] = sse_load;
3603 be_new_Keep(cls, irg, block, 1, keepin);
3608 /* transform call modes to the mode_Iu or mode_E */
3609 if(mode != mode_M) {
3610 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3614 return new_rd_Proj(dbg, irg, block, new_call, mode, proj);
3617 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3618 ir_graph *irg = env->irg;
3619 dbg_info *dbg = get_irn_dbg_info(node);
3620 ir_node *pred = get_Proj_pred(node);
3621 long proj = get_Proj_proj(node);
3623 if(is_Store(pred) || be_is_FrameStore(pred)) {
3624 if(proj == pn_Store_M) {
3625 return transform_node(env, pred);
3628 return new_r_Bad(irg);
3630 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3631 return gen_Proj_Load(env, node);
3632 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3633 return gen_Proj_DivMod(env, node);
3634 } else if(is_CopyB(pred)) {
3635 return gen_Proj_CopyB(env, node);
3636 } else if(is_Quot(pred)) {
3637 return gen_Proj_Quot(env, node);
3638 } else if(is_ia32_l_vfdiv(pred)) {
3639 return gen_Proj_l_vfdiv(env, node);
3640 } else if(be_is_SubSP(pred)) {
3641 return gen_Proj_be_SubSP(env, node);
3642 } else if(be_is_AddSP(pred)) {
3643 return gen_Proj_be_AddSP(env, node);
3644 } else if(be_is_Call(pred)) {
3645 return gen_Proj_be_Call(env, node);
3646 } else if(get_irn_op(pred) == op_Start) {
3647 if(proj == pn_Start_X_initial_exec) {
3648 ir_node *block = get_nodes_block(pred);
3651 block = transform_node(env, block);
3652 // we exchange the ProjX with a jump
3653 jump = new_rd_Jmp(dbg, irg, block);
3654 ir_fprintf(stderr, "created jump: %+F\n", jump);
3657 if(node == env->old_anchors[anchor_tls]) {
3658 return gen_Proj_tls(env, node);
3662 return duplicate_node(env, node);
3666 * Enters all transform functions into the generic pointer
3668 static void register_transformers(void) {
3669 ir_op *op_Max, *op_Min, *op_Mulh;
3671 /* first clear the generic function pointer for all ops */
3672 clear_irp_opcodes_generic_func();
3674 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3675 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3714 /* transform ops from intrinsic lowering */
3736 GEN(ia32_l_X87toSSE);
3737 GEN(ia32_l_SSEtoX87);
3742 /* we should never see these nodes */
3757 /* handle generic backend nodes */
3767 /* set the register for all Unknown nodes */
3770 op_Max = get_op_Max();
3773 op_Min = get_op_Min();
3776 op_Mulh = get_op_Mulh();
3784 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3788 int deps = get_irn_deps(old_node);
3790 for(i = 0; i < deps; ++i) {
3791 ir_node *dep = get_irn_dep(old_node, i);
3792 ir_node *new_dep = transform_node(env, dep);
3794 add_irn_dep(new_node, new_dep);
3798 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3800 ir_graph *irg = env->irg;
3801 dbg_info *dbg = get_irn_dbg_info(node);
3802 ir_mode *mode = get_irn_mode(node);
3803 ir_op *op = get_irn_op(node);
3808 block = transform_node(env, get_nodes_block(node));
3810 arity = get_irn_arity(node);
3811 if(op->opar == oparity_dynamic) {
3812 new_node = new_ir_node(dbg, irg, block, op, mode, -1, NULL);
3813 for(i = 0; i < arity; ++i) {
3814 ir_node *in = get_irn_n(node, i);
3815 in = transform_node(env, in);
3816 add_irn_n(new_node, in);
3819 ir_node **ins = alloca(arity * sizeof(ins[0]));
3820 for(i = 0; i < arity; ++i) {
3821 ir_node *in = get_irn_n(node, i);
3822 ins[i] = transform_node(env, in);
3825 new_node = new_ir_node(dbg, irg, block, op, mode, arity, ins);
3828 copy_node_attr(node, new_node);
3829 duplicate_deps(env, node, new_node);
3834 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3837 ir_op *op = get_irn_op(node);
3839 if(irn_visited(node)) {
3840 assert(get_new_node(node) != NULL);
3841 return get_new_node(node);
3844 mark_irn_visited(node);
3845 DEBUG_ONLY(set_new_node(node, NULL));
3847 if (op->ops.generic) {
3848 transform_func *transform = (transform_func *)op->ops.generic;
3850 new_node = (*transform)(env, node);
3851 assert(new_node != NULL);
3853 new_node = duplicate_node(env, node);
3855 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3857 set_new_node(node, new_node);
3858 mark_irn_visited(new_node);
3859 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3863 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3867 if(irn_visited(node))
3869 mark_irn_visited(node);
3871 assert(node_is_in_irgs_storage(env->irg, node));
3873 if(!is_Block(node)) {
3874 ir_node *block = get_nodes_block(node);
3875 ir_node *new_block = (ir_node*) get_irn_link(block);
3877 if(new_block != NULL) {
3878 set_nodes_block(node, new_block);
3882 fix_loops(env, block);
3885 arity = get_irn_arity(node);
3886 for(i = 0; i < arity; ++i) {
3887 ir_node *in = get_irn_n(node, i);
3888 ir_node *new = (ir_node*) get_irn_link(in);
3890 if(new != NULL && new != in) {
3891 set_irn_n(node, i, new);
3898 arity = get_irn_deps(node);
3899 for(i = 0; i < arity; ++i) {
3900 ir_node *in = get_irn_dep(node, i);
3901 ir_node *new = (ir_node*) get_irn_link(in);
3903 if(new != NULL && new != in) {
3904 set_irn_dep(node, i, new);
3912 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3917 *place = transform_node(env, *place);
3920 static void transform_nodes(ia32_code_gen_t *cg)
3923 ir_graph *irg = cg->irg;
3925 ia32_transform_env_t env;
3927 hook_dead_node_elim(irg, 1);
3929 inc_irg_visited(irg);
3933 env.visited = get_irg_visited(irg);
3934 env.worklist = new_pdeq();
3935 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3936 DEBUG_ONLY(env.mod = cg->mod);
3938 old_end = get_irg_end(irg);
3940 /* put all anchor nodes in the worklist */
3941 for(i = 0; i < anchor_max; ++i) {
3942 ir_node *anchor = irg->anchors[i];
3945 pdeq_putr(env.worklist, anchor);
3948 env.old_anchors[i] = anchor;
3949 // and set it to NULL to make sure we don't accidently use it
3950 irg->anchors[i] = NULL;
3953 // pre transform some anchors (so they are available in the other transform
3955 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3956 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3957 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3958 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3959 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3961 pre_transform_node(&cg->unknown_gp, &env);
3962 pre_transform_node(&cg->unknown_vfp, &env);
3963 pre_transform_node(&cg->unknown_xmm, &env);
3964 pre_transform_node(&cg->noreg_gp, &env);
3965 pre_transform_node(&cg->noreg_vfp, &env);
3966 pre_transform_node(&cg->noreg_xmm, &env);
3968 /* process worklist (this should transform all nodes in the graph) */
3969 while(!pdeq_empty(env.worklist)) {
3970 ir_node *node = pdeq_getl(env.worklist);
3971 transform_node(&env, node);
3974 /* fix loops and set new anchors*/
3975 inc_irg_visited(irg);
3976 for(i = 0; i < anchor_max; ++i) {
3977 ir_node *anchor = env.old_anchors[i];
3981 anchor = get_irn_link(anchor);
3982 fix_loops(&env, anchor);
3983 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3984 irg->anchors[i] = anchor;
3987 del_pdeq(env.worklist);
3989 hook_dead_node_elim(irg, 0);
3992 void ia32_transform_graph(ia32_code_gen_t *cg)
3994 ir_graph *irg = cg->irg;
3995 be_irg_t *birg = cg->birg;
3996 ir_graph *old_current_ir_graph = current_ir_graph;
3997 int old_interprocedural_view = get_interprocedural_view();
3998 struct obstack *old_obst = NULL;
3999 struct obstack *new_obst = NULL;
4001 current_ir_graph = irg;
4002 set_interprocedural_view(0);
4003 register_transformers();
4005 /* most analysis info is wrong after transformation */
4006 free_callee_info(irg);
4008 irg->outs_state = outs_none;
4010 free_loop_information(irg);
4011 set_irg_doms_inconsistent(irg);
4012 be_invalidate_liveness(birg);
4013 be_invalidate_dom_front(birg);
4015 /* create a new obstack */
4016 old_obst = irg->obst;
4017 new_obst = xmalloc(sizeof(*new_obst));
4018 obstack_init(new_obst);
4019 irg->obst = new_obst;
4020 irg->last_node_idx = 0;
4022 /* create new value table for CSE */
4023 del_identities(irg->value_table);
4024 irg->value_table = new_identities();
4026 /* do the main transformation */
4027 transform_nodes(cg);
4029 /* we don't want the globals anchor anymore */
4030 set_irg_globals(irg, new_r_Bad(irg));
4032 /* free the old obstack */
4033 obstack_free(old_obst, 0);
4037 current_ir_graph = old_current_ir_graph;
4038 set_interprocedural_view(old_interprocedural_view);
4040 /* recalculate edges */
4041 edges_deactivate(irg);
4042 edges_activate(irg);
4046 * Transforms a psi condition.
4048 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4051 /* if the mode is target mode, we have already seen this part of the tree */
4052 if (get_irn_mode(cond) == mode)
4055 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4057 set_irn_mode(cond, mode);
4059 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4060 ir_node *in = get_irn_n(cond, i);
4062 /* if in is a compare: transform into Set/xCmp */
4064 ir_node *new_op = NULL;
4065 ir_node *cmp = get_Proj_pred(in);
4066 ir_node *cmp_a = get_Cmp_left(cmp);
4067 ir_node *cmp_b = get_Cmp_right(cmp);
4068 dbg_info *dbg = get_irn_dbg_info(cmp);
4069 ir_graph *irg = get_irn_irg(cmp);
4070 ir_node *block = get_nodes_block(cmp);
4071 ir_node *noreg = ia32_new_NoReg_gp(cg);
4072 ir_node *nomem = new_rd_NoMem(irg);
4073 int pnc = get_Proj_proj(in);
4075 /* this is a compare */
4076 if (mode_is_float(mode)) {
4077 /* Psi is float, we need a floating point compare */
4080 ir_mode *m = get_irn_mode(cmp_a);
4082 if (! mode_is_float(m)) {
4083 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
4084 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
4086 else if (m == mode_F) {
4087 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4088 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
4089 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
4092 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4093 set_ia32_pncode(new_op, pnc);
4094 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4103 construct_binop_func *set_func = NULL;
4105 if (mode_is_float(get_irn_mode(cmp_a))) {
4106 /* 1st case: compare operands are floats */
4111 set_func = new_rd_ia32_xCmpSet;
4115 set_func = new_rd_ia32_vfCmpSet;
4118 pnc &= 7; /* fp compare -> int compare */
4121 /* 2nd case: compare operand are integer too */
4122 set_func = new_rd_ia32_CmpSet;
4125 new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4126 if(!mode_is_signed(mode))
4127 pnc |= ia32_pn_Cmp_Unsigned;
4129 set_ia32_pncode(new_op, pnc);
4130 set_ia32_am_support(new_op, ia32_am_Source);
4133 /* the the new compare as in */
4134 set_irn_n(cond, i, new_op);
4137 /* another complex condition */
4138 transform_psi_cond(in, mode, cg);
4144 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4145 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4146 * compare, which causes the compare result to be stores in a register. The
4147 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4149 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4150 ia32_code_gen_t *cg = env;
4151 ir_node *psi_sel, *new_cmp, *block;
4156 if (get_irn_opcode(node) != iro_Psi)
4159 psi_sel = get_Psi_cond(node, 0);
4161 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4162 if (is_Proj(psi_sel))
4165 //mode = get_irn_mode(node);
4166 // TODO this is probably wrong...
4169 transform_psi_cond(psi_sel, mode, cg);
4171 irg = get_irn_irg(node);
4172 block = get_nodes_block(node);
4174 /* we need to compare the evaluated condition tree with 0 */
4175 mode = get_irn_mode(node);
4176 if (mode_is_float(mode)) {
4177 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4178 /* BEWARE: new_r_Const_long works for floating point as well */
4179 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4180 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4183 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4184 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4187 set_Psi_cond(node, 0, new_cmp);