2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
55 #include "../benode_t.h"
56 #include "../besched.h"
58 #include "../beutil.h"
59 #include "../beirg_t.h"
61 #include "bearch_ia32_t.h"
62 #include "ia32_nodes_attr.h"
63 #include "ia32_transform.h"
64 #include "ia32_new_nodes.h"
65 #include "ia32_map_regs.h"
66 #include "ia32_dbg_stat.h"
67 #include "ia32_optimize.h"
68 #include "ia32_util.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
83 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
84 #define ENT_SFP_ABS "IA32_SFP_ABS"
85 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
88 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
90 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
92 typedef struct ia32_transform_env_t {
93 ir_graph *irg; /**< The irg, the node should be created in */
94 ia32_code_gen_t *cg; /**< The code generator */
95 int visited; /**< visited count that indicates whether a
96 node is already transformed */
97 pdeq *worklist; /**< worklist of nodes that still need to be
99 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
100 } ia32_transform_env_t;
102 static ia32_transform_env_t env;
104 extern ir_op *get_op_Mulh(void);
106 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
108 ir_node *op2, ir_node *mem);
110 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
114 typedef ir_node *(transform_func)(ir_node *node);
116 /****************************************************************************************************
118 * | | | | / _| | | (_)
119 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
120 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
121 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
122 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
124 ****************************************************************************************************/
126 static ir_node *duplicate_node(ir_node *node);
127 static ir_node *transform_node(ir_node *node);
128 static void duplicate_deps(ir_node *old_node, ir_node *new_node);
130 static INLINE int mode_needs_gp_reg(ir_mode *mode)
132 if(mode == mode_fpcw)
135 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
138 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
140 set_irn_link(old_node, new_node);
143 static INLINE ir_node *get_new_node(ir_node *old_node)
145 assert(irn_visited(old_node));
146 return (ir_node*) get_irn_link(old_node);
150 * Returns 1 if irn is a Const representing 0, 0 otherwise
152 static INLINE int is_ia32_Const_0(ir_node *irn) {
153 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
154 && tarval_is_null(get_ia32_Immop_tarval(irn));
158 * Returns 1 if irn is a Const representing 1, 0 otherwise
160 static INLINE int is_ia32_Const_1(ir_node *irn) {
161 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
162 && tarval_is_one(get_ia32_Immop_tarval(irn));
166 * Collects all Projs of a node into the node array. Index is the projnum.
167 * BEWARE: The caller has to assure the appropriate array size!
169 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
170 const ir_edge_t *edge;
171 assert(get_irn_mode(irn) == mode_T && "need mode_T");
173 memset(projs, 0, size * sizeof(projs[0]));
175 foreach_out_edge(irn, edge) {
176 ir_node *proj = get_edge_src_irn(edge);
177 int proj_proj = get_Proj_proj(proj);
178 assert(proj_proj < size);
179 projs[proj_proj] = proj;
184 * Renumbers the proj having pn_old in the array tp pn_new
185 * and removes the proj from the array.
187 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
188 fprintf(stderr, "Warning: renumber_Proj used!\n");
190 set_Proj_proj(projs[pn_old], pn_new);
191 projs[pn_old] = NULL;
196 * creates a unique ident by adding a number to a tag
198 * @param tag the tag string, must contain a %d if a number
201 static ident *unique_id(const char *tag)
203 static unsigned id = 0;
206 snprintf(str, sizeof(str), tag, ++id);
207 return new_id_from_str(str);
211 * Get a primitive type for a mode.
213 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
215 pmap_entry *e = pmap_find(types, mode);
220 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
221 res = new_type_primitive(new_id_from_str(buf), mode);
222 pmap_insert(types, mode, res);
230 * Get an entity that is initialized with a tarval
232 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
234 tarval *tv = get_Const_tarval(cnst);
235 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
240 ir_mode *mode = get_irn_mode(cnst);
241 ir_type *tp = get_Const_type(cnst);
242 if (tp == firm_unknown_type)
243 tp = get_prim_type(cg->isa->types, mode);
245 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
247 set_entity_ld_ident(res, get_entity_ident(res));
248 set_entity_visibility(res, visibility_local);
249 set_entity_variability(res, variability_constant);
250 set_entity_allocation(res, allocation_static);
252 /* we create a new entity here: It's initialization must resist on the
254 rem = current_ir_graph;
255 current_ir_graph = get_const_code_irg();
256 set_atomic_ent_value(res, new_Const_type(tv, tp));
257 current_ir_graph = rem;
259 pmap_insert(cg->isa->tv_ent, tv, res);
268 * Transforms a Const.
270 static ir_node *gen_Const(ir_node *node) {
271 ir_graph *irg = env.irg;
272 ir_node *block = transform_node(get_nodes_block(node));
273 dbg_info *dbgi = get_irn_dbg_info(node);
274 ir_mode *mode = get_irn_mode(node);
276 if (mode_is_float(mode)) {
278 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
279 ir_node *nomem = new_NoMem();
284 if (! USE_SSE2(env.cg)) {
285 cnst_classify_t clss = classify_Const(node);
287 if (clss == CNST_NULL) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (clss == CNST_ONE) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = get_entity_for_tv(env.cg, node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
297 set_ia32_am_support(load, ia32_am_Source);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
303 set_ia32_ls_mode(load, mode);
305 floatent = get_entity_for_tv(env.cg, node);
307 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
308 set_ia32_am_support(load, ia32_am_Source);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
314 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env.cg, node));
319 /* Const Nodes before the initial IncSP are a bad idea, because
320 * they could be spilled and we have no SP ready at that point yet.
321 * So add a dependency to the initial frame pointer calculation to
322 * avoid that situation.
324 if (get_irg_start_block(irg) == block) {
325 add_irn_dep(load, get_irg_frame(irg));
328 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env.cg, node));
331 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
334 if (get_irg_start_block(irg) == block) {
335 add_irn_dep(cnst, get_irg_frame(irg));
338 set_ia32_Const_attr(cnst, node);
339 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env.cg, node));
344 return new_r_Bad(irg);
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = env.irg;
352 ir_node *block = transform_node(get_nodes_block(node));
353 dbg_info *dbgi = get_irn_dbg_info(node);
354 ir_mode *mode = get_irn_mode(node);
357 if (mode_is_float(mode)) {
359 if (USE_SSE2(env.cg))
360 cnst = new_rd_ia32_xConst(dbgi, irg, block);
362 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
363 set_ia32_ls_mode(cnst, mode);
365 cnst = new_rd_ia32_Const(dbgi, irg, block);
368 /* Const Nodes before the initial IncSP are a bad idea, because
369 * they could be spilled and we have no SP ready at that point yet
371 if (get_irg_start_block(irg) == block) {
372 add_irn_dep(cnst, get_irg_frame(irg));
375 set_ia32_Const_attr(cnst, node);
376 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env.cg, node));
382 * SSE convert of an integer node into a floating point node.
384 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
385 ir_graph *irg, ir_node *block,
386 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
388 ir_node *noreg = ia32_new_NoReg_gp(cg);
389 ir_node *nomem = new_rd_NoMem(irg);
390 ir_node *old_pred = get_Cmp_left(old_node);
391 ir_mode *in_mode = get_irn_mode(old_pred);
392 int in_bits = get_mode_size_bits(in_mode);
393 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
395 set_ia32_ls_mode(conv, tgt_mode);
397 set_ia32_am_support(conv, ia32_am_Source);
399 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
405 * SSE convert of an float node into a double node.
407 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
408 ir_graph *irg, ir_node *block,
409 ir_node *in, ir_node *old_node)
411 ir_node *noreg = ia32_new_NoReg_gp(cg);
412 ir_node *nomem = new_rd_NoMem(irg);
413 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
415 set_ia32_am_support(conv, ia32_am_Source);
416 set_ia32_ls_mode(conv, mode_xmm);
417 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
422 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
423 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
424 static const struct {
426 const char *ent_name;
427 const char *cnst_str;
428 } names [ia32_known_const_max] = {
429 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
430 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
431 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
432 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
434 static ir_entity *ent_cache[ia32_known_const_max];
436 const char *tp_name, *ent_name, *cnst_str;
444 ent_name = names[kct].ent_name;
445 if (! ent_cache[kct]) {
446 tp_name = names[kct].tp_name;
447 cnst_str = names[kct].cnst_str;
449 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
451 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
452 tp = new_type_primitive(new_id_from_str(tp_name), mode);
453 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
455 set_entity_ld_ident(ent, get_entity_ident(ent));
456 set_entity_visibility(ent, visibility_local);
457 set_entity_variability(ent, variability_constant);
458 set_entity_allocation(ent, allocation_static);
460 /* we create a new entity here: It's initialization must resist on the
462 rem = current_ir_graph;
463 current_ir_graph = get_const_code_irg();
464 cnst = new_Const(mode, tv);
465 current_ir_graph = rem;
467 set_atomic_ent_value(ent, cnst);
469 /* cache the entry */
470 ent_cache[kct] = ent;
473 return ent_cache[kct];
478 * Prints the old node name on cg obst and returns a pointer to it.
480 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
481 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
483 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
484 obstack_1grow(isa->name_obst, 0);
485 return obstack_finish(isa->name_obst);
489 /* determine if one operator is an Imm */
490 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
492 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
494 return is_ia32_Cnst(op2) ? op2 : NULL;
498 /* determine if one operator is not an Imm */
499 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
500 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
503 static void fold_immediate(ir_node *node, int in1, int in2) {
507 if (!(env.cg->opt & IA32_OPT_IMMOPS))
510 left = get_irn_n(node, in1);
511 right = get_irn_n(node, in2);
512 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
513 /* we can only set right operand to immediate */
514 if(!is_ia32_commutative(node))
516 /* exchange left/right */
517 set_irn_n(node, in1, right);
518 set_irn_n(node, in2, ia32_get_admissible_noreg(env.cg, node, in2));
519 copy_ia32_Immop_attr(node, left);
520 } else if(is_ia32_Cnst(right)) {
521 set_irn_n(node, in2, ia32_get_admissible_noreg(env.cg, node, in2));
522 copy_ia32_Immop_attr(node, right);
527 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
531 * Construct a standard binary operation, set AM and immediate if required.
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
539 construct_binop_func *func)
541 ir_node *block = transform_node(get_nodes_block(node));
542 ir_node *new_op1 = transform_node(op1);
543 ir_node *new_op2 = transform_node(op2);
544 ir_node *new_node = NULL;
545 ir_graph *irg = env.irg;
546 dbg_info *dbgi = get_irn_dbg_info(node);
547 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
548 ir_node *nomem = new_NoMem();
550 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
551 if (func == new_rd_ia32_IMul) {
552 set_ia32_am_support(new_node, ia32_am_Source);
554 set_ia32_am_support(new_node, ia32_am_Full);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node));
558 if (is_op_commutative(get_irn_op(node))) {
559 set_ia32_commutative(new_node);
561 fold_immediate(new_node, 2, 3);
567 * Construct a standard binary operation, set AM and immediate if required.
569 * @param op1 The first operand
570 * @param op2 The second operand
571 * @param func The node constructor function
572 * @return The constructed ia32 node.
574 static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2,
575 construct_binop_func *func)
577 ir_node *block = transform_node(get_nodes_block(node));
578 ir_node *new_op1 = transform_node(op1);
579 ir_node *new_op2 = transform_node(op2);
580 ir_node *new_node = NULL;
581 dbg_info *dbgi = get_irn_dbg_info(node);
582 ir_graph *irg = env.irg;
583 ir_mode *mode = get_irn_mode(node);
584 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
585 ir_node *nomem = new_NoMem();
587 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
588 set_ia32_am_support(new_node, ia32_am_Source);
589 if (is_op_commutative(get_irn_op(node))) {
590 set_ia32_commutative(new_node);
592 if (USE_SSE2(env.cg)) {
593 set_ia32_ls_mode(new_node, mode);
596 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node));
603 * Construct a shift/rotate binary operation, sets AM and immediate if required.
605 * @param op1 The first operand
606 * @param op2 The second operand
607 * @param func The node constructor function
608 * @return The constructed ia32 node.
610 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
611 construct_binop_func *func)
613 ir_node *block = transform_node(get_nodes_block(node));
614 ir_node *new_op1 = transform_node(op1);
615 ir_node *new_op2 = transform_node(op2);
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = env.irg;
619 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
620 ir_node *nomem = new_NoMem();
625 assert(! mode_is_float(get_irn_mode(node))
626 && "Shift/Rotate with float not supported");
628 /* Check if immediate optimization is on and */
629 /* if it's an operation with immediate. */
630 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
631 expr_op = get_expr_op(new_op1, new_op2);
633 assert((expr_op || imm_op) && "invalid operands");
636 /* We have two consts here: not yet supported */
640 /* Limit imm_op within range imm8 */
642 tv = get_ia32_Immop_tarval(imm_op);
645 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
646 set_ia32_Immop_tarval(imm_op, tv);
653 /* integer operations */
655 /* This is shift/rot with const */
656 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
658 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
659 copy_ia32_Immop_attr(new_op, imm_op);
661 /* This is a normal shift/rot */
662 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
663 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
667 set_ia32_am_support(new_op, ia32_am_Dest);
669 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
671 set_ia32_emit_cl(new_op);
678 * Construct a standard unary operation, set AM and immediate if required.
680 * @param op The operand
681 * @param func The node constructor function
682 * @return The constructed ia32 node.
684 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
686 ir_node *block = transform_node(get_nodes_block(node));
687 ir_node *new_op = transform_node(op);
688 ir_node *new_node = NULL;
689 ir_graph *irg = env.irg;
690 dbg_info *dbgi = get_irn_dbg_info(node);
691 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
692 ir_node *nomem = new_NoMem();
694 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
695 DB((dbg, LEVEL_1, "INT unop ..."));
696 set_ia32_am_support(new_node, ia32_am_Dest);
698 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node));
705 * Creates an ia32 Add.
707 * @return the created ia32 Add node
709 static ir_node *gen_Add(ir_node *node) {
710 ir_node *block = transform_node(get_nodes_block(node));
711 ir_node *op1 = get_Add_left(node);
712 ir_node *new_op1 = transform_node(op1);
713 ir_node *op2 = get_Add_right(node);
714 ir_node *new_op2 = transform_node(op2);
715 ir_node *new_op = NULL;
716 ir_graph *irg = env.irg;
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_mode *mode = get_irn_mode(node);
719 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
720 ir_node *nomem = new_NoMem();
721 ir_node *expr_op, *imm_op;
723 /* Check if immediate optimization is on and */
724 /* if it's an operation with immediate. */
725 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
726 expr_op = get_expr_op(new_op1, new_op2);
728 assert((expr_op || imm_op) && "invalid operands");
730 if (mode_is_float(mode)) {
732 if (USE_SSE2(env.cg))
733 return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd);
735 return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd);
740 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
741 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
743 /* No expr_op means, that we have two const - one symconst and */
744 /* one tarval or another symconst - because this case is not */
745 /* covered by constant folding */
746 /* We need to check for: */
747 /* 1) symconst + const -> becomes a LEA */
748 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
749 /* linker doesn't support two symconsts */
751 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
752 /* this is the 2nd case */
753 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
754 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
755 set_ia32_am_flavour(new_op, ia32_am_OB);
756 set_ia32_am_support(new_op, ia32_am_Source);
757 set_ia32_op_type(new_op, ia32_AddrModeS);
759 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
760 } else if (tp1 == ia32_ImmSymConst) {
761 tarval *tv = get_ia32_Immop_tarval(new_op2);
762 long offs = get_tarval_long(tv);
764 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
765 add_irn_dep(new_op, get_irg_frame(irg));
766 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
768 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
769 add_ia32_am_offs_int(new_op, offs);
770 set_ia32_am_flavour(new_op, ia32_am_O);
771 set_ia32_am_support(new_op, ia32_am_Source);
772 set_ia32_op_type(new_op, ia32_AddrModeS);
773 } else if (tp2 == ia32_ImmSymConst) {
774 tarval *tv = get_ia32_Immop_tarval(new_op1);
775 long offs = get_tarval_long(tv);
777 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
778 add_irn_dep(new_op, get_irg_frame(irg));
779 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
781 add_ia32_am_offs_int(new_op, offs);
782 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
783 set_ia32_am_flavour(new_op, ia32_am_O);
784 set_ia32_am_support(new_op, ia32_am_Source);
785 set_ia32_op_type(new_op, ia32_AddrModeS);
787 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
788 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
789 tarval *restv = tarval_add(tv1, tv2);
791 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
793 new_op = new_rd_ia32_Const(dbgi, irg, block);
794 set_ia32_Const_tarval(new_op, restv);
795 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
798 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
801 if ((env.cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
802 tarval_classification_t class_tv, class_negtv;
803 tarval *tv = get_ia32_Immop_tarval(imm_op);
805 /* optimize tarvals */
806 class_tv = classify_tarval(tv);
807 class_negtv = classify_tarval(tarval_neg(tv));
809 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
810 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
811 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
812 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
814 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
815 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
816 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
817 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
823 /* This is a normal add */
824 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
827 set_ia32_am_support(new_op, ia32_am_Full);
828 set_ia32_commutative(new_op);
830 fold_immediate(new_op, 2, 3);
832 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
838 static ir_node *create_ia32_Mul(ir_node *node) {
839 ir_graph *irg = env.irg;
840 dbg_info *dbgi = get_irn_dbg_info(node);
841 ir_node *block = transform_node(get_nodes_block(node));
842 ir_node *op1 = get_Mul_left(node);
843 ir_node *op2 = get_Mul_right(node);
844 ir_node *new_op1 = transform_node(op1);
845 ir_node *new_op2 = transform_node(op2);
846 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
847 ir_node *proj_EAX, *proj_EDX, *res;
850 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
851 set_ia32_commutative(res);
852 set_ia32_am_support(res, ia32_am_Source);
854 /* imediates are not supported, so no fold_immediate */
855 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
856 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
868 * Creates an ia32 Mul.
870 * @return the created ia32 Mul node
872 static ir_node *gen_Mul(ir_node *node) {
873 ir_node *op1 = get_Mul_left(node);
874 ir_node *op2 = get_Mul_right(node);
875 ir_mode *mode = get_irn_mode(node);
877 if (mode_is_float(mode)) {
879 if (USE_SSE2(env.cg))
880 return gen_binop_float(node, op1, op2, new_rd_ia32_xMul);
882 return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul);
886 for the lower 32bit of the result it doesn't matter whether we use
887 signed or unsigned multiplication so we use IMul as it has fewer
890 return gen_binop(node, op1, op2, new_rd_ia32_IMul);
894 * Creates an ia32 Mulh.
895 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
896 * this result while Mul returns the lower 32 bit.
898 * @return the created ia32 Mulh node
900 static ir_node *gen_Mulh(ir_node *node) {
901 ir_node *block = transform_node(get_nodes_block(node));
902 ir_node *op1 = get_irn_n(node, 0);
903 ir_node *new_op1 = transform_node(op1);
904 ir_node *op2 = get_irn_n(node, 1);
905 ir_node *new_op2 = transform_node(op2);
906 ir_graph *irg = env.irg;
907 dbg_info *dbgi = get_irn_dbg_info(node);
908 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
909 ir_mode *mode = get_irn_mode(node);
910 ir_node *proj_EAX, *proj_EDX, *res;
913 assert(!mode_is_float(mode) && "Mulh with float not supported");
914 if (mode_is_signed(mode)) {
915 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
917 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
920 set_ia32_commutative(res);
921 set_ia32_am_support(res, ia32_am_Source);
923 set_ia32_am_support(res, ia32_am_Source);
925 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
926 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
930 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
938 * Creates an ia32 And.
940 * @return The created ia32 And node
942 static ir_node *gen_And(ir_node *node) {
943 ir_node *op1 = get_And_left(node);
944 ir_node *op2 = get_And_right(node);
946 assert (! mode_is_float(get_irn_mode(node)));
947 return gen_binop(node, op1, op2, new_rd_ia32_And);
953 * Creates an ia32 Or.
955 * @return The created ia32 Or node
957 static ir_node *gen_Or(ir_node *node) {
958 ir_node *op1 = get_Or_left(node);
959 ir_node *op2 = get_Or_right(node);
961 assert (! mode_is_float(get_irn_mode(node)));
962 return gen_binop(node, op1, op2, new_rd_ia32_Or);
968 * Creates an ia32 Eor.
970 * @return The created ia32 Eor node
972 static ir_node *gen_Eor(ir_node *node) {
973 ir_node *op1 = get_Eor_left(node);
974 ir_node *op2 = get_Eor_right(node);
976 assert(! mode_is_float(get_irn_mode(node)));
977 return gen_binop(node, op1, op2, new_rd_ia32_Xor);
983 * Creates an ia32 Max.
985 * @return the created ia32 Max node
987 static ir_node *gen_Max(ir_node *node) {
988 ir_node *block = transform_node(get_nodes_block(node));
989 ir_node *op1 = get_irn_n(node, 0);
990 ir_node *new_op1 = transform_node(op1);
991 ir_node *op2 = get_irn_n(node, 1);
992 ir_node *new_op2 = transform_node(op2);
993 ir_graph *irg = env.irg;
994 ir_mode *mode = get_irn_mode(node);
995 dbg_info *dbgi = get_irn_dbg_info(node);
996 ir_mode *op_mode = get_irn_mode(op1);
999 assert(get_mode_size_bits(mode) == 32);
1001 if (mode_is_float(mode)) {
1003 if (USE_SSE2(env.cg)) {
1004 new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax);
1006 panic("Can't create Max node");
1009 long pnc = pn_Cmp_Gt;
1010 if (! mode_is_signed(op_mode)) {
1011 pnc |= ia32_pn_Cmp_Unsigned;
1013 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1014 set_ia32_pncode(new_op, pnc);
1015 set_ia32_am_support(new_op, ia32_am_None);
1017 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1023 * Creates an ia32 Min.
1025 * @return the created ia32 Min node
1027 static ir_node *gen_Min(ir_node *node) {
1028 ir_node *block = transform_node(get_nodes_block(node));
1029 ir_node *op1 = get_irn_n(node, 0);
1030 ir_node *new_op1 = transform_node(op1);
1031 ir_node *op2 = get_irn_n(node, 1);
1032 ir_node *new_op2 = transform_node(op2);
1033 ir_graph *irg = env.irg;
1034 ir_mode *mode = get_irn_mode(node);
1035 dbg_info *dbgi = get_irn_dbg_info(node);
1036 ir_mode *op_mode = get_irn_mode(op1);
1039 assert(get_mode_size_bits(mode) == 32);
1041 if (mode_is_float(mode)) {
1043 if (USE_SSE2(env.cg)) {
1044 new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin);
1046 panic("can't create Min node");
1049 long pnc = pn_Cmp_Lt;
1050 if (! mode_is_signed(op_mode)) {
1051 pnc |= ia32_pn_Cmp_Unsigned;
1053 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1054 set_ia32_pncode(new_op, pnc);
1055 set_ia32_am_support(new_op, ia32_am_None);
1057 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1064 * Creates an ia32 Sub.
1066 * @return The created ia32 Sub node
1068 static ir_node *gen_Sub(ir_node *node) {
1069 ir_node *block = transform_node(get_nodes_block(node));
1070 ir_node *op1 = get_Sub_left(node);
1071 ir_node *new_op1 = transform_node(op1);
1072 ir_node *op2 = get_Sub_right(node);
1073 ir_node *new_op2 = transform_node(op2);
1074 ir_node *new_op = NULL;
1075 ir_graph *irg = env.irg;
1076 dbg_info *dbgi = get_irn_dbg_info(node);
1077 ir_mode *mode = get_irn_mode(node);
1078 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1079 ir_node *nomem = new_NoMem();
1080 ir_node *expr_op, *imm_op;
1082 /* Check if immediate optimization is on and */
1083 /* if it's an operation with immediate. */
1084 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1085 expr_op = get_expr_op(new_op1, new_op2);
1087 assert((expr_op || imm_op) && "invalid operands");
1089 if (mode_is_float(mode)) {
1091 if (USE_SSE2(env.cg))
1092 return gen_binop_float(node, op1, op2, new_rd_ia32_xSub);
1094 return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub);
1099 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1100 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1102 /* No expr_op means, that we have two const - one symconst and */
1103 /* one tarval or another symconst - because this case is not */
1104 /* covered by constant folding */
1105 /* We need to check for: */
1106 /* 1) symconst - const -> becomes a LEA */
1107 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1108 /* linker doesn't support two symconsts */
1109 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1110 /* this is the 2nd case */
1111 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1112 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1113 set_ia32_am_sc_sign(new_op);
1114 set_ia32_am_flavour(new_op, ia32_am_OB);
1116 DBG_OPT_LEA3(op1, op2, node, new_op);
1117 } else if (tp1 == ia32_ImmSymConst) {
1118 tarval *tv = get_ia32_Immop_tarval(new_op2);
1119 long offs = get_tarval_long(tv);
1121 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1122 add_irn_dep(new_op, get_irg_frame(irg));
1123 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1126 add_ia32_am_offs_int(new_op, -offs);
1127 set_ia32_am_flavour(new_op, ia32_am_O);
1128 set_ia32_am_support(new_op, ia32_am_Source);
1129 set_ia32_op_type(new_op, ia32_AddrModeS);
1130 } else if (tp2 == ia32_ImmSymConst) {
1131 tarval *tv = get_ia32_Immop_tarval(new_op1);
1132 long offs = get_tarval_long(tv);
1134 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1135 add_irn_dep(new_op, get_irg_frame(irg));
1136 DBG_OPT_LEA3(op1, op2, node, new_op);
1138 add_ia32_am_offs_int(new_op, offs);
1139 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1140 set_ia32_am_sc_sign(new_op);
1141 set_ia32_am_flavour(new_op, ia32_am_O);
1142 set_ia32_am_support(new_op, ia32_am_Source);
1143 set_ia32_op_type(new_op, ia32_AddrModeS);
1145 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1146 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1147 tarval *restv = tarval_sub(tv1, tv2);
1149 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1151 new_op = new_rd_ia32_Const(dbgi, irg, block);
1152 set_ia32_Const_tarval(new_op, restv);
1153 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1156 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1158 } else if (imm_op) {
1159 if ((env.cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1160 tarval_classification_t class_tv, class_negtv;
1161 tarval *tv = get_ia32_Immop_tarval(imm_op);
1163 /* optimize tarvals */
1164 class_tv = classify_tarval(tv);
1165 class_negtv = classify_tarval(tarval_neg(tv));
1167 if (class_tv == TV_CLASSIFY_ONE) {
1168 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1169 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1170 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1172 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1173 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1174 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1175 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1181 /* This is a normal sub */
1182 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1184 /* set AM support */
1185 set_ia32_am_support(new_op, ia32_am_Full);
1187 fold_immediate(new_op, 2, 3);
1189 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1197 * Generates an ia32 DivMod with additional infrastructure for the
1198 * register allocator if needed.
1200 * @param dividend -no comment- :)
1201 * @param divisor -no comment- :)
1202 * @param dm_flav flavour_Div/Mod/DivMod
1203 * @return The created ia32 DivMod node
1205 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1206 ir_node *divisor, ia32_op_flavour_t dm_flav)
1208 ir_node *block = transform_node(get_nodes_block(node));
1209 ir_node *new_dividend = transform_node(dividend);
1210 ir_node *new_divisor = transform_node(divisor);
1211 ir_graph *irg = env.irg;
1212 dbg_info *dbgi = get_irn_dbg_info(node);
1213 ir_mode *mode = get_irn_mode(node);
1214 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1215 ir_node *res, *proj_div, *proj_mod;
1216 ir_node *edx_node, *cltd;
1217 ir_node *in_keep[2];
1218 ir_node *mem, *new_mem;
1219 ir_node *projs[pn_DivMod_max];
1222 ia32_collect_Projs(node, projs, pn_DivMod_max);
1224 proj_div = proj_mod = NULL;
1228 mem = get_Div_mem(node);
1229 mode = get_Div_resmode(node);
1230 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1231 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1234 mem = get_Mod_mem(node);
1235 mode = get_Mod_resmode(node);
1236 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1237 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1239 case flavour_DivMod:
1240 mem = get_DivMod_mem(node);
1241 mode = get_DivMod_resmode(node);
1242 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1243 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1244 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1247 panic("invalid divmod flavour!");
1249 new_mem = transform_node(mem);
1251 if (mode_is_signed(mode)) {
1252 /* in signed mode, we need to sign extend the dividend */
1253 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1254 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1255 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1257 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1258 add_irn_dep(edx_node, be_abi_get_start_barrier(env.cg->birg->abi));
1259 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1262 if (mode_is_signed(mode)) {
1263 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1265 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1268 set_ia32_exc_label(res, has_exc);
1270 /* Matze: code can't handle this at the moment... */
1272 /* set AM support */
1273 set_ia32_am_support(res, ia32_am_Source);
1276 /* check, which Proj-Keep, we need to add */
1278 if (proj_div == NULL) {
1279 /* We have only mod result: add div res Proj-Keep */
1280 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1283 if (proj_mod == NULL) {
1284 /* We have only div result: add mod res Proj-Keep */
1285 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1289 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1291 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1298 * Wrapper for generate_DivMod. Sets flavour_Mod.
1301 static ir_node *gen_Mod(ir_node *node) {
1302 return generate_DivMod(node, get_Mod_left(node),
1303 get_Mod_right(node), flavour_Mod);
1307 * Wrapper for generate_DivMod. Sets flavour_Div.
1310 static ir_node *gen_Div(ir_node *node) {
1311 return generate_DivMod(node, get_Div_left(node),
1312 get_Div_right(node), flavour_Div);
1316 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1318 static ir_node *gen_DivMod(ir_node *node) {
1319 return generate_DivMod(node, get_DivMod_left(node),
1320 get_DivMod_right(node), flavour_DivMod);
1326 * Creates an ia32 floating Div.
1328 * @return The created ia32 xDiv node
1330 static ir_node *gen_Quot(ir_node *node) {
1331 ir_node *block = transform_node(get_nodes_block(node));
1332 ir_node *op1 = get_Quot_left(node);
1333 ir_node *new_op1 = transform_node(op1);
1334 ir_node *op2 = get_Quot_right(node);
1335 ir_node *new_op2 = transform_node(op2);
1336 ir_graph *irg = env.irg;
1337 dbg_info *dbgi = get_irn_dbg_info(node);
1338 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1339 ir_node *nomem = new_rd_NoMem(env.irg);
1343 if (USE_SSE2(env.cg)) {
1344 ir_mode *mode = get_irn_mode(op1);
1345 if (is_ia32_xConst(new_op2)) {
1346 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1347 set_ia32_am_support(new_op, ia32_am_None);
1348 copy_ia32_Immop_attr(new_op, new_op2);
1350 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1351 // Matze: disabled for now, spillslot coalescer fails
1352 //set_ia32_am_support(new_op, ia32_am_Source);
1354 set_ia32_ls_mode(new_op, mode);
1356 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1357 // Matze: disabled for now (spillslot coalescer fails)
1358 //set_ia32_am_support(new_op, ia32_am_Source);
1360 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1366 * Creates an ia32 Shl.
1368 * @return The created ia32 Shl node
1370 static ir_node *gen_Shl(ir_node *node) {
1371 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1378 * Creates an ia32 Shr.
1380 * @return The created ia32 Shr node
1382 static ir_node *gen_Shr(ir_node *node) {
1383 return gen_shift_binop(node, get_Shr_left(node),
1384 get_Shr_right(node), new_rd_ia32_Shr);
1390 * Creates an ia32 Sar.
1392 * @return The created ia32 Shrs node
1394 static ir_node *gen_Shrs(ir_node *node) {
1395 return gen_shift_binop(node, get_Shrs_left(node),
1396 get_Shrs_right(node), new_rd_ia32_Sar);
1402 * Creates an ia32 RotL.
1404 * @param op1 The first operator
1405 * @param op2 The second operator
1406 * @return The created ia32 RotL node
1408 static ir_node *gen_RotL(ir_node *node,
1409 ir_node *op1, ir_node *op2) {
1410 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1416 * Creates an ia32 RotR.
1417 * NOTE: There is no RotR with immediate because this would always be a RotL
1418 * "imm-mode_size_bits" which can be pre-calculated.
1420 * @param op1 The first operator
1421 * @param op2 The second operator
1422 * @return The created ia32 RotR node
1424 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1426 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1432 * Creates an ia32 RotR or RotL (depending on the found pattern).
1434 * @return The created ia32 RotL or RotR node
1436 static ir_node *gen_Rot(ir_node *node) {
1437 ir_node *rotate = NULL;
1438 ir_node *op1 = get_Rot_left(node);
1439 ir_node *op2 = get_Rot_right(node);
1441 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1442 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1443 that means we can create a RotR instead of an Add and a RotL */
1445 if (get_irn_op(op2) == op_Add) {
1447 ir_node *left = get_Add_left(add);
1448 ir_node *right = get_Add_right(add);
1449 if (is_Const(right)) {
1450 tarval *tv = get_Const_tarval(right);
1451 ir_mode *mode = get_irn_mode(node);
1452 long bits = get_mode_size_bits(mode);
1454 if (get_irn_op(left) == op_Minus &&
1455 tarval_is_long(tv) &&
1456 get_tarval_long(tv) == bits)
1458 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1459 rotate = gen_RotR(node, op1, get_Minus_op(left));
1464 if (rotate == NULL) {
1465 rotate = gen_RotL(node, op1, op2);
1474 * Transforms a Minus node.
1476 * @param op The Minus operand
1477 * @return The created ia32 Minus node
1479 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1480 ir_node *block = transform_node(get_nodes_block(node));
1481 ir_graph *irg = env.irg;
1482 dbg_info *dbgi = get_irn_dbg_info(node);
1483 ir_mode *mode = get_irn_mode(node);
1488 if (mode_is_float(mode)) {
1489 ir_node *new_op = transform_node(op);
1491 if (USE_SSE2(env.cg)) {
1492 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
1493 ir_node *noreg_fp = ia32_new_NoReg_fp(env.cg);
1494 ir_node *nomem = new_rd_NoMem(irg);
1496 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1498 size = get_mode_size_bits(mode);
1499 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1501 set_ia32_am_sc(res, ent);
1502 set_ia32_op_type(res, ia32_AddrModeS);
1503 set_ia32_ls_mode(res, mode);
1505 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1508 res = gen_unop(node, op, new_rd_ia32_Neg);
1511 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1517 * Transforms a Minus node.
1519 * @return The created ia32 Minus node
1521 static ir_node *gen_Minus(ir_node *node) {
1522 return gen_Minus_ex(node, get_Minus_op(node));
1527 * Transforms a Not node.
1529 * @return The created ia32 Not node
1531 static ir_node *gen_Not(ir_node *node) {
1532 ir_node *op = get_Not_op(node);
1534 assert (! mode_is_float(get_irn_mode(node)));
1535 return gen_unop(node, op, new_rd_ia32_Not);
1541 * Transforms an Abs node.
1543 * @return The created ia32 Abs node
1545 static ir_node *gen_Abs(ir_node *node) {
1546 ir_node *block = transform_node(get_nodes_block(node));
1547 ir_node *op = get_Abs_op(node);
1548 ir_node *new_op = transform_node(op);
1549 ir_graph *irg = env.irg;
1550 dbg_info *dbgi = get_irn_dbg_info(node);
1551 ir_mode *mode = get_irn_mode(node);
1552 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
1553 ir_node *noreg_fp = ia32_new_NoReg_fp(env.cg);
1554 ir_node *nomem = new_NoMem();
1555 ir_node *res, *p_eax, *p_edx;
1559 if (mode_is_float(mode)) {
1561 if (USE_SSE2(env.cg)) {
1562 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1564 size = get_mode_size_bits(mode);
1565 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1567 set_ia32_am_sc(res, ent);
1569 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1571 set_ia32_op_type(res, ia32_AddrModeS);
1572 set_ia32_ls_mode(res, mode);
1575 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1576 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1580 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1581 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1583 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1584 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1586 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1587 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1589 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1599 * Transforms a Load.
1601 * @return the created ia32 Load node
1603 static ir_node *gen_Load(ir_node *node) {
1604 ir_node *block = transform_node(get_nodes_block(node));
1605 ir_node *ptr = get_Load_ptr(node);
1606 ir_node *new_ptr = transform_node(ptr);
1607 ir_node *mem = get_Load_mem(node);
1608 ir_node *new_mem = transform_node(mem);
1609 ir_graph *irg = env.irg;
1610 dbg_info *dbgi = get_irn_dbg_info(node);
1611 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1612 ir_mode *mode = get_Load_mode(node);
1613 ir_node *lptr = new_ptr;
1616 ir_node *projs[pn_Load_max];
1617 ia32_am_flavour_t am_flav = ia32_am_B;
1619 ia32_collect_Projs(node, projs, pn_Load_max);
1622 check for special case: the loaded value might not be used (optimized, volatile, ...)
1623 we add a Proj + Keep for volatile loads and ignore all other cases
1625 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1626 /* add a result proj and a Keep to produce a pseudo use */
1627 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1628 be_new_Keep(arch_get_irn_reg_class(env.cg->arch_env, proj, -1), irg, block, 1, &proj);
1631 /* address might be a constant (symconst or absolute address) */
1632 if (is_ia32_Const(new_ptr)) {
1637 if (mode_is_float(mode)) {
1639 if (USE_SSE2(env.cg)) {
1640 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1642 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1645 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1648 /* base is a constant address */
1650 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1651 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1652 am_flav = ia32_am_N;
1654 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1655 long offs = get_tarval_long(tv);
1657 add_ia32_am_offs_int(new_op, offs);
1658 am_flav = ia32_am_O;
1662 set_ia32_am_support(new_op, ia32_am_Source);
1663 set_ia32_op_type(new_op, ia32_AddrModeS);
1664 set_ia32_am_flavour(new_op, am_flav);
1665 set_ia32_ls_mode(new_op, mode);
1667 /* make sure we are scheduled behind the initial IncSP/Barrier
1668 * to avoid spills being placed before it
1670 if (block == get_irg_start_block(irg)) {
1671 add_irn_dep(new_op, get_irg_frame(irg));
1674 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1675 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1683 * Transforms a Store.
1685 * @return the created ia32 Store node
1687 static ir_node *gen_Store(ir_node *node) {
1688 ir_node *block = transform_node(get_nodes_block(node));
1689 ir_node *ptr = get_Store_ptr(node);
1690 ir_node *new_ptr = transform_node(ptr);
1691 ir_node *val = get_Store_value(node);
1692 ir_node *new_val = transform_node(val);
1693 ir_node *mem = get_Store_mem(node);
1694 ir_node *new_mem = transform_node(mem);
1695 ir_graph *irg = env.irg;
1696 dbg_info *dbgi = get_irn_dbg_info(node);
1697 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1698 ir_node *sptr = new_ptr;
1699 ir_mode *mode = get_irn_mode(val);
1700 ir_node *sval = new_val;
1703 ia32_am_flavour_t am_flav = ia32_am_B;
1705 if (is_ia32_Const(new_val)) {
1706 assert(!mode_is_float(mode));
1710 /* address might be a constant (symconst or absolute address) */
1711 if (is_ia32_Const(new_ptr)) {
1716 if (mode_is_float(mode)) {
1718 if (USE_SSE2(env.cg)) {
1719 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1721 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1723 } else if (get_mode_size_bits(mode) == 8) {
1724 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1726 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1729 /* stored const is an immediate value */
1730 if (is_ia32_Const(new_val)) {
1731 assert(!mode_is_float(mode));
1732 copy_ia32_Immop_attr(new_op, new_val);
1735 /* base is an constant address */
1737 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1738 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1739 am_flav = ia32_am_N;
1741 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1742 long offs = get_tarval_long(tv);
1744 add_ia32_am_offs_int(new_op, offs);
1745 am_flav = ia32_am_O;
1749 set_ia32_am_support(new_op, ia32_am_Dest);
1750 set_ia32_op_type(new_op, ia32_AddrModeD);
1751 set_ia32_am_flavour(new_op, am_flav);
1752 set_ia32_ls_mode(new_op, mode);
1754 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1755 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1763 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1765 * @return The transformed node.
1767 static ir_node *gen_Cond(ir_node *node) {
1768 ir_node *block = transform_node(get_nodes_block(node));
1769 ir_graph *irg = env.irg;
1770 dbg_info *dbgi = get_irn_dbg_info(node);
1771 ir_node *sel = get_Cond_selector(node);
1772 ir_mode *sel_mode = get_irn_mode(sel);
1773 ir_node *res = NULL;
1774 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1775 ir_node *cnst, *expr;
1777 if (is_Proj(sel) && sel_mode == mode_b) {
1778 ir_node *pred = get_Proj_pred(sel);
1779 ir_node *cmp_a = get_Cmp_left(pred);
1780 ir_node *new_cmp_a = transform_node(cmp_a);
1781 ir_node *cmp_b = get_Cmp_right(pred);
1782 ir_node *new_cmp_b = transform_node(cmp_b);
1783 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1784 ir_node *nomem = new_NoMem();
1786 int pnc = get_Proj_proj(sel);
1787 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1788 pnc |= ia32_pn_Cmp_Unsigned;
1791 /* check if we can use a CondJmp with immediate */
1792 cnst = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1793 expr = get_expr_op(new_cmp_a, new_cmp_b);
1795 if (cnst != NULL && expr != NULL) {
1796 /* immop has to be the right operand, we might need to flip pnc */
1797 if(cnst != new_cmp_b) {
1798 pnc = get_inversed_pnc(pnc);
1801 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1802 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1803 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1805 /* a Cmp A =/!= 0 */
1806 ir_node *op1 = expr;
1807 ir_node *op2 = expr;
1810 /* check, if expr is an only once used And operation */
1811 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1812 op1 = get_irn_n(expr, 2);
1813 op2 = get_irn_n(expr, 3);
1815 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1817 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1818 set_ia32_pncode(res, pnc);
1821 copy_ia32_Immop_attr(res, expr);
1824 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1829 if (mode_is_float(cmp_mode)) {
1831 if (USE_SSE2(env.cg)) {
1832 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1833 set_ia32_ls_mode(res, cmp_mode);
1839 assert(get_mode_size_bits(cmp_mode) == 32);
1840 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1842 copy_ia32_Immop_attr(res, cnst);
1845 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1847 if (mode_is_float(cmp_mode)) {
1849 if (USE_SSE2(env.cg)) {
1850 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1851 set_ia32_ls_mode(res, cmp_mode);
1854 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1855 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1856 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1860 assert(get_mode_size_bits(cmp_mode) == 32);
1861 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1862 set_ia32_commutative(res);
1866 set_ia32_pncode(res, pnc);
1867 // Matze: disabled for now, because the default collect_spills_walker
1868 // is not able to detect the mode of the spilled value
1869 // moreover, the lea optimize phase freely exchanges left/right
1870 // without updating the pnc
1871 //set_ia32_am_support(res, ia32_am_Source);
1874 /* determine the smallest switch case value */
1875 ir_node *new_sel = transform_node(sel);
1876 int switch_min = INT_MAX;
1877 const ir_edge_t *edge;
1879 foreach_out_edge(node, edge) {
1880 int pn = get_Proj_proj(get_edge_src_irn(edge));
1881 switch_min = pn < switch_min ? pn : switch_min;
1885 /* if smallest switch case is not 0 we need an additional sub */
1886 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1887 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1888 add_ia32_am_offs_int(res, -switch_min);
1889 set_ia32_am_flavour(res, ia32_am_OB);
1890 set_ia32_am_support(res, ia32_am_Source);
1891 set_ia32_op_type(res, ia32_AddrModeS);
1894 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1895 set_ia32_pncode(res, get_Cond_defaultProj(node));
1898 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1905 * Transforms a CopyB node.
1907 * @return The transformed node.
1909 static ir_node *gen_CopyB(ir_node *node) {
1910 ir_node *block = transform_node(get_nodes_block(node));
1911 ir_node *src = get_CopyB_src(node);
1912 ir_node *new_src = transform_node(src);
1913 ir_node *dst = get_CopyB_dst(node);
1914 ir_node *new_dst = transform_node(dst);
1915 ir_node *mem = get_CopyB_mem(node);
1916 ir_node *new_mem = transform_node(mem);
1917 ir_node *res = NULL;
1918 ir_graph *irg = env.irg;
1919 dbg_info *dbgi = get_irn_dbg_info(node);
1920 int size = get_type_size_bytes(get_CopyB_type(node));
1921 ir_mode *dst_mode = get_irn_mode(dst);
1922 ir_mode *src_mode = get_irn_mode(src);
1926 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1927 /* then we need the size explicitly in ECX. */
1928 if (size >= 32 * 4) {
1929 rem = size & 0x3; /* size % 4 */
1932 res = new_rd_ia32_Const(dbgi, irg, block);
1933 add_irn_dep(res, be_abi_get_start_barrier(env.cg->birg->abi));
1934 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1936 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1937 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1939 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1940 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1941 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1942 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1943 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1946 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1947 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1949 /* ok: now attach Proj's because movsd will destroy esi and edi */
1950 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1951 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1952 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1955 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1963 * Transforms a Mux node into CMov.
1965 * @return The transformed node.
1967 static ir_node *gen_Mux(ir_node *node) {
1968 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, env.irg, env.block, \
1969 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1971 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1977 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1978 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1979 ir_node *psi_default);
1982 * Transforms a Psi node into CMov.
1984 * @return The transformed node.
1986 static ir_node *gen_Psi(ir_node *node) {
1987 ir_node *block = transform_node(get_nodes_block(node));
1988 ir_node *psi_true = get_Psi_val(node, 0);
1989 ir_node *new_psi_true = transform_node(psi_true);
1990 ir_node *psi_default = get_Psi_default(node);
1991 ir_node *new_psi_default = transform_node(psi_default);
1992 ia32_code_gen_t *cg = env.cg;
1993 ir_graph *irg = env.irg;
1994 dbg_info *dbgi = get_irn_dbg_info(node);
1995 ir_mode *mode = get_irn_mode(node);
1996 ir_node *cmp_proj = get_Mux_sel(node);
1997 ir_node *noreg = ia32_new_NoReg_gp(cg);
1998 ir_node *nomem = new_rd_NoMem(irg);
1999 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2000 ir_node *new_cmp_a, *new_cmp_b;
2004 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2006 cmp = get_Proj_pred(cmp_proj);
2007 cmp_a = get_Cmp_left(cmp);
2008 cmp_b = get_Cmp_right(cmp);
2009 cmp_mode = get_irn_mode(cmp_a);
2010 new_cmp_a = transform_node(cmp_a);
2011 new_cmp_b = transform_node(cmp_b);
2013 pnc = get_Proj_proj(cmp_proj);
2014 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2015 pnc |= ia32_pn_Cmp_Unsigned;
2018 if (mode_is_float(mode)) {
2019 /* floating point psi */
2022 /* 1st case: compare operands are float too */
2024 /* psi(cmp(a, b), t, f) can be done as: */
2025 /* tmp = cmp a, b */
2026 /* tmp2 = t and tmp */
2027 /* tmp3 = f and not tmp */
2028 /* res = tmp2 or tmp3 */
2030 /* in case the compare operands are int, we move them into xmm register */
2031 if (! mode_is_float(get_irn_mode(cmp_a))) {
2032 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2033 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2035 pnc |= 8; /* transform integer compare to fp compare */
2038 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2039 set_ia32_pncode(new_op, pnc);
2040 set_ia32_am_support(new_op, ia32_am_Source);
2041 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2043 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2044 set_ia32_am_support(and1, ia32_am_None);
2045 set_ia32_commutative(and1);
2046 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2048 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2049 set_ia32_am_support(and2, ia32_am_None);
2050 set_ia32_commutative(and2);
2051 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2053 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2054 set_ia32_am_support(new_op, ia32_am_None);
2055 set_ia32_commutative(new_op);
2056 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2060 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2061 set_ia32_pncode(new_op, pnc);
2062 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2067 construct_binop_func *set_func = NULL;
2068 cmov_func_t *cmov_func = NULL;
2070 if (mode_is_float(get_irn_mode(cmp_a))) {
2071 /* 1st case: compare operands are floats */
2076 set_func = new_rd_ia32_xCmpSet;
2077 cmov_func = new_rd_ia32_xCmpCMov;
2081 set_func = new_rd_ia32_vfCmpSet;
2082 cmov_func = new_rd_ia32_vfCmpCMov;
2085 pnc &= ~0x8; /* fp compare -> int compare */
2088 /* 2nd case: compare operand are integer too */
2089 set_func = new_rd_ia32_CmpSet;
2090 cmov_func = new_rd_ia32_CmpCMov;
2093 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2094 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2095 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2096 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2097 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2098 set_ia32_pncode(new_op, pnc);
2100 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2101 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2102 /* we invert condition and set default to 0 */
2103 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2104 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2107 /* otherwise: use CMOVcc */
2108 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2109 set_ia32_pncode(new_op, pnc);
2112 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2115 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2116 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2117 new_op = gen_binop(node, cmp_a, cmp_b, set_func);
2118 set_ia32_pncode(new_op, pnc);
2119 set_ia32_am_support(new_op, ia32_am_Source);
2121 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2122 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2123 /* we invert condition and set default to 0 */
2124 new_op = gen_binop(node, cmp_a, cmp_b, set_func);
2125 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2126 set_ia32_am_support(new_op, ia32_am_Source);
2129 /* otherwise: use CMOVcc */
2130 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2131 set_ia32_pncode(new_op, pnc);
2132 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2142 * Following conversion rules apply:
2146 * 1) n bit -> m bit n > m (downscale)
2148 * 2) n bit -> m bit n == m (sign change)
2150 * 3) n bit -> m bit n < m (upscale)
2151 * a) source is signed: movsx
2152 * b) source is unsigned: and with lower bits sets
2156 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2160 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2164 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2165 * x87 is mode_E internally, conversions happen only at load and store
2166 * in non-strict semantic
2170 * Create a conversion from x87 state register to general purpose.
2172 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2173 ir_node *block = transform_node(get_nodes_block(node));
2174 ir_node *op = get_Conv_op(node);
2175 ir_node *new_op = transform_node(op);
2176 ia32_code_gen_t *cg = env.cg;
2177 ir_graph *irg = env.irg;
2178 dbg_info *dbgi = get_irn_dbg_info(node);
2179 ir_node *noreg = ia32_new_NoReg_gp(cg);
2180 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2181 ir_node *fist, *load;
2184 fist = new_rd_ia32_vfist(dbgi, irg, block,
2185 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2187 set_ia32_use_frame(fist);
2188 set_ia32_am_support(fist, ia32_am_Dest);
2189 set_ia32_op_type(fist, ia32_AddrModeD);
2190 set_ia32_am_flavour(fist, ia32_am_B);
2191 set_ia32_ls_mode(fist, mode_Iu);
2192 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2195 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2197 set_ia32_use_frame(load);
2198 set_ia32_am_support(load, ia32_am_Source);
2199 set_ia32_op_type(load, ia32_AddrModeS);
2200 set_ia32_am_flavour(load, ia32_am_B);
2201 set_ia32_ls_mode(load, mode_Iu);
2202 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2204 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2208 * Create a conversion from general purpose to x87 register
2210 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2211 ir_node *block = transform_node(get_nodes_block(node));
2212 ir_node *op = get_Conv_op(node);
2213 ir_node *new_op = transform_node(op);
2214 ir_graph *irg = env.irg;
2215 dbg_info *dbgi = get_irn_dbg_info(node);
2216 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2217 ir_node *nomem = new_NoMem();
2218 ir_node *fild, *store;
2221 /* first convert to 32 bit if necessary */
2222 src_bits = get_mode_size_bits(src_mode);
2223 if (src_bits == 8) {
2224 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2225 set_ia32_am_support(new_op, ia32_am_Source);
2226 set_ia32_ls_mode(new_op, src_mode);
2227 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2228 } else if (src_bits < 32) {
2229 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2230 set_ia32_am_support(new_op, ia32_am_Source);
2231 set_ia32_ls_mode(new_op, src_mode);
2232 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2236 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2238 set_ia32_use_frame(store);
2239 set_ia32_am_support(store, ia32_am_Dest);
2240 set_ia32_op_type(store, ia32_AddrModeD);
2241 set_ia32_am_flavour(store, ia32_am_OB);
2242 set_ia32_ls_mode(store, mode_Iu);
2245 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2247 set_ia32_use_frame(fild);
2248 set_ia32_am_support(fild, ia32_am_Source);
2249 set_ia32_op_type(fild, ia32_AddrModeS);
2250 set_ia32_am_flavour(fild, ia32_am_OB);
2251 set_ia32_ls_mode(fild, mode_Iu);
2253 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2257 * Transforms a Conv node.
2259 * @param env The transformation environment
2260 * @return The created ia32 Conv node
2262 static ir_node *gen_Conv(ir_node *node) {
2263 ir_node *block = transform_node(get_nodes_block(node));
2264 ir_node *op = get_Conv_op(node);
2265 ir_node *new_op = transform_node(op);
2266 ir_graph *irg = env.irg;
2267 dbg_info *dbgi = get_irn_dbg_info(node);
2268 ir_mode *src_mode = get_irn_mode(op);
2269 ir_mode *tgt_mode = get_irn_mode(node);
2270 int src_bits = get_mode_size_bits(src_mode);
2271 int tgt_bits = get_mode_size_bits(tgt_mode);
2272 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2273 ir_node *nomem = new_rd_NoMem(irg);
2276 if (src_mode == tgt_mode) {
2277 if (get_Conv_strict(node)) {
2278 if (USE_SSE2(env.cg)) {
2279 /* when we are in SSE mode, we can kill all strict no-op conversion */
2283 /* this should be optimized already, but who knows... */
2284 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2285 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2290 if (mode_is_float(src_mode)) {
2291 /* we convert from float ... */
2292 if (mode_is_float(tgt_mode)) {
2294 if (USE_SSE2(env.cg)) {
2295 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2296 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2297 set_ia32_ls_mode(res, tgt_mode);
2299 // Matze: TODO what about strict convs?
2300 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2301 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2306 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2307 if (USE_SSE2(env.cg)) {
2308 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2309 set_ia32_ls_mode(res, src_mode);
2311 return gen_x87_fp_to_gp(node);
2315 /* we convert from int ... */
2316 if (mode_is_float(tgt_mode)) {
2319 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2320 if (USE_SSE2(env.cg)) {
2321 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2322 set_ia32_ls_mode(res, tgt_mode);
2323 if(src_bits == 32) {
2324 set_ia32_am_support(res, ia32_am_Source);
2327 return gen_x87_gp_to_fp(node, src_mode);
2331 ir_mode *smaller_mode;
2334 if (src_bits == tgt_bits) {
2335 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2339 if (src_bits < tgt_bits) {
2340 smaller_mode = src_mode;
2341 smaller_bits = src_bits;
2343 smaller_mode = tgt_mode;
2344 smaller_bits = tgt_bits;
2347 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2348 if (smaller_bits == 8) {
2349 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2350 set_ia32_ls_mode(res, smaller_mode);
2352 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2353 set_ia32_ls_mode(res, smaller_mode);
2355 set_ia32_am_support(res, ia32_am_Source);
2359 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
2365 int check_immediate_constraint(tarval *tv, char immediate_constraint_type)
2369 assert(tarval_is_long(tv));
2370 val = get_tarval_long(tv);
2372 switch (immediate_constraint_type) {
2376 return val >= 0 && val <= 32;
2378 return val >= 0 && val <= 63;
2380 return val >= -128 && val <= 127;
2382 return val == 0xff || val == 0xffff;
2384 return val >= 0 && val <= 3;
2386 return val >= 0 && val <= 255;
2388 return val >= 0 && val <= 127;
2392 panic("Invalid immediate constraint found");
2396 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2399 tarval *offset = NULL;
2400 int offset_sign = 0;
2401 ir_entity *symconst_ent = NULL;
2402 int symconst_sign = 0;
2404 ir_node *cnst = NULL;
2405 ir_node *symconst = NULL;
2412 mode = get_irn_mode(node);
2413 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2414 !mode_is_reference(mode)) {
2418 if(is_Minus(node)) {
2420 node = get_Minus_op(node);
2423 if(is_Const(node)) {
2426 offset_sign = minus;
2427 } else if(is_SymConst(node)) {
2430 symconst_sign = minus;
2431 } else if(is_Add(node)) {
2432 ir_node *left = get_Add_left(node);
2433 ir_node *right = get_Add_right(node);
2434 if(is_Const(left) && is_SymConst(right)) {
2437 symconst_sign = minus;
2438 offset_sign = minus;
2439 } else if(is_SymConst(left) && is_Const(right)) {
2442 symconst_sign = minus;
2443 offset_sign = minus;
2445 } else if(is_Sub(node)) {
2446 ir_node *left = get_Add_left(node);
2447 ir_node *right = get_Add_right(node);
2448 if(is_Const(left) && is_SymConst(right)) {
2451 symconst_sign = !minus;
2452 offset_sign = minus;
2453 } else if(is_SymConst(left) && is_Const(right)) {
2456 symconst_sign = minus;
2457 offset_sign = !minus;
2464 offset = get_Const_tarval(cnst);
2465 if(!tarval_is_long(offset)) {
2466 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2471 if(!check_immediate_constraint(offset, immediate_constraint_type))
2474 if(symconst != NULL) {
2475 if(immediate_constraint_type != 0) {
2476 /* we need full 32bits for symconsts */
2480 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2482 symconst_ent = get_SymConst_entity(symconst);
2486 dbgi = get_irn_dbg_info(node);
2487 block = get_irg_start_block(irg);
2488 res = new_rd_ia32_Immediate(dbgi, irg, block);
2489 arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2491 /* make sure we don't schedule stuff before the barrier */
2492 add_irn_dep(res, get_irg_frame(irg));
2494 /* misuse some fields for now... */
2495 attr = get_ia32_attr(res);
2496 attr->am_sc = symconst_ent;
2497 attr->data.am_sc_sign = symconst_sign;
2498 if(offset_sign && offset != NULL) {
2499 offset = tarval_neg(offset);
2501 attr->cnst_val.tv = offset;
2502 attr->data.imm_tp = ia32_ImmConst;
2507 typedef struct constraint_t constraint_t;
2508 struct constraint_t {
2511 const arch_register_req_t **out_reqs;
2513 const arch_register_req_t *req;
2514 unsigned immediate_possible;
2515 char immediate_type;
2518 void parse_asm_constraint(ir_node *node, int pos, constraint_t *constraint,
2521 int immediate_possible = 0;
2522 char immediate_type = 0;
2523 unsigned limited = 0;
2524 const arch_register_class_t *cls = NULL;
2526 struct obstack *obst;
2527 arch_register_req_t *req;
2528 unsigned *limited_ptr;
2532 /* TODO: replace all the asserts with nice error messages */
2534 printf("Constraint: %s\n", c);
2544 assert(cls == NULL ||
2545 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2546 cls = &ia32_reg_classes[CLASS_ia32_gp];
2547 limited |= 1 << REG_EAX;
2550 assert(cls == NULL ||
2551 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2552 cls = &ia32_reg_classes[CLASS_ia32_gp];
2553 limited |= 1 << REG_EBX;
2556 assert(cls == NULL ||
2557 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2558 cls = &ia32_reg_classes[CLASS_ia32_gp];
2559 limited |= 1 << REG_ECX;
2562 assert(cls == NULL ||
2563 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2564 cls = &ia32_reg_classes[CLASS_ia32_gp];
2565 limited |= 1 << REG_EDX;
2568 assert(cls == NULL ||
2569 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2570 cls = &ia32_reg_classes[CLASS_ia32_gp];
2571 limited |= 1 << REG_EDI;
2574 assert(cls == NULL ||
2575 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2576 cls = &ia32_reg_classes[CLASS_ia32_gp];
2577 limited |= 1 << REG_ESI;
2580 case 'q': /* q means lower part of the regs only, this makes no
2581 * difference to Q for us (we only assigne whole registers) */
2582 assert(cls == NULL ||
2583 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2584 cls = &ia32_reg_classes[CLASS_ia32_gp];
2585 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2589 assert(cls == NULL ||
2590 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2591 cls = &ia32_reg_classes[CLASS_ia32_gp];
2592 limited |= 1 << REG_EAX | 1 << REG_EDX;
2595 assert(cls == NULL ||
2596 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2597 cls = &ia32_reg_classes[CLASS_ia32_gp];
2598 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2599 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2606 assert(cls == NULL);
2607 cls = &ia32_reg_classes[CLASS_ia32_gp];
2613 assert(cls == NULL);
2614 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2619 assert(cls == NULL);
2620 /* TODO: check that sse2 is supported */
2621 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2631 assert(!immediate_possible);
2632 immediate_possible = 1;
2633 immediate_type = *c;
2637 assert(!immediate_possible);
2638 immediate_possible = 1;
2642 assert(!immediate_possible && cls == NULL);
2643 immediate_possible = 1;
2644 cls = &ia32_reg_classes[CLASS_ia32_gp];
2657 assert(constraint->is_in && "can only specify same constraint "
2660 sscanf(c, "%d%n", &same_as, &p);
2667 case 'E': /* no float consts yet */
2668 case 'F': /* no float consts yet */
2669 case 's': /* makes no sense on x86 */
2670 case 'X': /* we can't support that in firm */
2674 case '<': /* no autodecrement on x86 */
2675 case '>': /* no autoincrement on x86 */
2676 case 'C': /* sse constant not supported yet */
2677 case 'G': /* 80387 constant not supported yet */
2678 case 'y': /* we don't support mmx registers yet */
2679 case 'Z': /* not available in 32 bit mode */
2680 case 'e': /* not available in 32 bit mode */
2681 assert(0 && "asm constraint not supported");
2684 assert(0 && "unknown asm constraint found");
2691 const arch_register_req_t *other_constr;
2693 assert(cls == NULL && "same as and register constraint not supported");
2694 assert(!immediate_possible && "same as and immediate constraint not "
2696 assert(same_as < constraint->n_outs && "wrong constraint number in "
2697 "same_as constraint");
2699 other_constr = constraint->out_reqs[same_as];
2701 req = obstack_alloc(obst, sizeof(req[0]));
2702 req->cls = other_constr->cls;
2703 req->type = arch_register_req_type_should_be_same;
2704 req->limited = NULL;
2705 req->other_same = pos;
2706 req->other_different = -1;
2708 /* switch constraints. This is because in firm we have same_as
2709 * constraints on the output constraints while in the gcc asm syntax
2710 * they are specified on the input constraints */
2711 constraint->req = other_constr;
2712 constraint->out_reqs[same_as] = req;
2713 constraint->immediate_possible = 0;
2717 if(immediate_possible && cls == NULL) {
2718 cls = &ia32_reg_classes[CLASS_ia32_gp];
2720 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2721 assert(cls != NULL);
2723 if(immediate_possible) {
2724 assert(constraint->is_in
2725 && "imeediates make no sense for output constraints");
2727 /* todo: check types (no float input on 'r' constrainted in and such... */
2730 obst = get_irg_obstack(irg);
2733 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2734 limited_ptr = (unsigned*) (req+1);
2736 req = obstack_alloc(obst, sizeof(req[0]));
2738 memset(req, 0, sizeof(req[0]));
2741 req->type = arch_register_req_type_limited;
2742 *limited_ptr = limited;
2743 req->limited = limited_ptr;
2745 req->type = arch_register_req_type_normal;
2749 constraint->req = req;
2750 constraint->immediate_possible = immediate_possible;
2751 constraint->immediate_type = immediate_type;
2755 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2758 panic("Clobbers not supported yet");
2761 ir_node *gen_ASM(ir_node *node)
2764 ir_graph *irg = env.irg;
2765 ir_node *block = transform_node(get_nodes_block(node));
2766 dbg_info *dbgi = get_irn_dbg_info(node);
2773 const arch_register_req_t **out_reqs;
2774 const arch_register_req_t **in_reqs;
2775 struct obstack *obst;
2776 constraint_t parsed_constraint;
2778 /* assembler could contain float statements */
2781 /* transform inputs */
2782 arity = get_irn_arity(node);
2783 in = alloca(arity * sizeof(in[0]));
2784 memset(in, 0, arity * sizeof(in[0]));
2786 n_outs = get_ASM_n_output_constraints(node);
2787 n_clobbers = get_ASM_n_clobbers(node);
2788 out_arity = n_outs + n_clobbers;
2790 /* construct register constraints */
2791 obst = get_irg_obstack(irg);
2792 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2793 parsed_constraint.out_reqs = out_reqs;
2794 parsed_constraint.n_outs = n_outs;
2795 parsed_constraint.is_in = 0;
2796 for(i = 0; i < out_arity; ++i) {
2800 const ir_asm_constraint *constraint;
2801 constraint = & get_ASM_output_constraints(node) [i];
2802 c = get_id_str(constraint->constraint);
2803 parse_asm_constraint(node, i, &parsed_constraint, c);
2805 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2806 c = get_id_str(glob_id);
2807 parse_clobber(node, i, &parsed_constraint, c);
2809 out_reqs[i] = parsed_constraint.req;
2812 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2813 parsed_constraint.is_in = 1;
2814 for(i = 0; i < arity; ++i) {
2815 const ir_asm_constraint *constraint;
2819 constraint = & get_ASM_input_constraints(node) [i];
2820 constr_id = constraint->constraint;
2821 c = get_id_str(constr_id);
2822 parse_asm_constraint(node, i, &parsed_constraint, c);
2823 in_reqs[i] = parsed_constraint.req;
2825 if(parsed_constraint.immediate_possible) {
2826 ir_node *pred = get_irn_n(node, i);
2827 char imm_type = parsed_constraint.immediate_type;
2828 ir_node *immediate = try_create_Immediate(pred, imm_type);
2830 if(immediate != NULL) {
2836 /* transform inputs */
2837 for(i = 0; i < arity; ++i) {
2839 ir_node *transformed;
2844 pred = get_irn_n(node, i);
2845 transformed = transform_node(pred);
2846 in[i] = transformed;
2849 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2851 attr = get_ia32_attr(res);
2852 attr->cnst_val.asm_text = get_ASM_text(node);
2853 attr->data.imm_tp = ia32_ImmAsm;
2854 set_ia32_out_req_all(res, out_reqs);
2855 set_ia32_in_req_all(res, in_reqs);
2857 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
2862 /********************************************
2865 * | |__ ___ _ __ ___ __| | ___ ___
2866 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2867 * | |_) | __/ | | | (_) | (_| | __/\__ \
2868 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2870 ********************************************/
2872 static ir_node *gen_be_StackParam(ir_node *node) {
2873 ir_node *block = transform_node(get_nodes_block(node));
2874 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2875 ir_node *new_ptr = transform_node(ptr);
2876 ir_node *new_op = NULL;
2877 ir_graph *irg = env.irg;
2878 dbg_info *dbgi = get_irn_dbg_info(node);
2879 ir_node *nomem = new_rd_NoMem(env.irg);
2880 ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node);
2881 ir_mode *load_mode = get_irn_mode(node);
2882 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2886 if (mode_is_float(load_mode)) {
2888 if (USE_SSE2(env.cg)) {
2889 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2890 pn_res = pn_ia32_xLoad_res;
2891 proj_mode = mode_xmm;
2893 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2894 pn_res = pn_ia32_vfld_res;
2895 proj_mode = mode_vfp;
2898 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2899 proj_mode = mode_Iu;
2900 pn_res = pn_ia32_Load_res;
2903 set_ia32_frame_ent(new_op, ent);
2904 set_ia32_use_frame(new_op);
2906 set_ia32_am_support(new_op, ia32_am_Source);
2907 set_ia32_op_type(new_op, ia32_AddrModeS);
2908 set_ia32_am_flavour(new_op, ia32_am_B);
2909 set_ia32_ls_mode(new_op, load_mode);
2910 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2914 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2918 * Transforms a FrameAddr into an ia32 Add.
2920 static ir_node *gen_be_FrameAddr(ir_node *node) {
2921 ir_node *block = transform_node(get_nodes_block(node));
2922 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
2923 ir_node *new_op = transform_node(op);
2924 ir_graph *irg = env.irg;
2925 dbg_info *dbgi = get_irn_dbg_info(node);
2926 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2929 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2930 set_ia32_frame_ent(res, arch_get_frame_entity(env.cg->arch_env, node));
2931 set_ia32_am_support(res, ia32_am_Full);
2932 set_ia32_use_frame(res);
2933 set_ia32_am_flavour(res, ia32_am_OB);
2935 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
2941 * Transforms a FrameLoad into an ia32 Load.
2943 static ir_node *gen_be_FrameLoad(ir_node *node) {
2944 ir_node *block = transform_node(get_nodes_block(node));
2945 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2946 ir_node *new_mem = transform_node(mem);
2947 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2948 ir_node *new_ptr = transform_node(ptr);
2949 ir_node *new_op = NULL;
2950 ir_graph *irg = env.irg;
2951 dbg_info *dbgi = get_irn_dbg_info(node);
2952 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2953 ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node);
2954 ir_mode *mode = get_type_mode(get_entity_type(ent));
2955 ir_node *projs[pn_Load_max];
2957 ia32_collect_Projs(node, projs, pn_Load_max);
2959 if (mode_is_float(mode)) {
2961 if (USE_SSE2(env.cg)) {
2962 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2965 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2969 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2972 set_ia32_frame_ent(new_op, ent);
2973 set_ia32_use_frame(new_op);
2975 set_ia32_am_support(new_op, ia32_am_Source);
2976 set_ia32_op_type(new_op, ia32_AddrModeS);
2977 set_ia32_am_flavour(new_op, ia32_am_B);
2978 set_ia32_ls_mode(new_op, mode);
2980 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2987 * Transforms a FrameStore into an ia32 Store.
2989 static ir_node *gen_be_FrameStore(ir_node *node) {
2990 ir_node *block = transform_node(get_nodes_block(node));
2991 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2992 ir_node *new_mem = transform_node(mem);
2993 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2994 ir_node *new_ptr = transform_node(ptr);
2995 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2996 ir_node *new_val = transform_node(val);
2997 ir_node *new_op = NULL;
2998 ir_graph *irg = env.irg;
2999 dbg_info *dbgi = get_irn_dbg_info(node);
3000 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3001 ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node);
3002 ir_mode *mode = get_irn_mode(val);
3004 if (mode_is_float(mode)) {
3006 if (USE_SSE2(env.cg)) {
3007 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3009 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3011 } else if (get_mode_size_bits(mode) == 8) {
3012 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3014 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3017 set_ia32_frame_ent(new_op, ent);
3018 set_ia32_use_frame(new_op);
3020 set_ia32_am_support(new_op, ia32_am_Dest);
3021 set_ia32_op_type(new_op, ia32_AddrModeD);
3022 set_ia32_am_flavour(new_op, ia32_am_B);
3023 set_ia32_ls_mode(new_op, mode);
3025 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3031 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3033 static ir_node *gen_be_Return(ir_node *node) {
3034 ir_graph *irg = env.irg;
3035 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3036 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3037 ir_entity *ent = get_irg_entity(irg);
3038 ir_type *tp = get_entity_type(ent);
3043 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3044 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3047 int pn_ret_val, pn_ret_mem, arity, i;
3049 assert(ret_val != NULL);
3050 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env.cg)) {
3051 return duplicate_node(node);
3054 res_type = get_method_res_type(tp, 0);
3056 if (! is_Primitive_type(res_type)) {
3057 return duplicate_node(node);
3060 mode = get_type_mode(res_type);
3061 if (! mode_is_float(mode)) {
3062 return duplicate_node(node);
3065 assert(get_method_n_ress(tp) == 1);
3067 pn_ret_val = get_Proj_proj(ret_val);
3068 pn_ret_mem = get_Proj_proj(ret_mem);
3070 /* get the Barrier */
3071 barrier = get_Proj_pred(ret_val);
3073 /* get result input of the Barrier */
3074 ret_val = get_irn_n(barrier, pn_ret_val);
3075 new_ret_val = transform_node(ret_val);
3077 /* get memory input of the Barrier */
3078 ret_mem = get_irn_n(barrier, pn_ret_mem);
3079 new_ret_mem = transform_node(ret_mem);
3081 frame = get_irg_frame(irg);
3083 dbgi = get_irn_dbg_info(barrier);
3084 block = transform_node(get_nodes_block(barrier));
3086 noreg = ia32_new_NoReg_gp(env.cg);
3088 /* store xmm0 onto stack */
3089 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3090 set_ia32_ls_mode(sse_store, mode);
3091 set_ia32_op_type(sse_store, ia32_AddrModeD);
3092 set_ia32_use_frame(sse_store);
3093 set_ia32_am_flavour(sse_store, ia32_am_B);
3094 set_ia32_am_support(sse_store, ia32_am_Dest);
3097 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3098 set_ia32_ls_mode(fld, mode);
3099 set_ia32_op_type(fld, ia32_AddrModeS);
3100 set_ia32_use_frame(fld);
3101 set_ia32_am_flavour(fld, ia32_am_B);
3102 set_ia32_am_support(fld, ia32_am_Source);
3104 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3105 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3106 arch_set_irn_register(env.cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3108 /* create a new barrier */
3109 arity = get_irn_arity(barrier);
3110 in = alloca(arity * sizeof(in[0]));
3111 for (i = 0; i < arity; ++i) {
3114 if (i == pn_ret_val) {
3116 } else if (i == pn_ret_mem) {
3119 ir_node *in = get_irn_n(barrier, i);
3120 new_in = transform_node(in);
3125 new_barrier = new_ir_node(dbgi, irg, block,
3126 get_irn_op(barrier), get_irn_mode(barrier),
3128 copy_node_attr(barrier, new_barrier);
3129 duplicate_deps(barrier, new_barrier);
3130 set_new_node(barrier, new_barrier);
3131 mark_irn_visited(barrier);
3133 /* transform normally */
3134 return duplicate_node(node);
3138 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3140 static ir_node *gen_be_AddSP(ir_node *node) {
3141 ir_node *block = transform_node(get_nodes_block(node));
3142 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3143 ir_node *new_sz = transform_node(sz);
3144 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3145 ir_node *new_sp = transform_node(sp);
3146 ir_graph *irg = env.irg;
3147 dbg_info *dbgi = get_irn_dbg_info(node);
3148 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3149 ir_node *nomem = new_NoMem();
3152 /* ia32 stack grows in reverse direction, make a SubSP */
3153 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3154 set_ia32_am_support(new_op, ia32_am_Source);
3155 fold_immediate(new_op, 2, 3);
3157 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3163 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3165 static ir_node *gen_be_SubSP(ir_node *node) {
3166 ir_node *block = transform_node(get_nodes_block(node));
3167 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3168 ir_node *new_sz = transform_node(sz);
3169 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3170 ir_node *new_sp = transform_node(sp);
3171 ir_graph *irg = env.irg;
3172 dbg_info *dbgi = get_irn_dbg_info(node);
3173 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3174 ir_node *nomem = new_NoMem();
3177 /* ia32 stack grows in reverse direction, make an AddSP */
3178 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3179 set_ia32_am_support(new_op, ia32_am_Source);
3180 fold_immediate(new_op, 2, 3);
3182 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3188 * This function just sets the register for the Unknown node
3189 * as this is not done during register allocation because Unknown
3190 * is an "ignore" node.
3192 static ir_node *gen_Unknown(ir_node *node) {
3193 ir_mode *mode = get_irn_mode(node);
3195 if (mode_is_float(mode)) {
3196 if (USE_SSE2(env.cg))
3197 return ia32_new_Unknown_xmm(env.cg);
3199 return ia32_new_Unknown_vfp(env.cg);
3200 } else if (mode_needs_gp_reg(mode)) {
3201 return ia32_new_Unknown_gp(env.cg);
3203 assert(0 && "unsupported Unknown-Mode");
3210 * Change some phi modes
3212 static ir_node *gen_Phi(ir_node *node) {
3213 ir_node *block = transform_node(get_nodes_block(node));
3214 ir_graph *irg = env.irg;
3215 dbg_info *dbgi = get_irn_dbg_info(node);
3216 ir_mode *mode = get_irn_mode(node);
3220 if(mode_needs_gp_reg(mode)) {
3221 /* we shouldn't have any 64bit stuff around anymore */
3222 assert(get_mode_size_bits(mode) <= 32);
3223 /* all integer operations are on 32bit registers now */
3225 } else if(mode_is_float(mode)) {
3226 assert(mode == mode_D || mode == mode_F);
3227 if (USE_SSE2(env.cg)) {
3234 /* phi nodes allow loops, so we use the old arguments for now
3235 * and fix this later */
3236 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3237 copy_node_attr(node, phi);
3238 duplicate_deps(node, phi);
3240 set_new_node(node, phi);
3242 /* put the preds in the worklist */
3243 arity = get_irn_arity(node);
3244 for (i = 0; i < arity; ++i) {
3245 ir_node *pred = get_irn_n(node, i);
3246 pdeq_putr(env.worklist, pred);
3252 /**********************************************************************
3255 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3256 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3257 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3258 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3260 **********************************************************************/
3262 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3264 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3267 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3268 ir_node *val, ir_node *mem);
3271 * Transforms a lowered Load into a "real" one.
3273 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3274 ir_node *block = transform_node(get_nodes_block(node));
3275 ir_node *ptr = get_irn_n(node, 0);
3276 ir_node *new_ptr = transform_node(ptr);
3277 ir_node *mem = get_irn_n(node, 1);
3278 ir_node *new_mem = transform_node(mem);
3279 ir_graph *irg = env.irg;
3280 dbg_info *dbgi = get_irn_dbg_info(node);
3281 ir_mode *mode = get_ia32_ls_mode(node);
3282 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3286 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3287 lowering we have x87 nodes, so we need to enforce simulation.
3289 if (mode_is_float(mode)) {
3291 if (fp_unit == fp_x87)
3295 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3297 set_ia32_am_support(new_op, ia32_am_Source);
3298 set_ia32_op_type(new_op, ia32_AddrModeS);
3299 set_ia32_am_flavour(new_op, ia32_am_OB);
3300 set_ia32_am_offs_int(new_op, 0);
3301 set_ia32_am_scale(new_op, 1);
3302 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3303 if (is_ia32_am_sc_sign(node))
3304 set_ia32_am_sc_sign(new_op);
3305 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3306 if (is_ia32_use_frame(node)) {
3307 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3308 set_ia32_use_frame(new_op);
3311 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3317 * Transforms a lowered Store into a "real" one.
3319 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3320 ir_node *block = transform_node(get_nodes_block(node));
3321 ir_node *ptr = get_irn_n(node, 0);
3322 ir_node *new_ptr = transform_node(ptr);
3323 ir_node *val = get_irn_n(node, 1);
3324 ir_node *new_val = transform_node(val);
3325 ir_node *mem = get_irn_n(node, 2);
3326 ir_node *new_mem = transform_node(mem);
3327 ir_graph *irg = env.irg;
3328 dbg_info *dbgi = get_irn_dbg_info(node);
3329 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3330 ir_mode *mode = get_ia32_ls_mode(node);
3333 ia32_am_flavour_t am_flav = ia32_B;
3336 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3337 lowering we have x87 nodes, so we need to enforce simulation.
3339 if (mode_is_float(mode)) {
3341 if (fp_unit == fp_x87)
3345 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3347 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3349 add_ia32_am_offs_int(new_op, am_offs);
3352 set_ia32_am_support(new_op, ia32_am_Dest);
3353 set_ia32_op_type(new_op, ia32_AddrModeD);
3354 set_ia32_am_flavour(new_op, am_flav);
3355 set_ia32_ls_mode(new_op, mode);
3356 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3357 set_ia32_use_frame(new_op);
3359 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3366 * Transforms an ia32_l_XXX into a "real" XXX node
3368 * @param env The transformation environment
3369 * @return the created ia32 XXX node
3371 #define GEN_LOWERED_OP(op) \
3372 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3373 ir_mode *mode = get_irn_mode(node); \
3374 if (mode_is_float(mode)) \
3376 return gen_binop(node, get_binop_left(node), \
3377 get_binop_right(node), new_rd_ia32_##op); \
3380 #define GEN_LOWERED_x87_OP(op) \
3381 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3383 FORCE_x87(env.cg); \
3384 new_op = gen_binop_float(node, get_binop_left(node), \
3385 get_binop_right(node), new_rd_ia32_##op); \
3389 #define GEN_LOWERED_UNOP(op) \
3390 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3391 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3394 #define GEN_LOWERED_SHIFT_OP(op) \
3395 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3396 return gen_shift_binop(node, get_binop_left(node), \
3397 get_binop_right(node), new_rd_ia32_##op); \
3400 #define GEN_LOWERED_LOAD(op, fp_unit) \
3401 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3402 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3405 #define GEN_LOWERED_STORE(op, fp_unit) \
3406 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3407 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3414 GEN_LOWERED_OP(IMul)
3416 GEN_LOWERED_x87_OP(vfprem)
3417 GEN_LOWERED_x87_OP(vfmul)
3418 GEN_LOWERED_x87_OP(vfsub)
3420 GEN_LOWERED_UNOP(Neg)
3422 GEN_LOWERED_LOAD(vfild, fp_x87)
3423 GEN_LOWERED_LOAD(Load, fp_none)
3424 /*GEN_LOWERED_STORE(vfist, fp_x87)
3427 GEN_LOWERED_STORE(Store, fp_none)
3429 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3430 ir_node *block = transform_node(get_nodes_block(node));
3431 ir_node *left = get_binop_left(node);
3432 ir_node *new_left = transform_node(left);
3433 ir_node *right = get_binop_right(node);
3434 ir_node *new_right = transform_node(right);
3435 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3436 ir_graph *irg = env.irg;
3437 dbg_info *dbgi = get_irn_dbg_info(node);
3440 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3441 clear_ia32_commutative(vfdiv);
3442 set_ia32_am_support(vfdiv, ia32_am_Source);
3443 fold_immediate(vfdiv, 2, 3);
3445 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env.cg, node));
3453 * Transforms a l_MulS into a "real" MulS node.
3455 * @param env The transformation environment
3456 * @return the created ia32 Mul node
3458 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3459 ir_node *block = transform_node(get_nodes_block(node));
3460 ir_node *left = get_binop_left(node);
3461 ir_node *new_left = transform_node(left);
3462 ir_node *right = get_binop_right(node);
3463 ir_node *new_right = transform_node(right);
3464 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3465 ir_graph *irg = env.irg;
3466 dbg_info *dbgi = get_irn_dbg_info(node);
3469 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3470 /* and then skip the result Proj, because all needed Projs are already there. */
3471 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3472 clear_ia32_commutative(muls);
3473 set_ia32_am_support(muls, ia32_am_Source);
3474 fold_immediate(muls, 2, 3);
3476 /* check if EAX and EDX proj exist, add missing one */
3477 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3478 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3479 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3481 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env.cg, node));
3486 GEN_LOWERED_SHIFT_OP(Shl)
3487 GEN_LOWERED_SHIFT_OP(Shr)
3488 GEN_LOWERED_SHIFT_OP(Sar)
3491 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3492 * op1 - target to be shifted
3493 * op2 - contains bits to be shifted into target
3495 * Only op3 can be an immediate.
3497 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3498 ir_node *op2, ir_node *count)
3500 ir_node *block = transform_node(get_nodes_block(node));
3501 ir_node *new_op1 = transform_node(op1);
3502 ir_node *new_op2 = transform_node(op2);
3503 ir_node *new_count = transform_node(count);
3504 ir_node *new_op = NULL;
3505 ir_graph *irg = env.irg;
3506 dbg_info *dbgi = get_irn_dbg_info(node);
3507 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3508 ir_node *nomem = new_NoMem();
3512 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3514 /* Check if immediate optimization is on and */
3515 /* if it's an operation with immediate. */
3516 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3518 /* Limit imm_op within range imm8 */
3520 tv = get_ia32_Immop_tarval(imm_op);
3523 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3524 set_ia32_Immop_tarval(imm_op, tv);
3531 /* integer operations */
3533 /* This is ShiftD with const */
3534 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3536 if (is_ia32_l_ShlD(node))
3537 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3538 new_op1, new_op2, noreg, nomem);
3540 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3541 new_op1, new_op2, noreg, nomem);
3542 copy_ia32_Immop_attr(new_op, imm_op);
3545 /* This is a normal ShiftD */
3546 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3547 if (is_ia32_l_ShlD(node))
3548 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3549 new_op1, new_op2, new_count, nomem);
3551 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3552 new_op1, new_op2, new_count, nomem);
3555 /* set AM support */
3556 // Matze: node has unsupported format (6inputs)
3557 //set_ia32_am_support(new_op, ia32_am_Dest);
3559 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3561 set_ia32_emit_cl(new_op);
3566 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3567 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3568 get_irn_n(node, 1), get_irn_n(node, 2));
3571 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3572 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3573 get_irn_n(node, 1), get_irn_n(node, 2));
3577 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3579 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3580 ir_node *block = transform_node(get_nodes_block(node));
3581 ir_node *val = get_irn_n(node, 1);
3582 ir_node *new_val = transform_node(val);
3583 ia32_code_gen_t *cg = env.cg;
3584 ir_node *res = NULL;
3585 ir_graph *irg = env.irg;
3587 ir_node *noreg, *new_ptr, *new_mem;
3594 mem = get_irn_n(node, 2);
3595 new_mem = transform_node(mem);
3596 ptr = get_irn_n(node, 0);
3597 new_ptr = transform_node(ptr);
3598 noreg = ia32_new_NoReg_gp(cg);
3599 dbgi = get_irn_dbg_info(node);
3601 /* Store x87 -> MEM */
3602 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3603 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3604 set_ia32_use_frame(res);
3605 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3606 set_ia32_am_support(res, ia32_am_Dest);
3607 set_ia32_am_flavour(res, ia32_B);
3608 set_ia32_op_type(res, ia32_AddrModeD);
3610 /* Load MEM -> SSE */
3611 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3612 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3613 set_ia32_use_frame(res);
3614 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3615 set_ia32_am_support(res, ia32_am_Source);
3616 set_ia32_am_flavour(res, ia32_B);
3617 set_ia32_op_type(res, ia32_AddrModeS);
3618 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3624 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3626 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3627 ir_node *block = transform_node(get_nodes_block(node));
3628 ir_node *val = get_irn_n(node, 1);
3629 ir_node *new_val = transform_node(val);
3630 ia32_code_gen_t *cg = env.cg;
3631 ir_graph *irg = env.irg;
3632 ir_node *res = NULL;
3633 ir_entity *fent = get_ia32_frame_ent(node);
3634 ir_mode *lsmode = get_ia32_ls_mode(node);
3636 ir_node *noreg, *new_ptr, *new_mem;
3640 if (! USE_SSE2(cg)) {
3641 /* SSE unit is not used -> skip this node. */
3645 ptr = get_irn_n(node, 0);
3646 new_ptr = transform_node(ptr);
3647 mem = get_irn_n(node, 2);
3648 new_mem = transform_node(mem);
3649 noreg = ia32_new_NoReg_gp(cg);
3650 dbgi = get_irn_dbg_info(node);
3652 /* Store SSE -> MEM */
3653 if (is_ia32_xLoad(skip_Proj(new_val))) {
3654 ir_node *ld = skip_Proj(new_val);
3656 /* we can vfld the value directly into the fpu */
3657 fent = get_ia32_frame_ent(ld);
3658 ptr = get_irn_n(ld, 0);
3659 offs = get_ia32_am_offs_int(ld);
3661 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3662 set_ia32_frame_ent(res, fent);
3663 set_ia32_use_frame(res);
3664 set_ia32_ls_mode(res, lsmode);
3665 set_ia32_am_support(res, ia32_am_Dest);
3666 set_ia32_am_flavour(res, ia32_B);
3667 set_ia32_op_type(res, ia32_AddrModeD);
3671 /* Load MEM -> x87 */
3672 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3673 set_ia32_frame_ent(res, fent);
3674 set_ia32_use_frame(res);
3675 set_ia32_ls_mode(res, lsmode);
3676 add_ia32_am_offs_int(res, offs);
3677 set_ia32_am_support(res, ia32_am_Source);
3678 set_ia32_am_flavour(res, ia32_B);
3679 set_ia32_op_type(res, ia32_AddrModeS);
3680 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3685 /*********************************************************
3688 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3689 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3690 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3691 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3693 *********************************************************/
3696 * the BAD transformer.
3698 static ir_node *bad_transform(ir_node *node) {
3699 panic("No transform function for %+F available.\n", node);
3703 static ir_node *gen_End(ir_node *node) {
3704 /* end has to be duplicated manually because we need a dynamic in array */
3705 ir_graph *irg = env.irg;
3706 dbg_info *dbgi = get_irn_dbg_info(node);
3707 ir_node *block = transform_node(get_nodes_block(node));
3711 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3712 copy_node_attr(node, new_end);
3713 duplicate_deps(node, new_end);
3715 set_irg_end(irg, new_end);
3716 set_new_node(new_end, new_end);
3718 /* transform preds */
3719 arity = get_irn_arity(node);
3720 for (i = 0; i < arity; ++i) {
3721 ir_node *in = get_irn_n(node, i);
3722 ir_node *new_in = transform_node(in);
3724 add_End_keepalive(new_end, new_in);
3730 static ir_node *gen_Block(ir_node *node) {
3731 ir_graph *irg = env.irg;
3732 dbg_info *dbgi = get_irn_dbg_info(node);
3733 ir_node *start_block = env.old_anchors[anchor_start_block];
3738 * We replace the ProjX from the start node with a jump,
3739 * so the startblock has no preds anymore now
3741 if (node == start_block) {
3742 return new_rd_Block(dbgi, irg, 0, NULL);
3745 /* we use the old blocks for now, because jumps allow cycles in the graph
3746 * we have to fix this later */
3747 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3748 get_irn_arity(node), get_irn_in(node) + 1);
3749 copy_node_attr(node, block);
3751 #ifdef DEBUG_libfirm
3752 block->node_nr = node->node_nr;
3754 set_new_node(node, block);
3756 /* put the preds in the worklist */
3757 arity = get_irn_arity(node);
3758 for (i = 0; i < arity; ++i) {
3759 ir_node *in = get_irn_n(node, i);
3760 pdeq_putr(env.worklist, in);
3766 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3767 ir_node *block = transform_node(get_nodes_block(node));
3768 ir_node *pred = get_Proj_pred(node);
3769 ir_node *new_pred = transform_node(pred);
3770 ir_graph *irg = env.irg;
3771 dbg_info *dbgi = get_irn_dbg_info(node);
3772 long proj = get_Proj_proj(node);
3774 if (proj == pn_be_AddSP_res) {
3775 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3776 arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3778 } else if (proj == pn_be_AddSP_M) {
3779 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3783 return new_rd_Unknown(irg, get_irn_mode(node));
3786 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3787 ir_node *block = transform_node(get_nodes_block(node));
3788 ir_node *pred = get_Proj_pred(node);
3789 ir_node *new_pred = transform_node(pred);
3790 ir_graph *irg = env.irg;
3791 dbg_info *dbgi = get_irn_dbg_info(node);
3792 long proj = get_Proj_proj(node);
3794 if (proj == pn_be_SubSP_res) {
3795 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3796 arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3798 } else if (proj == pn_be_SubSP_M) {
3799 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3803 return new_rd_Unknown(irg, get_irn_mode(node));
3806 static ir_node *gen_Proj_Load(ir_node *node) {
3807 ir_node *block = transform_node(get_nodes_block(node));
3808 ir_node *pred = get_Proj_pred(node);
3809 ir_node *new_pred = transform_node(pred);
3810 ir_graph *irg = env.irg;
3811 dbg_info *dbgi = get_irn_dbg_info(node);
3812 long proj = get_Proj_proj(node);
3814 /* renumber the proj */
3815 if (is_ia32_Load(new_pred)) {
3816 if (proj == pn_Load_res) {
3817 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3818 } else if (proj == pn_Load_M) {
3819 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3821 } else if (is_ia32_xLoad(new_pred)) {
3822 if (proj == pn_Load_res) {
3823 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3824 } else if (proj == pn_Load_M) {
3825 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3827 } else if (is_ia32_vfld(new_pred)) {
3828 if (proj == pn_Load_res) {
3829 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3830 } else if (proj == pn_Load_M) {
3831 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3836 return new_rd_Unknown(irg, get_irn_mode(node));
3839 static ir_node *gen_Proj_DivMod(ir_node *node) {
3840 ir_node *block = transform_node(get_nodes_block(node));
3841 ir_node *pred = get_Proj_pred(node);
3842 ir_node *new_pred = transform_node(pred);
3843 ir_graph *irg = env.irg;
3844 dbg_info *dbgi = get_irn_dbg_info(node);
3845 ir_mode *mode = get_irn_mode(node);
3846 long proj = get_Proj_proj(node);
3848 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3850 switch (get_irn_opcode(pred)) {
3854 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3856 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3864 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3866 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3874 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3875 case pn_DivMod_res_div:
3876 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3877 case pn_DivMod_res_mod:
3878 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3888 return new_rd_Unknown(irg, mode);
3891 static ir_node *gen_Proj_CopyB(ir_node *node) {
3892 ir_node *block = transform_node(get_nodes_block(node));
3893 ir_node *pred = get_Proj_pred(node);
3894 ir_node *new_pred = transform_node(pred);
3895 ir_graph *irg = env.irg;
3896 dbg_info *dbgi = get_irn_dbg_info(node);
3897 ir_mode *mode = get_irn_mode(node);
3898 long proj = get_Proj_proj(node);
3901 case pn_CopyB_M_regular:
3902 if (is_ia32_CopyB_i(new_pred)) {
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3904 } else if (is_ia32_CopyB(new_pred)) {
3905 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3913 return new_rd_Unknown(irg, mode);
3916 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3917 ir_node *block = transform_node(get_nodes_block(node));
3918 ir_node *pred = get_Proj_pred(node);
3919 ir_node *new_pred = transform_node(pred);
3920 ir_graph *irg = env.irg;
3921 dbg_info *dbgi = get_irn_dbg_info(node);
3922 ir_mode *mode = get_irn_mode(node);
3923 long proj = get_Proj_proj(node);
3926 case pn_ia32_l_vfdiv_M:
3927 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3928 case pn_ia32_l_vfdiv_res:
3929 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3934 return new_rd_Unknown(irg, mode);
3937 static ir_node *gen_Proj_Quot(ir_node *node) {
3938 ir_node *block = transform_node(get_nodes_block(node));
3939 ir_node *pred = get_Proj_pred(node);
3940 ir_node *new_pred = transform_node(pred);
3941 ir_graph *irg = env.irg;
3942 dbg_info *dbgi = get_irn_dbg_info(node);
3943 ir_mode *mode = get_irn_mode(node);
3944 long proj = get_Proj_proj(node);
3948 if (is_ia32_xDiv(new_pred)) {
3949 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3950 } else if (is_ia32_vfdiv(new_pred)) {
3951 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3955 if (is_ia32_xDiv(new_pred)) {
3956 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3957 } else if (is_ia32_vfdiv(new_pred)) {
3958 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3966 return new_rd_Unknown(irg, mode);
3969 static ir_node *gen_Proj_tls(ir_node *node) {
3970 ir_node *block = transform_node(get_nodes_block(node));
3971 ir_graph *irg = env.irg;
3972 dbg_info *dbgi = NULL;
3973 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3978 static ir_node *gen_Proj_be_Call(ir_node *node) {
3979 ir_node *block = transform_node(get_nodes_block(node));
3980 ir_node *call = get_Proj_pred(node);
3981 ir_node *new_call = transform_node(call);
3982 ir_graph *irg = env.irg;
3983 dbg_info *dbgi = get_irn_dbg_info(node);
3984 long proj = get_Proj_proj(node);
3985 ir_mode *mode = get_irn_mode(node);
3987 const arch_register_class_t *cls;
3989 /* The following is kinda tricky: If we're using SSE, then we have to
3990 * move the result value of the call in floating point registers to an
3991 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3992 * after the call, we have to make sure to correctly make the
3993 * MemProj and the result Proj use these 2 nodes
3995 if (proj == pn_be_Call_M_regular) {
3996 // get new node for result, are we doing the sse load/store hack?
3997 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3998 ir_node *call_res_new;
3999 ir_node *call_res_pred = NULL;
4001 if (call_res != NULL) {
4002 call_res_new = transform_node(call_res);
4003 call_res_pred = get_Proj_pred(call_res_new);
4006 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4007 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4009 assert(is_ia32_xLoad(call_res_pred));
4010 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
4013 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env.cg)) {
4015 ir_node *frame = get_irg_frame(irg);
4016 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
4018 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4020 const arch_register_class_t *cls;
4022 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
4023 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4025 /* store st(0) onto stack */
4026 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
4028 set_ia32_ls_mode(fstp, mode);
4029 set_ia32_op_type(fstp, ia32_AddrModeD);
4030 set_ia32_use_frame(fstp);
4031 set_ia32_am_flavour(fstp, ia32_am_B);
4032 set_ia32_am_support(fstp, ia32_am_Dest);
4034 /* load into SSE register */
4035 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4036 set_ia32_ls_mode(sse_load, mode);
4037 set_ia32_op_type(sse_load, ia32_AddrModeS);
4038 set_ia32_use_frame(sse_load);
4039 set_ia32_am_flavour(sse_load, ia32_am_B);
4040 set_ia32_am_support(sse_load, ia32_am_Source);
4042 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
4044 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4046 /* get a Proj representing a caller save register */
4047 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4048 assert(is_Proj(p) && "Proj expected.");
4050 /* user of the the proj is the Keep */
4051 p = get_edge_src_irn(get_irn_out_edge_first(p));
4052 assert(be_is_Keep(p) && "Keep expected.");
4054 /* keep the result */
4055 cls = arch_get_irn_reg_class(env.cg->arch_env, sse_load, -1);
4056 keepin[0] = sse_load;
4057 be_new_Keep(cls, irg, block, 1, keepin);
4062 /* transform call modes */
4063 if (mode_is_data(mode)) {
4064 cls = arch_get_irn_reg_class(env.cg->arch_env, node, -1);
4068 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4071 static ir_node *gen_Proj(ir_node *node) {
4072 ir_graph *irg = env.irg;
4073 dbg_info *dbgi = get_irn_dbg_info(node);
4074 ir_node *pred = get_Proj_pred(node);
4075 long proj = get_Proj_proj(node);
4077 if (is_Store(pred) || be_is_FrameStore(pred)) {
4078 if (proj == pn_Store_M) {
4079 return transform_node(pred);
4082 return new_r_Bad(irg);
4084 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4085 return gen_Proj_Load(node);
4086 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4087 return gen_Proj_DivMod(node);
4088 } else if (is_CopyB(pred)) {
4089 return gen_Proj_CopyB(node);
4090 } else if (is_Quot(pred)) {
4091 return gen_Proj_Quot(node);
4092 } else if (is_ia32_l_vfdiv(pred)) {
4093 return gen_Proj_l_vfdiv(node);
4094 } else if (be_is_SubSP(pred)) {
4095 return gen_Proj_be_SubSP(node);
4096 } else if (be_is_AddSP(pred)) {
4097 return gen_Proj_be_AddSP(node);
4098 } else if (be_is_Call(pred)) {
4099 return gen_Proj_be_Call(node);
4100 } else if (get_irn_op(pred) == op_Start) {
4101 if (proj == pn_Start_X_initial_exec) {
4102 ir_node *block = get_nodes_block(pred);
4105 /* we exchange the ProjX with a jump */
4106 block = transform_node(block);
4107 jump = new_rd_Jmp(dbgi, irg, block);
4108 ir_fprintf(stderr, "created jump: %+F\n", jump);
4111 if (node == env.old_anchors[anchor_tls]) {
4112 return gen_Proj_tls(node);
4115 ir_node *new_pred = transform_node(pred);
4116 ir_node *block = transform_node(get_nodes_block(node));
4117 ir_mode *mode = get_irn_mode(node);
4118 if (mode_needs_gp_reg(mode)) {
4119 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4120 get_Proj_proj(node));
4121 #ifdef DEBUG_libfirm
4122 new_proj->node_nr = node->node_nr;
4128 return duplicate_node(node);
4132 * Enters all transform functions into the generic pointer
4134 static void register_transformers(void) {
4135 ir_op *op_Max, *op_Min, *op_Mulh;
4137 /* first clear the generic function pointer for all ops */
4138 clear_irp_opcodes_generic_func();
4140 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4141 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4181 /* transform ops from intrinsic lowering */
4201 /* GEN(ia32_l_vfist); TODO */
4203 GEN(ia32_l_X87toSSE);
4204 GEN(ia32_l_SSEtoX87);
4209 /* we should never see these nodes */
4224 /* handle generic backend nodes */
4234 /* set the register for all Unknown nodes */
4237 op_Max = get_op_Max();
4240 op_Min = get_op_Min();
4243 op_Mulh = get_op_Mulh();
4251 static void duplicate_deps(ir_node *old_node, ir_node *new_node)
4254 int deps = get_irn_deps(old_node);
4256 for (i = 0; i < deps; ++i) {
4257 ir_node *dep = get_irn_dep(old_node, i);
4258 ir_node *new_dep = transform_node(dep);
4260 add_irn_dep(new_node, new_dep);
4264 static ir_node *duplicate_node(ir_node *node)
4266 ir_node *block = transform_node(get_nodes_block(node));
4267 ir_graph *irg = env.irg;
4268 dbg_info *dbgi = get_irn_dbg_info(node);
4269 ir_mode *mode = get_irn_mode(node);
4270 ir_op *op = get_irn_op(node);
4274 arity = get_irn_arity(node);
4275 if (op->opar == oparity_dynamic) {
4276 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
4277 for (i = 0; i < arity; ++i) {
4278 ir_node *in = get_irn_n(node, i);
4279 in = transform_node(in);
4280 add_irn_n(new_node, in);
4283 ir_node **ins = alloca(arity * sizeof(ins[0]));
4284 for (i = 0; i < arity; ++i) {
4285 ir_node *in = get_irn_n(node, i);
4286 ins[i] = transform_node(in);
4289 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
4292 copy_node_attr(node, new_node);
4293 duplicate_deps(node, new_node);
4295 #ifdef DEBUG_libfirm
4296 new_node->node_nr = node->node_nr;
4303 * Calls transformation function for given node and marks it visited.
4305 static ir_node *transform_node(ir_node *node) {
4309 if (irn_visited(node)) {
4310 new_node = get_new_node(node);
4311 assert(new_node != NULL);
4315 mark_irn_visited(node);
4316 DEBUG_ONLY(set_new_node(node, NULL));
4318 op = get_irn_op(node);
4319 if (op->ops.generic) {
4320 transform_func *transform = (transform_func *)op->ops.generic;
4322 new_node = transform(node);
4323 assert(new_node != NULL);
4325 new_node = duplicate_node(node);
4327 DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
4329 set_new_node(node, new_node);
4330 mark_irn_visited(new_node);
4331 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
4336 * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
4338 static void fix_loops(ir_node *node) {
4341 if (irn_visited(node))
4344 mark_irn_visited(node);
4346 assert(node_is_in_irgs_storage(env.irg, node));
4348 if (! is_Block(node)) {
4349 ir_node *block = get_nodes_block(node);
4350 ir_node *new_block = (ir_node *)get_irn_link(block);
4352 if (new_block != NULL) {
4353 set_nodes_block(node, new_block);
4360 arity = get_irn_arity(node);
4361 for (i = 0; i < arity; ++i) {
4362 ir_node *in = get_irn_n(node, i);
4363 ir_node *nw = (ir_node *)get_irn_link(in);
4365 if (nw != NULL && nw != in) {
4366 set_irn_n(node, i, nw);
4373 arity = get_irn_deps(node);
4374 for (i = 0; i < arity; ++i) {
4375 ir_node *in = get_irn_dep(node, i);
4376 ir_node *nw = (ir_node *)get_irn_link(in);
4378 if (nw != NULL && nw != in) {
4379 set_irn_dep(node, i, nw);
4387 static void pre_transform_node(ir_node **place)
4392 *place = transform_node(*place);
4396 * Transforms all nodes. Deletes the old obstack and creates a new one.
4398 static void transform_nodes(ia32_code_gen_t *cg) {
4400 ir_graph *irg = cg->irg;
4403 hook_dead_node_elim(irg, 1);
4405 inc_irg_visited(irg);
4409 env.visited = get_irg_visited(irg);
4410 env.worklist = new_pdeq();
4411 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
4413 old_end = get_irg_end(irg);
4415 /* put all anchor nodes in the worklist */
4416 for (i = 0; i < anchor_max; ++i) {
4417 ir_node *anchor = irg->anchors[i];
4421 pdeq_putr(env.worklist, anchor);
4423 /* remember anchor */
4424 env.old_anchors[i] = anchor;
4425 /* and set it to NULL to make sure we don't accidently use it */
4426 irg->anchors[i] = NULL;
4429 /* pre transform some anchors (so they are available in the other transform
4431 set_irg_bad(irg, transform_node(env.old_anchors[anchor_bad]));
4432 set_irg_no_mem(irg, transform_node(env.old_anchors[anchor_no_mem]));
4433 set_irg_start_block(irg, transform_node(env.old_anchors[anchor_start_block]));
4434 set_irg_start(irg, transform_node(env.old_anchors[anchor_start]));
4435 set_irg_frame(irg, transform_node(env.old_anchors[anchor_frame]));
4437 pre_transform_node(&cg->unknown_gp);
4438 pre_transform_node(&cg->unknown_vfp);
4439 pre_transform_node(&cg->unknown_xmm);
4440 pre_transform_node(&cg->noreg_gp);
4441 pre_transform_node(&cg->noreg_vfp);
4442 pre_transform_node(&cg->noreg_xmm);
4444 /* process worklist (this should transform all nodes in the graph) */
4445 while (! pdeq_empty(env.worklist)) {
4446 ir_node *node = pdeq_getl(env.worklist);
4447 transform_node(node);
4450 /* fix loops and set new anchors*/
4451 inc_irg_visited(irg);
4452 for (i = 0; i < anchor_max; ++i) {
4453 ir_node *anchor = env.old_anchors[i];
4458 anchor = get_irn_link(anchor);
4460 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4461 irg->anchors[i] = anchor;
4464 del_pdeq(env.worklist);
4466 hook_dead_node_elim(irg, 0);
4469 void ia32_transform_graph(ia32_code_gen_t *cg)
4471 ir_graph *irg = cg->irg;
4472 be_irg_t *birg = cg->birg;
4473 ir_graph *old_current_ir_graph = current_ir_graph;
4474 int old_interprocedural_view = get_interprocedural_view();
4475 struct obstack *old_obst = NULL;
4476 struct obstack *new_obst = NULL;
4478 current_ir_graph = irg;
4479 set_interprocedural_view(0);
4480 register_transformers();
4482 /* most analysis info is wrong after transformation */
4483 free_callee_info(irg);
4485 irg->outs_state = outs_none;
4487 free_loop_information(irg);
4488 set_irg_doms_inconsistent(irg);
4489 be_invalidate_liveness(birg);
4490 be_invalidate_dom_front(birg);
4492 /* create a new obstack */
4493 old_obst = irg->obst;
4494 new_obst = xmalloc(sizeof(*new_obst));
4495 obstack_init(new_obst);
4496 irg->obst = new_obst;
4497 irg->last_node_idx = 0;
4499 /* create new value table for CSE */
4500 del_identities(irg->value_table);
4501 irg->value_table = new_identities();
4503 /* do the main transformation */
4504 transform_nodes(cg);
4506 /* we don't want the globals anchor anymore */
4507 set_irg_globals(irg, new_r_Bad(irg));
4509 /* free the old obstack */
4510 obstack_free(old_obst, 0);
4514 current_ir_graph = old_current_ir_graph;
4515 set_interprocedural_view(old_interprocedural_view);
4517 /* recalculate edges */
4518 edges_deactivate(irg);
4519 edges_activate(irg);
4523 * Transforms a psi condition.
4525 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4528 /* if the mode is target mode, we have already seen this part of the tree */
4529 if (get_irn_mode(cond) == mode)
4532 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4534 set_irn_mode(cond, mode);
4536 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4537 ir_node *in = get_irn_n(cond, i);
4539 /* if in is a compare: transform into Set/xCmp */
4541 ir_node *new_op = NULL;
4542 ir_node *cmp = get_Proj_pred(in);
4543 ir_node *cmp_a = get_Cmp_left(cmp);
4544 ir_node *cmp_b = get_Cmp_right(cmp);
4545 dbg_info *dbgi = get_irn_dbg_info(cmp);
4546 ir_graph *irg = get_irn_irg(cmp);
4547 ir_node *block = get_nodes_block(cmp);
4548 ir_node *noreg = ia32_new_NoReg_gp(cg);
4549 ir_node *nomem = new_rd_NoMem(irg);
4550 int pnc = get_Proj_proj(in);
4552 /* this is a compare */
4553 if (mode_is_float(mode)) {
4554 /* Psi is float, we need a floating point compare */
4557 ir_mode *m = get_irn_mode(cmp_a);
4559 if (! mode_is_float(m)) {
4560 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4561 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4562 } else if (m == mode_F) {
4563 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4564 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4565 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4568 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4569 set_ia32_pncode(new_op, pnc);
4570 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4577 construct_binop_func *set_func = NULL;
4579 if (mode_is_float(get_irn_mode(cmp_a))) {
4580 /* 1st case: compare operands are floats */
4585 set_func = new_rd_ia32_xCmpSet;
4588 set_func = new_rd_ia32_vfCmpSet;
4591 pnc &= 7; /* fp compare -> int compare */
4593 /* 2nd case: compare operand are integer too */
4594 set_func = new_rd_ia32_CmpSet;
4597 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4598 if (! mode_is_signed(mode))
4599 pnc |= ia32_pn_Cmp_Unsigned;
4601 set_ia32_pncode(new_op, pnc);
4602 set_ia32_am_support(new_op, ia32_am_Source);
4605 /* the the new compare as in */
4606 set_irn_n(cond, i, new_op);
4608 /* another complex condition */
4609 transform_psi_cond(in, mode, cg);
4615 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4616 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4617 * each compare, which causes the compare result to be stored in a register. The
4618 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4620 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4621 ia32_code_gen_t *cg = env;
4622 ir_node *psi_sel, *new_cmp, *block;
4627 if (get_irn_opcode(node) != iro_Psi)
4630 psi_sel = get_Psi_cond(node, 0);
4632 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4633 if (is_Proj(psi_sel)) {
4634 assert(is_Cmp(get_Proj_pred(psi_sel)));
4638 //mode = get_irn_mode(node);
4639 // TODO probably wrong...
4642 transform_psi_cond(psi_sel, mode, cg);
4644 irg = get_irn_irg(node);
4645 block = get_nodes_block(node);
4647 /* we need to compare the evaluated condition tree with 0 */
4648 mode = get_irn_mode(node);
4649 if (mode_is_float(mode)) {
4650 /* BEWARE: new_r_Const_long works for floating point as well */
4651 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4653 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4654 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4655 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4657 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4658 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4659 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4662 set_Psi_cond(node, 0, new_cmp);
4665 void ia32_init_transform(void)
4667 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");