18 #include "../benode_t.h"
19 #include "bearch_ia32_t.h"
21 #include "ia32_nodes_attr.h"
22 #include "../arch/archop.h" /* we need this for Min and Max nodes */
23 #include "ia32_transform.h"
24 #include "ia32_new_nodes.h"
26 #include "gen_ia32_regalloc_if.h"
28 #define SFP_SIGN "0x80000000"
29 #define DFP_SIGN "0x8000000000000000"
30 #define SFP_ABS "0x7FFFFFFF"
31 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
33 #define TP_SFP_SIGN "ia32_sfp_sign"
34 #define TP_DFP_SIGN "ia32_dfp_sign"
35 #define TP_SFP_ABS "ia32_sfp_abs"
36 #define TP_DFP_ABS "ia32_dfp_abs"
38 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
39 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
40 #define ENT_SFP_ABS "IA32_SFP_ABS"
41 #define ENT_DFP_ABS "IA32_DFP_ABS"
43 extern ir_op *get_op_Mulh(void);
45 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
46 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
48 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
49 ir_node *op, ir_node *mem, ir_mode *mode);
52 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
55 /****************************************************************************************************
57 * | | | | / _| | | (_)
58 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
59 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
60 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
61 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
63 ****************************************************************************************************/
70 /* Compares two (entity, tarval) combinations */
71 static int cmp_tv_ent(const void *a, const void *b, size_t len) {
72 const struct tv_ent *e1 = a;
73 const struct tv_ent *e2 = b;
75 return !(e1->tv == e2->tv);
78 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
79 static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
80 static set *const_set = NULL;
92 const_set = new_set(cmp_tv_ent, 10);
97 tp_name = TP_SFP_SIGN;
98 ent_name = ENT_SFP_SIGN;
102 tp_name = TP_DFP_SIGN;
103 ent_name = ENT_DFP_SIGN;
107 tp_name = TP_SFP_ABS;
108 ent_name = ENT_SFP_ABS;
112 tp_name = TP_DFP_ABS;
113 ent_name = ENT_DFP_ABS;
119 key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
122 entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
125 tp = new_type_primitive(new_id_from_str(tp_name), mode);
126 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
128 set_entity_ld_ident(ent, get_entity_ident(ent));
129 set_entity_visibility(ent, visibility_local);
130 set_entity_variability(ent, variability_constant);
131 set_entity_allocation(ent, allocation_static);
133 /* we create a new entity here: It's initialization must resist on the
135 rem = current_ir_graph;
136 current_ir_graph = get_const_code_irg();
137 cnst = new_Const(mode, key.tv);
138 current_ir_graph = rem;
140 set_atomic_ent_value(ent, cnst);
142 /* set the entry for hashmap */
151 /* determine if one operator is an Imm */
152 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
154 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
155 else return is_ia32_Cnst(op2) ? op2 : NULL;
158 /* determine if one operator is not an Imm */
159 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
160 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
165 * Construct a standard binary operation, set AM and immediate if required.
167 * @param env The transformation environment
168 * @param op1 The first operand
169 * @param op2 The second operand
170 * @param func The node constructor function
171 * @return The constructed ia32 node.
173 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
174 ir_node *new_op = NULL;
175 ir_mode *mode = env->mode;
176 dbg_info *dbg = env->dbg;
177 ir_graph *irg = env->irg;
178 ir_node *block = env->block;
179 firm_dbg_module_t *mod = env->mod;
180 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
181 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
182 ir_node *nomem = new_NoMem();
183 ir_node *expr_op, *imm_op;
185 /* Check if immediate optimization is on and */
186 /* if it's an operation with immediate. */
187 if (! env->cg->opt.immops) {
191 else if (is_op_commutative(get_irn_op(env->irn))) {
192 imm_op = get_immediate_op(op1, op2);
193 expr_op = get_expr_op(op1, op2);
196 imm_op = get_immediate_op(NULL, op2);
197 expr_op = get_expr_op(op1, op2);
200 assert((expr_op || imm_op) && "invalid operands");
203 /* We have two consts here: not yet supported */
207 if (mode_is_float(mode)) {
208 /* floating point operations */
210 DB((mod, LEVEL_1, "FP with immediate ..."));
211 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
212 set_ia32_Immop_attr(new_op, imm_op);
213 set_ia32_am_support(new_op, ia32_am_None);
216 DB((mod, LEVEL_1, "FP binop ..."));
217 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
218 set_ia32_am_support(new_op, ia32_am_Source);
222 /* integer operations */
224 /* This is expr + const */
225 DB((mod, LEVEL_1, "INT with immediate ..."));
226 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
227 set_ia32_Immop_attr(new_op, imm_op);
230 set_ia32_am_support(new_op, ia32_am_Dest);
233 DB((mod, LEVEL_1, "INT binop ..."));
234 /* This is a normal operation */
235 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
238 set_ia32_am_support(new_op, ia32_am_Full);
242 if (is_op_commutative(get_irn_op(env->irn))) {
243 set_ia32_commutative(new_op);
246 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
252 * Construct a shift/rotate binary operation, sets AM and immediate if required.
254 * @param env The transformation environment
255 * @param op1 The first operand
256 * @param op2 The second operand
257 * @param func The node constructor function
258 * @return The constructed ia32 node.
260 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
261 ir_node *new_op = NULL;
262 ir_mode *mode = env->mode;
263 dbg_info *dbg = env->dbg;
264 ir_graph *irg = env->irg;
265 ir_node *block = env->block;
266 firm_dbg_module_t *mod = env->mod;
267 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
268 ir_node *nomem = new_NoMem();
269 ir_node *expr_op, *imm_op;
272 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
274 /* Check if immediate optimization is on and */
275 /* if it's an operation with immediate. */
276 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
277 expr_op = get_expr_op(op1, op2);
279 assert((expr_op || imm_op) && "invalid operands");
282 /* We have two consts here: not yet supported */
286 /* Limit imm_op within range imm8 */
288 tv = get_ia32_Immop_tarval(imm_op);
291 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
298 /* integer operations */
300 /* This is shift/rot with const */
301 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
303 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
304 set_ia32_Immop_attr(new_op, imm_op);
307 /* This is a normal shift/rot */
308 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
309 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
313 set_ia32_am_support(new_op, ia32_am_Dest);
315 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
320 * Construct a standard unary operation, set AM and immediate if required.
322 * @param env The transformation environment
323 * @param op The operand
324 * @param func The node constructor function
325 * @return The constructed ia32 node.
327 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
328 ir_node *new_op = NULL;
329 ir_mode *mode = env->mode;
330 dbg_info *dbg = env->dbg;
331 firm_dbg_module_t *mod = env->mod;
332 ir_graph *irg = env->irg;
333 ir_node *block = env->block;
334 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
335 ir_node *nomem = new_NoMem();
337 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
339 if (mode_is_float(mode)) {
340 DB((mod, LEVEL_1, "FP unop ..."));
341 /* floating point operations don't support implicit store */
342 set_ia32_am_support(new_op, ia32_am_None);
345 DB((mod, LEVEL_1, "INT unop ..."));
346 set_ia32_am_support(new_op, ia32_am_Dest);
349 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
355 * Creates an ia32 Add with immediate.
357 * @param env The transformation environment
358 * @param expr_op The expression operator
359 * @param const_op The constant
360 * @return the created ia32 Add node
362 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
363 ir_node *new_op = NULL;
364 tarval *tv = get_ia32_Immop_tarval(const_op);
365 firm_dbg_module_t *mod = env->mod;
366 dbg_info *dbg = env->dbg;
367 ir_graph *irg = env->irg;
368 ir_node *block = env->block;
369 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
370 ir_node *nomem = new_NoMem();
372 tarval_classification_t class_tv, class_negtv;
374 /* try to optimize to inc/dec */
375 if (env->cg->opt.incdec && tv) {
376 /* optimize tarvals */
377 class_tv = classify_tarval(tv);
378 class_negtv = classify_tarval(tarval_neg(tv));
380 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
381 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
382 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
385 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
386 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
387 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
393 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
394 set_ia32_Immop_attr(new_op, const_op);
401 * Creates an ia32 Add.
403 * @param dbg firm node dbg
404 * @param block the block the new node should belong to
405 * @param op1 first operator
406 * @param op2 second operator
407 * @param mode node mode
408 * @return the created ia32 Add node
410 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
411 ir_node *new_op = NULL;
412 dbg_info *dbg = env->dbg;
413 ir_mode *mode = env->mode;
414 ir_graph *irg = env->irg;
415 ir_node *block = env->block;
416 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
417 ir_node *nomem = new_NoMem();
418 ir_node *expr_op, *imm_op;
420 /* Check if immediate optimization is on and */
421 /* if it's an operation with immediate. */
422 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
423 expr_op = get_expr_op(op1, op2);
425 assert((expr_op || imm_op) && "invalid operands");
427 if (mode_is_float(mode)) {
428 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
433 /* No expr_op means, that we have two const - one symconst and */
434 /* one tarval or another symconst - because this case is not */
435 /* covered by constant folding */
437 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
438 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
439 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
442 set_ia32_am_support(new_op, ia32_am_Source);
443 set_ia32_op_type(new_op, ia32_AddrModeS);
444 set_ia32_am_flavour(new_op, ia32_am_O);
446 /* Lea doesn't need a Proj */
450 /* This is expr + const */
451 new_op = gen_imm_Add(env, expr_op, imm_op);
454 set_ia32_am_support(new_op, ia32_am_Dest);
457 /* This is a normal add */
458 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
461 set_ia32_am_support(new_op, ia32_am_Full);
465 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
471 * Creates an ia32 Mul.
473 * @param dbg firm node dbg
474 * @param block the block the new node should belong to
475 * @param op1 first operator
476 * @param op2 second operator
477 * @param mode node mode
478 * @return the created ia32 Mul node
480 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
483 if (mode_is_float(env->mode)) {
484 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
487 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
496 * Creates an ia32 Mulh.
497 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
498 * this result while Mul returns the lower 32 bit.
500 * @param env The transformation environment
501 * @param op1 The first operator
502 * @param op2 The second operator
503 * @return the created ia32 Mulh node
505 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
506 ir_node *proj_EAX, *proj_EDX, *mulh;
509 assert(mode_is_float(env->mode) && "Mulh with float not supported");
510 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
511 mulh = get_Proj_pred(proj_EAX);
512 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
514 /* to be on the save side */
515 set_Proj_proj(proj_EAX, pn_EAX);
517 if (get_ia32_cnst(mulh)) {
518 /* Mulh with const cannot have AM */
519 set_ia32_am_support(mulh, ia32_am_None);
522 /* Mulh cannot have AM for destination */
523 set_ia32_am_support(mulh, ia32_am_Source);
529 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
537 * Creates an ia32 And.
539 * @param env The transformation environment
540 * @param op1 The first operator
541 * @param op2 The second operator
542 * @return The created ia32 And node
544 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
545 if (mode_is_float(env->mode)) {
546 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
549 return gen_binop(env, op1, op2, new_rd_ia32_And);
556 * Creates an ia32 Or.
558 * @param env The transformation environment
559 * @param op1 The first operator
560 * @param op2 The second operator
561 * @return The created ia32 Or node
563 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
564 if (mode_is_float(env->mode)) {
565 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
568 return gen_binop(env, op1, op2, new_rd_ia32_Or);
575 * Creates an ia32 Eor.
577 * @param env The transformation environment
578 * @param op1 The first operator
579 * @param op2 The second operator
580 * @return The created ia32 Eor node
582 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
583 if (mode_is_float(env->mode)) {
584 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
587 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
594 * Creates an ia32 Max.
596 * @param env The transformation environment
597 * @param op1 The first operator
598 * @param op2 The second operator
599 * @return the created ia32 Max node
601 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
604 if (mode_is_float(env->mode)) {
605 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
608 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
609 set_ia32_am_support(new_op, ia32_am_None);
618 * Creates an ia32 Min.
620 * @param env The transformation environment
621 * @param op1 The first operator
622 * @param op2 The second operator
623 * @return the created ia32 Min node
625 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
628 if (mode_is_float(env->mode)) {
629 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
632 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
633 set_ia32_am_support(new_op, ia32_am_None);
642 * Creates an ia32 Sub with immediate.
644 * @param env The transformation environment
645 * @param op1 The first operator
646 * @param op2 The second operator
647 * @return The created ia32 Sub node
649 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
650 ir_node *new_op = NULL;
651 tarval *tv = get_ia32_Immop_tarval(const_op);
652 firm_dbg_module_t *mod = env->mod;
653 dbg_info *dbg = env->dbg;
654 ir_graph *irg = env->irg;
655 ir_node *block = env->block;
656 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
657 ir_node *nomem = new_NoMem();
659 tarval_classification_t class_tv, class_negtv;
661 /* try to optimize to inc/dec */
662 if (env->cg->opt.incdec && tv) {
663 /* optimize tarvals */
664 class_tv = classify_tarval(tv);
665 class_negtv = classify_tarval(tarval_neg(tv));
667 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
668 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
669 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
672 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
673 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
674 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
680 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
681 set_ia32_Immop_attr(new_op, const_op);
688 * Creates an ia32 Sub.
690 * @param env The transformation environment
691 * @param op1 The first operator
692 * @param op2 The second operator
693 * @return The created ia32 Sub node
695 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
696 ir_node *new_op = NULL;
697 dbg_info *dbg = env->dbg;
698 ir_mode *mode = env->mode;
699 ir_graph *irg = env->irg;
700 ir_node *block = env->block;
701 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
702 ir_node *nomem = new_NoMem();
703 ir_node *expr_op, *imm_op;
705 /* Check if immediate optimization is on and */
706 /* if it's an operation with immediate. */
707 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
708 expr_op = get_expr_op(op1, op2);
710 assert((expr_op || imm_op) && "invalid operands");
712 if (mode_is_float(mode)) {
713 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
718 /* No expr_op means, that we have two const - one symconst and */
719 /* one tarval or another symconst - because this case is not */
720 /* covered by constant folding */
722 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
723 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
724 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
727 set_ia32_am_support(new_op, ia32_am_Source);
728 set_ia32_op_type(new_op, ia32_AddrModeS);
729 set_ia32_am_flavour(new_op, ia32_am_O);
731 /* Lea doesn't need a Proj */
735 /* This is expr - const */
736 new_op = gen_imm_Sub(env, expr_op, imm_op);
739 set_ia32_am_support(new_op, ia32_am_Dest);
742 /* This is a normal sub */
743 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
746 set_ia32_am_support(new_op, ia32_am_Full);
750 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
756 * Generates an ia32 DivMod with additional infrastructure for the
757 * register allocator if needed.
759 * @param env The transformation environment
760 * @param dividend -no comment- :)
761 * @param divisor -no comment- :)
762 * @param dm_flav flavour_Div/Mod/DivMod
763 * @return The created ia32 DivMod node
765 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
767 ir_node *edx_node, *cltd;
769 dbg_info *dbg = env->dbg;
770 ir_graph *irg = env->irg;
771 ir_node *block = env->block;
772 ir_mode *mode = env->mode;
773 ir_node *irn = env->irn;
778 mem = get_Div_mem(irn);
781 mem = get_Mod_mem(irn);
784 mem = get_DivMod_mem(irn);
790 if (mode_is_signed(mode)) {
791 /* in signed mode, we need to sign extend the dividend */
792 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
793 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
794 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
797 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
798 set_ia32_Const_type(edx_node, ia32_Const);
799 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
802 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode);
804 set_ia32_flavour(res, dm_flav);
805 set_ia32_n_res(res, 2);
807 /* Only one proj is used -> We must add a second proj and */
808 /* connect this one to a Keep node to eat up the second */
809 /* destroyed register. */
810 if (get_irn_n_edges(irn) == 1) {
811 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
812 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
814 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
815 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
818 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
821 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
829 * Wrapper for generate_DivMod. Sets flavour_Mod.
831 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
832 return generate_DivMod(env, op1, op2, flavour_Mod);
838 * Wrapper for generate_DivMod. Sets flavour_Div.
840 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
841 return generate_DivMod(env, op1, op2, flavour_Div);
847 * Wrapper for generate_DivMod. Sets flavour_DivMod.
849 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
850 return generate_DivMod(env, op1, op2, flavour_DivMod);
856 * Creates an ia32 floating Div.
858 * @param env The transformation environment
859 * @param op1 The first operator
860 * @param op2 The second operator
861 * @return The created ia32 fDiv node
863 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
864 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
865 ir_node *nomem = new_rd_NoMem(env->irg);
868 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
869 set_ia32_am_support(new_op, ia32_am_Source);
877 * Creates an ia32 Shl.
879 * @param env The transformation environment
880 * @param op1 The first operator
881 * @param op2 The second operator
882 * @return The created ia32 Shl node
884 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
885 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
891 * Creates an ia32 Shr.
893 * @param env The transformation environment
894 * @param op1 The first operator
895 * @param op2 The second operator
896 * @return The created ia32 Shr node
898 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
899 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
905 * Creates an ia32 Shrs.
907 * @param env The transformation environment
908 * @param op1 The first operator
909 * @param op2 The second operator
910 * @return The created ia32 Shrs node
912 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
913 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
919 * Creates an ia32 RotL.
921 * @param env The transformation environment
922 * @param op1 The first operator
923 * @param op2 The second operator
924 * @return The created ia32 RotL node
926 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
927 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
933 * Creates an ia32 RotR.
934 * NOTE: There is no RotR with immediate because this would always be a RotL
935 * "imm-mode_size_bits" which can be pre-calculated.
937 * @param env The transformation environment
938 * @param op1 The first operator
939 * @param op2 The second operator
940 * @return The created ia32 RotR node
942 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
943 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
949 * Creates an ia32 RotR or RotL (depending on the found pattern).
951 * @param env The transformation environment
952 * @param op1 The first operator
953 * @param op2 The second operator
954 * @return The created ia32 RotL or RotR node
956 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
957 ir_node *rotate = NULL;
959 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
960 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
961 that means we can create a RotR instead of an Add and a RotL */
964 ir_node *pred = get_Proj_pred(op2);
966 if (is_ia32_Add(pred)) {
967 ir_node *pred_pred = get_irn_n(pred, 2);
968 tarval *tv = get_ia32_Immop_tarval(pred);
969 long bits = get_mode_size_bits(env->mode);
971 if (is_Proj(pred_pred)) {
972 pred_pred = get_Proj_pred(pred_pred);
975 if (is_ia32_Minus(pred_pred) &&
976 tarval_is_long(tv) &&
977 get_tarval_long(tv) == bits)
979 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
980 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
987 rotate = gen_RotL(env, op1, op2);
996 * Transforms a Conv node.
998 * @param env The transformation environment
999 * @param op The operator
1000 * @return The created ia32 Conv node
1002 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1003 return new_rd_ia32_Conv(env->dbg, env->irg, env->block, op, env->mode);
1009 * Transforms a Minus node.
1011 * @param env The transformation environment
1012 * @param op The operator
1013 * @return The created ia32 Minus node
1015 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1018 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1019 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1020 ir_node *nomem = new_rd_NoMem(env->irg);
1023 if (mode_is_float(env->mode)) {
1024 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1026 size = get_mode_size_bits(env->mode);
1027 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1029 set_ia32_sc(new_op, name);
1031 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1034 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1043 * Transforms a Not node.
1045 * @param env The transformation environment
1046 * @param op The operator
1047 * @return The created ia32 Not node
1049 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1052 if (mode_is_float(env->mode)) {
1056 new_op = gen_unop(env, op, new_rd_ia32_Not);
1065 * Transforms an Abs node.
1067 * @param env The transformation environment
1068 * @param op The operator
1069 * @return The created ia32 Abs node
1071 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1072 ir_node *res, *p_eax, *p_edx;
1073 dbg_info *dbg = env->dbg;
1074 ir_mode *mode = env->mode;
1075 ir_graph *irg = env->irg;
1076 ir_node *block = env->block;
1077 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1078 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1079 ir_node *nomem = new_NoMem();
1083 if (mode_is_float(mode)) {
1084 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1086 size = get_mode_size_bits(mode);
1087 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1089 set_ia32_sc(res, name);
1091 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1094 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1095 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1096 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1097 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1098 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1099 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1100 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1109 * Transforms a Load.
1111 * @param mod the debug module
1112 * @param block the block the new node should belong to
1113 * @param node the ir Load node
1114 * @param mode node mode
1115 * @return the created ia32 Load node
1117 static ir_node *gen_Load(ia32_transform_env_t *env) {
1118 ir_node *node = env->irn;
1119 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1122 if (mode_is_float(env->mode)) {
1123 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1126 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1129 set_ia32_am_support(new_op, ia32_am_Source);
1130 set_ia32_op_type(new_op, ia32_AddrModeS);
1131 set_ia32_am_flavour(new_op, ia32_B);
1132 set_ia32_ls_mode(new_op, get_Load_mode(node));
1140 * Transforms a Store.
1142 * @param mod the debug module
1143 * @param block the block the new node should belong to
1144 * @param node the ir Store node
1145 * @param mode node mode
1146 * @return the created ia32 Store node
1148 static ir_node *gen_Store(ia32_transform_env_t *env) {
1149 ir_node *node = env->irn;
1150 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1151 ir_node *val = get_Store_value(node);
1152 ir_node *ptr = get_Store_ptr(node);
1153 ir_node *mem = get_Store_mem(node);
1154 ir_node *sval = val;
1157 /* in case of storing a const -> make it an attribute */
1158 if (is_ia32_Cnst(val)) {
1162 if (mode_is_float(env->mode)) {
1163 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1166 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1169 /* stored const is an attribute (saves a register) */
1170 if (is_ia32_Cnst(val)) {
1171 set_ia32_Immop_attr(new_op, val);
1174 set_ia32_am_support(new_op, ia32_am_Dest);
1175 set_ia32_op_type(new_op, ia32_AddrModeD);
1176 set_ia32_am_flavour(new_op, ia32_B);
1177 set_ia32_ls_mode(new_op, get_irn_mode(val));
1184 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1186 * @param env The transformation environment
1187 * @return The transformed node.
1189 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1190 dbg_info *dbg = env->dbg;
1191 ir_graph *irg = env->irg;
1192 ir_node *block = env->block;
1193 ir_node *node = env->irn;
1194 ir_node *sel = get_Cond_selector(node);
1195 ir_mode *sel_mode = get_irn_mode(sel);
1196 ir_node *res = NULL;
1197 ir_node *pred = NULL;
1198 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1199 ir_node *nomem = new_NoMem();
1200 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1202 if (is_Proj(sel) && sel_mode == mode_b) {
1203 pred = get_Proj_pred(sel);
1205 /* get both compare operators */
1206 cmp_a = get_Cmp_left(pred);
1207 cmp_b = get_Cmp_right(pred);
1209 /* check if we can use a CondJmp with immediate */
1210 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1211 expr = get_expr_op(cmp_a, cmp_b);
1214 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1215 set_ia32_Immop_attr(res, cnst);
1218 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1221 set_ia32_pncode(res, get_Proj_proj(sel));
1222 set_ia32_am_support(res, ia32_am_Source);
1225 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1226 set_ia32_pncode(res, get_Cond_defaultProj(node));
1235 * Transforms a CopyB node.
1237 * @param env The transformation environment
1238 * @return The transformed node.
1240 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1241 ir_node *res = NULL;
1242 dbg_info *dbg = env->dbg;
1243 ir_graph *irg = env->irg;
1244 ir_mode *mode = env->mode;
1245 ir_node *block = env->block;
1246 ir_node *node = env->irn;
1247 ir_node *src = get_CopyB_src(node);
1248 ir_node *dst = get_CopyB_dst(node);
1249 ir_node *mem = get_CopyB_mem(node);
1250 int size = get_type_size_bytes(get_CopyB_type(node));
1253 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1254 /* then we need the size explicitly in ECX. */
1255 if (size >= 16 * 4) {
1256 rem = size & 0x3; /* size % 4 */
1259 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1260 set_ia32_op_type(res, ia32_Const);
1261 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1263 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1264 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1267 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1268 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1277 * Transforms a Mux node into CMov.
1279 * @param env The transformation environment
1280 * @return The transformed node.
1282 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1283 ir_node *node = env->irn;
1285 return new_rd_ia32_CMov(env->dbg, env->irg, env->block,
1286 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1291 /********************************************
1294 * | |__ ___ _ __ ___ __| | ___ ___
1295 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1296 * | |_) | __/ | | | (_) | (_| | __/\__ \
1297 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1299 ********************************************/
1301 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1302 ir_node *new_op = NULL;
1303 ir_node *node = env->irn;
1304 ir_node *op = get_irn_n(node, 0);
1305 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1306 ir_node *nomem = new_rd_NoMem(env->irg);
1308 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1309 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1310 set_ia32_am_support(new_op, ia32_am_Full);
1311 set_ia32_use_frame(new_op);
1313 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1316 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1317 ir_node *new_op = NULL;
1322 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1323 ir_node *new_op = NULL;
1330 /*********************************************************
1333 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1334 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1335 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1336 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1338 *********************************************************/
1341 * Transforms the given firm node (and maybe some other related nodes)
1342 * into one or more assembler nodes.
1344 * @param node the firm node
1345 * @param env the debug module
1347 void ia32_transform_node(ir_node *node, void *env) {
1348 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1349 opcode code = get_irn_opcode(node);
1350 ir_node *asm_node = NULL;
1351 ia32_transform_env_t tenv;
1356 tenv.block = get_nodes_block(node);
1357 tenv.dbg = get_irn_dbg_info(node);
1358 tenv.irg = current_ir_graph;
1360 tenv.mod = cgenv->mod;
1361 tenv.mode = get_irn_mode(node);
1364 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1365 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1366 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1367 #define IGN(a) case iro_##a: break
1368 #define BAD(a) case iro_##a: goto bad
1369 #define OTHER_BIN(a) \
1370 if (get_irn_op(node) == get_op_##a()) { \
1371 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1375 if (be_is_##a(node)) { \
1376 asm_node = gen_##a(&tenv); \
1380 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1427 /* constant transformation happens earlier */
1456 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1460 /* exchange nodes if a new one was generated */
1462 exchange(node, asm_node);
1463 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1466 DB((tenv.mod, LEVEL_1, "ignored\n"));