2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
122 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
123 dbg_info *dbgi, ir_node *new_block,
127 * Return true if a mode can be stored in the GP register set
129 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
130 if(mode == mode_fpcw)
132 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
136 * Returns 1 if irn is a Const representing 0, 0 otherwise
138 static INLINE int is_ia32_Const_0(ir_node *irn) {
139 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
140 && tarval_is_null(get_ia32_Immop_tarval(irn));
144 * Returns 1 if irn is a Const representing 1, 0 otherwise
146 static INLINE int is_ia32_Const_1(ir_node *irn) {
147 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
148 && tarval_is_one(get_ia32_Immop_tarval(irn));
152 * Collects all Projs of a node into the node array. Index is the projnum.
153 * BEWARE: The caller has to assure the appropriate array size!
155 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
156 const ir_edge_t *edge;
157 assert(get_irn_mode(irn) == mode_T && "need mode_T");
159 memset(projs, 0, size * sizeof(projs[0]));
161 foreach_out_edge(irn, edge) {
162 ir_node *proj = get_edge_src_irn(edge);
163 int proj_proj = get_Proj_proj(proj);
164 assert(proj_proj < size);
165 projs[proj_proj] = proj;
170 * Renumbers the proj having pn_old in the array tp pn_new
171 * and removes the proj from the array.
173 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
174 fprintf(stderr, "Warning: renumber_Proj used!\n");
176 set_Proj_proj(projs[pn_old], pn_new);
177 projs[pn_old] = NULL;
182 * creates a unique ident by adding a number to a tag
184 * @param tag the tag string, must contain a %d if a number
187 static ident *unique_id(const char *tag)
189 static unsigned id = 0;
192 snprintf(str, sizeof(str), tag, ++id);
193 return new_id_from_str(str);
197 * Get a primitive type for a mode.
199 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
201 pmap_entry *e = pmap_find(types, mode);
206 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
207 res = new_type_primitive(new_id_from_str(buf), mode);
208 set_type_alignment_bytes(res, 16);
209 pmap_insert(types, mode, res);
217 * Get an entity that is initialized with a tarval
219 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
221 tarval *tv = get_Const_tarval(cnst);
222 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
227 ir_mode *mode = get_irn_mode(cnst);
228 ir_type *tp = get_Const_type(cnst);
229 if (tp == firm_unknown_type)
230 tp = get_prim_type(cg->isa->types, mode);
232 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
234 set_entity_ld_ident(res, get_entity_ident(res));
235 set_entity_visibility(res, visibility_local);
236 set_entity_variability(res, variability_constant);
237 set_entity_allocation(res, allocation_static);
239 /* we create a new entity here: It's initialization must resist on the
241 rem = current_ir_graph;
242 current_ir_graph = get_const_code_irg();
243 set_atomic_ent_value(res, new_Const_type(tv, tp));
244 current_ir_graph = rem;
246 pmap_insert(cg->isa->tv_ent, tv, res);
254 static int is_Const_0(ir_node *node) {
258 return classify_Const(node) == CNST_NULL;
261 static int is_Const_1(ir_node *node) {
265 return classify_Const(node) == CNST_ONE;
269 * Transforms a Const.
271 static ir_node *gen_Const(ir_node *node) {
272 ir_graph *irg = current_ir_graph;
273 ir_node *old_block = get_nodes_block(node);
274 ir_node *block = be_transform_node(old_block);
275 dbg_info *dbgi = get_irn_dbg_info(node);
276 ir_mode *mode = get_irn_mode(node);
278 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env_cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env_cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env_cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
313 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet.
322 * So add a dependency to the initial frame pointer calculation to
323 * avoid that situation.
325 if (get_irg_start_block(irg) == block) {
326 add_irn_dep(load, get_irg_frame(irg));
329 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
332 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
339 set_ia32_Const_attr(cnst, node);
340 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
345 return new_r_Bad(irg);
349 * Transforms a SymConst.
351 static ir_node *gen_SymConst(ir_node *node) {
352 ir_graph *irg = current_ir_graph;
353 ir_node *old_block = get_nodes_block(node);
354 ir_node *block = be_transform_node(old_block);
355 dbg_info *dbgi = get_irn_dbg_info(node);
356 ir_mode *mode = get_irn_mode(node);
359 if (mode_is_float(mode)) {
360 if (USE_SSE2(env_cg))
361 cnst = new_rd_ia32_xConst(dbgi, irg, block);
363 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
364 //set_ia32_ls_mode(cnst, mode);
365 set_ia32_ls_mode(cnst, mode_E);
367 cnst = new_rd_ia32_Const(dbgi, irg, block);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 set_ia32_Const_attr(cnst, node);
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
389 } names [ia32_known_const_max] = {
390 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
391 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
392 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
393 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
412 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
413 tp = new_type_primitive(new_id_from_str(tp_name), mode);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 /* determine if one operator is an Imm */
451 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
453 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
455 return is_ia32_Cnst(op2) ? op2 : NULL;
459 /* determine if one operator is not an Imm */
460 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
461 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
464 static void fold_immediate(ir_node *node, int in1, int in2) {
468 if (!(env_cg->opt & IA32_OPT_IMMOPS))
471 left = get_irn_n(node, in1);
472 right = get_irn_n(node, in2);
473 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
474 /* we can only set right operand to immediate */
475 if(!is_ia32_commutative(node))
477 /* exchange left/right */
478 set_irn_n(node, in1, right);
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, left);
481 } else if(is_ia32_Cnst(right)) {
482 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
483 copy_ia32_Immop_attr(node, right);
488 clear_ia32_commutative(node);
489 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
490 get_ia32_am_arity(node));
494 * Construct a standard binary operation, set AM and immediate if required.
496 * @param op1 The first operand
497 * @param op2 The second operand
498 * @param func The node constructor function
499 * @return The constructed ia32 node.
501 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
502 construct_binop_func *func, int commutative)
504 ir_node *block = be_transform_node(get_nodes_block(node));
505 ir_graph *irg = current_ir_graph;
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
508 ir_node *nomem = new_NoMem();
511 ir_node *new_op1 = be_transform_node(op1);
512 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
513 if (is_ia32_Immediate(new_op2)) {
517 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
518 if (func == new_rd_ia32_IMul) {
519 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
521 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
524 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
526 set_ia32_commutative(new_node);
533 * Construct a standard binary operation, set AM and immediate if required.
535 * @param op1 The first operand
536 * @param op2 The second operand
537 * @param func The node constructor function
538 * @return The constructed ia32 node.
540 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
541 construct_binop_func *func)
543 ir_node *block = be_transform_node(get_nodes_block(node));
544 ir_node *new_op1 = be_transform_node(op1);
545 ir_node *new_op2 = be_transform_node(op2);
546 ir_node *new_node = NULL;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_graph *irg = current_ir_graph;
549 ir_mode *mode = get_irn_mode(node);
550 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
551 ir_node *nomem = new_NoMem();
553 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
555 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
556 if (is_op_commutative(get_irn_op(node))) {
557 set_ia32_commutative(new_node);
559 set_ia32_ls_mode(new_node, mode);
561 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
566 static ir_node *get_fpcw(void)
569 if(initial_fpcw != NULL)
572 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
573 &ia32_fp_cw_regs[REG_FPCW]);
574 initial_fpcw = be_transform_node(fpcw);
580 * Construct a standard binary operation, set AM and immediate if required.
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
588 construct_binop_float_func *func)
590 ir_node *block = be_transform_node(get_nodes_block(node));
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *new_op2 = be_transform_node(op2);
593 ir_node *new_node = NULL;
594 dbg_info *dbgi = get_irn_dbg_info(node);
595 ir_graph *irg = current_ir_graph;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
601 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
602 if (is_op_commutative(get_irn_op(node))) {
603 set_ia32_commutative(new_node);
606 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
612 * Construct a shift/rotate binary operation, sets AM and immediate if required.
614 * @param op1 The first operand
615 * @param op2 The second operand
616 * @param func The node constructor function
617 * @return The constructed ia32 node.
619 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
620 construct_binop_func *func)
622 ir_node *block = be_transform_node(get_nodes_block(node));
623 ir_node *new_op1 = be_transform_node(op1);
625 ir_node *new_op = NULL;
626 dbg_info *dbgi = get_irn_dbg_info(node);
627 ir_graph *irg = current_ir_graph;
628 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
629 ir_node *nomem = new_NoMem();
631 assert(! mode_is_float(get_irn_mode(node))
632 && "Shift/Rotate with float not supported");
634 new_op2 = create_immediate_or_transform(op2, 'N');
636 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
639 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
641 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
643 set_ia32_emit_cl(new_op);
650 * Construct a standard unary operation, set AM and immediate if required.
652 * @param op The operand
653 * @param func The node constructor function
654 * @return The constructed ia32 node.
656 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
658 ir_node *block = be_transform_node(get_nodes_block(node));
659 ir_node *new_op = be_transform_node(op);
660 ir_node *new_node = NULL;
661 ir_graph *irg = current_ir_graph;
662 dbg_info *dbgi = get_irn_dbg_info(node);
663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
664 ir_node *nomem = new_NoMem();
666 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
667 DB((dbg, LEVEL_1, "INT unop ..."));
668 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
670 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
676 * Creates an ia32 Add.
678 * @return the created ia32 Add node
680 static ir_node *gen_Add(ir_node *node) {
681 ir_node *block = be_transform_node(get_nodes_block(node));
682 ir_node *op1 = get_Add_left(node);
683 ir_node *new_op1 = be_transform_node(op1);
684 ir_node *op2 = get_Add_right(node);
685 ir_node *new_op2 = be_transform_node(op2);
686 ir_node *new_op = NULL;
687 ir_graph *irg = current_ir_graph;
688 dbg_info *dbgi = get_irn_dbg_info(node);
689 ir_mode *mode = get_irn_mode(node);
690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
691 ir_node *nomem = new_NoMem();
692 ir_node *expr_op, *imm_op;
694 /* Check if immediate optimization is on and */
695 /* if it's an operation with immediate. */
696 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
697 expr_op = get_expr_op(new_op1, new_op2);
699 assert((expr_op || imm_op) && "invalid operands");
701 if (mode_is_float(mode)) {
702 if (USE_SSE2(env_cg))
703 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
705 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
710 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
711 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
713 /* No expr_op means, that we have two const - one symconst and */
714 /* one tarval or another symconst - because this case is not */
715 /* covered by constant folding */
716 /* We need to check for: */
717 /* 1) symconst + const -> becomes a LEA */
718 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
719 /* linker doesn't support two symconsts */
721 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
722 /* this is the 2nd case */
723 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
725 set_ia32_am_flavour(new_op, ia32_am_B);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
728 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 } else if (tp1 == ia32_ImmSymConst) {
730 tarval *tv = get_ia32_Immop_tarval(new_op2);
731 long offs = get_tarval_long(tv);
733 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
734 add_irn_dep(new_op, get_irg_frame(irg));
735 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
738 add_ia32_am_offs_int(new_op, offs);
739 set_ia32_am_flavour(new_op, ia32_am_OB);
740 set_ia32_op_type(new_op, ia32_AddrModeS);
741 } else if (tp2 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op1);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
746 add_irn_dep(new_op, get_irg_frame(irg));
747 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
751 set_ia32_am_flavour(new_op, ia32_am_OB);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
754 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
755 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
756 tarval *restv = tarval_add(tv1, tv2);
758 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
760 new_op = new_rd_ia32_Const(dbgi, irg, block);
761 set_ia32_Const_tarval(new_op, restv);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
769 tarval_classification_t class_tv, class_negtv;
770 tarval *tv = get_ia32_Immop_tarval(imm_op);
772 /* optimize tarvals */
773 class_tv = classify_tarval(tv);
774 class_negtv = classify_tarval(tarval_neg(tv));
776 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
777 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
778 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
781 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
782 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
783 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
784 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
790 /* This is a normal add */
791 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
794 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
795 set_ia32_commutative(new_op);
797 fold_immediate(new_op, 2, 3);
799 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
805 * Creates an ia32 Mul.
807 * @return the created ia32 Mul node
809 static ir_node *gen_Mul(ir_node *node) {
810 ir_node *op1 = get_Mul_left(node);
811 ir_node *op2 = get_Mul_right(node);
812 ir_mode *mode = get_irn_mode(node);
814 if (mode_is_float(mode)) {
815 if (USE_SSE2(env_cg))
816 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
818 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
822 for the lower 32bit of the result it doesn't matter whether we use
823 signed or unsigned multiplication so we use IMul as it has fewer
826 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
830 * Creates an ia32 Mulh.
831 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
832 * this result while Mul returns the lower 32 bit.
834 * @return the created ia32 Mulh node
836 static ir_node *gen_Mulh(ir_node *node) {
837 ir_node *block = be_transform_node(get_nodes_block(node));
838 ir_node *op1 = get_irn_n(node, 0);
839 ir_node *new_op1 = be_transform_node(op1);
840 ir_node *op2 = get_irn_n(node, 1);
841 ir_node *new_op2 = be_transform_node(op2);
842 ir_graph *irg = current_ir_graph;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
845 ir_mode *mode = get_irn_mode(node);
846 ir_node *proj_EDX, *res;
848 assert(!mode_is_float(mode) && "Mulh with float not supported");
849 if (mode_is_signed(mode)) {
850 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
851 new_op2, new_NoMem());
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
868 * Creates an ia32 And.
870 * @return The created ia32 And node
872 static ir_node *gen_And(ir_node *node) {
873 ir_node *op1 = get_And_left(node);
874 ir_node *op2 = get_And_right(node);
875 assert(! mode_is_float(get_irn_mode(node)));
877 /* check for zero extension first */
879 tarval *tv = get_Const_tarval(op2);
880 long v = get_tarval_long(tv);
882 if (v == 0xFF || v == 0xFFFF) {
883 dbg_info *dbgi = get_irn_dbg_info(node);
884 ir_node *block = be_transform_node(get_nodes_block(node));
885 ir_node *new_op = be_transform_node(op1);
895 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
896 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
902 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
908 * Creates an ia32 Or.
910 * @return The created ia32 Or node
912 static ir_node *gen_Or(ir_node *node) {
913 ir_node *op1 = get_Or_left(node);
914 ir_node *op2 = get_Or_right(node);
916 assert (! mode_is_float(get_irn_mode(node)));
917 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
923 * Creates an ia32 Eor.
925 * @return The created ia32 Eor node
927 static ir_node *gen_Eor(ir_node *node) {
928 ir_node *op1 = get_Eor_left(node);
929 ir_node *op2 = get_Eor_right(node);
931 assert(! mode_is_float(get_irn_mode(node)));
932 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
937 * Creates an ia32 Sub.
939 * @return The created ia32 Sub node
941 static ir_node *gen_Sub(ir_node *node) {
942 ir_node *block = be_transform_node(get_nodes_block(node));
943 ir_node *op1 = get_Sub_left(node);
944 ir_node *new_op1 = be_transform_node(op1);
945 ir_node *op2 = get_Sub_right(node);
946 ir_node *new_op2 = be_transform_node(op2);
947 ir_node *new_op = NULL;
948 ir_graph *irg = current_ir_graph;
949 dbg_info *dbgi = get_irn_dbg_info(node);
950 ir_mode *mode = get_irn_mode(node);
951 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
952 ir_node *nomem = new_NoMem();
953 ir_node *expr_op, *imm_op;
955 /* Check if immediate optimization is on and */
956 /* if it's an operation with immediate. */
957 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
958 expr_op = get_expr_op(new_op1, new_op2);
960 assert((expr_op || imm_op) && "invalid operands");
962 if (mode_is_float(mode)) {
963 if (USE_SSE2(env_cg))
964 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
966 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
971 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
972 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
974 /* No expr_op means, that we have two const - one symconst and */
975 /* one tarval or another symconst - because this case is not */
976 /* covered by constant folding */
977 /* We need to check for: */
978 /* 1) symconst - const -> becomes a LEA */
979 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
980 /* linker doesn't support two symconsts */
981 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
982 /* this is the 2nd case */
983 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
984 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
985 set_ia32_am_sc_sign(new_op);
986 set_ia32_am_flavour(new_op, ia32_am_B);
988 DBG_OPT_LEA3(op1, op2, node, new_op);
989 } else if (tp1 == ia32_ImmSymConst) {
990 tarval *tv = get_ia32_Immop_tarval(new_op2);
991 long offs = get_tarval_long(tv);
993 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
994 add_irn_dep(new_op, get_irg_frame(irg));
995 DBG_OPT_LEA3(op1, op2, node, new_op);
997 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
998 add_ia32_am_offs_int(new_op, -offs);
999 set_ia32_am_flavour(new_op, ia32_am_OB);
1000 set_ia32_op_type(new_op, ia32_AddrModeS);
1001 } else if (tp2 == ia32_ImmSymConst) {
1002 tarval *tv = get_ia32_Immop_tarval(new_op1);
1003 long offs = get_tarval_long(tv);
1005 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1006 add_irn_dep(new_op, get_irg_frame(irg));
1007 DBG_OPT_LEA3(op1, op2, node, new_op);
1009 add_ia32_am_offs_int(new_op, offs);
1010 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1011 set_ia32_am_sc_sign(new_op);
1012 set_ia32_am_flavour(new_op, ia32_am_OB);
1013 set_ia32_op_type(new_op, ia32_AddrModeS);
1015 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1016 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1017 tarval *restv = tarval_sub(tv1, tv2);
1019 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1021 new_op = new_rd_ia32_Const(dbgi, irg, block);
1022 set_ia32_Const_tarval(new_op, restv);
1023 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1026 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1028 } else if (imm_op) {
1029 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1030 tarval_classification_t class_tv, class_negtv;
1031 tarval *tv = get_ia32_Immop_tarval(imm_op);
1033 /* optimize tarvals */
1034 class_tv = classify_tarval(tv);
1035 class_negtv = classify_tarval(tarval_neg(tv));
1037 if (class_tv == TV_CLASSIFY_ONE) {
1038 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1039 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1040 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1042 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1043 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1044 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1051 /* This is a normal sub */
1052 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1054 /* set AM support */
1055 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1057 fold_immediate(new_op, 2, 3);
1059 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1067 * Generates an ia32 DivMod with additional infrastructure for the
1068 * register allocator if needed.
1070 * @param dividend -no comment- :)
1071 * @param divisor -no comment- :)
1072 * @param dm_flav flavour_Div/Mod/DivMod
1073 * @return The created ia32 DivMod node
1075 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1076 ir_node *divisor, ia32_op_flavour_t dm_flav)
1078 ir_node *block = be_transform_node(get_nodes_block(node));
1079 ir_node *new_dividend = be_transform_node(dividend);
1080 ir_node *new_divisor = be_transform_node(divisor);
1081 ir_graph *irg = current_ir_graph;
1082 dbg_info *dbgi = get_irn_dbg_info(node);
1083 ir_mode *mode = get_irn_mode(node);
1084 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1085 ir_node *res, *proj_div, *proj_mod;
1086 ir_node *sign_extension;
1087 ir_node *mem, *new_mem;
1088 ir_node *projs[pn_DivMod_max];
1091 ia32_collect_Projs(node, projs, pn_DivMod_max);
1093 proj_div = proj_mod = NULL;
1097 mem = get_Div_mem(node);
1098 mode = get_Div_resmode(node);
1099 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1100 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1103 mem = get_Mod_mem(node);
1104 mode = get_Mod_resmode(node);
1105 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1106 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1108 case flavour_DivMod:
1109 mem = get_DivMod_mem(node);
1110 mode = get_DivMod_resmode(node);
1111 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1112 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1113 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1116 panic("invalid divmod flavour!");
1118 new_mem = be_transform_node(mem);
1120 if (mode_is_signed(mode)) {
1121 /* in signed mode, we need to sign extend the dividend */
1122 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1123 add_irn_dep(produceval, get_irg_frame(irg));
1124 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1127 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1128 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1130 add_irn_dep(sign_extension, get_irg_frame(irg));
1133 if (mode_is_signed(mode)) {
1134 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1135 sign_extension, new_divisor, new_mem, dm_flav);
1137 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1138 sign_extension, new_divisor, new_mem, dm_flav);
1141 set_ia32_exc_label(res, has_exc);
1142 set_irn_pinned(res, get_irn_pinned(node));
1143 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1145 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1152 * Wrapper for generate_DivMod. Sets flavour_Mod.
1155 static ir_node *gen_Mod(ir_node *node) {
1156 return generate_DivMod(node, get_Mod_left(node),
1157 get_Mod_right(node), flavour_Mod);
1161 * Wrapper for generate_DivMod. Sets flavour_Div.
1164 static ir_node *gen_Div(ir_node *node) {
1165 return generate_DivMod(node, get_Div_left(node),
1166 get_Div_right(node), flavour_Div);
1170 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1172 static ir_node *gen_DivMod(ir_node *node) {
1173 return generate_DivMod(node, get_DivMod_left(node),
1174 get_DivMod_right(node), flavour_DivMod);
1180 * Creates an ia32 floating Div.
1182 * @return The created ia32 xDiv node
1184 static ir_node *gen_Quot(ir_node *node) {
1185 ir_node *block = be_transform_node(get_nodes_block(node));
1186 ir_node *op1 = get_Quot_left(node);
1187 ir_node *new_op1 = be_transform_node(op1);
1188 ir_node *op2 = get_Quot_right(node);
1189 ir_node *new_op2 = be_transform_node(op2);
1190 ir_graph *irg = current_ir_graph;
1191 dbg_info *dbgi = get_irn_dbg_info(node);
1192 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1193 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1196 if (USE_SSE2(env_cg)) {
1197 ir_mode *mode = get_irn_mode(op1);
1198 if (is_ia32_xConst(new_op2)) {
1199 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1200 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1201 copy_ia32_Immop_attr(new_op, new_op2);
1203 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1204 // Matze: disabled for now, spillslot coalescer fails
1205 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1207 set_ia32_ls_mode(new_op, mode);
1209 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1210 new_op2, nomem, get_fpcw());
1211 // Matze: disabled for now (spillslot coalescer fails)
1212 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1214 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1220 * Creates an ia32 Shl.
1222 * @return The created ia32 Shl node
1224 static ir_node *gen_Shl(ir_node *node) {
1225 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1232 * Creates an ia32 Shr.
1234 * @return The created ia32 Shr node
1236 static ir_node *gen_Shr(ir_node *node) {
1237 return gen_shift_binop(node, get_Shr_left(node),
1238 get_Shr_right(node), new_rd_ia32_Shr);
1244 * Creates an ia32 Sar.
1246 * @return The created ia32 Shrs node
1248 static ir_node *gen_Shrs(ir_node *node) {
1249 ir_node *left = get_Shrs_left(node);
1250 ir_node *right = get_Shrs_right(node);
1251 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1252 tarval *tv = get_Const_tarval(right);
1253 long val = get_tarval_long(tv);
1255 /* this is a sign extension */
1256 ir_graph *irg = current_ir_graph;
1257 dbg_info *dbgi = get_irn_dbg_info(node);
1258 ir_node *block = be_transform_node(get_nodes_block(node));
1260 ir_node *new_op = be_transform_node(op);
1261 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1262 add_irn_dep(pval, get_irg_frame(irg));
1264 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1268 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1274 * Creates an ia32 RotL.
1276 * @param op1 The first operator
1277 * @param op2 The second operator
1278 * @return The created ia32 RotL node
1280 static ir_node *gen_RotL(ir_node *node,
1281 ir_node *op1, ir_node *op2) {
1282 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1288 * Creates an ia32 RotR.
1289 * NOTE: There is no RotR with immediate because this would always be a RotL
1290 * "imm-mode_size_bits" which can be pre-calculated.
1292 * @param op1 The first operator
1293 * @param op2 The second operator
1294 * @return The created ia32 RotR node
1296 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1298 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1304 * Creates an ia32 RotR or RotL (depending on the found pattern).
1306 * @return The created ia32 RotL or RotR node
1308 static ir_node *gen_Rot(ir_node *node) {
1309 ir_node *rotate = NULL;
1310 ir_node *op1 = get_Rot_left(node);
1311 ir_node *op2 = get_Rot_right(node);
1313 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1314 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1315 that means we can create a RotR instead of an Add and a RotL */
1317 if (get_irn_op(op2) == op_Add) {
1319 ir_node *left = get_Add_left(add);
1320 ir_node *right = get_Add_right(add);
1321 if (is_Const(right)) {
1322 tarval *tv = get_Const_tarval(right);
1323 ir_mode *mode = get_irn_mode(node);
1324 long bits = get_mode_size_bits(mode);
1326 if (get_irn_op(left) == op_Minus &&
1327 tarval_is_long(tv) &&
1328 get_tarval_long(tv) == bits)
1330 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1331 rotate = gen_RotR(node, op1, get_Minus_op(left));
1336 if (rotate == NULL) {
1337 rotate = gen_RotL(node, op1, op2);
1346 * Transforms a Minus node.
1348 * @param op The Minus operand
1349 * @return The created ia32 Minus node
1351 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1352 ir_node *block = be_transform_node(get_nodes_block(node));
1353 ir_graph *irg = current_ir_graph;
1354 dbg_info *dbgi = get_irn_dbg_info(node);
1355 ir_mode *mode = get_irn_mode(node);
1360 if (mode_is_float(mode)) {
1361 ir_node *new_op = be_transform_node(op);
1362 if (USE_SSE2(env_cg)) {
1363 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1364 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1365 ir_node *nomem = new_rd_NoMem(irg);
1367 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1369 size = get_mode_size_bits(mode);
1370 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1372 set_ia32_am_sc(res, ent);
1373 set_ia32_op_type(res, ia32_AddrModeS);
1374 set_ia32_ls_mode(res, mode);
1376 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1379 res = gen_unop(node, op, new_rd_ia32_Neg);
1382 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1388 * Transforms a Minus node.
1390 * @return The created ia32 Minus node
1392 static ir_node *gen_Minus(ir_node *node) {
1393 return gen_Minus_ex(node, get_Minus_op(node));
1396 static ir_node *gen_bin_Not(ir_node *node)
1398 ir_graph *irg = current_ir_graph;
1399 dbg_info *dbgi = get_irn_dbg_info(node);
1400 ir_node *block = be_transform_node(get_nodes_block(node));
1401 ir_node *op = get_Not_op(node);
1402 ir_node *new_op = be_transform_node(op);
1403 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1404 ir_node *nomem = new_NoMem();
1405 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1406 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1408 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1412 * Transforms a Not node.
1414 * @return The created ia32 Not node
1416 static ir_node *gen_Not(ir_node *node) {
1417 ir_node *op = get_Not_op(node);
1418 ir_mode *mode = get_irn_mode(node);
1420 if(mode == mode_b) {
1421 return gen_bin_Not(node);
1424 assert (! mode_is_float(get_irn_mode(node)));
1425 return gen_unop(node, op, new_rd_ia32_Not);
1431 * Transforms an Abs node.
1433 * @return The created ia32 Abs node
1435 static ir_node *gen_Abs(ir_node *node) {
1436 ir_node *block = be_transform_node(get_nodes_block(node));
1437 ir_node *op = get_Abs_op(node);
1438 ir_node *new_op = be_transform_node(op);
1439 ir_graph *irg = current_ir_graph;
1440 dbg_info *dbgi = get_irn_dbg_info(node);
1441 ir_mode *mode = get_irn_mode(node);
1442 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1443 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1444 ir_node *nomem = new_NoMem();
1449 if (mode_is_float(mode)) {
1450 if (USE_SSE2(env_cg)) {
1451 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1453 size = get_mode_size_bits(mode);
1454 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1456 set_ia32_am_sc(res, ent);
1458 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1460 set_ia32_op_type(res, ia32_AddrModeS);
1461 set_ia32_ls_mode(res, mode);
1464 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1465 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1469 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1470 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1473 add_irn_dep(pval, get_irg_frame(irg));
1474 SET_IA32_ORIG_NODE(sign_extension,
1475 ia32_get_old_node_name(env_cg, node));
1477 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1478 sign_extension, nomem);
1479 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1481 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1482 sign_extension, nomem);
1483 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1492 * Transforms a Load.
1494 * @return the created ia32 Load node
1496 static ir_node *gen_Load(ir_node *node) {
1497 ir_node *old_block = get_nodes_block(node);
1498 ir_node *block = be_transform_node(old_block);
1499 ir_node *ptr = get_Load_ptr(node);
1500 ir_node *new_ptr = be_transform_node(ptr);
1501 ir_node *mem = get_Load_mem(node);
1502 ir_node *new_mem = be_transform_node(mem);
1503 ir_graph *irg = current_ir_graph;
1504 dbg_info *dbgi = get_irn_dbg_info(node);
1505 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1506 ir_mode *mode = get_Load_mode(node);
1508 ir_node *lptr = new_ptr;
1511 ia32_am_flavour_t am_flav = ia32_am_B;
1513 /* address might be a constant (symconst or absolute address) */
1514 if (is_ia32_Const(new_ptr)) {
1519 if (mode_is_float(mode)) {
1520 if (USE_SSE2(env_cg)) {
1521 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1522 res_mode = mode_xmm;
1524 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1525 res_mode = mode_vfp;
1531 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1535 /* base is a constant address */
1537 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1538 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1539 am_flav = ia32_am_N;
1541 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1542 long offs = get_tarval_long(tv);
1544 add_ia32_am_offs_int(new_op, offs);
1545 am_flav = ia32_am_O;
1549 set_irn_pinned(new_op, get_irn_pinned(node));
1550 set_ia32_op_type(new_op, ia32_AddrModeS);
1551 set_ia32_am_flavour(new_op, am_flav);
1552 set_ia32_ls_mode(new_op, mode);
1554 /* make sure we are scheduled behind the initial IncSP/Barrier
1555 * to avoid spills being placed before it
1557 if (block == get_irg_start_block(irg)) {
1558 add_irn_dep(new_op, get_irg_frame(irg));
1561 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1562 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1570 * Transforms a Store.
1572 * @return the created ia32 Store node
1574 static ir_node *gen_Store(ir_node *node) {
1575 ir_node *block = be_transform_node(get_nodes_block(node));
1576 ir_node *ptr = get_Store_ptr(node);
1577 ir_node *new_ptr = be_transform_node(ptr);
1578 ir_node *val = get_Store_value(node);
1580 ir_node *mem = get_Store_mem(node);
1581 ir_node *new_mem = be_transform_node(mem);
1582 ir_graph *irg = current_ir_graph;
1583 dbg_info *dbgi = get_irn_dbg_info(node);
1584 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1585 ir_node *sptr = new_ptr;
1586 ir_mode *mode = get_irn_mode(val);
1589 ia32_am_flavour_t am_flav = ia32_am_B;
1591 /* address might be a constant (symconst or absolute address) */
1592 if (is_ia32_Const(new_ptr)) {
1597 if (mode_is_float(mode)) {
1598 new_val = be_transform_node(val);
1599 if (USE_SSE2(env_cg)) {
1600 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1603 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1607 new_val = create_immediate_or_transform(val, 0);
1611 if (get_mode_size_bits(mode) == 8) {
1612 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1615 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1620 /* base is an constant address */
1622 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1623 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1624 am_flav = ia32_am_N;
1626 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1627 long offs = get_tarval_long(tv);
1629 add_ia32_am_offs_int(new_op, offs);
1630 am_flav = ia32_am_O;
1634 set_irn_pinned(new_op, get_irn_pinned(node));
1635 set_ia32_op_type(new_op, ia32_AddrModeD);
1636 set_ia32_am_flavour(new_op, am_flav);
1637 set_ia32_ls_mode(new_op, mode);
1639 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1640 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1645 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1650 if(get_mode_size_bits(mode) == 32)
1654 if(is_ia32_Immediate(new_op))
1657 if(mode_is_signed(mode))
1662 block = get_nodes_block(new_op);
1663 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1666 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1667 ir_node *cmp_left, ir_node *cmp_right)
1669 ir_node *new_cmp_left;
1670 ir_node *new_cmp_right;
1677 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1679 if(cmp_right != NULL && !is_Const_0(cmp_right))
1682 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1683 and_left = get_And_left(cmp_left);
1684 and_right = get_And_right(cmp_left);
1686 mode = get_irn_mode(and_left);
1687 new_cmp_left = be_transform_node(and_left);
1688 new_cmp_right = create_immediate_or_transform(and_right, 0);
1690 mode = get_irn_mode(cmp_left);
1691 new_cmp_left = be_transform_node(cmp_left);
1692 new_cmp_right = be_transform_node(cmp_left);
1695 assert(get_mode_size_bits(mode) <= 32);
1696 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1697 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1698 noreg = ia32_new_NoReg_gp(env_cg);
1699 nomem = new_NoMem();
1701 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1702 new_cmp_left, new_cmp_right, nomem, pnc);
1703 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1708 static ir_node *create_Switch(ir_node *node)
1710 ir_graph *irg = current_ir_graph;
1711 dbg_info *dbgi = get_irn_dbg_info(node);
1712 ir_node *block = be_transform_node(get_nodes_block(node));
1713 ir_node *sel = get_Cond_selector(node);
1714 ir_node *new_sel = be_transform_node(sel);
1716 int switch_min = INT_MAX;
1717 const ir_edge_t *edge;
1719 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1721 /* determine the smallest switch case value */
1722 foreach_out_edge(node, edge) {
1723 ir_node *proj = get_edge_src_irn(edge);
1724 int pn = get_Proj_proj(proj);
1729 if (switch_min != 0) {
1730 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1732 /* if smallest switch case is not 0 we need an additional sub */
1733 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1734 add_ia32_am_offs_int(new_sel, -switch_min);
1735 set_ia32_am_flavour(new_sel, ia32_am_OB);
1736 set_ia32_op_type(new_sel, ia32_AddrModeS);
1738 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1741 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1742 set_ia32_pncode(res, get_Cond_defaultProj(node));
1744 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1750 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1752 * @return The transformed node.
1754 static ir_node *gen_Cond(ir_node *node) {
1755 ir_node *block = be_transform_node(get_nodes_block(node));
1756 ir_graph *irg = current_ir_graph;
1757 dbg_info *dbgi = get_irn_dbg_info(node);
1758 ir_node *sel = get_Cond_selector(node);
1759 ir_mode *sel_mode = get_irn_mode(sel);
1760 ir_node *res = NULL;
1761 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1768 ir_node *nomem = new_NoMem();
1771 if (sel_mode != mode_b) {
1772 return create_Switch(node);
1775 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1776 /* it's some mode_b value but not a direct comparison -> create a
1778 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1779 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1783 cmp = get_Proj_pred(sel);
1784 cmp_a = get_Cmp_left(cmp);
1785 cmp_b = get_Cmp_right(cmp);
1786 cmp_mode = get_irn_mode(cmp_a);
1787 pnc = get_Proj_proj(sel);
1788 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1789 pnc |= ia32_pn_Cmp_Unsigned;
1792 if(mode_needs_gp_reg(cmp_mode)) {
1793 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1795 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1800 new_cmp_a = be_transform_node(cmp_a);
1801 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1803 if (mode_is_float(cmp_mode)) {
1804 if (USE_SSE2(env_cg)) {
1805 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1807 set_ia32_commutative(res);
1808 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1809 set_ia32_ls_mode(res, cmp_mode);
1811 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1812 set_ia32_commutative(res);
1815 /** workaround smaller compare modes with converts...
1816 * We could easily support 16bit compares, for 8 bit we have to set
1817 * additional register constraints, which we don't do yet
1819 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1820 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1822 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1823 new_cmp_a, new_cmp_b, nomem, pnc);
1824 set_ia32_commutative(res);
1825 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1828 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1836 * Transforms a CopyB node.
1838 * @return The transformed node.
1840 static ir_node *gen_CopyB(ir_node *node) {
1841 ir_node *block = be_transform_node(get_nodes_block(node));
1842 ir_node *src = get_CopyB_src(node);
1843 ir_node *new_src = be_transform_node(src);
1844 ir_node *dst = get_CopyB_dst(node);
1845 ir_node *new_dst = be_transform_node(dst);
1846 ir_node *mem = get_CopyB_mem(node);
1847 ir_node *new_mem = be_transform_node(mem);
1848 ir_node *res = NULL;
1849 ir_graph *irg = current_ir_graph;
1850 dbg_info *dbgi = get_irn_dbg_info(node);
1851 int size = get_type_size_bytes(get_CopyB_type(node));
1854 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1855 /* then we need the size explicitly in ECX. */
1856 if (size >= 32 * 4) {
1857 rem = size & 0x3; /* size % 4 */
1860 res = new_rd_ia32_Const(dbgi, irg, block);
1861 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1862 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1864 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1865 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1867 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1868 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1871 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1877 ir_node *gen_be_Copy(ir_node *node)
1879 ir_node *result = be_duplicate_node(node);
1880 ir_mode *mode = get_irn_mode(result);
1882 if (mode_needs_gp_reg(mode)) {
1883 set_irn_mode(result, mode_Iu);
1890 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1891 dbg_info *dbgi, ir_node *block)
1893 ir_graph *irg = current_ir_graph;
1894 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1895 ir_node *nomem = new_rd_NoMem(irg);
1897 ir_node *new_cmp_left;
1898 ir_node *new_cmp_right;
1901 /* can we use a test instruction? */
1902 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1903 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1904 if(is_And(cmp_left) &&
1905 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1906 ir_node *and_left = get_And_left(cmp_left);
1907 ir_node *and_right = get_And_right(cmp_left);
1909 mode = get_irn_mode(and_left);
1910 new_cmp_left = be_transform_node(and_left);
1911 new_cmp_right = create_immediate_or_transform(and_right, 0);
1913 mode = get_irn_mode(cmp_left);
1914 new_cmp_left = be_transform_node(cmp_left);
1915 new_cmp_right = be_transform_node(cmp_left);
1918 assert(get_mode_size_bits(mode) <= 32);
1919 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1920 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1922 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1923 new_cmp_left, new_cmp_right, nomem, pnc);
1924 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1929 mode = get_irn_mode(cmp_left);
1931 new_cmp_left = be_transform_node(cmp_left);
1932 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1934 assert(get_mode_size_bits(mode) <= 32);
1935 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1936 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1938 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1939 new_cmp_left, new_cmp_right, nomem, pnc);
1944 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1945 ir_node *val_true, ir_node *val_false,
1946 dbg_info *dbgi, ir_node *block)
1948 ir_graph *irg = current_ir_graph;
1949 ir_node *new_val_true = be_transform_node(val_true);
1950 ir_node *new_val_false = be_transform_node(val_false);
1951 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1952 ir_node *nomem = new_NoMem();
1953 ir_node *new_cmp_left;
1954 ir_node *new_cmp_right;
1957 /* cmovs with unknowns are pointless... */
1958 if(is_Unknown(val_true)) {
1959 #ifdef DEBUG_libfirm
1960 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1962 return new_val_false;
1964 if(is_Unknown(val_false)) {
1965 #ifdef DEBUG_libfirm
1966 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1968 return new_val_true;
1971 /* can we use a test instruction? */
1972 if(is_Const_0(cmp_right)) {
1973 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1974 if(is_And(cmp_left) &&
1975 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1976 ir_node *and_left = get_And_left(cmp_left);
1977 ir_node *and_right = get_And_right(cmp_left);
1979 new_cmp_left = be_transform_node(and_left);
1980 new_cmp_right = create_immediate_or_transform(and_right, 0);
1982 new_cmp_left = be_transform_node(cmp_left);
1983 new_cmp_right = be_transform_node(cmp_left);
1986 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1987 new_cmp_left, new_cmp_right, nomem,
1988 new_val_true, new_val_false, pnc);
1989 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1994 new_cmp_left = be_transform_node(cmp_left);
1995 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1997 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1998 new_cmp_right, nomem, new_val_true, new_val_false,
2000 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2007 * Transforms a Psi node into CMov.
2009 * @return The transformed node.
2011 static ir_node *gen_Psi(ir_node *node) {
2012 ir_node *psi_true = get_Psi_val(node, 0);
2013 ir_node *psi_default = get_Psi_default(node);
2014 ia32_code_gen_t *cg = env_cg;
2015 ir_node *cond = get_Psi_cond(node, 0);
2016 ir_node *block = be_transform_node(get_nodes_block(node));
2017 dbg_info *dbgi = get_irn_dbg_info(node);
2024 assert(get_Psi_n_conds(node) == 1);
2025 assert(get_irn_mode(cond) == mode_b);
2027 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2028 /* a mode_b value, we have to compare it against 0 */
2030 cmp_right = new_Const_long(mode_Iu, 0);
2034 ir_node *cmp = get_Proj_pred(cond);
2036 cmp_left = get_Cmp_left(cmp);
2037 cmp_right = get_Cmp_right(cmp);
2038 cmp_mode = get_irn_mode(cmp_left);
2039 pnc = get_Proj_proj(cond);
2041 assert(!mode_is_float(cmp_mode));
2043 if (!mode_is_signed(cmp_mode)) {
2044 pnc |= ia32_pn_Cmp_Unsigned;
2048 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2049 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2050 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2051 pnc = get_negated_pnc(pnc, cmp_mode);
2052 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2054 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2057 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2063 * Following conversion rules apply:
2067 * 1) n bit -> m bit n > m (downscale)
2069 * 2) n bit -> m bit n == m (sign change)
2071 * 3) n bit -> m bit n < m (upscale)
2072 * a) source is signed: movsx
2073 * b) source is unsigned: and with lower bits sets
2077 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2081 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2085 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2086 * x87 is mode_E internally, conversions happen only at load and store
2087 * in non-strict semantic
2091 * Create a conversion from x87 state register to general purpose.
2093 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2094 ir_node *block = be_transform_node(get_nodes_block(node));
2095 ir_node *op = get_Conv_op(node);
2096 ir_node *new_op = be_transform_node(op);
2097 ia32_code_gen_t *cg = env_cg;
2098 ir_graph *irg = current_ir_graph;
2099 dbg_info *dbgi = get_irn_dbg_info(node);
2100 ir_node *noreg = ia32_new_NoReg_gp(cg);
2101 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2102 ir_node *fist, *load;
2105 fist = new_rd_ia32_vfist(dbgi, irg, block,
2106 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2108 set_irn_pinned(fist, op_pin_state_floats);
2109 set_ia32_use_frame(fist);
2110 set_ia32_op_type(fist, ia32_AddrModeD);
2111 set_ia32_am_flavour(fist, ia32_am_B);
2112 set_ia32_ls_mode(fist, mode_Iu);
2113 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2116 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2118 set_irn_pinned(load, op_pin_state_floats);
2119 set_ia32_use_frame(load);
2120 set_ia32_op_type(load, ia32_AddrModeS);
2121 set_ia32_am_flavour(load, ia32_am_B);
2122 set_ia32_ls_mode(load, mode_Iu);
2123 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2125 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2128 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2130 ir_node *block = get_nodes_block(node);
2131 ir_graph *irg = current_ir_graph;
2132 dbg_info *dbgi = get_irn_dbg_info(node);
2133 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2134 ir_node *nomem = new_NoMem();
2135 ir_node *frame = get_irg_frame(irg);
2136 ir_node *store, *load;
2139 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2141 set_ia32_use_frame(store);
2142 set_ia32_op_type(store, ia32_AddrModeD);
2143 set_ia32_am_flavour(store, ia32_am_OB);
2144 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2146 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2148 set_ia32_use_frame(load);
2149 set_ia32_op_type(load, ia32_AddrModeS);
2150 set_ia32_am_flavour(load, ia32_am_OB);
2151 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2153 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2158 * Create a conversion from general purpose to x87 register
2160 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2161 ir_node *block = be_transform_node(get_nodes_block(node));
2162 ir_node *op = get_Conv_op(node);
2163 ir_node *new_op = be_transform_node(op);
2164 ir_graph *irg = current_ir_graph;
2165 dbg_info *dbgi = get_irn_dbg_info(node);
2166 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2167 ir_node *nomem = new_NoMem();
2168 ir_node *fild, *store;
2172 /* first convert to 32 bit if necessary */
2173 src_bits = get_mode_size_bits(src_mode);
2174 if (src_bits == 8) {
2175 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2176 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2177 set_ia32_ls_mode(new_op, src_mode);
2178 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2179 } else if (src_bits < 32) {
2180 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2181 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2182 set_ia32_ls_mode(new_op, src_mode);
2183 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2187 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2189 set_ia32_use_frame(store);
2190 set_ia32_op_type(store, ia32_AddrModeD);
2191 set_ia32_am_flavour(store, ia32_am_OB);
2192 set_ia32_ls_mode(store, mode_Iu);
2195 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2197 set_ia32_use_frame(fild);
2198 set_ia32_op_type(fild, ia32_AddrModeS);
2199 set_ia32_am_flavour(fild, ia32_am_OB);
2200 set_ia32_ls_mode(fild, mode_Iu);
2202 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2208 * Crete a conversion from one integer mode into another one
2210 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2211 dbg_info *dbgi, ir_node *new_block,
2214 ir_graph *irg = current_ir_graph;
2215 int src_bits = get_mode_size_bits(src_mode);
2216 int tgt_bits = get_mode_size_bits(tgt_mode);
2217 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2218 ir_node *nomem = new_rd_NoMem(irg);
2220 ir_mode *smaller_mode;
2223 if (src_bits < tgt_bits) {
2224 smaller_mode = src_mode;
2225 smaller_bits = src_bits;
2227 smaller_mode = tgt_mode;
2228 smaller_bits = tgt_bits;
2231 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2232 if (smaller_bits == 8) {
2233 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2235 set_ia32_ls_mode(res, smaller_mode);
2237 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2239 set_ia32_ls_mode(res, smaller_mode);
2241 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2247 * Transforms a Conv node.
2249 * @return The created ia32 Conv node
2251 static ir_node *gen_Conv(ir_node *node) {
2252 ir_node *block = be_transform_node(get_nodes_block(node));
2253 ir_node *op = get_Conv_op(node);
2254 ir_node *new_op = be_transform_node(op);
2255 ir_graph *irg = current_ir_graph;
2256 dbg_info *dbgi = get_irn_dbg_info(node);
2257 ir_mode *src_mode = get_irn_mode(op);
2258 ir_mode *tgt_mode = get_irn_mode(node);
2259 int src_bits = get_mode_size_bits(src_mode);
2260 int tgt_bits = get_mode_size_bits(tgt_mode);
2261 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2262 ir_node *nomem = new_rd_NoMem(irg);
2265 if (src_mode == mode_b) {
2266 assert(mode_is_int(tgt_mode));
2267 /* nothing to do, we already model bools as 0/1 ints */
2271 if (src_mode == tgt_mode) {
2272 if (get_Conv_strict(node)) {
2273 if (USE_SSE2(env_cg)) {
2274 /* when we are in SSE mode, we can kill all strict no-op conversion */
2278 /* this should be optimized already, but who knows... */
2279 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2280 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2285 if (mode_is_float(src_mode)) {
2286 /* we convert from float ... */
2287 if (mode_is_float(tgt_mode)) {
2288 if(src_mode == mode_E && tgt_mode == mode_D
2289 && !get_Conv_strict(node)) {
2290 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2295 if (USE_SSE2(env_cg)) {
2296 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2297 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2298 set_ia32_ls_mode(res, tgt_mode);
2300 if(get_Conv_strict(node)) {
2301 res = create_strict_conv(tgt_mode, new_op);
2302 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2305 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2310 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2311 if (USE_SSE2(env_cg)) {
2312 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2313 set_ia32_ls_mode(res, src_mode);
2315 return gen_x87_fp_to_gp(node);
2319 /* we convert from int ... */
2320 if (mode_is_float(tgt_mode)) {
2322 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2323 if (USE_SSE2(env_cg)) {
2324 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2325 set_ia32_ls_mode(res, tgt_mode);
2326 if(src_bits == 32) {
2327 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2330 res = gen_x87_gp_to_fp(node, src_mode);
2331 if(get_Conv_strict(node)) {
2332 res = create_strict_conv(tgt_mode, res);
2333 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2334 ia32_get_old_node_name(env_cg, node));
2338 } else if(tgt_mode == mode_b) {
2339 /* mode_b lowering already took care that we only have 0/1 values */
2340 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2341 src_mode, tgt_mode));
2345 if (src_bits == tgt_bits) {
2346 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2347 src_mode, tgt_mode));
2351 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2355 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2361 int check_immediate_constraint(long val, char immediate_constraint_type)
2363 switch (immediate_constraint_type) {
2367 return val >= 0 && val <= 32;
2369 return val >= 0 && val <= 63;
2371 return val >= -128 && val <= 127;
2373 return val == 0xff || val == 0xffff;
2375 return val >= 0 && val <= 3;
2377 return val >= 0 && val <= 255;
2379 return val >= 0 && val <= 127;
2383 panic("Invalid immediate constraint found");
2388 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2391 tarval *offset = NULL;
2392 int offset_sign = 0;
2394 ir_entity *symconst_ent = NULL;
2395 int symconst_sign = 0;
2397 ir_node *cnst = NULL;
2398 ir_node *symconst = NULL;
2404 mode = get_irn_mode(node);
2405 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2409 if(is_Minus(node)) {
2411 node = get_Minus_op(node);
2414 if(is_Const(node)) {
2417 offset_sign = minus;
2418 } else if(is_SymConst(node)) {
2421 symconst_sign = minus;
2422 } else if(is_Add(node)) {
2423 ir_node *left = get_Add_left(node);
2424 ir_node *right = get_Add_right(node);
2425 if(is_Const(left) && is_SymConst(right)) {
2428 symconst_sign = minus;
2429 offset_sign = minus;
2430 } else if(is_SymConst(left) && is_Const(right)) {
2433 symconst_sign = minus;
2434 offset_sign = minus;
2436 } else if(is_Sub(node)) {
2437 ir_node *left = get_Sub_left(node);
2438 ir_node *right = get_Sub_right(node);
2439 if(is_Const(left) && is_SymConst(right)) {
2442 symconst_sign = !minus;
2443 offset_sign = minus;
2444 } else if(is_SymConst(left) && is_Const(right)) {
2447 symconst_sign = minus;
2448 offset_sign = !minus;
2455 offset = get_Const_tarval(cnst);
2456 if(tarval_is_long(offset)) {
2457 val = get_tarval_long(offset);
2458 } else if(tarval_is_null(offset)) {
2461 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2466 if(!check_immediate_constraint(val, immediate_constraint_type))
2469 if(symconst != NULL) {
2470 if(immediate_constraint_type != 0) {
2471 /* we need full 32bits for symconsts */
2475 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2477 symconst_ent = get_SymConst_entity(symconst);
2479 if(cnst == NULL && symconst == NULL)
2482 if(offset_sign && offset != NULL) {
2483 offset = tarval_neg(offset);
2486 irg = current_ir_graph;
2487 dbgi = get_irn_dbg_info(node);
2488 block = get_irg_start_block(irg);
2489 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2490 symconst_sign, val);
2491 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2497 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2499 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2500 if (new_node == NULL) {
2501 new_node = be_transform_node(node);
2506 typedef struct constraint_t constraint_t;
2507 struct constraint_t {
2510 const arch_register_req_t **out_reqs;
2512 const arch_register_req_t *req;
2513 unsigned immediate_possible;
2514 char immediate_type;
2517 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2519 int immediate_possible = 0;
2520 char immediate_type = 0;
2521 unsigned limited = 0;
2522 const arch_register_class_t *cls = NULL;
2524 struct obstack *obst;
2525 arch_register_req_t *req;
2526 unsigned *limited_ptr;
2530 /* TODO: replace all the asserts with nice error messages */
2532 printf("Constraint: %s\n", c);
2542 assert(cls == NULL ||
2543 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2544 cls = &ia32_reg_classes[CLASS_ia32_gp];
2545 limited |= 1 << REG_EAX;
2548 assert(cls == NULL ||
2549 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2550 cls = &ia32_reg_classes[CLASS_ia32_gp];
2551 limited |= 1 << REG_EBX;
2554 assert(cls == NULL ||
2555 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2556 cls = &ia32_reg_classes[CLASS_ia32_gp];
2557 limited |= 1 << REG_ECX;
2560 assert(cls == NULL ||
2561 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2562 cls = &ia32_reg_classes[CLASS_ia32_gp];
2563 limited |= 1 << REG_EDX;
2566 assert(cls == NULL ||
2567 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2568 cls = &ia32_reg_classes[CLASS_ia32_gp];
2569 limited |= 1 << REG_EDI;
2572 assert(cls == NULL ||
2573 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2574 cls = &ia32_reg_classes[CLASS_ia32_gp];
2575 limited |= 1 << REG_ESI;
2578 case 'q': /* q means lower part of the regs only, this makes no
2579 * difference to Q for us (we only assigne whole registers) */
2580 assert(cls == NULL ||
2581 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2582 cls = &ia32_reg_classes[CLASS_ia32_gp];
2583 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2587 assert(cls == NULL ||
2588 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2589 cls = &ia32_reg_classes[CLASS_ia32_gp];
2590 limited |= 1 << REG_EAX | 1 << REG_EDX;
2593 assert(cls == NULL ||
2594 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2595 cls = &ia32_reg_classes[CLASS_ia32_gp];
2596 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2597 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2604 assert(cls == NULL);
2605 cls = &ia32_reg_classes[CLASS_ia32_gp];
2611 /* TODO: mark values so the x87 simulator knows about t and u */
2612 assert(cls == NULL);
2613 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2618 assert(cls == NULL);
2619 /* TODO: check that sse2 is supported */
2620 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2630 assert(!immediate_possible);
2631 immediate_possible = 1;
2632 immediate_type = *c;
2636 assert(!immediate_possible);
2637 immediate_possible = 1;
2641 assert(!immediate_possible && cls == NULL);
2642 immediate_possible = 1;
2643 cls = &ia32_reg_classes[CLASS_ia32_gp];
2656 assert(constraint->is_in && "can only specify same constraint "
2659 sscanf(c, "%d%n", &same_as, &p);
2666 case 'E': /* no float consts yet */
2667 case 'F': /* no float consts yet */
2668 case 's': /* makes no sense on x86 */
2669 case 'X': /* we can't support that in firm */
2673 case '<': /* no autodecrement on x86 */
2674 case '>': /* no autoincrement on x86 */
2675 case 'C': /* sse constant not supported yet */
2676 case 'G': /* 80387 constant not supported yet */
2677 case 'y': /* we don't support mmx registers yet */
2678 case 'Z': /* not available in 32 bit mode */
2679 case 'e': /* not available in 32 bit mode */
2680 assert(0 && "asm constraint not supported");
2683 assert(0 && "unknown asm constraint found");
2690 const arch_register_req_t *other_constr;
2692 assert(cls == NULL && "same as and register constraint not supported");
2693 assert(!immediate_possible && "same as and immediate constraint not "
2695 assert(same_as < constraint->n_outs && "wrong constraint number in "
2696 "same_as constraint");
2698 other_constr = constraint->out_reqs[same_as];
2700 req = obstack_alloc(obst, sizeof(req[0]));
2701 req->cls = other_constr->cls;
2702 req->type = arch_register_req_type_should_be_same;
2703 req->limited = NULL;
2704 req->other_same = pos;
2705 req->other_different = -1;
2707 /* switch constraints. This is because in firm we have same_as
2708 * constraints on the output constraints while in the gcc asm syntax
2709 * they are specified on the input constraints */
2710 constraint->req = other_constr;
2711 constraint->out_reqs[same_as] = req;
2712 constraint->immediate_possible = 0;
2716 if(immediate_possible && cls == NULL) {
2717 cls = &ia32_reg_classes[CLASS_ia32_gp];
2719 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2720 assert(cls != NULL);
2722 if(immediate_possible) {
2723 assert(constraint->is_in
2724 && "imeediates make no sense for output constraints");
2726 /* todo: check types (no float input on 'r' constrainted in and such... */
2728 irg = current_ir_graph;
2729 obst = get_irg_obstack(irg);
2732 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2733 limited_ptr = (unsigned*) (req+1);
2735 req = obstack_alloc(obst, sizeof(req[0]));
2737 memset(req, 0, sizeof(req[0]));
2740 req->type = arch_register_req_type_limited;
2741 *limited_ptr = limited;
2742 req->limited = limited_ptr;
2744 req->type = arch_register_req_type_normal;
2748 constraint->req = req;
2749 constraint->immediate_possible = immediate_possible;
2750 constraint->immediate_type = immediate_type;
2754 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2761 panic("Clobbers not supported yet");
2764 ir_node *gen_ASM(ir_node *node)
2767 ir_graph *irg = current_ir_graph;
2768 ir_node *block = be_transform_node(get_nodes_block(node));
2769 dbg_info *dbgi = get_irn_dbg_info(node);
2776 ia32_asm_attr_t *attr;
2777 const arch_register_req_t **out_reqs;
2778 const arch_register_req_t **in_reqs;
2779 struct obstack *obst;
2780 constraint_t parsed_constraint;
2782 /* transform inputs */
2783 arity = get_irn_arity(node);
2784 in = alloca(arity * sizeof(in[0]));
2785 memset(in, 0, arity * sizeof(in[0]));
2787 n_outs = get_ASM_n_output_constraints(node);
2788 n_clobbers = get_ASM_n_clobbers(node);
2789 out_arity = n_outs + n_clobbers;
2791 /* construct register constraints */
2792 obst = get_irg_obstack(irg);
2793 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2794 parsed_constraint.out_reqs = out_reqs;
2795 parsed_constraint.n_outs = n_outs;
2796 parsed_constraint.is_in = 0;
2797 for(i = 0; i < out_arity; ++i) {
2801 const ir_asm_constraint *constraint;
2802 constraint = & get_ASM_output_constraints(node) [i];
2803 c = get_id_str(constraint->constraint);
2804 parse_asm_constraint(i, &parsed_constraint, c);
2806 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2807 c = get_id_str(glob_id);
2808 parse_clobber(node, i, &parsed_constraint, c);
2810 out_reqs[i] = parsed_constraint.req;
2813 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2814 parsed_constraint.is_in = 1;
2815 for(i = 0; i < arity; ++i) {
2816 const ir_asm_constraint *constraint;
2820 constraint = & get_ASM_input_constraints(node) [i];
2821 constr_id = constraint->constraint;
2822 c = get_id_str(constr_id);
2823 parse_asm_constraint(i, &parsed_constraint, c);
2824 in_reqs[i] = parsed_constraint.req;
2826 if(parsed_constraint.immediate_possible) {
2827 ir_node *pred = get_irn_n(node, i);
2828 char imm_type = parsed_constraint.immediate_type;
2829 ir_node *immediate = try_create_Immediate(pred, imm_type);
2831 if(immediate != NULL) {
2837 /* transform inputs */
2838 for(i = 0; i < arity; ++i) {
2840 ir_node *transformed;
2845 pred = get_irn_n(node, i);
2846 transformed = be_transform_node(pred);
2847 in[i] = transformed;
2850 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2852 generic_attr = get_irn_generic_attr(res);
2853 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2854 attr->asm_text = get_ASM_text(node);
2855 set_ia32_out_req_all(res, out_reqs);
2856 set_ia32_in_req_all(res, in_reqs);
2858 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2863 /********************************************
2866 * | |__ ___ _ __ ___ __| | ___ ___
2867 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2868 * | |_) | __/ | | | (_) | (_| | __/\__ \
2869 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2871 ********************************************/
2873 static ir_node *gen_be_StackParam(ir_node *node) {
2874 ir_node *block = be_transform_node(get_nodes_block(node));
2875 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2876 ir_node *new_ptr = be_transform_node(ptr);
2877 ir_node *new_op = NULL;
2878 ir_graph *irg = current_ir_graph;
2879 dbg_info *dbgi = get_irn_dbg_info(node);
2880 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2881 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2882 ir_mode *load_mode = get_irn_mode(node);
2883 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2887 if (mode_is_float(load_mode)) {
2888 if (USE_SSE2(env_cg)) {
2889 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2890 pn_res = pn_ia32_xLoad_res;
2891 proj_mode = mode_xmm;
2893 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2894 pn_res = pn_ia32_vfld_res;
2895 proj_mode = mode_vfp;
2898 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2899 proj_mode = mode_Iu;
2900 pn_res = pn_ia32_Load_res;
2903 set_irn_pinned(new_op, op_pin_state_floats);
2904 set_ia32_frame_ent(new_op, ent);
2905 set_ia32_use_frame(new_op);
2907 set_ia32_op_type(new_op, ia32_AddrModeS);
2908 set_ia32_am_flavour(new_op, ia32_am_B);
2909 set_ia32_ls_mode(new_op, load_mode);
2910 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2914 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2918 * Transforms a FrameAddr into an ia32 Add.
2920 static ir_node *gen_be_FrameAddr(ir_node *node) {
2921 ir_node *block = be_transform_node(get_nodes_block(node));
2922 ir_node *op = be_get_FrameAddr_frame(node);
2923 ir_node *new_op = be_transform_node(op);
2924 ir_graph *irg = current_ir_graph;
2925 dbg_info *dbgi = get_irn_dbg_info(node);
2926 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2929 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2930 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2931 set_ia32_use_frame(res);
2932 set_ia32_am_flavour(res, ia32_am_OB);
2934 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2940 * Transforms a FrameLoad into an ia32 Load.
2942 static ir_node *gen_be_FrameLoad(ir_node *node) {
2943 ir_node *block = be_transform_node(get_nodes_block(node));
2944 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2945 ir_node *new_mem = be_transform_node(mem);
2946 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2947 ir_node *new_ptr = be_transform_node(ptr);
2948 ir_node *new_op = NULL;
2949 ir_graph *irg = current_ir_graph;
2950 dbg_info *dbgi = get_irn_dbg_info(node);
2951 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2952 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2953 ir_mode *mode = get_type_mode(get_entity_type(ent));
2954 ir_node *projs[pn_Load_max];
2956 ia32_collect_Projs(node, projs, pn_Load_max);
2958 if (mode_is_float(mode)) {
2959 if (USE_SSE2(env_cg)) {
2960 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2963 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2967 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2970 set_irn_pinned(new_op, op_pin_state_floats);
2971 set_ia32_frame_ent(new_op, ent);
2972 set_ia32_use_frame(new_op);
2974 set_ia32_op_type(new_op, ia32_AddrModeS);
2975 set_ia32_am_flavour(new_op, ia32_am_B);
2976 set_ia32_ls_mode(new_op, mode);
2977 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2979 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2986 * Transforms a FrameStore into an ia32 Store.
2988 static ir_node *gen_be_FrameStore(ir_node *node) {
2989 ir_node *block = be_transform_node(get_nodes_block(node));
2990 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2991 ir_node *new_mem = be_transform_node(mem);
2992 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2993 ir_node *new_ptr = be_transform_node(ptr);
2994 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2995 ir_node *new_val = be_transform_node(val);
2996 ir_node *new_op = NULL;
2997 ir_graph *irg = current_ir_graph;
2998 dbg_info *dbgi = get_irn_dbg_info(node);
2999 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3000 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3001 ir_mode *mode = get_irn_mode(val);
3003 if (mode_is_float(mode)) {
3004 if (USE_SSE2(env_cg)) {
3005 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3007 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3009 } else if (get_mode_size_bits(mode) == 8) {
3010 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3012 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3015 set_ia32_frame_ent(new_op, ent);
3016 set_ia32_use_frame(new_op);
3018 set_ia32_op_type(new_op, ia32_AddrModeD);
3019 set_ia32_am_flavour(new_op, ia32_am_B);
3020 set_ia32_ls_mode(new_op, mode);
3022 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3028 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3030 static ir_node *gen_be_Return(ir_node *node) {
3031 ir_graph *irg = current_ir_graph;
3032 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3033 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3034 ir_entity *ent = get_irg_entity(irg);
3035 ir_type *tp = get_entity_type(ent);
3040 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3041 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3044 int pn_ret_val, pn_ret_mem, arity, i;
3046 assert(ret_val != NULL);
3047 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3048 return be_duplicate_node(node);
3051 res_type = get_method_res_type(tp, 0);
3053 if (! is_Primitive_type(res_type)) {
3054 return be_duplicate_node(node);
3057 mode = get_type_mode(res_type);
3058 if (! mode_is_float(mode)) {
3059 return be_duplicate_node(node);
3062 assert(get_method_n_ress(tp) == 1);
3064 pn_ret_val = get_Proj_proj(ret_val);
3065 pn_ret_mem = get_Proj_proj(ret_mem);
3067 /* get the Barrier */
3068 barrier = get_Proj_pred(ret_val);
3070 /* get result input of the Barrier */
3071 ret_val = get_irn_n(barrier, pn_ret_val);
3072 new_ret_val = be_transform_node(ret_val);
3074 /* get memory input of the Barrier */
3075 ret_mem = get_irn_n(barrier, pn_ret_mem);
3076 new_ret_mem = be_transform_node(ret_mem);
3078 frame = get_irg_frame(irg);
3080 dbgi = get_irn_dbg_info(barrier);
3081 block = be_transform_node(get_nodes_block(barrier));
3083 noreg = ia32_new_NoReg_gp(env_cg);
3085 /* store xmm0 onto stack */
3086 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3087 new_ret_val, new_ret_mem);
3088 set_ia32_ls_mode(sse_store, mode);
3089 set_ia32_op_type(sse_store, ia32_AddrModeD);
3090 set_ia32_use_frame(sse_store);
3091 set_ia32_am_flavour(sse_store, ia32_am_B);
3093 /* load into x87 register */
3094 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3095 set_ia32_op_type(fld, ia32_AddrModeS);
3096 set_ia32_use_frame(fld);
3097 set_ia32_am_flavour(fld, ia32_am_B);
3099 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3100 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3102 /* create a new barrier */
3103 arity = get_irn_arity(barrier);
3104 in = alloca(arity * sizeof(in[0]));
3105 for (i = 0; i < arity; ++i) {
3108 if (i == pn_ret_val) {
3110 } else if (i == pn_ret_mem) {
3113 ir_node *in = get_irn_n(barrier, i);
3114 new_in = be_transform_node(in);
3119 new_barrier = new_ir_node(dbgi, irg, block,
3120 get_irn_op(barrier), get_irn_mode(barrier),
3122 copy_node_attr(barrier, new_barrier);
3123 be_duplicate_deps(barrier, new_barrier);
3124 be_set_transformed_node(barrier, new_barrier);
3125 mark_irn_visited(barrier);
3127 /* transform normally */
3128 return be_duplicate_node(node);
3132 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3134 static ir_node *gen_be_AddSP(ir_node *node) {
3135 ir_node *block = be_transform_node(get_nodes_block(node));
3136 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3138 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3139 ir_node *new_sp = be_transform_node(sp);
3140 ir_graph *irg = current_ir_graph;
3141 dbg_info *dbgi = get_irn_dbg_info(node);
3142 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3143 ir_node *nomem = new_NoMem();
3146 new_sz = create_immediate_or_transform(sz, 0);
3148 /* ia32 stack grows in reverse direction, make a SubSP */
3149 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3151 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3152 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3158 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3160 static ir_node *gen_be_SubSP(ir_node *node) {
3161 ir_node *block = be_transform_node(get_nodes_block(node));
3162 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3164 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3165 ir_node *new_sp = be_transform_node(sp);
3166 ir_graph *irg = current_ir_graph;
3167 dbg_info *dbgi = get_irn_dbg_info(node);
3168 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3169 ir_node *nomem = new_NoMem();
3172 new_sz = create_immediate_or_transform(sz, 0);
3174 /* ia32 stack grows in reverse direction, make an AddSP */
3175 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3176 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3183 * This function just sets the register for the Unknown node
3184 * as this is not done during register allocation because Unknown
3185 * is an "ignore" node.
3187 static ir_node *gen_Unknown(ir_node *node) {
3188 ir_mode *mode = get_irn_mode(node);
3190 if (mode_is_float(mode)) {
3192 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3193 if (USE_SSE2(env_cg))
3194 return ia32_new_Unknown_xmm(env_cg);
3196 return ia32_new_Unknown_vfp(env_cg);
3198 ir_graph *irg = current_ir_graph;
3199 dbg_info *dbgi = get_irn_dbg_info(node);
3200 ir_node *block = get_irg_start_block(irg);
3201 return new_rd_ia32_vfldz(dbgi, irg, block);
3203 } else if (mode_needs_gp_reg(mode)) {
3204 return ia32_new_Unknown_gp(env_cg);
3206 assert(0 && "unsupported Unknown-Mode");
3213 * Change some phi modes
3215 static ir_node *gen_Phi(ir_node *node) {
3216 ir_node *block = be_transform_node(get_nodes_block(node));
3217 ir_graph *irg = current_ir_graph;
3218 dbg_info *dbgi = get_irn_dbg_info(node);
3219 ir_mode *mode = get_irn_mode(node);
3222 if(mode_needs_gp_reg(mode)) {
3223 /* we shouldn't have any 64bit stuff around anymore */
3224 assert(get_mode_size_bits(mode) <= 32);
3225 /* all integer operations are on 32bit registers now */
3227 } else if(mode_is_float(mode)) {
3228 if (USE_SSE2(env_cg)) {
3235 /* phi nodes allow loops, so we use the old arguments for now
3236 * and fix this later */
3237 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3238 copy_node_attr(node, phi);
3239 be_duplicate_deps(node, phi);
3241 be_set_transformed_node(node, phi);
3242 be_enqueue_preds(node);
3250 static ir_node *gen_IJmp(ir_node *node) {
3251 ir_node *block = be_transform_node(get_nodes_block(node));
3252 ir_graph *irg = current_ir_graph;
3253 dbg_info *dbgi = get_irn_dbg_info(node);
3254 ir_node *new_op = be_transform_node(get_IJmp_target(node));
3255 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3256 ir_node *nomem = new_NoMem();
3259 new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
3260 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
3262 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3268 /**********************************************************************
3271 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3272 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3273 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3274 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3276 **********************************************************************/
3278 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3280 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3283 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3284 ir_node *val, ir_node *mem);
3287 * Transforms a lowered Load into a "real" one.
3289 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3291 ir_node *block = be_transform_node(get_nodes_block(node));
3292 ir_node *ptr = get_irn_n(node, 0);
3293 ir_node *new_ptr = be_transform_node(ptr);
3294 ir_node *mem = get_irn_n(node, 1);
3295 ir_node *new_mem = be_transform_node(mem);
3296 ir_graph *irg = current_ir_graph;
3297 dbg_info *dbgi = get_irn_dbg_info(node);
3298 ir_mode *mode = get_ia32_ls_mode(node);
3299 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3302 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3304 set_ia32_op_type(new_op, ia32_AddrModeS);
3305 set_ia32_am_flavour(new_op, ia32_am_OB);
3306 set_ia32_am_offs_int(new_op, 0);
3307 set_ia32_am_scale(new_op, 1);
3308 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3309 if (is_ia32_am_sc_sign(node))
3310 set_ia32_am_sc_sign(new_op);
3311 set_ia32_ls_mode(new_op, mode);
3312 if (is_ia32_use_frame(node)) {
3313 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3314 set_ia32_use_frame(new_op);
3317 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3323 * Transforms a lowered Store into a "real" one.
3325 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3327 ir_node *block = be_transform_node(get_nodes_block(node));
3328 ir_node *ptr = get_irn_n(node, 0);
3329 ir_node *new_ptr = be_transform_node(ptr);
3330 ir_node *val = get_irn_n(node, 1);
3331 ir_node *new_val = be_transform_node(val);
3332 ir_node *mem = get_irn_n(node, 2);
3333 ir_node *new_mem = be_transform_node(mem);
3334 ir_graph *irg = current_ir_graph;
3335 dbg_info *dbgi = get_irn_dbg_info(node);
3336 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3337 ir_mode *mode = get_ia32_ls_mode(node);
3340 ia32_am_flavour_t am_flav = ia32_B;
3342 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3344 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3346 add_ia32_am_offs_int(new_op, am_offs);
3349 set_ia32_op_type(new_op, ia32_AddrModeD);
3350 set_ia32_am_flavour(new_op, am_flav);
3351 set_ia32_ls_mode(new_op, mode);
3352 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3353 set_ia32_use_frame(new_op);
3355 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3362 * Transforms an ia32_l_XXX into a "real" XXX node
3364 * @param env The transformation environment
3365 * @return the created ia32 XXX node
3367 #define GEN_LOWERED_OP(op) \
3368 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3369 return gen_binop(node, get_binop_left(node), \
3370 get_binop_right(node), new_rd_ia32_##op,0); \
3373 #define GEN_LOWERED_x87_OP(op) \
3374 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3376 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3377 get_binop_right(node), new_rd_ia32_##op); \
3381 #define GEN_LOWERED_UNOP(op) \
3382 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3383 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3386 #define GEN_LOWERED_SHIFT_OP(op) \
3387 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3388 return gen_shift_binop(node, get_binop_left(node), \
3389 get_binop_right(node), new_rd_ia32_##op); \
3392 #define GEN_LOWERED_LOAD(op) \
3393 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3394 return gen_lowered_Load(node, new_rd_ia32_##op); \
3397 #define GEN_LOWERED_STORE(op) \
3398 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3399 return gen_lowered_Store(node, new_rd_ia32_##op); \
3406 GEN_LOWERED_OP(IMul)
3408 GEN_LOWERED_x87_OP(vfprem)
3409 GEN_LOWERED_x87_OP(vfmul)
3410 GEN_LOWERED_x87_OP(vfsub)
3412 GEN_LOWERED_UNOP(Neg)
3414 GEN_LOWERED_LOAD(vfild)
3415 GEN_LOWERED_LOAD(Load)
3416 // GEN_LOWERED_STORE(vfist) TODO
3417 GEN_LOWERED_STORE(Store)
3419 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3420 ir_node *block = be_transform_node(get_nodes_block(node));
3421 ir_node *left = get_binop_left(node);
3422 ir_node *new_left = be_transform_node(left);
3423 ir_node *right = get_binop_right(node);
3424 ir_node *new_right = be_transform_node(right);
3425 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3426 ir_graph *irg = current_ir_graph;
3427 dbg_info *dbgi = get_irn_dbg_info(node);
3428 ir_node *fpcw = get_fpcw();
3431 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3432 new_right, new_NoMem(), fpcw);
3433 clear_ia32_commutative(vfdiv);
3434 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3436 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3442 * Transforms a l_MulS into a "real" MulS node.
3444 * @param env The transformation environment
3445 * @return the created ia32 Mul node
3447 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3448 ir_node *block = be_transform_node(get_nodes_block(node));
3449 ir_node *left = get_binop_left(node);
3450 ir_node *new_left = be_transform_node(left);
3451 ir_node *right = get_binop_right(node);
3452 ir_node *new_right = be_transform_node(right);
3453 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3454 ir_graph *irg = current_ir_graph;
3455 dbg_info *dbgi = get_irn_dbg_info(node);
3457 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3458 /* and then skip the result Proj, because all needed Projs are already there. */
3459 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3460 new_right, new_NoMem());
3461 clear_ia32_commutative(muls);
3462 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3464 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3469 GEN_LOWERED_SHIFT_OP(Shl)
3470 GEN_LOWERED_SHIFT_OP(Shr)
3471 GEN_LOWERED_SHIFT_OP(Sar)
3474 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3475 * op1 - target to be shifted
3476 * op2 - contains bits to be shifted into target
3478 * Only op3 can be an immediate.
3480 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3481 ir_node *op2, ir_node *count)
3483 ir_node *block = be_transform_node(get_nodes_block(node));
3484 ir_node *new_op1 = be_transform_node(op1);
3485 ir_node *new_op2 = be_transform_node(op2);
3486 ir_node *new_count = be_transform_node(count);
3487 ir_node *new_op = NULL;
3488 ir_graph *irg = current_ir_graph;
3489 dbg_info *dbgi = get_irn_dbg_info(node);
3490 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3491 ir_node *nomem = new_NoMem();
3495 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3497 /* Check if immediate optimization is on and */
3498 /* if it's an operation with immediate. */
3499 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3501 /* Limit imm_op within range imm8 */
3503 tv = get_ia32_Immop_tarval(imm_op);
3506 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3507 set_ia32_Immop_tarval(imm_op, tv);
3514 /* integer operations */
3516 /* This is ShiftD with const */
3517 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3519 if (is_ia32_l_ShlD(node))
3520 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3521 new_op1, new_op2, noreg, nomem);
3523 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3524 new_op1, new_op2, noreg, nomem);
3525 copy_ia32_Immop_attr(new_op, imm_op);
3528 /* This is a normal ShiftD */
3529 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3530 if (is_ia32_l_ShlD(node))
3531 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3532 new_op1, new_op2, new_count, nomem);
3534 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3535 new_op1, new_op2, new_count, nomem);
3538 /* set AM support */
3539 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3541 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3543 set_ia32_emit_cl(new_op);
3548 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3549 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3550 get_irn_n(node, 1), get_irn_n(node, 2));
3553 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3554 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3555 get_irn_n(node, 1), get_irn_n(node, 2));
3559 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3561 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3562 ir_node *block = be_transform_node(get_nodes_block(node));
3563 ir_node *val = get_irn_n(node, 1);
3564 ir_node *new_val = be_transform_node(val);
3565 ia32_code_gen_t *cg = env_cg;
3566 ir_node *res = NULL;
3567 ir_graph *irg = current_ir_graph;
3569 ir_node *noreg, *new_ptr, *new_mem;
3576 mem = get_irn_n(node, 2);
3577 new_mem = be_transform_node(mem);
3578 ptr = get_irn_n(node, 0);
3579 new_ptr = be_transform_node(ptr);
3580 noreg = ia32_new_NoReg_gp(cg);
3581 dbgi = get_irn_dbg_info(node);
3583 /* Store x87 -> MEM */
3584 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3585 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3586 set_ia32_use_frame(res);
3587 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3588 set_ia32_am_flavour(res, ia32_B);
3589 set_ia32_op_type(res, ia32_AddrModeD);
3591 /* Load MEM -> SSE */
3592 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3593 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3594 set_ia32_use_frame(res);
3595 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3596 set_ia32_am_flavour(res, ia32_B);
3597 set_ia32_op_type(res, ia32_AddrModeS);
3598 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3604 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3606 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3607 ir_node *block = be_transform_node(get_nodes_block(node));
3608 ir_node *val = get_irn_n(node, 1);
3609 ir_node *new_val = be_transform_node(val);
3610 ia32_code_gen_t *cg = env_cg;
3611 ir_graph *irg = current_ir_graph;
3612 ir_node *res = NULL;
3613 ir_entity *fent = get_ia32_frame_ent(node);
3614 ir_mode *lsmode = get_ia32_ls_mode(node);
3616 ir_node *noreg, *new_ptr, *new_mem;
3620 if (! USE_SSE2(cg)) {
3621 /* SSE unit is not used -> skip this node. */
3625 ptr = get_irn_n(node, 0);
3626 new_ptr = be_transform_node(ptr);
3627 mem = get_irn_n(node, 2);
3628 new_mem = be_transform_node(mem);
3629 noreg = ia32_new_NoReg_gp(cg);
3630 dbgi = get_irn_dbg_info(node);
3632 /* Store SSE -> MEM */
3633 if (is_ia32_xLoad(skip_Proj(new_val))) {
3634 ir_node *ld = skip_Proj(new_val);
3636 /* we can vfld the value directly into the fpu */
3637 fent = get_ia32_frame_ent(ld);
3638 ptr = get_irn_n(ld, 0);
3639 offs = get_ia32_am_offs_int(ld);
3641 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3642 set_ia32_frame_ent(res, fent);
3643 set_ia32_use_frame(res);
3644 set_ia32_ls_mode(res, lsmode);
3645 set_ia32_am_flavour(res, ia32_B);
3646 set_ia32_op_type(res, ia32_AddrModeD);
3650 /* Load MEM -> x87 */
3651 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3652 set_ia32_frame_ent(res, fent);
3653 set_ia32_use_frame(res);
3654 add_ia32_am_offs_int(res, offs);
3655 set_ia32_am_flavour(res, ia32_B);
3656 set_ia32_op_type(res, ia32_AddrModeS);
3657 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3662 /*********************************************************
3665 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3666 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3667 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3668 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3670 *********************************************************/
3673 * the BAD transformer.
3675 static ir_node *bad_transform(ir_node *node) {
3676 panic("No transform function for %+F available.\n", node);
3681 * Transform the Projs of an AddSP.
3683 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3684 ir_node *block = be_transform_node(get_nodes_block(node));
3685 ir_node *pred = get_Proj_pred(node);
3686 ir_node *new_pred = be_transform_node(pred);
3687 ir_graph *irg = current_ir_graph;
3688 dbg_info *dbgi = get_irn_dbg_info(node);
3689 long proj = get_Proj_proj(node);
3691 if (proj == pn_be_AddSP_sp) {
3692 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3693 pn_ia32_SubSP_stack);
3694 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3696 } else if(proj == pn_be_AddSP_res) {
3697 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3698 pn_ia32_SubSP_addr);
3699 } else if (proj == pn_be_AddSP_M) {
3700 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3704 return new_rd_Unknown(irg, get_irn_mode(node));
3708 * Transform the Projs of a SubSP.
3710 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3711 ir_node *block = be_transform_node(get_nodes_block(node));
3712 ir_node *pred = get_Proj_pred(node);
3713 ir_node *new_pred = be_transform_node(pred);
3714 ir_graph *irg = current_ir_graph;
3715 dbg_info *dbgi = get_irn_dbg_info(node);
3716 long proj = get_Proj_proj(node);
3718 if (proj == pn_be_SubSP_sp) {
3719 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3720 pn_ia32_AddSP_stack);
3721 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3723 } else if (proj == pn_be_SubSP_M) {
3724 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3728 return new_rd_Unknown(irg, get_irn_mode(node));
3732 * Transform and renumber the Projs from a Load.
3734 static ir_node *gen_Proj_Load(ir_node *node) {
3735 ir_node *block = be_transform_node(get_nodes_block(node));
3736 ir_node *pred = get_Proj_pred(node);
3737 ir_node *new_pred = be_transform_node(pred);
3738 ir_graph *irg = current_ir_graph;
3739 dbg_info *dbgi = get_irn_dbg_info(node);
3740 long proj = get_Proj_proj(node);
3742 /* renumber the proj */
3743 if (is_ia32_Load(new_pred)) {
3744 if (proj == pn_Load_res) {
3745 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3746 } else if (proj == pn_Load_M) {
3747 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3749 } else if (is_ia32_xLoad(new_pred)) {
3750 if (proj == pn_Load_res) {
3751 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3752 } else if (proj == pn_Load_M) {
3753 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3755 } else if (is_ia32_vfld(new_pred)) {
3756 if (proj == pn_Load_res) {
3757 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3758 } else if (proj == pn_Load_M) {
3759 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3764 return new_rd_Unknown(irg, get_irn_mode(node));
3768 * Transform and renumber the Projs from a DivMod like instruction.
3770 static ir_node *gen_Proj_DivMod(ir_node *node) {
3771 ir_node *block = be_transform_node(get_nodes_block(node));
3772 ir_node *pred = get_Proj_pred(node);
3773 ir_node *new_pred = be_transform_node(pred);
3774 ir_graph *irg = current_ir_graph;
3775 dbg_info *dbgi = get_irn_dbg_info(node);
3776 ir_mode *mode = get_irn_mode(node);
3777 long proj = get_Proj_proj(node);
3779 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3781 switch (get_irn_opcode(pred)) {
3785 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3787 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3795 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3797 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3805 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3806 case pn_DivMod_res_div:
3807 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3808 case pn_DivMod_res_mod:
3809 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3819 return new_rd_Unknown(irg, mode);
3823 * Transform and renumber the Projs from a CopyB.
3825 static ir_node *gen_Proj_CopyB(ir_node *node) {
3826 ir_node *block = be_transform_node(get_nodes_block(node));
3827 ir_node *pred = get_Proj_pred(node);
3828 ir_node *new_pred = be_transform_node(pred);
3829 ir_graph *irg = current_ir_graph;
3830 dbg_info *dbgi = get_irn_dbg_info(node);
3831 ir_mode *mode = get_irn_mode(node);
3832 long proj = get_Proj_proj(node);
3835 case pn_CopyB_M_regular:
3836 if (is_ia32_CopyB_i(new_pred)) {
3837 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3838 } else if (is_ia32_CopyB(new_pred)) {
3839 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3847 return new_rd_Unknown(irg, mode);
3851 * Transform and renumber the Projs from a vfdiv.
3853 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3854 ir_node *block = be_transform_node(get_nodes_block(node));
3855 ir_node *pred = get_Proj_pred(node);
3856 ir_node *new_pred = be_transform_node(pred);
3857 ir_graph *irg = current_ir_graph;
3858 dbg_info *dbgi = get_irn_dbg_info(node);
3859 ir_mode *mode = get_irn_mode(node);
3860 long proj = get_Proj_proj(node);
3863 case pn_ia32_l_vfdiv_M:
3864 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3865 case pn_ia32_l_vfdiv_res:
3866 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3871 return new_rd_Unknown(irg, mode);
3875 * Transform and renumber the Projs from a Quot.
3877 static ir_node *gen_Proj_Quot(ir_node *node) {
3878 ir_node *block = be_transform_node(get_nodes_block(node));
3879 ir_node *pred = get_Proj_pred(node);
3880 ir_node *new_pred = be_transform_node(pred);
3881 ir_graph *irg = current_ir_graph;
3882 dbg_info *dbgi = get_irn_dbg_info(node);
3883 ir_mode *mode = get_irn_mode(node);
3884 long proj = get_Proj_proj(node);
3888 if (is_ia32_xDiv(new_pred)) {
3889 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3890 } else if (is_ia32_vfdiv(new_pred)) {
3891 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3895 if (is_ia32_xDiv(new_pred)) {
3896 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3897 } else if (is_ia32_vfdiv(new_pred)) {
3898 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3906 return new_rd_Unknown(irg, mode);
3910 * Transform the Thread Local Storage Proj.
3912 static ir_node *gen_Proj_tls(ir_node *node) {
3913 ir_node *block = be_transform_node(get_nodes_block(node));
3914 ir_graph *irg = current_ir_graph;
3915 dbg_info *dbgi = NULL;
3916 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3922 * Transform the Projs from a be_Call.
3924 static ir_node *gen_Proj_be_Call(ir_node *node) {
3925 ir_node *block = be_transform_node(get_nodes_block(node));
3926 ir_node *call = get_Proj_pred(node);
3927 ir_node *new_call = be_transform_node(call);
3928 ir_graph *irg = current_ir_graph;
3929 dbg_info *dbgi = get_irn_dbg_info(node);
3930 long proj = get_Proj_proj(node);
3931 ir_mode *mode = get_irn_mode(node);
3933 const arch_register_class_t *cls;
3935 /* The following is kinda tricky: If we're using SSE, then we have to
3936 * move the result value of the call in floating point registers to an
3937 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3938 * after the call, we have to make sure to correctly make the
3939 * MemProj and the result Proj use these 2 nodes
3941 if (proj == pn_be_Call_M_regular) {
3942 // get new node for result, are we doing the sse load/store hack?
3943 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3944 ir_node *call_res_new;
3945 ir_node *call_res_pred = NULL;
3947 if (call_res != NULL) {
3948 call_res_new = be_transform_node(call_res);
3949 call_res_pred = get_Proj_pred(call_res_new);
3952 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3953 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3954 pn_be_Call_M_regular);
3956 assert(is_ia32_xLoad(call_res_pred));
3957 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3961 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3963 ir_node *frame = get_irg_frame(irg);
3964 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3966 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3969 /* in case there is no memory output: create one to serialize the copy
3971 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3972 pn_be_Call_M_regular);
3973 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3974 pn_be_Call_first_res);
3976 /* store st(0) onto stack */
3977 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3979 set_ia32_op_type(fstp, ia32_AddrModeD);
3980 set_ia32_use_frame(fstp);
3981 set_ia32_am_flavour(fstp, ia32_am_B);
3983 /* load into SSE register */
3984 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3985 set_ia32_ls_mode(sse_load, mode);
3986 set_ia32_op_type(sse_load, ia32_AddrModeS);
3987 set_ia32_use_frame(sse_load);
3988 set_ia32_am_flavour(sse_load, ia32_am_B);
3990 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3994 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3996 /* get a Proj representing a caller save register */
3997 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3998 assert(is_Proj(p) && "Proj expected.");
4000 /* user of the the proj is the Keep */
4001 p = get_edge_src_irn(get_irn_out_edge_first(p));
4002 assert(be_is_Keep(p) && "Keep expected.");
4008 /* transform call modes */
4009 if (mode_is_data(mode)) {
4010 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4014 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4018 * Transform the Projs from a Cmp.
4020 static ir_node *gen_Proj_Cmp(ir_node *node)
4022 /* normally Cmps are processed when looking at Cond nodes, but this case
4023 * can happen in complicated Psi conditions */
4025 ir_node *cmp = get_Proj_pred(node);
4026 long pnc = get_Proj_proj(node);
4027 ir_node *cmp_left = get_Cmp_left(cmp);
4028 ir_node *cmp_right = get_Cmp_right(cmp);
4029 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4030 dbg_info *dbgi = get_irn_dbg_info(cmp);
4031 ir_node *block = be_transform_node(get_nodes_block(node));
4034 assert(!mode_is_float(cmp_mode));
4036 if(!mode_is_signed(cmp_mode)) {
4037 pnc |= ia32_pn_Cmp_Unsigned;
4040 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4041 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4047 * Transform and potentially renumber Proj nodes.
4049 static ir_node *gen_Proj(ir_node *node) {
4050 ir_graph *irg = current_ir_graph;
4051 dbg_info *dbgi = get_irn_dbg_info(node);
4052 ir_node *pred = get_Proj_pred(node);
4053 long proj = get_Proj_proj(node);
4055 if (is_Store(pred) || be_is_FrameStore(pred)) {
4056 if (proj == pn_Store_M) {
4057 return be_transform_node(pred);
4060 return new_r_Bad(irg);
4062 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4063 return gen_Proj_Load(node);
4064 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4065 return gen_Proj_DivMod(node);
4066 } else if (is_CopyB(pred)) {
4067 return gen_Proj_CopyB(node);
4068 } else if (is_Quot(pred)) {
4069 return gen_Proj_Quot(node);
4070 } else if (is_ia32_l_vfdiv(pred)) {
4071 return gen_Proj_l_vfdiv(node);
4072 } else if (be_is_SubSP(pred)) {
4073 return gen_Proj_be_SubSP(node);
4074 } else if (be_is_AddSP(pred)) {
4075 return gen_Proj_be_AddSP(node);
4076 } else if (be_is_Call(pred)) {
4077 return gen_Proj_be_Call(node);
4078 } else if (is_Cmp(pred)) {
4079 return gen_Proj_Cmp(node);
4080 } else if (get_irn_op(pred) == op_Start) {
4081 if (proj == pn_Start_X_initial_exec) {
4082 ir_node *block = get_nodes_block(pred);
4085 /* we exchange the ProjX with a jump */
4086 block = be_transform_node(block);
4087 jump = new_rd_Jmp(dbgi, irg, block);
4090 if (node == be_get_old_anchor(anchor_tls)) {
4091 return gen_Proj_tls(node);
4094 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4098 ir_node *new_pred = be_transform_node(pred);
4099 ir_node *block = be_transform_node(get_nodes_block(node));
4100 ir_mode *mode = get_irn_mode(node);
4101 if (mode_needs_gp_reg(mode)) {
4102 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4103 get_Proj_proj(node));
4104 #ifdef DEBUG_libfirm
4105 new_proj->node_nr = node->node_nr;
4111 return be_duplicate_node(node);
4115 * Enters all transform functions into the generic pointer
4117 static void register_transformers(void)
4121 /* first clear the generic function pointer for all ops */
4122 clear_irp_opcodes_generic_func();
4124 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4125 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4162 /* transform ops from intrinsic lowering */
4182 /* GEN(ia32_l_vfist); TODO */
4184 GEN(ia32_l_X87toSSE);
4185 GEN(ia32_l_SSEtoX87);
4190 /* we should never see these nodes */
4205 /* handle generic backend nodes */
4216 /* set the register for all Unknown nodes */
4219 op_Mulh = get_op_Mulh();
4228 * Pre-transform all unknown and noreg nodes.
4230 static void ia32_pretransform_node(void *arch_cg) {
4231 ia32_code_gen_t *cg = arch_cg;
4233 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4234 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4235 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4236 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4237 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4238 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4243 void add_missing_keep_walker(ir_node *node, void *data)
4246 unsigned found_projs = 0;
4247 const ir_edge_t *edge;
4248 ir_mode *mode = get_irn_mode(node);
4253 if(!is_ia32_irn(node))
4256 n_outs = get_ia32_n_res(node);
4259 if(is_ia32_SwitchJmp(node))
4262 assert(n_outs < (int) sizeof(unsigned) * 8);
4263 foreach_out_edge(node, edge) {
4264 ir_node *proj = get_edge_src_irn(edge);
4265 int pn = get_Proj_proj(proj);
4267 assert(pn < n_outs);
4268 found_projs |= 1 << pn;
4272 /* are keeps missing? */
4274 for(i = 0; i < n_outs; ++i) {
4277 const arch_register_req_t *req;
4278 const arch_register_class_t *class;
4280 if(found_projs & (1 << i)) {
4284 req = get_ia32_out_req(node, i);
4290 block = get_nodes_block(node);
4291 in[0] = new_r_Proj(current_ir_graph, block, node,
4292 arch_register_class_mode(class), i);
4293 if(last_keep != NULL) {
4294 be_Keep_add_node(last_keep, class, in[0]);
4296 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4302 * Adds missing keeps to nodes
4305 void add_missing_keeps(ia32_code_gen_t *cg)
4307 ir_graph *irg = be_get_birg_irg(cg->birg);
4308 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4311 /* do the transformation */
4312 void ia32_transform_graph(ia32_code_gen_t *cg) {
4313 register_transformers();
4315 initial_fpcw = NULL;
4316 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4317 edges_verify(cg->irg);
4318 add_missing_keeps(cg);
4319 edges_verify(cg->irg);
4322 void ia32_init_transform(void)
4324 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");