2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
39 #define SFP_SIGN "0x80000000"
40 #define DFP_SIGN "0x8000000000000000"
41 #define SFP_ABS "0x7FFFFFFF"
42 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
44 #define TP_SFP_SIGN "ia32_sfp_sign"
45 #define TP_DFP_SIGN "ia32_dfp_sign"
46 #define TP_SFP_ABS "ia32_sfp_abs"
47 #define TP_DFP_ABS "ia32_dfp_abs"
49 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
50 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
51 #define ENT_SFP_ABS "IA32_SFP_ABS"
52 #define ENT_DFP_ABS "IA32_DFP_ABS"
54 extern ir_op *get_op_Mulh(void);
56 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
57 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
59 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
60 ir_node *op, ir_node *mem, ir_mode *mode);
63 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
66 /****************************************************************************************************
68 * | | | | / _| | | (_)
69 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
70 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
71 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
72 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
74 ****************************************************************************************************/
77 * Gets the Proj with number pn from irn.
79 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
80 const ir_edge_t *edge;
82 assert(get_irn_mode(irn) == mode_T && "need mode_T");
84 foreach_out_edge(irn, edge) {
85 proj = get_edge_src_irn(edge);
87 if (get_Proj_proj(proj) == pn)
94 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
95 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
100 } names [ia32_known_const_max] = {
101 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
102 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
103 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
104 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
106 static struct entity *ent_cache[ia32_known_const_max];
108 const char *tp_name, *ent_name, *cnst_str;
115 ent_name = names[kct].ent_name;
116 if (! ent_cache[kct]) {
117 tp_name = names[kct].tp_name;
118 cnst_str = names[kct].cnst_str;
120 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
121 tp = new_type_primitive(new_id_from_str(tp_name), mode);
122 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
124 set_entity_ld_ident(ent, get_entity_ident(ent));
125 set_entity_visibility(ent, visibility_local);
126 set_entity_variability(ent, variability_constant);
127 set_entity_allocation(ent, allocation_static);
129 /* we create a new entity here: It's initialization must resist on the
131 rem = current_ir_graph;
132 current_ir_graph = get_const_code_irg();
133 cnst = new_Const(mode, tv);
134 current_ir_graph = rem;
136 set_atomic_ent_value(ent, cnst);
138 /* cache the entry */
139 ent_cache[kct] = ent;
142 return get_entity_ident(ent_cache[kct]);
147 * Prints the old node name on cg obst and returns a pointer to it.
149 const char *ia32_get_old_node_name(ia32_transform_env_t *env) {
150 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
152 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
153 obstack_1grow(isa->name_obst, 0);
154 isa->name_obst_size += obstack_object_size(isa->name_obst);
155 return obstack_finish(isa->name_obst);
159 /* determine if one operator is an Imm */
160 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
162 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
163 else return is_ia32_Cnst(op2) ? op2 : NULL;
166 /* determine if one operator is not an Imm */
167 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
168 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
173 * Construct a standard binary operation, set AM and immediate if required.
175 * @param env The transformation environment
176 * @param op1 The first operand
177 * @param op2 The second operand
178 * @param func The node constructor function
179 * @return The constructed ia32 node.
181 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
182 ir_node *new_op = NULL;
183 ir_mode *mode = env->mode;
184 dbg_info *dbg = env->dbg;
185 ir_graph *irg = env->irg;
186 ir_node *block = env->block;
187 firm_dbg_module_t *mod = env->mod;
188 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
189 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
190 ir_node *nomem = new_NoMem();
191 ir_node *expr_op, *imm_op;
193 /* Check if immediate optimization is on and */
194 /* if it's an operation with immediate. */
195 if (! env->cg->opt.immops) {
199 else if (is_op_commutative(get_irn_op(env->irn))) {
200 imm_op = get_immediate_op(op1, op2);
201 expr_op = get_expr_op(op1, op2);
204 imm_op = get_immediate_op(NULL, op2);
205 expr_op = get_expr_op(op1, op2);
208 assert((expr_op || imm_op) && "invalid operands");
211 /* We have two consts here: not yet supported */
215 if (mode_is_float(mode)) {
216 /* floating point operations */
218 DB((mod, LEVEL_1, "FP with immediate ..."));
219 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
220 set_ia32_Immop_attr(new_op, imm_op);
221 set_ia32_am_support(new_op, ia32_am_None);
224 DB((mod, LEVEL_1, "FP binop ..."));
225 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
226 set_ia32_am_support(new_op, ia32_am_Source);
230 /* integer operations */
232 /* This is expr + const */
233 DB((mod, LEVEL_1, "INT with immediate ..."));
234 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
235 set_ia32_Immop_attr(new_op, imm_op);
238 set_ia32_am_support(new_op, ia32_am_Dest);
241 DB((mod, LEVEL_1, "INT binop ..."));
242 /* This is a normal operation */
243 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
246 set_ia32_am_support(new_op, ia32_am_Full);
250 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
252 set_ia32_res_mode(new_op, mode);
254 if (is_op_commutative(get_irn_op(env->irn))) {
255 set_ia32_commutative(new_op);
258 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
264 * Construct a shift/rotate binary operation, sets AM and immediate if required.
266 * @param env The transformation environment
267 * @param op1 The first operand
268 * @param op2 The second operand
269 * @param func The node constructor function
270 * @return The constructed ia32 node.
272 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
273 ir_node *new_op = NULL;
274 ir_mode *mode = env->mode;
275 dbg_info *dbg = env->dbg;
276 ir_graph *irg = env->irg;
277 ir_node *block = env->block;
278 firm_dbg_module_t *mod = env->mod;
279 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
280 ir_node *nomem = new_NoMem();
281 ir_node *expr_op, *imm_op;
284 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
286 /* Check if immediate optimization is on and */
287 /* if it's an operation with immediate. */
288 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
289 expr_op = get_expr_op(op1, op2);
291 assert((expr_op || imm_op) && "invalid operands");
294 /* We have two consts here: not yet supported */
298 /* Limit imm_op within range imm8 */
300 tv = get_ia32_Immop_tarval(imm_op);
303 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
310 /* integer operations */
312 /* This is shift/rot with const */
313 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
315 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
316 set_ia32_Immop_attr(new_op, imm_op);
319 /* This is a normal shift/rot */
320 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
321 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
325 set_ia32_am_support(new_op, ia32_am_Dest);
327 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
329 set_ia32_res_mode(new_op, mode);
330 set_ia32_emit_cl(new_op);
332 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
337 * Construct a standard unary operation, set AM and immediate if required.
339 * @param env The transformation environment
340 * @param op The operand
341 * @param func The node constructor function
342 * @return The constructed ia32 node.
344 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
345 ir_node *new_op = NULL;
346 ir_mode *mode = env->mode;
347 dbg_info *dbg = env->dbg;
348 firm_dbg_module_t *mod = env->mod;
349 ir_graph *irg = env->irg;
350 ir_node *block = env->block;
351 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
352 ir_node *nomem = new_NoMem();
354 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
356 if (mode_is_float(mode)) {
357 DB((mod, LEVEL_1, "FP unop ..."));
358 /* floating point operations don't support implicit store */
359 set_ia32_am_support(new_op, ia32_am_None);
362 DB((mod, LEVEL_1, "INT unop ..."));
363 set_ia32_am_support(new_op, ia32_am_Dest);
366 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
368 set_ia32_res_mode(new_op, mode);
370 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
376 * Creates an ia32 Add with immediate.
378 * @param env The transformation environment
379 * @param expr_op The expression operator
380 * @param const_op The constant
381 * @return the created ia32 Add node
383 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
384 ir_node *new_op = NULL;
385 tarval *tv = get_ia32_Immop_tarval(const_op);
386 firm_dbg_module_t *mod = env->mod;
387 dbg_info *dbg = env->dbg;
388 ir_graph *irg = env->irg;
389 ir_node *block = env->block;
390 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
391 ir_node *nomem = new_NoMem();
393 tarval_classification_t class_tv, class_negtv;
395 /* try to optimize to inc/dec */
396 if (env->cg->opt.incdec && tv) {
397 /* optimize tarvals */
398 class_tv = classify_tarval(tv);
399 class_negtv = classify_tarval(tarval_neg(tv));
401 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
402 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
403 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
406 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
407 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
408 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
414 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
415 set_ia32_Immop_attr(new_op, const_op);
422 * Creates an ia32 Add.
424 * @param dbg firm node dbg
425 * @param block the block the new node should belong to
426 * @param op1 first operator
427 * @param op2 second operator
428 * @param mode node mode
429 * @return the created ia32 Add node
431 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
432 ir_node *new_op = NULL;
433 dbg_info *dbg = env->dbg;
434 ir_mode *mode = env->mode;
435 ir_graph *irg = env->irg;
436 ir_node *block = env->block;
437 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
438 ir_node *nomem = new_NoMem();
439 ir_node *expr_op, *imm_op;
441 /* Check if immediate optimization is on and */
442 /* if it's an operation with immediate. */
443 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
444 expr_op = get_expr_op(op1, op2);
446 assert((expr_op || imm_op) && "invalid operands");
448 if (mode_is_float(mode)) {
449 if (USE_SSE2(env->cg))
450 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
452 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
458 /* No expr_op means, that we have two const - one symconst and */
459 /* one tarval or another symconst - because this case is not */
460 /* covered by constant folding */
461 /* We need to check for: */
462 /* 1) symconst + const -> becomes a LEA */
463 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
464 /* linker doesn't support two symconsts */
466 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
467 /* this is the 2nd case */
468 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
469 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
470 set_ia32_am_flavour(new_op, ia32_am_OB);
473 /* this is the 1st case */
474 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
476 if (get_ia32_op_type(op1) == ia32_SymConst) {
477 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
478 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
481 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
482 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
484 set_ia32_am_flavour(new_op, ia32_am_O);
488 set_ia32_am_support(new_op, ia32_am_Source);
489 set_ia32_op_type(new_op, ia32_AddrModeS);
491 /* Lea doesn't need a Proj */
495 /* This is expr + const */
496 new_op = gen_imm_Add(env, expr_op, imm_op);
499 set_ia32_am_support(new_op, ia32_am_Dest);
502 /* This is a normal add */
503 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
506 set_ia32_am_support(new_op, ia32_am_Full);
510 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
512 set_ia32_res_mode(new_op, mode);
514 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
520 * Creates an ia32 Mul.
522 * @param dbg firm node dbg
523 * @param block the block the new node should belong to
524 * @param op1 first operator
525 * @param op2 second operator
526 * @param mode node mode
527 * @return the created ia32 Mul node
529 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
532 if (mode_is_float(env->mode)) {
533 if (USE_SSE2(env->cg))
534 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
536 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
539 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
548 * Creates an ia32 Mulh.
549 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
550 * this result while Mul returns the lower 32 bit.
552 * @param env The transformation environment
553 * @param op1 The first operator
554 * @param op2 The second operator
555 * @return the created ia32 Mulh node
557 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
558 ir_node *proj_EAX, *proj_EDX, *mulh;
561 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
562 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
563 mulh = get_Proj_pred(proj_EAX);
564 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
566 /* to be on the save side */
567 set_Proj_proj(proj_EAX, pn_EAX);
569 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
570 /* Mulh with const cannot have AM */
571 set_ia32_am_support(mulh, ia32_am_None);
574 /* Mulh cannot have AM for destination */
575 set_ia32_am_support(mulh, ia32_am_Source);
581 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
589 * Creates an ia32 And.
591 * @param env The transformation environment
592 * @param op1 The first operator
593 * @param op2 The second operator
594 * @return The created ia32 And node
596 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
597 assert (! mode_is_float(env->mode));
598 return gen_binop(env, op1, op2, new_rd_ia32_And);
604 * Creates an ia32 Or.
606 * @param env The transformation environment
607 * @param op1 The first operator
608 * @param op2 The second operator
609 * @return The created ia32 Or node
611 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
612 assert (! mode_is_float(env->mode));
613 return gen_binop(env, op1, op2, new_rd_ia32_Or);
619 * Creates an ia32 Eor.
621 * @param env The transformation environment
622 * @param op1 The first operator
623 * @param op2 The second operator
624 * @return The created ia32 Eor node
626 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
627 assert(! mode_is_float(env->mode));
628 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
634 * Creates an ia32 Max.
636 * @param env The transformation environment
637 * @param op1 The first operator
638 * @param op2 The second operator
639 * @return the created ia32 Max node
641 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
644 if (mode_is_float(env->mode)) {
645 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
648 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
649 set_ia32_am_support(new_op, ia32_am_None);
650 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
659 * Creates an ia32 Min.
661 * @param env The transformation environment
662 * @param op1 The first operator
663 * @param op2 The second operator
664 * @return the created ia32 Min node
666 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
669 if (mode_is_float(env->mode)) {
670 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
673 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
674 set_ia32_am_support(new_op, ia32_am_None);
675 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
684 * Creates an ia32 Sub with immediate.
686 * @param env The transformation environment
687 * @param op1 The first operator
688 * @param op2 The second operator
689 * @return The created ia32 Sub node
691 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
692 ir_node *new_op = NULL;
693 tarval *tv = get_ia32_Immop_tarval(const_op);
694 firm_dbg_module_t *mod = env->mod;
695 dbg_info *dbg = env->dbg;
696 ir_graph *irg = env->irg;
697 ir_node *block = env->block;
698 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
699 ir_node *nomem = new_NoMem();
701 tarval_classification_t class_tv, class_negtv;
703 /* try to optimize to inc/dec */
704 if (env->cg->opt.incdec && tv) {
705 /* optimize tarvals */
706 class_tv = classify_tarval(tv);
707 class_negtv = classify_tarval(tarval_neg(tv));
709 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
710 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
711 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
714 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
715 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
716 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
722 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
723 set_ia32_Immop_attr(new_op, const_op);
730 * Creates an ia32 Sub.
732 * @param env The transformation environment
733 * @param op1 The first operator
734 * @param op2 The second operator
735 * @return The created ia32 Sub node
737 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
738 ir_node *new_op = NULL;
739 dbg_info *dbg = env->dbg;
740 ir_mode *mode = env->mode;
741 ir_graph *irg = env->irg;
742 ir_node *block = env->block;
743 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
744 ir_node *nomem = new_NoMem();
745 ir_node *expr_op, *imm_op;
747 /* Check if immediate optimization is on and */
748 /* if it's an operation with immediate. */
749 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
750 expr_op = get_expr_op(op1, op2);
752 assert((expr_op || imm_op) && "invalid operands");
754 if (mode_is_float(mode)) {
755 if (USE_SSE2(env->cg))
756 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
758 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
763 /* No expr_op means, that we have two const - one symconst and */
764 /* one tarval or another symconst - because this case is not */
765 /* covered by constant folding */
766 /* We need to check for: */
767 /* 1) symconst + const -> becomes a LEA */
768 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
769 /* linker doesn't support two symconsts */
771 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
772 /* this is the 2nd case */
773 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
774 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
775 set_ia32_am_sc_sign(new_op);
776 set_ia32_am_flavour(new_op, ia32_am_OB);
779 /* this is the 1st case */
780 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
782 if (get_ia32_op_type(op1) == ia32_SymConst) {
783 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
784 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
787 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
788 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
789 set_ia32_am_sc_sign(new_op);
791 set_ia32_am_flavour(new_op, ia32_am_O);
795 set_ia32_am_support(new_op, ia32_am_Source);
796 set_ia32_op_type(new_op, ia32_AddrModeS);
798 /* Lea doesn't need a Proj */
802 /* This is expr - const */
803 new_op = gen_imm_Sub(env, expr_op, imm_op);
806 set_ia32_am_support(new_op, ia32_am_Dest);
809 /* This is a normal sub */
810 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
813 set_ia32_am_support(new_op, ia32_am_Full);
817 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
819 set_ia32_res_mode(new_op, mode);
821 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
827 * Generates an ia32 DivMod with additional infrastructure for the
828 * register allocator if needed.
830 * @param env The transformation environment
831 * @param dividend -no comment- :)
832 * @param divisor -no comment- :)
833 * @param dm_flav flavour_Div/Mod/DivMod
834 * @return The created ia32 DivMod node
836 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
838 ir_node *edx_node, *cltd;
840 dbg_info *dbg = env->dbg;
841 ir_graph *irg = env->irg;
842 ir_node *block = env->block;
843 ir_mode *mode = env->mode;
844 ir_node *irn = env->irn;
849 mem = get_Div_mem(irn);
850 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
853 mem = get_Mod_mem(irn);
854 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
857 mem = get_DivMod_mem(irn);
858 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
864 if (mode_is_signed(mode)) {
865 /* in signed mode, we need to sign extend the dividend */
866 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
867 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
868 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
871 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
872 set_ia32_Const_type(edx_node, ia32_Const);
873 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
876 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
878 set_ia32_flavour(res, dm_flav);
879 set_ia32_n_res(res, 2);
881 /* Only one proj is used -> We must add a second proj and */
882 /* connect this one to a Keep node to eat up the second */
883 /* destroyed register. */
884 if (get_irn_n_edges(irn) == 1) {
885 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
886 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
888 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
889 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
892 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
895 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
898 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
900 set_ia32_res_mode(res, mode_Is);
907 * Wrapper for generate_DivMod. Sets flavour_Mod.
909 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
910 return generate_DivMod(env, op1, op2, flavour_Mod);
916 * Wrapper for generate_DivMod. Sets flavour_Div.
918 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
919 return generate_DivMod(env, op1, op2, flavour_Div);
925 * Wrapper for generate_DivMod. Sets flavour_DivMod.
927 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
928 return generate_DivMod(env, op1, op2, flavour_DivMod);
934 * Creates an ia32 floating Div.
936 * @param env The transformation environment
937 * @param op1 The first operator
938 * @param op2 The second operator
939 * @return The created ia32 fDiv node
941 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
942 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
944 ir_node *nomem = new_rd_NoMem(env->irg);
946 if (USE_SSE2(env->cg)) {
948 if (is_ia32_fConst(op2)) {
949 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
950 set_ia32_am_support(new_op, ia32_am_None);
951 set_ia32_Immop_attr(new_op, op2);
954 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
955 set_ia32_am_support(new_op, ia32_am_Source);
959 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
960 set_ia32_am_support(new_op, ia32_am_Source);
962 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
963 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
971 * Creates an ia32 Shl.
973 * @param env The transformation environment
974 * @param op1 The first operator
975 * @param op2 The second operator
976 * @return The created ia32 Shl node
978 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
979 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
985 * Creates an ia32 Shr.
987 * @param env The transformation environment
988 * @param op1 The first operator
989 * @param op2 The second operator
990 * @return The created ia32 Shr node
992 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
993 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
999 * Creates an ia32 Shrs.
1001 * @param env The transformation environment
1002 * @param op1 The first operator
1003 * @param op2 The second operator
1004 * @return The created ia32 Shrs node
1006 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1007 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
1013 * Creates an ia32 RotL.
1015 * @param env The transformation environment
1016 * @param op1 The first operator
1017 * @param op2 The second operator
1018 * @return The created ia32 RotL node
1020 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1021 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1027 * Creates an ia32 RotR.
1028 * NOTE: There is no RotR with immediate because this would always be a RotL
1029 * "imm-mode_size_bits" which can be pre-calculated.
1031 * @param env The transformation environment
1032 * @param op1 The first operator
1033 * @param op2 The second operator
1034 * @return The created ia32 RotR node
1036 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1037 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1043 * Creates an ia32 RotR or RotL (depending on the found pattern).
1045 * @param env The transformation environment
1046 * @param op1 The first operator
1047 * @param op2 The second operator
1048 * @return The created ia32 RotL or RotR node
1050 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1051 ir_node *rotate = NULL;
1053 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1054 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1055 that means we can create a RotR instead of an Add and a RotL */
1058 ir_node *pred = get_Proj_pred(op2);
1060 if (is_ia32_Add(pred)) {
1061 ir_node *pred_pred = get_irn_n(pred, 2);
1062 tarval *tv = get_ia32_Immop_tarval(pred);
1063 long bits = get_mode_size_bits(env->mode);
1065 if (is_Proj(pred_pred)) {
1066 pred_pred = get_Proj_pred(pred_pred);
1069 if (is_ia32_Minus(pred_pred) &&
1070 tarval_is_long(tv) &&
1071 get_tarval_long(tv) == bits)
1073 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1074 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1081 rotate = gen_RotL(env, op1, op2);
1090 * Transforms a Minus node.
1092 * @param env The transformation environment
1093 * @param op The operator
1094 * @return The created ia32 Minus node
1096 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1099 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1100 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1101 ir_node *nomem = new_rd_NoMem(env->irg);
1104 if (mode_is_float(env->mode)) {
1105 if (USE_SSE2(env->cg)) {
1106 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1108 size = get_mode_size_bits(env->mode);
1109 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1111 set_ia32_sc(new_op, name);
1113 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1115 set_ia32_res_mode(new_op, env->mode);
1116 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1118 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1121 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1122 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1126 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1135 * Transforms a Not node.
1137 * @param env The transformation environment
1138 * @param op The operator
1139 * @return The created ia32 Not node
1141 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1142 assert (! mode_is_float(env->mode));
1143 return gen_unop(env, op, new_rd_ia32_Not);
1149 * Transforms an Abs node.
1151 * @param env The transformation environment
1152 * @param op The operator
1153 * @return The created ia32 Abs node
1155 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1156 ir_node *res, *p_eax, *p_edx;
1157 dbg_info *dbg = env->dbg;
1158 ir_mode *mode = env->mode;
1159 ir_graph *irg = env->irg;
1160 ir_node *block = env->block;
1161 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1162 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1163 ir_node *nomem = new_NoMem();
1167 if (mode_is_float(mode)) {
1168 if (USE_SSE2(env->cg)) {
1169 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1171 size = get_mode_size_bits(mode);
1172 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1174 set_ia32_sc(res, name);
1176 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1178 set_ia32_res_mode(res, mode);
1179 set_ia32_immop_type(res, ia32_ImmSymConst);
1181 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1184 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1185 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1189 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1190 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1191 set_ia32_res_mode(res, mode);
1193 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1194 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1196 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1197 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1198 set_ia32_res_mode(res, mode);
1200 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1202 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1203 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1204 set_ia32_res_mode(res, mode);
1206 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1215 * Transforms a Load.
1217 * @param mod the debug module
1218 * @param block the block the new node should belong to
1219 * @param node the ir Load node
1220 * @param mode node mode
1221 * @return the created ia32 Load node
1223 static ir_node *gen_Load(ia32_transform_env_t *env) {
1224 ir_node *node = env->irn;
1225 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1226 ir_node *ptr = get_Load_ptr(node);
1227 ir_mode *mode = get_Load_mode(node);
1228 const char *offs = NULL;
1230 ia32_am_flavour_t am_flav = ia32_B;
1232 /* address might be a constant (symconst or absolute address) */
1233 if (is_ia32_Const(ptr)) {
1234 offs = get_ia32_cnst(ptr);
1238 if (mode_is_float(mode)) {
1239 if (USE_SSE2(env->cg))
1240 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
1242 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
1245 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
1248 /* base is an constant address */
1250 add_ia32_am_offs(new_op, offs);
1254 set_ia32_am_support(new_op, ia32_am_Source);
1255 set_ia32_op_type(new_op, ia32_AddrModeS);
1256 set_ia32_am_flavour(new_op, am_flav);
1257 set_ia32_ls_mode(new_op, mode);
1259 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1267 * Transforms a Store.
1269 * @param mod the debug module
1270 * @param block the block the new node should belong to
1271 * @param node the ir Store node
1272 * @param mode node mode
1273 * @return the created ia32 Store node
1275 static ir_node *gen_Store(ia32_transform_env_t *env) {
1276 ir_node *node = env->irn;
1277 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1278 ir_node *val = get_Store_value(node);
1279 ir_node *ptr = get_Store_ptr(node);
1280 ir_node *mem = get_Store_mem(node);
1281 ir_mode *mode = get_irn_mode(val);
1282 ir_node *sval = val;
1283 const char *offs = NULL;
1285 ia32_am_flavour_t am_flav = ia32_B;
1286 ia32_immop_type_t immop = ia32_ImmNone;
1288 /* in case of storing a const (but not a symconst) -> make it an attribute */
1289 if (is_ia32_Cnst(val)) {
1290 switch (get_ia32_op_type(val)) {
1292 immop = ia32_ImmConst;
1295 immop = ia32_ImmSymConst;
1298 assert(0 && "unsupported Const type");
1303 /* address might be a constant (symconst or absolute address) */
1304 if (is_ia32_Const(ptr)) {
1305 offs = get_ia32_cnst(ptr);
1309 if (mode_is_float(mode)) {
1310 if (USE_SSE2(env->cg))
1311 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1313 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1315 else if (get_mode_size_bits(mode) == 8) {
1316 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1319 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1322 /* stored const is an attribute (saves a register) */
1323 if (is_ia32_Cnst(val)) {
1324 set_ia32_Immop_attr(new_op, val);
1327 /* base is an constant address */
1329 add_ia32_am_offs(new_op, offs);
1333 set_ia32_am_support(new_op, ia32_am_Dest);
1334 set_ia32_op_type(new_op, ia32_AddrModeD);
1335 set_ia32_am_flavour(new_op, am_flav);
1336 set_ia32_ls_mode(new_op, get_irn_mode(val));
1337 set_ia32_immop_type(new_op, immop);
1339 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1347 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1349 * @param env The transformation environment
1350 * @return The transformed node.
1352 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1353 dbg_info *dbg = env->dbg;
1354 ir_graph *irg = env->irg;
1355 ir_node *block = env->block;
1356 ir_node *node = env->irn;
1357 ir_node *sel = get_Cond_selector(node);
1358 ir_mode *sel_mode = get_irn_mode(sel);
1359 ir_node *res = NULL;
1360 ir_node *pred = NULL;
1361 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1362 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1364 if (is_Proj(sel) && sel_mode == mode_b) {
1365 ir_node *nomem = new_NoMem();
1367 pred = get_Proj_pred(sel);
1369 /* get both compare operators */
1370 cmp_a = get_Cmp_left(pred);
1371 cmp_b = get_Cmp_right(pred);
1373 /* check if we can use a CondJmp with immediate */
1374 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1375 expr = get_expr_op(cmp_a, cmp_b);
1378 pn_Cmp pnc = get_Proj_proj(sel);
1380 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1381 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1382 /* a Cmp A =/!= 0 */
1383 ir_node *op1 = expr;
1384 ir_node *op2 = expr;
1385 ir_node *and = skip_Proj(expr);
1386 const char *cnst = NULL;
1388 /* check, if expr is an only once used And operation */
1389 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1390 op1 = get_irn_n(and, 2);
1391 op2 = get_irn_n(and, 3);
1393 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1395 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1396 set_ia32_pncode(res, get_Proj_proj(sel));
1397 set_ia32_res_mode(res, get_irn_mode(op1));
1400 copy_ia32_Immop_attr(res, and);
1403 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1408 if (mode_is_float(get_irn_mode(expr))) {
1409 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1412 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1414 set_ia32_Immop_attr(res, cnst);
1415 set_ia32_res_mode(res, get_irn_mode(expr));
1418 if (mode_is_float(get_irn_mode(cmp_a))) {
1419 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1422 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1424 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1427 set_ia32_pncode(res, get_Proj_proj(sel));
1428 set_ia32_am_support(res, ia32_am_Source);
1431 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1432 set_ia32_pncode(res, get_Cond_defaultProj(node));
1433 set_ia32_res_mode(res, get_irn_mode(sel));
1436 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1443 * Transforms a CopyB node.
1445 * @param env The transformation environment
1446 * @return The transformed node.
1448 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1449 ir_node *res = NULL;
1450 dbg_info *dbg = env->dbg;
1451 ir_graph *irg = env->irg;
1452 ir_mode *mode = env->mode;
1453 ir_node *block = env->block;
1454 ir_node *node = env->irn;
1455 ir_node *src = get_CopyB_src(node);
1456 ir_node *dst = get_CopyB_dst(node);
1457 ir_node *mem = get_CopyB_mem(node);
1458 int size = get_type_size_bytes(get_CopyB_type(node));
1461 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1462 /* then we need the size explicitly in ECX. */
1463 if (size >= 16 * 4) {
1464 rem = size & 0x3; /* size % 4 */
1467 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1468 set_ia32_op_type(res, ia32_Const);
1469 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1471 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1472 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1475 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1476 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1477 set_ia32_immop_type(res, ia32_ImmConst);
1480 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
1488 * Transforms a Mux node into CMov.
1490 * @param env The transformation environment
1491 * @return The transformed node.
1493 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1494 ir_node *node = env->irn;
1495 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1496 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1498 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1505 * Following conversion rules apply:
1509 * 1) n bit -> m bit n > m (downscale)
1510 * a) target is signed: movsx
1511 * b) target is unsigned: and with lower bits sets
1512 * 2) n bit -> m bit n == m (sign change)
1514 * 3) n bit -> m bit n < m (upscale)
1515 * a) source is signed: movsx
1516 * b) source is unsigned: and with lower bits sets
1520 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1524 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1525 * if target mode < 32bit: additional INT -> INT conversion (see above)
1529 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1530 * x87 is mode_E internally, conversions happen only at load and store
1531 * in non-strict semantic
1534 //static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1535 // ir_mode *src_mode, ir_mode *tgt_mode)
1537 // int n = get_mode_size_bits(src_mode);
1538 // int m = get_mode_size_bits(tgt_mode);
1539 // dbg_info *dbg = env->dbg;
1540 // ir_graph *irg = env->irg;
1541 // ir_node *block = env->block;
1542 // ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1543 // ir_node *nomem = new_rd_NoMem(irg);
1544 // ir_node *new_op, *proj;
1545 // assert(n > m && "downscale expected");
1546 // if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1547 // /* ASHL Sn, n - m */
1548 // new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1549 // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1550 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1551 // set_ia32_am_support(new_op, ia32_am_Source);
1552 // SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1553 // /* ASHR Sn, n - m */
1554 // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1555 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1558 // new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1559 // set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1565 * Transforms a Conv node.
1567 * @param env The transformation environment
1568 * @param op The operator
1569 * @return The created ia32 Conv node
1571 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1572 dbg_info *dbg = env->dbg;
1573 ir_graph *irg = env->irg;
1574 ir_mode *src_mode = get_irn_mode(op);
1575 ir_mode *tgt_mode = env->mode;
1576 int src_bits = get_mode_size_bits(src_mode);
1577 int tgt_bits = get_mode_size_bits(tgt_mode);
1578 ir_node *block = env->block;
1579 ir_node *new_op = NULL;
1580 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1581 ir_node *nomem = new_rd_NoMem(irg);
1582 firm_dbg_module_t *mod = env->mod;
1585 if (src_mode == tgt_mode) {
1586 /* this can happen when changing mode_P to mode_Is */
1587 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1588 edges_reroute(env->irn, op, irg);
1590 else if (mode_is_float(src_mode)) {
1591 /* we convert from float ... */
1592 if (mode_is_float(tgt_mode)) {
1594 if (USE_SSE2(env->cg)) {
1595 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1596 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1599 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1600 edges_reroute(env->irn, op, irg);
1605 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1606 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1607 /* if target mode is not int: add an additional downscale convert */
1608 if (tgt_bits < 32) {
1609 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1610 set_ia32_res_mode(new_op, tgt_mode);
1611 set_ia32_am_support(new_op, ia32_am_Source);
1613 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1615 if (tgt_bits == 8 || src_bits == 8) {
1616 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1619 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1625 /* we convert from int ... */
1626 if (mode_is_float(tgt_mode)) {
1628 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1629 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1633 if (get_mode_size_bits(src_mode) == tgt_bits) {
1634 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1635 edges_reroute(env->irn, op, irg);
1638 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1639 if (tgt_bits == 8 || src_bits == 8) {
1640 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1643 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1650 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1651 set_ia32_res_mode(new_op, tgt_mode);
1653 set_ia32_am_support(new_op, ia32_am_Source);
1655 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1663 /********************************************
1666 * | |__ ___ _ __ ___ __| | ___ ___
1667 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1668 * | |_) | __/ | | | (_) | (_| | __/\__ \
1669 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1671 ********************************************/
1673 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1674 ir_node *new_op = NULL;
1675 ir_node *node = env->irn;
1676 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1677 ir_node *mem = new_rd_NoMem(env->irg);
1678 ir_node *ptr = get_irn_n(node, 0);
1679 entity *ent = be_get_frame_entity(node);
1680 ir_mode *mode = env->mode;
1682 // /* If the StackParam has only one user -> */
1683 // /* put it in the Block where the user resides */
1684 // if (get_irn_n_edges(node) == 1) {
1685 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1688 if (mode_is_float(mode)) {
1689 if (USE_SSE2(env->cg))
1690 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1692 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1695 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1698 set_ia32_frame_ent(new_op, ent);
1699 set_ia32_use_frame(new_op);
1701 set_ia32_am_support(new_op, ia32_am_Source);
1702 set_ia32_op_type(new_op, ia32_AddrModeS);
1703 set_ia32_am_flavour(new_op, ia32_B);
1704 set_ia32_ls_mode(new_op, mode);
1706 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1708 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1712 * Transforms a FrameAddr into an ia32 Add.
1714 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1715 ir_node *new_op = NULL;
1716 ir_node *node = env->irn;
1717 ir_node *op = get_irn_n(node, 0);
1718 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1719 ir_node *nomem = new_rd_NoMem(env->irg);
1721 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1722 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1723 set_ia32_am_support(new_op, ia32_am_Full);
1724 set_ia32_use_frame(new_op);
1725 set_ia32_immop_type(new_op, ia32_ImmConst);
1727 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1729 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1733 * Transforms a FrameLoad into an ia32 Load.
1735 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1736 ir_node *new_op = NULL;
1737 ir_node *node = env->irn;
1738 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1739 ir_node *mem = get_irn_n(node, 0);
1740 ir_node *ptr = get_irn_n(node, 1);
1741 entity *ent = be_get_frame_entity(node);
1742 ir_mode *mode = get_type_mode(get_entity_type(ent));
1744 if (mode_is_float(mode)) {
1745 if (USE_SSE2(env->cg))
1746 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1748 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1751 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1754 set_ia32_frame_ent(new_op, ent);
1755 set_ia32_use_frame(new_op);
1757 set_ia32_am_support(new_op, ia32_am_Source);
1758 set_ia32_op_type(new_op, ia32_AddrModeS);
1759 set_ia32_am_flavour(new_op, ia32_B);
1760 set_ia32_ls_mode(new_op, mode);
1762 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1769 * Transforms a FrameStore into an ia32 Store.
1771 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1772 ir_node *new_op = NULL;
1773 ir_node *node = env->irn;
1774 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1775 ir_node *mem = get_irn_n(node, 0);
1776 ir_node *ptr = get_irn_n(node, 1);
1777 ir_node *val = get_irn_n(node, 2);
1778 entity *ent = be_get_frame_entity(node);
1779 ir_mode *mode = get_irn_mode(val);
1781 if (mode_is_float(mode)) {
1782 if (USE_SSE2(env->cg))
1783 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1785 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1787 else if (get_mode_size_bits(mode) == 8) {
1788 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1791 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1794 set_ia32_frame_ent(new_op, ent);
1795 set_ia32_use_frame(new_op);
1797 set_ia32_am_support(new_op, ia32_am_Dest);
1798 set_ia32_op_type(new_op, ia32_AddrModeD);
1799 set_ia32_am_flavour(new_op, ia32_B);
1800 set_ia32_ls_mode(new_op, mode);
1802 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
1809 /*********************************************************
1812 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1813 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1814 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1815 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1817 *********************************************************/
1820 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1821 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1823 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1824 ia32_transform_env_t tenv;
1825 ir_node *in1, *in2, *noreg, *nomem, *res;
1826 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1828 /* Return if AM node or not a Sub or fSub */
1829 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1832 noreg = ia32_new_NoReg_gp(cg);
1833 nomem = new_rd_NoMem(cg->irg);
1834 in1 = get_irn_n(irn, 2);
1835 in2 = get_irn_n(irn, 3);
1836 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1837 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1838 out_reg = get_ia32_out_reg(irn, 0);
1840 tenv.block = get_nodes_block(irn);
1841 tenv.dbg = get_irn_dbg_info(irn);
1845 tenv.mode = get_ia32_res_mode(irn);
1848 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1849 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1850 /* generate the neg src2 */
1851 res = gen_Minus(&tenv, in2);
1852 arch_set_irn_register(cg->arch_env, res, in2_reg);
1854 /* add to schedule */
1855 sched_add_before(irn, res);
1857 /* generate the add */
1858 if (mode_is_float(tenv.mode)) {
1859 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1860 set_ia32_am_support(res, ia32_am_Source);
1863 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1864 set_ia32_am_support(res, ia32_am_Full);
1867 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(&tenv));
1869 slots = get_ia32_slots(res);
1872 /* add to schedule */
1873 sched_add_before(irn, res);
1875 /* remove the old sub */
1878 /* exchange the add and the sub */
1884 * Transforms a LEA into an Add if possible
1885 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1887 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
1888 ia32_am_flavour_t am_flav;
1890 ir_node *res = NULL;
1891 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
1893 ia32_transform_env_t tenv;
1894 const arch_register_t *out_reg, *base_reg, *index_reg;
1897 if (! is_ia32_Lea(irn))
1900 am_flav = get_ia32_am_flavour(irn);
1902 /* only some LEAs can be transformed to an Add */
1903 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
1906 noreg = ia32_new_NoReg_gp(cg);
1907 nomem = new_rd_NoMem(cg->irg);
1910 base = get_irn_n(irn, 0);
1911 index = get_irn_n(irn,1);
1913 offs = get_ia32_am_offs(irn);
1915 /* offset has a explicit sign -> we need to skip + */
1916 if (offs && offs[0] == '+')
1919 out_reg = arch_get_irn_register(cg->arch_env, irn);
1920 base_reg = arch_get_irn_register(cg->arch_env, base);
1921 index_reg = arch_get_irn_register(cg->arch_env, index);
1923 tenv.block = get_nodes_block(irn);
1924 tenv.dbg = get_irn_dbg_info(irn);
1928 tenv.mode = get_irn_mode(irn);
1931 switch(get_ia32_am_flavour(irn)) {
1933 /* out register must be same as base register */
1934 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1940 /* out register must be same as base register */
1941 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1948 /* out register must be same as index register */
1949 if (! REGS_ARE_EQUAL(out_reg, index_reg))
1956 /* out register must be same as one in register */
1957 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
1961 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
1966 /* in registers a different from out -> no Add possible */
1973 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
1974 arch_set_irn_register(cg->arch_env, res, out_reg);
1975 set_ia32_op_type(res, ia32_Normal);
1978 set_ia32_cnst(res, offs);
1979 set_ia32_immop_type(res, ia32_ImmConst);
1982 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(&tenv));
1984 /* add Add to schedule */
1985 sched_add_before(irn, res);
1987 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
1989 /* add result Proj to schedule */
1990 sched_add_before(irn, res);
1992 /* remove the old LEA */
1995 /* exchange the Add and the LEA */
2000 * Transforms the given firm node (and maybe some other related nodes)
2001 * into one or more assembler nodes.
2003 * @param node the firm node
2004 * @param env the debug module
2006 void ia32_transform_node(ir_node *node, void *env) {
2007 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
2009 ir_node *asm_node = NULL;
2010 ia32_transform_env_t tenv;
2015 tenv.block = get_nodes_block(node);
2016 tenv.dbg = get_irn_dbg_info(node);
2017 tenv.irg = current_ir_graph;
2019 tenv.mod = cgenv->mod;
2020 tenv.mode = get_irn_mode(node);
2023 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
2024 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
2025 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
2026 #define IGN(a) case iro_##a: break
2027 #define BAD(a) case iro_##a: goto bad
2028 #define OTHER_BIN(a) \
2029 if (get_irn_op(node) == get_op_##a()) { \
2030 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
2034 if (be_is_##a(node)) { \
2035 asm_node = gen_##a(&tenv); \
2039 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
2041 code = get_irn_opcode(node);
2087 /* constant transformation happens earlier */
2117 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
2121 /* exchange nodes if a new one was generated */
2123 exchange(node, asm_node);
2124 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2127 DB((tenv.mod, LEVEL_1, "ignored\n"));