2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "archop.h" /* we need this for Min and Max nodes */
57 #include "../benode_t.h"
58 #include "../besched.h"
60 #include "../beutil.h"
61 #include "../beirg_t.h"
63 #include "bearch_ia32_t.h"
64 #include "ia32_nodes_attr.h"
65 #include "ia32_transform.h"
66 #include "ia32_new_nodes.h"
67 #include "ia32_map_regs.h"
68 #include "ia32_dbg_stat.h"
69 #include "ia32_optimize.h"
70 #include "ia32_util.h"
72 #include "gen_ia32_regalloc_if.h"
74 #define SFP_SIGN "0x80000000"
75 #define DFP_SIGN "0x8000000000000000"
76 #define SFP_ABS "0x7FFFFFFF"
77 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 typedef struct ia32_transform_env_t {
95 ir_graph *irg; /**< The irg, the node should be created in */
96 ia32_code_gen_t *cg; /**< The code generator */
97 int visited; /**< visited count that indicates whether a
98 node is already transformed */
99 pdeq *worklist; /**< worklist of nodes that still need to be
101 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
102 } ia32_transform_env_t;
104 extern ir_op *get_op_Mulh(void);
106 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
108 ir_node *op2, ir_node *mem);
110 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
114 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
116 /****************************************************************************************************
118 * | | | | / _| | | (_)
119 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
120 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
121 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
122 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
124 ****************************************************************************************************/
126 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
127 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
128 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
131 static INLINE int mode_needs_gp_reg(ir_mode *mode)
133 if(mode == mode_fpcw)
136 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
139 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
141 set_irn_link(old_node, new_node);
144 static INLINE ir_node *get_new_node(ir_node *old_node)
146 assert(irn_visited(old_node));
147 return (ir_node*) get_irn_link(old_node);
151 * Returns 1 if irn is a Const representing 0, 0 otherwise
153 static INLINE int is_ia32_Const_0(ir_node *irn) {
154 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
155 && tarval_is_null(get_ia32_Immop_tarval(irn));
159 * Returns 1 if irn is a Const representing 1, 0 otherwise
161 static INLINE int is_ia32_Const_1(ir_node *irn) {
162 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
163 && tarval_is_one(get_ia32_Immop_tarval(irn));
167 * Collects all Projs of a node into the node array. Index is the projnum.
168 * BEWARE: The caller has to assure the appropriate array size!
170 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
171 const ir_edge_t *edge;
172 assert(get_irn_mode(irn) == mode_T && "need mode_T");
174 memset(projs, 0, size * sizeof(projs[0]));
176 foreach_out_edge(irn, edge) {
177 ir_node *proj = get_edge_src_irn(edge);
178 int proj_proj = get_Proj_proj(proj);
179 assert(proj_proj < size);
180 projs[proj_proj] = proj;
185 * Renumbers the proj having pn_old in the array tp pn_new
186 * and removes the proj from the array.
188 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
189 fprintf(stderr, "Warning: renumber_Proj used!\n");
191 set_Proj_proj(projs[pn_old], pn_new);
192 projs[pn_old] = NULL;
197 * creates a unique ident by adding a number to a tag
199 * @param tag the tag string, must contain a %d if a number
202 static ident *unique_id(const char *tag)
204 static unsigned id = 0;
207 snprintf(str, sizeof(str), tag, ++id);
208 return new_id_from_str(str);
212 * Get a primitive type for a mode.
214 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
216 pmap_entry *e = pmap_find(types, mode);
221 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
222 res = new_type_primitive(new_id_from_str(buf), mode);
223 pmap_insert(types, mode, res);
231 * Get an entity that is initialized with a tarval
233 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
235 tarval *tv = get_Const_tarval(cnst);
236 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
241 ir_mode *mode = get_irn_mode(cnst);
242 ir_type *tp = get_Const_type(cnst);
243 if (tp == firm_unknown_type)
244 tp = get_prim_type(cg->isa->types, mode);
246 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
248 set_entity_ld_ident(res, get_entity_ident(res));
249 set_entity_visibility(res, visibility_local);
250 set_entity_variability(res, variability_constant);
251 set_entity_allocation(res, allocation_static);
253 /* we create a new entity here: It's initialization must resist on the
255 rem = current_ir_graph;
256 current_ir_graph = get_const_code_irg();
257 set_atomic_ent_value(res, new_Const_type(tv, tp));
258 current_ir_graph = rem;
260 pmap_insert(cg->isa->tv_ent, tv, res);
269 * Transforms a Const.
271 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
272 ir_graph *irg = env->irg;
273 ir_node *block = transform_node(env, get_nodes_block(node));
274 dbg_info *dbgi = get_irn_dbg_info(node);
275 ir_mode *mode = get_irn_mode(node);
277 if (mode_is_float(mode)) {
279 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
280 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env->cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env->cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
298 set_ia32_am_support(load, ia32_am_Source);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env->cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_am_support(load, ia32_am_Source);
310 set_ia32_op_type(load, ia32_AddrModeS);
311 set_ia32_am_flavour(load, ia32_am_N);
312 set_ia32_am_sc(load, floatent);
313 set_ia32_ls_mode(load, mode);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(load, get_irg_frame(irg));
327 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
330 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
333 if (get_irg_start_block(irg) == block) {
334 add_irn_dep(cnst, get_irg_frame(irg));
337 set_ia32_Const_attr(cnst, node);
338 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
343 return new_r_Bad(irg);
347 * Transforms a SymConst.
349 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
350 ir_graph *irg = env->irg;
351 ir_node *block = transform_node(env, get_nodes_block(node));
352 dbg_info *dbgi = get_irn_dbg_info(node);
353 ir_mode *mode = get_irn_mode(node);
356 if (mode_is_float(mode)) {
358 if (USE_SSE2(env->cg))
359 cnst = new_rd_ia32_xConst(dbgi, irg, block);
361 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
362 set_ia32_ls_mode(cnst, mode);
364 cnst = new_rd_ia32_Const(dbgi, irg, block);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 set_ia32_Const_attr(cnst, node);
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
381 * SSE convert of an integer node into a floating point node.
383 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
384 ir_graph *irg, ir_node *block,
385 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
387 ir_node *noreg = ia32_new_NoReg_gp(cg);
388 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *old_pred = get_Cmp_left(old_node);
390 ir_mode *in_mode = get_irn_mode(old_pred);
391 int in_bits = get_mode_size_bits(in_mode);
392 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
394 set_ia32_ls_mode(conv, tgt_mode);
396 set_ia32_am_support(conv, ia32_am_Source);
398 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
404 * SSE convert of an float node into a double node.
406 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
407 ir_graph *irg, ir_node *block,
408 ir_node *in, ir_node *old_node)
410 ir_node *noreg = ia32_new_NoReg_gp(cg);
411 ir_node *nomem = new_rd_NoMem(irg);
412 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
414 set_ia32_am_support(conv, ia32_am_Source);
415 set_ia32_ls_mode(conv, mode_xmm);
416 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
421 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
422 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
423 static const struct {
425 const char *ent_name;
426 const char *cnst_str;
427 } names [ia32_known_const_max] = {
428 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
429 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
430 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
431 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
433 static ir_entity *ent_cache[ia32_known_const_max];
435 const char *tp_name, *ent_name, *cnst_str;
443 ent_name = names[kct].ent_name;
444 if (! ent_cache[kct]) {
445 tp_name = names[kct].tp_name;
446 cnst_str = names[kct].cnst_str;
448 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
450 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
451 tp = new_type_primitive(new_id_from_str(tp_name), mode);
452 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
454 set_entity_ld_ident(ent, get_entity_ident(ent));
455 set_entity_visibility(ent, visibility_local);
456 set_entity_variability(ent, variability_constant);
457 set_entity_allocation(ent, allocation_static);
459 /* we create a new entity here: It's initialization must resist on the
461 rem = current_ir_graph;
462 current_ir_graph = get_const_code_irg();
463 cnst = new_Const(mode, tv);
464 current_ir_graph = rem;
466 set_atomic_ent_value(ent, cnst);
468 /* cache the entry */
469 ent_cache[kct] = ent;
472 return ent_cache[kct];
477 * Prints the old node name on cg obst and returns a pointer to it.
479 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
480 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
482 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
483 obstack_1grow(isa->name_obst, 0);
484 return obstack_finish(isa->name_obst);
488 /* determine if one operator is an Imm */
489 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
491 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
493 return is_ia32_Cnst(op2) ? op2 : NULL;
497 /* determine if one operator is not an Imm */
498 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
499 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
502 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
506 if (! (env->cg->opt & IA32_OPT_IMMOPS))
509 left = get_irn_n(node, in1);
510 right = get_irn_n(node, in2);
511 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
512 /* we can only set right operand to immediate */
513 if(!is_ia32_commutative(node))
515 /* exchange left/right */
516 set_irn_n(node, in1, right);
517 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
518 copy_ia32_Immop_attr(node, left);
519 } else if(is_ia32_Cnst(right)) {
520 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
521 copy_ia32_Immop_attr(node, right);
526 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param env The transformation environment
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
539 ir_node *op1, ir_node *op2,
540 construct_binop_func *func)
542 ir_node *block = transform_node(env, get_nodes_block(node));
543 ir_node *new_op1 = transform_node(env, op1);
544 ir_node *new_op2 = transform_node(env, op2);
545 ir_node *new_node = NULL;
546 ir_graph *irg = env->irg;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
549 ir_node *nomem = new_NoMem();
551 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
552 if (func == new_rd_ia32_IMul) {
553 set_ia32_am_support(new_node, ia32_am_Source);
555 set_ia32_am_support(new_node, ia32_am_Full);
558 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
559 if (is_op_commutative(get_irn_op(node))) {
560 set_ia32_commutative(new_node);
562 fold_immediate(env, new_node, 2, 3);
568 * Construct a standard binary operation, set AM and immediate if required.
570 * @param env The transformation environment
571 * @param op1 The first operand
572 * @param op2 The second operand
573 * @param func The node constructor function
574 * @return The constructed ia32 node.
576 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
577 ir_node *op1, ir_node *op2,
578 construct_binop_func *func)
580 ir_node *block = transform_node(env, get_nodes_block(node));
581 ir_node *new_op1 = transform_node(env, op1);
582 ir_node *new_op2 = transform_node(env, op2);
583 ir_node *new_node = NULL;
584 dbg_info *dbgi = get_irn_dbg_info(node);
585 ir_graph *irg = env->irg;
586 ir_mode *mode = get_irn_mode(node);
587 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
588 ir_node *nomem = new_NoMem();
590 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
591 set_ia32_am_support(new_node, ia32_am_Source);
592 if (is_op_commutative(get_irn_op(node))) {
593 set_ia32_commutative(new_node);
595 if (USE_SSE2(env->cg)) {
596 set_ia32_ls_mode(new_node, mode);
599 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
606 * Construct a shift/rotate binary operation, sets AM and immediate if required.
608 * @param env The transformation environment
609 * @param op1 The first operand
610 * @param op2 The second operand
611 * @param func The node constructor function
612 * @return The constructed ia32 node.
614 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
615 ir_node *op1, ir_node *op2,
616 construct_binop_func *func)
618 ir_node *block = transform_node(env, get_nodes_block(node));
619 ir_node *new_op1 = transform_node(env, op1);
620 ir_node *new_op2 = transform_node(env, op2);
621 ir_node *new_op = NULL;
622 dbg_info *dbgi = get_irn_dbg_info(node);
623 ir_graph *irg = env->irg;
624 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
625 ir_node *nomem = new_NoMem();
630 assert(! mode_is_float(get_irn_mode(node))
631 && "Shift/Rotate with float not supported");
633 /* Check if immediate optimization is on and */
634 /* if it's an operation with immediate. */
635 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
636 expr_op = get_expr_op(new_op1, new_op2);
638 assert((expr_op || imm_op) && "invalid operands");
641 /* We have two consts here: not yet supported */
645 /* Limit imm_op within range imm8 */
647 tv = get_ia32_Immop_tarval(imm_op);
650 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
651 set_ia32_Immop_tarval(imm_op, tv);
658 /* integer operations */
660 /* This is shift/rot with const */
661 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
663 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
664 copy_ia32_Immop_attr(new_op, imm_op);
666 /* This is a normal shift/rot */
667 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
668 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
672 set_ia32_am_support(new_op, ia32_am_Dest);
674 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
676 set_ia32_emit_cl(new_op);
683 * Construct a standard unary operation, set AM and immediate if required.
685 * @param env The transformation environment
686 * @param op The operand
687 * @param func The node constructor function
688 * @return The constructed ia32 node.
690 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
691 construct_unop_func *func)
693 ir_node *block = transform_node(env, get_nodes_block(node));
694 ir_node *new_op = transform_node(env, op);
695 ir_node *new_node = NULL;
696 ir_graph *irg = env->irg;
697 dbg_info *dbgi = get_irn_dbg_info(node);
698 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
699 ir_node *nomem = new_NoMem();
701 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
702 DB((dbg, LEVEL_1, "INT unop ..."));
703 set_ia32_am_support(new_node, ia32_am_Dest);
705 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
712 * Creates an ia32 Add.
714 * @param env The transformation environment
715 * @return the created ia32 Add node
717 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
718 ir_node *block = transform_node(env, get_nodes_block(node));
719 ir_node *op1 = get_Add_left(node);
720 ir_node *new_op1 = transform_node(env, op1);
721 ir_node *op2 = get_Add_right(node);
722 ir_node *new_op2 = transform_node(env, op2);
723 ir_node *new_op = NULL;
724 ir_graph *irg = env->irg;
725 dbg_info *dbgi = get_irn_dbg_info(node);
726 ir_mode *mode = get_irn_mode(node);
727 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
728 ir_node *nomem = new_NoMem();
729 ir_node *expr_op, *imm_op;
731 /* Check if immediate optimization is on and */
732 /* if it's an operation with immediate. */
733 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
734 expr_op = get_expr_op(new_op1, new_op2);
736 assert((expr_op || imm_op) && "invalid operands");
738 if (mode_is_float(mode)) {
740 if (USE_SSE2(env->cg))
741 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
743 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
748 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
749 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
751 /* No expr_op means, that we have two const - one symconst and */
752 /* one tarval or another symconst - because this case is not */
753 /* covered by constant folding */
754 /* We need to check for: */
755 /* 1) symconst + const -> becomes a LEA */
756 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
757 /* linker doesn't support two symconsts */
759 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
760 /* this is the 2nd case */
761 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
762 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
763 set_ia32_am_flavour(new_op, ia32_am_OB);
764 set_ia32_am_support(new_op, ia32_am_Source);
765 set_ia32_op_type(new_op, ia32_AddrModeS);
767 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
768 } else if (tp1 == ia32_ImmSymConst) {
769 tarval *tv = get_ia32_Immop_tarval(new_op2);
770 long offs = get_tarval_long(tv);
772 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
773 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
775 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
776 add_ia32_am_offs_int(new_op, offs);
777 set_ia32_am_flavour(new_op, ia32_am_O);
778 set_ia32_am_support(new_op, ia32_am_Source);
779 set_ia32_op_type(new_op, ia32_AddrModeS);
780 } else if (tp2 == ia32_ImmSymConst) {
781 tarval *tv = get_ia32_Immop_tarval(new_op1);
782 long offs = get_tarval_long(tv);
784 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
785 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
787 add_ia32_am_offs_int(new_op, offs);
788 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
789 set_ia32_am_flavour(new_op, ia32_am_O);
790 set_ia32_am_support(new_op, ia32_am_Source);
791 set_ia32_op_type(new_op, ia32_AddrModeS);
793 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
794 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
795 tarval *restv = tarval_add(tv1, tv2);
797 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
799 new_op = new_rd_ia32_Const(dbgi, irg, block);
800 set_ia32_Const_tarval(new_op, restv);
801 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
804 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
807 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
808 tarval_classification_t class_tv, class_negtv;
809 tarval *tv = get_ia32_Immop_tarval(imm_op);
811 /* optimize tarvals */
812 class_tv = classify_tarval(tv);
813 class_negtv = classify_tarval(tarval_neg(tv));
815 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
816 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
817 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
818 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
820 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
821 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
822 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
823 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
829 /* This is a normal add */
830 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
833 set_ia32_am_support(new_op, ia32_am_Full);
834 set_ia32_commutative(new_op);
836 fold_immediate(env, new_op, 2, 3);
838 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
844 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
845 ir_graph *irg = env->irg;
846 dbg_info *dbgi = get_irn_dbg_info(node);
847 ir_node *block = transform_node(env, get_nodes_block(node));
848 ir_node *op1 = get_Mul_left(node);
849 ir_node *op2 = get_Mul_right(node);
850 ir_node *new_op1 = transform_node(env, op1);
851 ir_node *new_op2 = transform_node(env, op2);
852 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
853 ir_node *proj_EAX, *proj_EDX, *res;
856 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source);
860 /* imediates are not supported, so no fold_immediate */
861 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
862 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
866 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
874 * Creates an ia32 Mul.
876 * @param env The transformation environment
877 * @return the created ia32 Mul node
879 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
880 ir_node *op1 = get_Mul_left(node);
881 ir_node *op2 = get_Mul_right(node);
882 ir_mode *mode = get_irn_mode(node);
884 if (mode_is_float(mode)) {
886 if (USE_SSE2(env->cg))
887 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
889 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
893 for the lower 32bit of the result it doesn't matter whether we use
894 signed or unsigned multiplication so we use IMul as it has fewer
897 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
901 * Creates an ia32 Mulh.
902 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
903 * this result while Mul returns the lower 32 bit.
905 * @param env The transformation environment
906 * @return the created ia32 Mulh node
908 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
909 ir_node *block = transform_node(env, get_nodes_block(node));
910 ir_node *op1 = get_irn_n(node, 0);
911 ir_node *new_op1 = transform_node(env, op1);
912 ir_node *op2 = get_irn_n(node, 1);
913 ir_node *new_op2 = transform_node(env, op2);
914 ir_graph *irg = env->irg;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
917 ir_mode *mode = get_irn_mode(node);
918 ir_node *proj_EAX, *proj_EDX, *res;
921 assert(!mode_is_float(mode) && "Mulh with float not supported");
922 if (mode_is_signed(mode)) {
923 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
925 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
928 set_ia32_commutative(res);
929 set_ia32_am_support(res, ia32_am_Source);
931 set_ia32_am_support(res, ia32_am_Source);
933 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
934 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
938 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
946 * Creates an ia32 And.
948 * @param env The transformation environment
949 * @return The created ia32 And node
951 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
952 ir_node *op1 = get_And_left(node);
953 ir_node *op2 = get_And_right(node);
955 assert (! mode_is_float(get_irn_mode(node)));
956 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
962 * Creates an ia32 Or.
964 * @param env The transformation environment
965 * @return The created ia32 Or node
967 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
968 ir_node *op1 = get_Or_left(node);
969 ir_node *op2 = get_Or_right(node);
971 assert (! mode_is_float(get_irn_mode(node)));
972 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
978 * Creates an ia32 Eor.
980 * @param env The transformation environment
981 * @return The created ia32 Eor node
983 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
984 ir_node *op1 = get_Eor_left(node);
985 ir_node *op2 = get_Eor_right(node);
987 assert(! mode_is_float(get_irn_mode(node)));
988 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
994 * Creates an ia32 Max.
996 * @param env The transformation environment
997 * @return the created ia32 Max node
999 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
1000 ir_node *block = transform_node(env, get_nodes_block(node));
1001 ir_node *op1 = get_irn_n(node, 0);
1002 ir_node *new_op1 = transform_node(env, op1);
1003 ir_node *op2 = get_irn_n(node, 1);
1004 ir_node *new_op2 = transform_node(env, op2);
1005 ir_graph *irg = env->irg;
1006 ir_mode *mode = get_irn_mode(node);
1007 dbg_info *dbgi = get_irn_dbg_info(node);
1008 ir_mode *op_mode = get_irn_mode(op1);
1011 assert(get_mode_size_bits(mode) == 32);
1013 if (mode_is_float(mode)) {
1015 if (USE_SSE2(env->cg)) {
1016 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1018 panic("Can't create Max node");
1021 long pnc = pn_Cmp_Gt;
1022 if (! mode_is_signed(op_mode)) {
1023 pnc |= ia32_pn_Cmp_Unsigned;
1025 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1026 set_ia32_pncode(new_op, pnc);
1027 set_ia32_am_support(new_op, ia32_am_None);
1029 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1035 * Creates an ia32 Min.
1037 * @param env The transformation environment
1038 * @return the created ia32 Min node
1040 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1041 ir_node *block = transform_node(env, get_nodes_block(node));
1042 ir_node *op1 = get_irn_n(node, 0);
1043 ir_node *new_op1 = transform_node(env, op1);
1044 ir_node *op2 = get_irn_n(node, 1);
1045 ir_node *new_op2 = transform_node(env, op2);
1046 ir_graph *irg = env->irg;
1047 ir_mode *mode = get_irn_mode(node);
1048 dbg_info *dbgi = get_irn_dbg_info(node);
1049 ir_mode *op_mode = get_irn_mode(op1);
1052 assert(get_mode_size_bits(mode) == 32);
1054 if (mode_is_float(mode)) {
1056 if (USE_SSE2(env->cg)) {
1057 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1059 panic("can't create Min node");
1062 long pnc = pn_Cmp_Lt;
1063 if (! mode_is_signed(op_mode)) {
1064 pnc |= ia32_pn_Cmp_Unsigned;
1066 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1067 set_ia32_pncode(new_op, pnc);
1068 set_ia32_am_support(new_op, ia32_am_None);
1070 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1077 * Creates an ia32 Sub.
1079 * @param env The transformation environment
1080 * @return The created ia32 Sub node
1082 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1083 ir_node *block = transform_node(env, get_nodes_block(node));
1084 ir_node *op1 = get_Sub_left(node);
1085 ir_node *new_op1 = transform_node(env, op1);
1086 ir_node *op2 = get_Sub_right(node);
1087 ir_node *new_op2 = transform_node(env, op2);
1088 ir_node *new_op = NULL;
1089 ir_graph *irg = env->irg;
1090 dbg_info *dbgi = get_irn_dbg_info(node);
1091 ir_mode *mode = get_irn_mode(node);
1092 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1093 ir_node *nomem = new_NoMem();
1094 ir_node *expr_op, *imm_op;
1096 /* Check if immediate optimization is on and */
1097 /* if it's an operation with immediate. */
1098 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1099 expr_op = get_expr_op(new_op1, new_op2);
1101 assert((expr_op || imm_op) && "invalid operands");
1103 if (mode_is_float(mode)) {
1105 if (USE_SSE2(env->cg))
1106 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1108 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1113 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1114 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1116 /* No expr_op means, that we have two const - one symconst and */
1117 /* one tarval or another symconst - because this case is not */
1118 /* covered by constant folding */
1119 /* We need to check for: */
1120 /* 1) symconst - const -> becomes a LEA */
1121 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1122 /* linker doesn't support two symconsts */
1123 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1124 /* this is the 2nd case */
1125 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1126 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1127 set_ia32_am_sc_sign(new_op);
1128 set_ia32_am_flavour(new_op, ia32_am_OB);
1130 DBG_OPT_LEA3(op1, op2, node, new_op);
1131 } else if (tp1 == ia32_ImmSymConst) {
1132 tarval *tv = get_ia32_Immop_tarval(new_op2);
1133 long offs = get_tarval_long(tv);
1135 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1136 DBG_OPT_LEA3(op1, op2, node, new_op);
1138 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1139 add_ia32_am_offs_int(new_op, -offs);
1140 set_ia32_am_flavour(new_op, ia32_am_O);
1141 set_ia32_am_support(new_op, ia32_am_Source);
1142 set_ia32_op_type(new_op, ia32_AddrModeS);
1143 } else if (tp2 == ia32_ImmSymConst) {
1144 tarval *tv = get_ia32_Immop_tarval(new_op1);
1145 long offs = get_tarval_long(tv);
1147 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1148 DBG_OPT_LEA3(op1, op2, node, new_op);
1150 add_ia32_am_offs_int(new_op, offs);
1151 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1152 set_ia32_am_sc_sign(new_op);
1153 set_ia32_am_flavour(new_op, ia32_am_O);
1154 set_ia32_am_support(new_op, ia32_am_Source);
1155 set_ia32_op_type(new_op, ia32_AddrModeS);
1157 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1158 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1159 tarval *restv = tarval_sub(tv1, tv2);
1161 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1163 new_op = new_rd_ia32_Const(dbgi, irg, block);
1164 set_ia32_Const_tarval(new_op, restv);
1165 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1168 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1170 } else if (imm_op) {
1171 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1172 tarval_classification_t class_tv, class_negtv;
1173 tarval *tv = get_ia32_Immop_tarval(imm_op);
1175 /* optimize tarvals */
1176 class_tv = classify_tarval(tv);
1177 class_negtv = classify_tarval(tarval_neg(tv));
1179 if (class_tv == TV_CLASSIFY_ONE) {
1180 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1181 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1182 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1184 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1185 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1186 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1187 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1193 /* This is a normal sub */
1194 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1196 /* set AM support */
1197 set_ia32_am_support(new_op, ia32_am_Full);
1199 fold_immediate(env, new_op, 2, 3);
1201 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1209 * Generates an ia32 DivMod with additional infrastructure for the
1210 * register allocator if needed.
1212 * @param env The transformation environment
1213 * @param dividend -no comment- :)
1214 * @param divisor -no comment- :)
1215 * @param dm_flav flavour_Div/Mod/DivMod
1216 * @return The created ia32 DivMod node
1218 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1219 ir_node *dividend, ir_node *divisor,
1220 ia32_op_flavour_t dm_flav)
1222 ir_node *block = transform_node(env, get_nodes_block(node));
1223 ir_node *new_dividend = transform_node(env, dividend);
1224 ir_node *new_divisor = transform_node(env, divisor);
1225 ir_graph *irg = env->irg;
1226 dbg_info *dbgi = get_irn_dbg_info(node);
1227 ir_mode *mode = get_irn_mode(node);
1228 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1229 ir_node *res, *proj_div, *proj_mod;
1230 ir_node *edx_node, *cltd;
1231 ir_node *in_keep[2];
1232 ir_node *mem, *new_mem;
1233 ir_node *projs[pn_DivMod_max];
1236 ia32_collect_Projs(node, projs, pn_DivMod_max);
1242 mem = get_Div_mem(node);
1243 mode = get_Div_resmode(node);
1244 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1247 mem = get_Mod_mem(node);
1248 mode = get_Mod_resmode(node);
1249 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1251 case flavour_DivMod:
1252 mem = get_DivMod_mem(node);
1253 mode = get_DivMod_resmode(node);
1254 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1255 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1258 panic("invalid divmod flavour!");
1260 new_mem = transform_node(env, mem);
1262 if (mode_is_signed(mode)) {
1263 /* in signed mode, we need to sign extend the dividend */
1264 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1265 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1266 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1268 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1269 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1270 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1273 if (mode_is_signed(mode)) {
1274 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1276 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1279 /* Matze: code can't handle this at the moment... */
1281 /* set AM support */
1282 set_ia32_am_support(res, ia32_am_Source);
1285 set_ia32_n_res(res, 2);
1287 /* check, which Proj-Keep, we need to add */
1289 if (proj_div == NULL) {
1290 /* We have only mod result: add div res Proj-Keep */
1291 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1294 if (proj_mod == NULL) {
1295 /* We have only div result: add mod res Proj-Keep */
1296 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1300 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1302 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1309 * Wrapper for generate_DivMod. Sets flavour_Mod.
1311 * @param env The transformation environment
1313 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1314 return generate_DivMod(env, node, get_Mod_left(node),
1315 get_Mod_right(node), flavour_Mod);
1319 * Wrapper for generate_DivMod. Sets flavour_Div.
1321 * @param env The transformation environment
1323 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1324 return generate_DivMod(env, node, get_Div_left(node),
1325 get_Div_right(node), flavour_Div);
1329 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1331 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1332 return generate_DivMod(env, node, get_DivMod_left(node),
1333 get_DivMod_right(node), flavour_DivMod);
1339 * Creates an ia32 floating Div.
1341 * @param env The transformation environment
1342 * @return The created ia32 xDiv node
1344 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1345 ir_node *block = transform_node(env, get_nodes_block(node));
1346 ir_node *op1 = get_Quot_left(node);
1347 ir_node *new_op1 = transform_node(env, op1);
1348 ir_node *op2 = get_Quot_right(node);
1349 ir_node *new_op2 = transform_node(env, op2);
1350 ir_graph *irg = env->irg;
1351 dbg_info *dbgi = get_irn_dbg_info(node);
1352 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1353 ir_node *nomem = new_rd_NoMem(env->irg);
1357 if (USE_SSE2(env->cg)) {
1358 ir_mode *mode = get_irn_mode(op1);
1359 if (is_ia32_xConst(new_op2)) {
1360 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1361 set_ia32_am_support(new_op, ia32_am_None);
1362 copy_ia32_Immop_attr(new_op, new_op2);
1364 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1365 // Matze: disabled for now, spillslot coalescer fails
1366 //set_ia32_am_support(new_op, ia32_am_Source);
1368 set_ia32_ls_mode(new_op, mode);
1370 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1371 // Matze: disabled for now (spillslot coalescer fails)
1372 //set_ia32_am_support(new_op, ia32_am_Source);
1374 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1380 * Creates an ia32 Shl.
1382 * @param env The transformation environment
1383 * @return The created ia32 Shl node
1385 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1386 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1393 * Creates an ia32 Shr.
1395 * @param env The transformation environment
1396 * @return The created ia32 Shr node
1398 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1399 return gen_shift_binop(env, node, get_Shr_left(node),
1400 get_Shr_right(node), new_rd_ia32_Shr);
1406 * Creates an ia32 Sar.
1408 * @param env The transformation environment
1409 * @return The created ia32 Shrs node
1411 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1412 return gen_shift_binop(env, node, get_Shrs_left(node),
1413 get_Shrs_right(node), new_rd_ia32_Sar);
1419 * Creates an ia32 RotL.
1421 * @param env The transformation environment
1422 * @param op1 The first operator
1423 * @param op2 The second operator
1424 * @return The created ia32 RotL node
1426 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1427 ir_node *op1, ir_node *op2) {
1428 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1434 * Creates an ia32 RotR.
1435 * NOTE: There is no RotR with immediate because this would always be a RotL
1436 * "imm-mode_size_bits" which can be pre-calculated.
1438 * @param env The transformation environment
1439 * @param op1 The first operator
1440 * @param op2 The second operator
1441 * @return The created ia32 RotR node
1443 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1445 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1451 * Creates an ia32 RotR or RotL (depending on the found pattern).
1453 * @param env The transformation environment
1454 * @return The created ia32 RotL or RotR node
1456 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1457 ir_node *rotate = NULL;
1458 ir_node *op1 = get_Rot_left(node);
1459 ir_node *op2 = get_Rot_right(node);
1461 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1462 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1463 that means we can create a RotR instead of an Add and a RotL */
1465 if (get_irn_op(op2) == op_Add) {
1467 ir_node *left = get_Add_left(add);
1468 ir_node *right = get_Add_right(add);
1469 if (is_Const(right)) {
1470 tarval *tv = get_Const_tarval(right);
1471 ir_mode *mode = get_irn_mode(node);
1472 long bits = get_mode_size_bits(mode);
1474 if (get_irn_op(left) == op_Minus &&
1475 tarval_is_long(tv) &&
1476 get_tarval_long(tv) == bits)
1478 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1479 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1484 if (rotate == NULL) {
1485 rotate = gen_RotL(env, node, op1, op2);
1494 * Transforms a Minus node.
1496 * @param env The transformation environment
1497 * @param op The Minus operand
1498 * @return The created ia32 Minus node
1500 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1501 ir_node *block = transform_node(env, get_nodes_block(node));
1502 ir_graph *irg = env->irg;
1503 dbg_info *dbgi = get_irn_dbg_info(node);
1504 ir_mode *mode = get_irn_mode(node);
1509 if (mode_is_float(mode)) {
1510 ir_node *new_op = transform_node(env, op);
1512 if (USE_SSE2(env->cg)) {
1513 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1514 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1515 ir_node *nomem = new_rd_NoMem(irg);
1517 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1519 size = get_mode_size_bits(mode);
1520 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1522 set_ia32_am_sc(res, ent);
1523 set_ia32_op_type(res, ia32_AddrModeS);
1524 set_ia32_ls_mode(res, mode);
1526 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1529 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1532 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1538 * Transforms a Minus node.
1540 * @param env The transformation environment
1541 * @return The created ia32 Minus node
1543 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1544 return gen_Minus_ex(env, node, get_Minus_op(node));
1549 * Transforms a Not node.
1551 * @param env The transformation environment
1552 * @return The created ia32 Not node
1554 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1555 ir_node *op = get_Not_op(node);
1557 assert (! mode_is_float(get_irn_mode(node)));
1558 return gen_unop(env, node, op, new_rd_ia32_Not);
1564 * Transforms an Abs node.
1566 * @param env The transformation environment
1567 * @return The created ia32 Abs node
1569 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1570 ir_node *block = transform_node(env, get_nodes_block(node));
1571 ir_node *op = get_Abs_op(node);
1572 ir_node *new_op = transform_node(env, op);
1573 ir_graph *irg = env->irg;
1574 dbg_info *dbgi = get_irn_dbg_info(node);
1575 ir_mode *mode = get_irn_mode(node);
1576 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1577 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1578 ir_node *nomem = new_NoMem();
1579 ir_node *res, *p_eax, *p_edx;
1583 if (mode_is_float(mode)) {
1585 if (USE_SSE2(env->cg)) {
1586 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1588 size = get_mode_size_bits(mode);
1589 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1591 set_ia32_am_sc(res, ent);
1593 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1595 set_ia32_op_type(res, ia32_AddrModeS);
1596 set_ia32_ls_mode(res, mode);
1599 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1600 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1604 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1605 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1607 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1608 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1610 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1613 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1614 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1623 * Transforms a Load.
1625 * @param env The transformation environment
1626 * @return the created ia32 Load node
1628 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1629 ir_node *block = transform_node(env, get_nodes_block(node));
1630 ir_node *ptr = get_Load_ptr(node);
1631 ir_node *new_ptr = transform_node(env, ptr);
1632 ir_node *mem = get_Load_mem(node);
1633 ir_node *new_mem = transform_node(env, mem);
1634 ir_graph *irg = env->irg;
1635 dbg_info *dbgi = get_irn_dbg_info(node);
1636 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1637 ir_mode *mode = get_Load_mode(node);
1638 ir_node *lptr = new_ptr;
1641 ir_node *projs[pn_Load_max];
1642 ia32_am_flavour_t am_flav = ia32_am_B;
1644 ia32_collect_Projs(node, projs, pn_Load_max);
1647 check for special case: the loaded value might not be used (optimized, volatile, ...)
1648 we add a Proj + Keep for volatile loads and ignore all other cases
1650 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1651 /* add a result proj and a Keep to produce a pseudo use */
1652 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1653 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1656 /* address might be a constant (symconst or absolute address) */
1657 if (is_ia32_Const(new_ptr)) {
1662 if (mode_is_float(mode)) {
1664 if (USE_SSE2(env->cg)) {
1665 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1667 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1670 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1673 /* base is a constant address */
1675 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1676 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1677 am_flav = ia32_am_N;
1679 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1680 long offs = get_tarval_long(tv);
1682 add_ia32_am_offs_int(new_op, offs);
1683 am_flav = ia32_am_O;
1687 set_ia32_am_support(new_op, ia32_am_Source);
1688 set_ia32_op_type(new_op, ia32_AddrModeS);
1689 set_ia32_am_flavour(new_op, am_flav);
1690 set_ia32_ls_mode(new_op, mode);
1692 /* make sure we are scheduled behind the initial IncSP/Barrier
1693 * to avoid spills being placed before it
1695 if (block == get_irg_start_block(irg)) {
1696 add_irn_dep(new_op, get_irg_frame(irg));
1699 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1707 * Transforms a Store.
1709 * @param env The transformation environment
1710 * @return the created ia32 Store node
1712 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1713 ir_node *block = transform_node(env, get_nodes_block(node));
1714 ir_node *ptr = get_Store_ptr(node);
1715 ir_node *new_ptr = transform_node(env, ptr);
1716 ir_node *val = get_Store_value(node);
1717 ir_node *new_val = transform_node(env, val);
1718 ir_node *mem = get_Store_mem(node);
1719 ir_node *new_mem = transform_node(env, mem);
1720 ir_graph *irg = env->irg;
1721 dbg_info *dbgi = get_irn_dbg_info(node);
1722 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1723 ir_node *sptr = new_ptr;
1724 ir_mode *mode = get_irn_mode(val);
1725 ir_node *sval = new_val;
1728 ia32_am_flavour_t am_flav = ia32_am_B;
1730 if (is_ia32_Const(new_val)) {
1731 assert(!mode_is_float(mode));
1735 /* address might be a constant (symconst or absolute address) */
1736 if (is_ia32_Const(new_ptr)) {
1741 if (mode_is_float(mode)) {
1743 if (USE_SSE2(env->cg)) {
1744 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1746 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1748 } else if (get_mode_size_bits(mode) == 8) {
1749 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1751 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1754 /* stored const is an immediate value */
1755 if (is_ia32_Const(new_val)) {
1756 assert(!mode_is_float(mode));
1757 copy_ia32_Immop_attr(new_op, new_val);
1760 /* base is an constant address */
1762 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1763 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1764 am_flav = ia32_am_N;
1766 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1767 long offs = get_tarval_long(tv);
1769 add_ia32_am_offs_int(new_op, offs);
1770 am_flav = ia32_am_O;
1774 set_ia32_am_support(new_op, ia32_am_Dest);
1775 set_ia32_op_type(new_op, ia32_AddrModeD);
1776 set_ia32_am_flavour(new_op, am_flav);
1777 set_ia32_ls_mode(new_op, mode);
1779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1787 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1789 * @param env The transformation environment
1790 * @return The transformed node.
1792 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1793 ir_node *block = transform_node(env, get_nodes_block(node));
1794 ir_graph *irg = env->irg;
1795 dbg_info *dbgi = get_irn_dbg_info(node);
1796 ir_node *sel = get_Cond_selector(node);
1797 ir_mode *sel_mode = get_irn_mode(sel);
1798 ir_node *res = NULL;
1799 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1800 ir_node *cnst, *expr;
1802 if (is_Proj(sel) && sel_mode == mode_b) {
1803 ir_node *pred = get_Proj_pred(sel);
1804 ir_node *cmp_a = get_Cmp_left(pred);
1805 ir_node *new_cmp_a = transform_node(env, cmp_a);
1806 ir_node *cmp_b = get_Cmp_right(pred);
1807 ir_node *new_cmp_b = transform_node(env, cmp_b);
1808 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1809 ir_node *nomem = new_NoMem();
1811 int pnc = get_Proj_proj(sel);
1812 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1813 pnc |= ia32_pn_Cmp_Unsigned;
1816 /* check if we can use a CondJmp with immediate */
1817 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1818 expr = get_expr_op(new_cmp_a, new_cmp_b);
1820 if (cnst != NULL && expr != NULL) {
1821 /* immop has to be the right operand, we might need to flip pnc */
1822 if(cnst != new_cmp_b) {
1823 pnc = get_inversed_pnc(pnc);
1826 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1827 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1828 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1830 /* a Cmp A =/!= 0 */
1831 ir_node *op1 = expr;
1832 ir_node *op2 = expr;
1835 /* check, if expr is an only once used And operation */
1836 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1837 op1 = get_irn_n(expr, 2);
1838 op2 = get_irn_n(expr, 3);
1840 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1842 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1843 set_ia32_pncode(res, pnc);
1846 copy_ia32_Immop_attr(res, expr);
1849 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1854 if (mode_is_float(cmp_mode)) {
1856 if (USE_SSE2(env->cg)) {
1857 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1858 set_ia32_ls_mode(res, cmp_mode);
1864 assert(get_mode_size_bits(cmp_mode) == 32);
1865 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1867 copy_ia32_Immop_attr(res, cnst);
1870 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1872 if (mode_is_float(cmp_mode)) {
1874 if (USE_SSE2(env->cg)) {
1875 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1876 set_ia32_ls_mode(res, cmp_mode);
1879 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1880 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1881 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1885 assert(get_mode_size_bits(cmp_mode) == 32);
1886 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1887 set_ia32_commutative(res);
1891 set_ia32_pncode(res, pnc);
1892 // Matze: disabled for now, because the default collect_spills_walker
1893 // is not able to detect the mode of the spilled value
1894 // moreover, the lea optimize phase freely exchanges left/right
1895 // without updating the pnc
1896 //set_ia32_am_support(res, ia32_am_Source);
1899 /* determine the smallest switch case value */
1900 ir_node *new_sel = transform_node(env, sel);
1901 int switch_min = INT_MAX;
1902 const ir_edge_t *edge;
1904 foreach_out_edge(node, edge) {
1905 int pn = get_Proj_proj(get_edge_src_irn(edge));
1906 switch_min = pn < switch_min ? pn : switch_min;
1910 /* if smallest switch case is not 0 we need an additional sub */
1911 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1912 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1913 add_ia32_am_offs_int(res, -switch_min);
1914 set_ia32_am_flavour(res, ia32_am_OB);
1915 set_ia32_am_support(res, ia32_am_Source);
1916 set_ia32_op_type(res, ia32_AddrModeS);
1919 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1920 set_ia32_pncode(res, get_Cond_defaultProj(node));
1923 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1930 * Transforms a CopyB node.
1932 * @param env The transformation environment
1933 * @return The transformed node.
1935 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1936 ir_node *block = transform_node(env, get_nodes_block(node));
1937 ir_node *src = get_CopyB_src(node);
1938 ir_node *new_src = transform_node(env, src);
1939 ir_node *dst = get_CopyB_dst(node);
1940 ir_node *new_dst = transform_node(env, dst);
1941 ir_node *mem = get_CopyB_mem(node);
1942 ir_node *new_mem = transform_node(env, mem);
1943 ir_node *res = NULL;
1944 ir_graph *irg = env->irg;
1945 dbg_info *dbgi = get_irn_dbg_info(node);
1946 int size = get_type_size_bytes(get_CopyB_type(node));
1947 ir_mode *dst_mode = get_irn_mode(dst);
1948 ir_mode *src_mode = get_irn_mode(src);
1952 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1953 /* then we need the size explicitly in ECX. */
1954 if (size >= 32 * 4) {
1955 rem = size & 0x3; /* size % 4 */
1958 res = new_rd_ia32_Const(dbgi, irg, block);
1959 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1960 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1962 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1963 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1965 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1966 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1967 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1968 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1969 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1972 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1973 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1975 /* ok: now attach Proj's because movsd will destroy esi and edi */
1976 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1977 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1978 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1981 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1989 * Transforms a Mux node into CMov.
1991 * @param env The transformation environment
1992 * @return The transformed node.
1994 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1995 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
1996 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1998 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2004 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2005 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2006 ir_node *psi_default);
2009 * Transforms a Psi node into CMov.
2011 * @param env The transformation environment
2012 * @return The transformed node.
2014 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2015 ir_node *block = transform_node(env, get_nodes_block(node));
2016 ir_node *psi_true = get_Psi_val(node, 0);
2017 ir_node *new_psi_true = transform_node(env, psi_true);
2018 ir_node *psi_default = get_Psi_default(node);
2019 ir_node *new_psi_default = transform_node(env, psi_default);
2020 ia32_code_gen_t *cg = env->cg;
2021 ir_graph *irg = env->irg;
2022 dbg_info *dbgi = get_irn_dbg_info(node);
2023 ir_mode *mode = get_irn_mode(node);
2024 ir_node *cmp_proj = get_Mux_sel(node);
2025 ir_node *noreg = ia32_new_NoReg_gp(cg);
2026 ir_node *nomem = new_rd_NoMem(irg);
2027 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2028 ir_node *new_cmp_a, *new_cmp_b;
2032 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2034 cmp = get_Proj_pred(cmp_proj);
2035 cmp_a = get_Cmp_left(cmp);
2036 cmp_b = get_Cmp_right(cmp);
2037 cmp_mode = get_irn_mode(cmp_a);
2038 new_cmp_a = transform_node(env, cmp_a);
2039 new_cmp_b = transform_node(env, cmp_b);
2041 pnc = get_Proj_proj(cmp_proj);
2042 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2043 pnc |= ia32_pn_Cmp_Unsigned;
2046 if (mode_is_float(mode)) {
2047 /* floating point psi */
2050 /* 1st case: compare operands are float too */
2052 /* psi(cmp(a, b), t, f) can be done as: */
2053 /* tmp = cmp a, b */
2054 /* tmp2 = t and tmp */
2055 /* tmp3 = f and not tmp */
2056 /* res = tmp2 or tmp3 */
2058 /* in case the compare operands are int, we move them into xmm register */
2059 if (! mode_is_float(get_irn_mode(cmp_a))) {
2060 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2061 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2063 pnc |= 8; /* transform integer compare to fp compare */
2066 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2067 set_ia32_pncode(new_op, pnc);
2068 set_ia32_am_support(new_op, ia32_am_Source);
2069 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2071 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2072 set_ia32_am_support(and1, ia32_am_None);
2073 set_ia32_commutative(and1);
2074 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2076 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2077 set_ia32_am_support(and2, ia32_am_None);
2078 set_ia32_commutative(and2);
2079 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2081 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2082 set_ia32_am_support(new_op, ia32_am_None);
2083 set_ia32_commutative(new_op);
2084 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2088 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2089 set_ia32_pncode(new_op, pnc);
2090 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2095 construct_binop_func *set_func = NULL;
2096 cmov_func_t *cmov_func = NULL;
2098 if (mode_is_float(get_irn_mode(cmp_a))) {
2099 /* 1st case: compare operands are floats */
2104 set_func = new_rd_ia32_xCmpSet;
2105 cmov_func = new_rd_ia32_xCmpCMov;
2109 set_func = new_rd_ia32_vfCmpSet;
2110 cmov_func = new_rd_ia32_vfCmpCMov;
2113 pnc &= ~0x8; /* fp compare -> int compare */
2116 /* 2nd case: compare operand are integer too */
2117 set_func = new_rd_ia32_CmpSet;
2118 cmov_func = new_rd_ia32_CmpCMov;
2121 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2122 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2123 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2124 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2125 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2126 set_ia32_pncode(new_op, pnc);
2128 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2129 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2130 /* we invert condition and set default to 0 */
2131 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2132 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2135 /* otherwise: use CMOVcc */
2136 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2137 set_ia32_pncode(new_op, pnc);
2140 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2143 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2144 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2145 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2146 set_ia32_pncode(new_op, pnc);
2147 set_ia32_am_support(new_op, ia32_am_Source);
2149 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2150 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2151 /* we invert condition and set default to 0 */
2152 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2153 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2154 set_ia32_am_support(new_op, ia32_am_Source);
2157 /* otherwise: use CMOVcc */
2158 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2159 set_ia32_pncode(new_op, pnc);
2160 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2170 * Following conversion rules apply:
2174 * 1) n bit -> m bit n > m (downscale)
2176 * 2) n bit -> m bit n == m (sign change)
2178 * 3) n bit -> m bit n < m (upscale)
2179 * a) source is signed: movsx
2180 * b) source is unsigned: and with lower bits sets
2184 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2188 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2192 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2193 * x87 is mode_E internally, conversions happen only at load and store
2194 * in non-strict semantic
2198 * Create a conversion from x87 state register to general purpose.
2200 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2201 ir_node *block = transform_node(env, get_nodes_block(node));
2202 ir_node *op = get_Conv_op(node);
2203 ir_node *new_op = transform_node(env, op);
2204 ia32_code_gen_t *cg = env->cg;
2205 ir_graph *irg = env->irg;
2206 dbg_info *dbgi = get_irn_dbg_info(node);
2207 ir_node *noreg = ia32_new_NoReg_gp(cg);
2208 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2209 ir_node *fist, *load;
2212 fist = new_rd_ia32_vfist(dbgi, irg, block,
2213 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2215 set_ia32_use_frame(fist);
2216 set_ia32_am_support(fist, ia32_am_Dest);
2217 set_ia32_op_type(fist, ia32_AddrModeD);
2218 set_ia32_am_flavour(fist, ia32_am_B);
2219 set_ia32_ls_mode(fist, mode_Iu);
2220 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2223 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2225 set_ia32_use_frame(load);
2226 set_ia32_am_support(load, ia32_am_Source);
2227 set_ia32_op_type(load, ia32_AddrModeS);
2228 set_ia32_am_flavour(load, ia32_am_B);
2229 set_ia32_ls_mode(load, mode_Iu);
2230 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2232 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2236 * Create a conversion from general purpose to x87 register
2238 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2239 ir_node *block = transform_node(env, get_nodes_block(node));
2240 ir_node *op = get_Conv_op(node);
2241 ir_node *new_op = transform_node(env, op);
2242 ir_graph *irg = env->irg;
2243 dbg_info *dbgi = get_irn_dbg_info(node);
2244 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2245 ir_node *nomem = new_NoMem();
2246 ir_node *fild, *store;
2249 /* first convert to 32 bit if necessary */
2250 src_bits = get_mode_size_bits(src_mode);
2251 if (src_bits == 8) {
2252 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2253 set_ia32_am_support(new_op, ia32_am_Source);
2254 set_ia32_ls_mode(new_op, src_mode);
2255 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2256 } else if (src_bits < 32) {
2257 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2258 set_ia32_am_support(new_op, ia32_am_Source);
2259 set_ia32_ls_mode(new_op, src_mode);
2260 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2264 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2266 set_ia32_use_frame(store);
2267 set_ia32_am_support(store, ia32_am_Dest);
2268 set_ia32_op_type(store, ia32_AddrModeD);
2269 set_ia32_am_flavour(store, ia32_am_OB);
2270 set_ia32_ls_mode(store, mode_Iu);
2273 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2275 set_ia32_use_frame(fild);
2276 set_ia32_am_support(fild, ia32_am_Source);
2277 set_ia32_op_type(fild, ia32_AddrModeS);
2278 set_ia32_am_flavour(fild, ia32_am_OB);
2279 set_ia32_ls_mode(fild, mode_Iu);
2281 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2285 * Transforms a Conv node.
2287 * @param env The transformation environment
2288 * @return The created ia32 Conv node
2290 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2291 ir_node *block = transform_node(env, get_nodes_block(node));
2292 ir_node *op = get_Conv_op(node);
2293 ir_node *new_op = transform_node(env, op);
2294 ir_graph *irg = env->irg;
2295 dbg_info *dbgi = get_irn_dbg_info(node);
2296 ir_mode *src_mode = get_irn_mode(op);
2297 ir_mode *tgt_mode = get_irn_mode(node);
2298 int src_bits = get_mode_size_bits(src_mode);
2299 int tgt_bits = get_mode_size_bits(tgt_mode);
2300 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2301 ir_node *nomem = new_rd_NoMem(irg);
2304 if (src_mode == tgt_mode) {
2305 if (get_Conv_strict(node)) {
2306 if (USE_SSE2(env->cg)) {
2307 /* when we are in SSE mode, we can kill all strict no-op conversion */
2311 /* this should be optimized already, but who knows... */
2312 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2313 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2318 if (mode_is_float(src_mode)) {
2319 /* we convert from float ... */
2320 if (mode_is_float(tgt_mode)) {
2322 if (USE_SSE2(env->cg)) {
2323 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2324 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2325 set_ia32_ls_mode(res, tgt_mode);
2327 // Matze: TODO what about strict convs?
2328 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2329 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2334 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2335 if (USE_SSE2(env->cg)) {
2336 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2337 set_ia32_ls_mode(res, src_mode);
2339 return gen_x87_fp_to_gp(env, node);
2343 /* we convert from int ... */
2344 if (mode_is_float(tgt_mode)) {
2347 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2348 if (USE_SSE2(env->cg)) {
2349 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2350 set_ia32_ls_mode(res, tgt_mode);
2351 if(src_bits == 32) {
2352 set_ia32_am_support(res, ia32_am_Source);
2355 return gen_x87_gp_to_fp(env, node, src_mode);
2359 ir_mode *smaller_mode;
2362 if (src_bits == tgt_bits) {
2363 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2367 if (src_bits < tgt_bits) {
2368 smaller_mode = src_mode;
2369 smaller_bits = src_bits;
2371 smaller_mode = tgt_mode;
2372 smaller_bits = tgt_bits;
2376 The following is not correct, we can't change the mode,
2377 maybe others are using the load too
2378 better move this to a separate phase!
2382 if(is_Proj(new_op)) {
2383 /* load operations do already sign/zero extend, so we have
2384 * nothing left to do */
2385 ir_node *pred = get_Proj_pred(new_op);
2386 if(is_ia32_Load(pred)) {
2387 set_ia32_ls_mode(pred, smaller_mode);
2393 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2394 if (smaller_bits == 8) {
2395 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2396 set_ia32_ls_mode(res, smaller_mode);
2398 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2399 set_ia32_ls_mode(res, smaller_mode);
2401 set_ia32_am_support(res, ia32_am_Source);
2405 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2412 /********************************************
2415 * | |__ ___ _ __ ___ __| | ___ ___
2416 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2417 * | |_) | __/ | | | (_) | (_| | __/\__ \
2418 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2420 ********************************************/
2422 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2423 ir_node *block = transform_node(env, get_nodes_block(node));
2424 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2425 ir_node *new_ptr = transform_node(env, ptr);
2426 ir_node *new_op = NULL;
2427 ir_graph *irg = env->irg;
2428 dbg_info *dbgi = get_irn_dbg_info(node);
2429 ir_node *nomem = new_rd_NoMem(env->irg);
2430 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2431 ir_mode *load_mode = get_irn_mode(node);
2432 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2436 if (mode_is_float(load_mode)) {
2438 if (USE_SSE2(env->cg)) {
2439 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2440 pn_res = pn_ia32_xLoad_res;
2441 proj_mode = mode_xmm;
2443 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2444 pn_res = pn_ia32_vfld_res;
2445 proj_mode = mode_vfp;
2448 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2449 proj_mode = mode_Iu;
2450 pn_res = pn_ia32_Load_res;
2453 set_ia32_frame_ent(new_op, ent);
2454 set_ia32_use_frame(new_op);
2456 set_ia32_am_support(new_op, ia32_am_Source);
2457 set_ia32_op_type(new_op, ia32_AddrModeS);
2458 set_ia32_am_flavour(new_op, ia32_am_B);
2459 set_ia32_ls_mode(new_op, load_mode);
2460 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2462 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2464 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2468 * Transforms a FrameAddr into an ia32 Add.
2470 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2471 ir_node *block = transform_node(env, get_nodes_block(node));
2472 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
2473 ir_node *new_op = transform_node(env, op);
2474 ir_graph *irg = env->irg;
2475 dbg_info *dbgi = get_irn_dbg_info(node);
2476 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2479 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2480 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2481 set_ia32_am_support(res, ia32_am_Full);
2482 set_ia32_use_frame(res);
2483 set_ia32_am_flavour(res, ia32_am_OB);
2485 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2491 * Transforms a FrameLoad into an ia32 Load.
2493 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2494 ir_node *block = transform_node(env, get_nodes_block(node));
2495 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2496 ir_node *new_mem = transform_node(env, mem);
2497 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2498 ir_node *new_ptr = transform_node(env, ptr);
2499 ir_node *new_op = NULL;
2500 ir_graph *irg = env->irg;
2501 dbg_info *dbgi = get_irn_dbg_info(node);
2502 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2503 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2504 ir_mode *mode = get_type_mode(get_entity_type(ent));
2505 ir_node *projs[pn_Load_max];
2507 ia32_collect_Projs(node, projs, pn_Load_max);
2509 if (mode_is_float(mode)) {
2511 if (USE_SSE2(env->cg)) {
2512 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2515 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2519 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2522 set_ia32_frame_ent(new_op, ent);
2523 set_ia32_use_frame(new_op);
2525 set_ia32_am_support(new_op, ia32_am_Source);
2526 set_ia32_op_type(new_op, ia32_AddrModeS);
2527 set_ia32_am_flavour(new_op, ia32_am_B);
2528 set_ia32_ls_mode(new_op, mode);
2530 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2537 * Transforms a FrameStore into an ia32 Store.
2539 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2540 ir_node *block = transform_node(env, get_nodes_block(node));
2541 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2542 ir_node *new_mem = transform_node(env, mem);
2543 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2544 ir_node *new_ptr = transform_node(env, ptr);
2545 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2546 ir_node *new_val = transform_node(env, val);
2547 ir_node *new_op = NULL;
2548 ir_graph *irg = env->irg;
2549 dbg_info *dbgi = get_irn_dbg_info(node);
2550 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2551 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2552 ir_mode *mode = get_irn_mode(val);
2554 if (mode_is_float(mode)) {
2556 if (USE_SSE2(env->cg)) {
2557 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2559 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2561 } else if (get_mode_size_bits(mode) == 8) {
2562 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2564 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2567 set_ia32_frame_ent(new_op, ent);
2568 set_ia32_use_frame(new_op);
2570 set_ia32_am_support(new_op, ia32_am_Dest);
2571 set_ia32_op_type(new_op, ia32_AddrModeD);
2572 set_ia32_am_flavour(new_op, ia32_am_B);
2573 set_ia32_ls_mode(new_op, mode);
2575 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2581 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2583 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2584 ir_graph *irg = env->irg;
2585 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2586 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2587 ir_entity *ent = get_irg_entity(irg);
2588 ir_type *tp = get_entity_type(ent);
2593 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2594 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2596 int pn_ret_val, pn_ret_mem, arity, i;
2598 assert(ret_val != NULL);
2599 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2600 return duplicate_node(env, node);
2603 res_type = get_method_res_type(tp, 0);
2605 if (! is_Primitive_type(res_type)) {
2606 return duplicate_node(env, node);
2609 mode = get_type_mode(res_type);
2610 if (! mode_is_float(mode)) {
2611 return duplicate_node(env, node);
2614 assert(get_method_n_ress(tp) == 1);
2616 pn_ret_val = get_Proj_proj(ret_val);
2617 pn_ret_mem = get_Proj_proj(ret_mem);
2619 /* get the Barrier */
2620 barrier = get_Proj_pred(ret_val);
2622 /* get result input of the Barrier */
2623 ret_val = get_irn_n(barrier, pn_ret_val);
2624 new_ret_val = transform_node(env, ret_val);
2626 /* get memory input of the Barrier */
2627 ret_mem = get_irn_n(barrier, pn_ret_mem);
2628 new_ret_mem = transform_node(env, ret_mem);
2630 frame = get_irg_frame(irg);
2632 dbgi = get_irn_dbg_info(barrier);
2633 block = transform_node(env, get_nodes_block(barrier));
2635 /* store xmm0 onto stack */
2636 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2637 set_ia32_ls_mode(sse_store, mode);
2638 set_ia32_op_type(sse_store, ia32_AddrModeD);
2639 set_ia32_use_frame(sse_store);
2640 set_ia32_am_flavour(sse_store, ia32_am_B);
2641 set_ia32_am_support(sse_store, ia32_am_Dest);
2644 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2645 set_ia32_ls_mode(fld, mode);
2646 set_ia32_op_type(fld, ia32_AddrModeS);
2647 set_ia32_use_frame(fld);
2648 set_ia32_am_flavour(fld, ia32_am_B);
2649 set_ia32_am_support(fld, ia32_am_Source);
2651 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2652 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2653 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2655 /* create a new barrier */
2656 arity = get_irn_arity(barrier);
2657 in = alloca(arity * sizeof(in[0]));
2658 for (i = 0; i < arity; ++i) {
2661 if (i == pn_ret_val) {
2663 } else if (i == pn_ret_mem) {
2666 ir_node *in = get_irn_n(barrier, i);
2667 new_in = transform_node(env, in);
2672 new_barrier = new_ir_node(dbgi, irg, block,
2673 get_irn_op(barrier), get_irn_mode(barrier),
2675 copy_node_attr(barrier, new_barrier);
2676 duplicate_deps(env, barrier, new_barrier);
2677 set_new_node(barrier, new_barrier);
2678 mark_irn_visited(barrier);
2680 /* transform normally */
2681 return duplicate_node(env, node);
2685 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2687 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2688 ir_node *block = transform_node(env, get_nodes_block(node));
2689 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2690 ir_node *new_sz = transform_node(env, sz);
2691 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2692 ir_node *new_sp = transform_node(env, sp);
2693 ir_graph *irg = env->irg;
2694 dbg_info *dbgi = get_irn_dbg_info(node);
2695 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2696 ir_node *nomem = new_NoMem();
2699 /* ia32 stack grows in reverse direction, make a SubSP */
2700 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2701 set_ia32_am_support(new_op, ia32_am_Source);
2702 fold_immediate(env, new_op, 2, 3);
2704 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2710 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2712 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2713 ir_node *block = transform_node(env, get_nodes_block(node));
2714 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2715 ir_node *new_sz = transform_node(env, sz);
2716 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2717 ir_node *new_sp = transform_node(env, sp);
2718 ir_graph *irg = env->irg;
2719 dbg_info *dbgi = get_irn_dbg_info(node);
2720 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2721 ir_node *nomem = new_NoMem();
2724 /* ia32 stack grows in reverse direction, make an AddSP */
2725 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2726 set_ia32_am_support(new_op, ia32_am_Source);
2727 fold_immediate(env, new_op, 2, 3);
2729 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2735 * This function just sets the register for the Unknown node
2736 * as this is not done during register allocation because Unknown
2737 * is an "ignore" node.
2739 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2740 ir_mode *mode = get_irn_mode(node);
2742 if (mode_is_float(mode)) {
2743 if (USE_SSE2(env->cg))
2744 return ia32_new_Unknown_xmm(env->cg);
2746 return ia32_new_Unknown_vfp(env->cg);
2747 } else if (mode_needs_gp_reg(mode)) {
2748 return ia32_new_Unknown_gp(env->cg);
2750 assert(0 && "unsupported Unknown-Mode");
2757 * Change some phi modes
2759 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2760 ir_node *block = transform_node(env, get_nodes_block(node));
2761 ir_graph *irg = env->irg;
2762 dbg_info *dbgi = get_irn_dbg_info(node);
2763 ir_mode *mode = get_irn_mode(node);
2767 if(mode_needs_gp_reg(mode)) {
2768 /* we shouldn't have any 64bit stuff around anymore */
2769 assert(get_mode_size_bits(mode) <= 32);
2770 /* all integer operations are on 32bit registers now */
2772 } else if(mode_is_float(mode)) {
2773 assert(mode == mode_D || mode == mode_F);
2774 if (USE_SSE2(env->cg)) {
2781 /* phi nodes allow loops, so we use the old arguments for now
2782 * and fix this later */
2783 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2784 copy_node_attr(node, phi);
2785 duplicate_deps(env, node, phi);
2787 set_new_node(node, phi);
2789 /* put the preds in the worklist */
2790 arity = get_irn_arity(node);
2791 for (i = 0; i < arity; ++i) {
2792 ir_node *pred = get_irn_n(node, i);
2793 pdeq_putr(env->worklist, pred);
2799 /**********************************************************************
2802 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2803 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2804 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2805 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2807 **********************************************************************/
2809 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2811 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2814 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2815 ir_node *val, ir_node *mem);
2818 * Transforms a lowered Load into a "real" one.
2820 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2821 ir_node *block = transform_node(env, get_nodes_block(node));
2822 ir_node *ptr = get_irn_n(node, 0);
2823 ir_node *new_ptr = transform_node(env, ptr);
2824 ir_node *mem = get_irn_n(node, 1);
2825 ir_node *new_mem = transform_node(env, mem);
2826 ir_graph *irg = env->irg;
2827 dbg_info *dbgi = get_irn_dbg_info(node);
2828 ir_mode *mode = get_ia32_ls_mode(node);
2829 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2833 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2834 lowering we have x87 nodes, so we need to enforce simulation.
2836 if (mode_is_float(mode)) {
2838 if (fp_unit == fp_x87)
2842 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2844 set_ia32_am_support(new_op, ia32_am_Source);
2845 set_ia32_op_type(new_op, ia32_AddrModeS);
2846 set_ia32_am_flavour(new_op, ia32_am_OB);
2847 set_ia32_am_offs_int(new_op, 0);
2848 set_ia32_am_scale(new_op, 1);
2849 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2850 if (is_ia32_am_sc_sign(node))
2851 set_ia32_am_sc_sign(new_op);
2852 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2853 if (is_ia32_use_frame(node)) {
2854 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2855 set_ia32_use_frame(new_op);
2858 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2864 * Transforms a lowered Store into a "real" one.
2866 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2867 ir_node *block = transform_node(env, get_nodes_block(node));
2868 ir_node *ptr = get_irn_n(node, 0);
2869 ir_node *new_ptr = transform_node(env, ptr);
2870 ir_node *val = get_irn_n(node, 1);
2871 ir_node *new_val = transform_node(env, val);
2872 ir_node *mem = get_irn_n(node, 2);
2873 ir_node *new_mem = transform_node(env, mem);
2874 ir_graph *irg = env->irg;
2875 dbg_info *dbgi = get_irn_dbg_info(node);
2876 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2877 ir_mode *mode = get_ia32_ls_mode(node);
2880 ia32_am_flavour_t am_flav = ia32_B;
2883 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2884 lowering we have x87 nodes, so we need to enforce simulation.
2886 if (mode_is_float(mode)) {
2888 if (fp_unit == fp_x87)
2892 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2894 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2896 add_ia32_am_offs_int(new_op, am_offs);
2899 set_ia32_am_support(new_op, ia32_am_Dest);
2900 set_ia32_op_type(new_op, ia32_AddrModeD);
2901 set_ia32_am_flavour(new_op, am_flav);
2902 set_ia32_ls_mode(new_op, mode);
2903 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2904 set_ia32_use_frame(new_op);
2906 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2913 * Transforms an ia32_l_XXX into a "real" XXX node
2915 * @param env The transformation environment
2916 * @return the created ia32 XXX node
2918 #define GEN_LOWERED_OP(op) \
2919 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2920 ir_mode *mode = get_irn_mode(node); \
2921 if (mode_is_float(mode)) \
2923 return gen_binop(env, node, get_binop_left(node), \
2924 get_binop_right(node), new_rd_ia32_##op); \
2927 #define GEN_LOWERED_x87_OP(op) \
2928 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2930 FORCE_x87(env->cg); \
2931 new_op = gen_binop_float(env, node, get_binop_left(node), \
2932 get_binop_right(node), new_rd_ia32_##op); \
2936 #define GEN_LOWERED_UNOP(op) \
2937 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2938 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2941 #define GEN_LOWERED_SHIFT_OP(op) \
2942 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2943 return gen_shift_binop(env, node, get_binop_left(node), \
2944 get_binop_right(node), new_rd_ia32_##op); \
2947 #define GEN_LOWERED_LOAD(op, fp_unit) \
2948 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2949 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2952 #define GEN_LOWERED_STORE(op, fp_unit) \
2953 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2954 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2961 GEN_LOWERED_OP(IMul)
2963 GEN_LOWERED_x87_OP(vfprem)
2964 GEN_LOWERED_x87_OP(vfmul)
2965 GEN_LOWERED_x87_OP(vfsub)
2967 GEN_LOWERED_UNOP(Neg)
2969 GEN_LOWERED_LOAD(vfild, fp_x87)
2970 GEN_LOWERED_LOAD(Load, fp_none)
2971 /*GEN_LOWERED_STORE(vfist, fp_x87)
2974 GEN_LOWERED_STORE(Store, fp_none)
2976 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2977 ir_node *block = transform_node(env, get_nodes_block(node));
2978 ir_node *left = get_binop_left(node);
2979 ir_node *new_left = transform_node(env, left);
2980 ir_node *right = get_binop_right(node);
2981 ir_node *new_right = transform_node(env, right);
2982 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2983 ir_graph *irg = env->irg;
2984 dbg_info *dbgi = get_irn_dbg_info(node);
2987 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2988 clear_ia32_commutative(vfdiv);
2989 set_ia32_am_support(vfdiv, ia32_am_Source);
2990 fold_immediate(env, vfdiv, 2, 3);
2992 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3000 * Transforms a l_MulS into a "real" MulS node.
3002 * @param env The transformation environment
3003 * @return the created ia32 Mul node
3005 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3006 ir_node *block = transform_node(env, get_nodes_block(node));
3007 ir_node *left = get_binop_left(node);
3008 ir_node *new_left = transform_node(env, left);
3009 ir_node *right = get_binop_right(node);
3010 ir_node *new_right = transform_node(env, right);
3011 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3012 ir_graph *irg = env->irg;
3013 dbg_info *dbgi = get_irn_dbg_info(node);
3016 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3017 /* and then skip the result Proj, because all needed Projs are already there. */
3018 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3019 clear_ia32_commutative(muls);
3020 set_ia32_am_support(muls, ia32_am_Source);
3021 fold_immediate(env, muls, 2, 3);
3023 /* check if EAX and EDX proj exist, add missing one */
3024 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3025 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3026 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3028 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3033 GEN_LOWERED_SHIFT_OP(Shl)
3034 GEN_LOWERED_SHIFT_OP(Shr)
3035 GEN_LOWERED_SHIFT_OP(Sar)
3038 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3039 * op1 - target to be shifted
3040 * op2 - contains bits to be shifted into target
3042 * Only op3 can be an immediate.
3044 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3045 ir_node *op1, ir_node *op2,
3048 ir_node *block = transform_node(env, get_nodes_block(node));
3049 ir_node *new_op1 = transform_node(env, op1);
3050 ir_node *new_op2 = transform_node(env, op2);
3051 ir_node *new_count = transform_node(env, count);
3052 ir_node *new_op = NULL;
3053 ir_graph *irg = env->irg;
3054 dbg_info *dbgi = get_irn_dbg_info(node);
3055 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3056 ir_node *nomem = new_NoMem();
3060 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3062 /* Check if immediate optimization is on and */
3063 /* if it's an operation with immediate. */
3064 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3066 /* Limit imm_op within range imm8 */
3068 tv = get_ia32_Immop_tarval(imm_op);
3071 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3072 set_ia32_Immop_tarval(imm_op, tv);
3079 /* integer operations */
3081 /* This is ShiftD with const */
3082 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3084 if (is_ia32_l_ShlD(node))
3085 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3086 new_op1, new_op2, noreg, nomem);
3088 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3089 new_op1, new_op2, noreg, nomem);
3090 copy_ia32_Immop_attr(new_op, imm_op);
3093 /* This is a normal ShiftD */
3094 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3095 if (is_ia32_l_ShlD(node))
3096 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3097 new_op1, new_op2, new_count, nomem);
3099 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3100 new_op1, new_op2, new_count, nomem);
3103 /* set AM support */
3104 // Matze: node has unsupported format (6inputs)
3105 //set_ia32_am_support(new_op, ia32_am_Dest);
3107 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3109 set_ia32_emit_cl(new_op);
3114 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3115 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3116 get_irn_n(node, 1), get_irn_n(node, 2));
3119 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3120 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3121 get_irn_n(node, 1), get_irn_n(node, 2));
3125 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3127 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3128 ir_node *block = transform_node(env, get_nodes_block(node));
3129 ir_node *val = get_irn_n(node, 1);
3130 ir_node *new_val = transform_node(env, val);
3131 ia32_code_gen_t *cg = env->cg;
3132 ir_node *res = NULL;
3133 ir_graph *irg = env->irg;
3135 ir_node *noreg, *new_ptr, *new_mem;
3142 mem = get_irn_n(node, 2);
3143 new_mem = transform_node(env, mem);
3144 ptr = get_irn_n(node, 0);
3145 new_ptr = transform_node(env, ptr);
3146 noreg = ia32_new_NoReg_gp(cg);
3147 dbgi = get_irn_dbg_info(node);
3149 /* Store x87 -> MEM */
3150 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3151 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3152 set_ia32_use_frame(res);
3153 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3154 set_ia32_am_support(res, ia32_am_Dest);
3155 set_ia32_am_flavour(res, ia32_B);
3156 set_ia32_op_type(res, ia32_AddrModeD);
3158 /* Load MEM -> SSE */
3159 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3160 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3161 set_ia32_use_frame(res);
3162 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3163 set_ia32_am_support(res, ia32_am_Source);
3164 set_ia32_am_flavour(res, ia32_B);
3165 set_ia32_op_type(res, ia32_AddrModeS);
3166 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3172 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3174 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3175 ir_node *block = transform_node(env, get_nodes_block(node));
3176 ir_node *val = get_irn_n(node, 1);
3177 ir_node *new_val = transform_node(env, val);
3178 ia32_code_gen_t *cg = env->cg;
3179 ir_graph *irg = env->irg;
3180 ir_node *res = NULL;
3181 ir_entity *fent = get_ia32_frame_ent(node);
3182 ir_mode *lsmode = get_ia32_ls_mode(node);
3184 ir_node *noreg, *new_ptr, *new_mem;
3188 if (! USE_SSE2(cg)) {
3189 /* SSE unit is not used -> skip this node. */
3193 ptr = get_irn_n(node, 0);
3194 new_ptr = transform_node(env, ptr);
3195 mem = get_irn_n(node, 2);
3196 new_mem = transform_node(env, mem);
3197 noreg = ia32_new_NoReg_gp(cg);
3198 dbgi = get_irn_dbg_info(node);
3200 /* Store SSE -> MEM */
3201 if (is_ia32_xLoad(skip_Proj(new_val))) {
3202 ir_node *ld = skip_Proj(new_val);
3204 /* we can vfld the value directly into the fpu */
3205 fent = get_ia32_frame_ent(ld);
3206 ptr = get_irn_n(ld, 0);
3207 offs = get_ia32_am_offs_int(ld);
3209 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3210 set_ia32_frame_ent(res, fent);
3211 set_ia32_use_frame(res);
3212 set_ia32_ls_mode(res, lsmode);
3213 set_ia32_am_support(res, ia32_am_Dest);
3214 set_ia32_am_flavour(res, ia32_B);
3215 set_ia32_op_type(res, ia32_AddrModeD);
3219 /* Load MEM -> x87 */
3220 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3221 set_ia32_frame_ent(res, fent);
3222 set_ia32_use_frame(res);
3223 set_ia32_ls_mode(res, lsmode);
3224 add_ia32_am_offs_int(res, offs);
3225 set_ia32_am_support(res, ia32_am_Source);
3226 set_ia32_am_flavour(res, ia32_B);
3227 set_ia32_op_type(res, ia32_AddrModeS);
3228 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3233 /*********************************************************
3236 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3237 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3238 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3239 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3241 *********************************************************/
3244 * the BAD transformer.
3246 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3247 panic("No transform function for %+F available.\n", node);
3251 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3252 /* end has to be duplicated manually because we need a dynamic in array */
3253 ir_graph *irg = env->irg;
3254 dbg_info *dbgi = get_irn_dbg_info(node);
3255 ir_node *block = transform_node(env, get_nodes_block(node));
3259 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3260 copy_node_attr(node, new_end);
3261 duplicate_deps(env, node, new_end);
3263 set_irg_end(irg, new_end);
3264 set_new_node(new_end, new_end);
3266 /* transform preds */
3267 arity = get_irn_arity(node);
3268 for (i = 0; i < arity; ++i) {
3269 ir_node *in = get_irn_n(node, i);
3270 ir_node *new_in = transform_node(env, in);
3272 add_End_keepalive(new_end, new_in);
3278 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3279 ir_graph *irg = env->irg;
3280 dbg_info *dbgi = get_irn_dbg_info(node);
3281 ir_node *start_block = env->old_anchors[anchor_start_block];
3286 * We replace the ProjX from the start node with a jump,
3287 * so the startblock has no preds anymore now
3289 if (node == start_block) {
3290 return new_rd_Block(dbgi, irg, 0, NULL);
3293 /* we use the old blocks for now, because jumps allow cycles in the graph
3294 * we have to fix this later */
3295 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3296 get_irn_arity(node), get_irn_in(node) + 1);
3297 copy_node_attr(node, block);
3299 #ifdef DEBUG_libfirm
3300 block->node_nr = node->node_nr;
3302 set_new_node(node, block);
3304 /* put the preds in the worklist */
3305 arity = get_irn_arity(node);
3306 for (i = 0; i < arity; ++i) {
3307 ir_node *in = get_irn_n(node, i);
3308 pdeq_putr(env->worklist, in);
3314 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3315 ir_node *block = transform_node(env, get_nodes_block(node));
3316 ir_node *pred = get_Proj_pred(node);
3317 ir_node *new_pred = transform_node(env, pred);
3318 ir_graph *irg = env->irg;
3319 dbg_info *dbgi = get_irn_dbg_info(node);
3320 long proj = get_Proj_proj(node);
3322 if (proj == pn_be_AddSP_res) {
3323 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3324 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3326 } else if (proj == pn_be_AddSP_M) {
3327 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3331 return new_rd_Unknown(irg, get_irn_mode(node));
3334 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3335 ir_node *block = transform_node(env, get_nodes_block(node));
3336 ir_node *pred = get_Proj_pred(node);
3337 ir_node *new_pred = transform_node(env, pred);
3338 ir_graph *irg = env->irg;
3339 dbg_info *dbgi = get_irn_dbg_info(node);
3340 long proj = get_Proj_proj(node);
3342 if (proj == pn_be_SubSP_res) {
3343 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3344 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3346 } else if (proj == pn_be_SubSP_M) {
3347 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3351 return new_rd_Unknown(irg, get_irn_mode(node));
3354 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3355 ir_node *block = transform_node(env, get_nodes_block(node));
3356 ir_node *pred = get_Proj_pred(node);
3357 ir_node *new_pred = transform_node(env, pred);
3358 ir_graph *irg = env->irg;
3359 dbg_info *dbgi = get_irn_dbg_info(node);
3360 long proj = get_Proj_proj(node);
3362 /* renumber the proj */
3363 if (is_ia32_Load(new_pred)) {
3364 if (proj == pn_Load_res) {
3365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3366 } else if (proj == pn_Load_M) {
3367 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3369 } else if (is_ia32_xLoad(new_pred)) {
3370 if (proj == pn_Load_res) {
3371 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3372 } else if (proj == pn_Load_M) {
3373 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3375 } else if (is_ia32_vfld(new_pred)) {
3376 if (proj == pn_Load_res) {
3377 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3378 } else if (proj == pn_Load_M) {
3379 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3384 return new_rd_Unknown(irg, get_irn_mode(node));
3387 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3388 ir_node *block = transform_node(env, get_nodes_block(node));
3389 ir_node *pred = get_Proj_pred(node);
3390 ir_node *new_pred = transform_node(env, pred);
3391 ir_graph *irg = env->irg;
3392 dbg_info *dbgi = get_irn_dbg_info(node);
3393 ir_mode *mode = get_irn_mode(node);
3394 long proj = get_Proj_proj(node);
3396 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3398 switch (get_irn_opcode(pred)) {
3402 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3404 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3412 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3414 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3422 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3423 case pn_DivMod_res_div:
3424 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3425 case pn_DivMod_res_mod:
3426 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3436 return new_rd_Unknown(irg, mode);
3439 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) {
3440 ir_node *block = transform_node(env, get_nodes_block(node));
3441 ir_node *pred = get_Proj_pred(node);
3442 ir_node *new_pred = transform_node(env, pred);
3443 ir_graph *irg = env->irg;
3444 dbg_info *dbgi = get_irn_dbg_info(node);
3445 ir_mode *mode = get_irn_mode(node);
3446 long proj = get_Proj_proj(node);
3449 case pn_CopyB_M_regular:
3450 if (is_ia32_CopyB_i(new_pred)) {
3451 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3452 } else if (is_ia32_CopyB(new_pred)) {
3453 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3461 return new_rd_Unknown(irg, mode);
3464 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3465 ir_node *block = transform_node(env, get_nodes_block(node));
3466 ir_node *pred = get_Proj_pred(node);
3467 ir_node *new_pred = transform_node(env, pred);
3468 ir_graph *irg = env->irg;
3469 dbg_info *dbgi = get_irn_dbg_info(node);
3470 ir_mode *mode = get_irn_mode(node);
3471 long proj = get_Proj_proj(node);
3474 case pn_ia32_l_vfdiv_M:
3475 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3476 case pn_ia32_l_vfdiv_res:
3477 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3482 return new_rd_Unknown(irg, mode);
3485 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) {
3486 ir_node *block = transform_node(env, get_nodes_block(node));
3487 ir_node *pred = get_Proj_pred(node);
3488 ir_node *new_pred = transform_node(env, pred);
3489 ir_graph *irg = env->irg;
3490 dbg_info *dbgi = get_irn_dbg_info(node);
3491 ir_mode *mode = get_irn_mode(node);
3492 long proj = get_Proj_proj(node);
3496 if (is_ia32_xDiv(new_pred)) {
3497 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3498 } else if (is_ia32_vfdiv(new_pred)) {
3499 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3503 if (is_ia32_xDiv(new_pred)) {
3504 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3505 } else if (is_ia32_vfdiv(new_pred)) {
3506 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3514 return new_rd_Unknown(irg, mode);
3517 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3518 ir_node *block = transform_node(env, get_nodes_block(node));
3519 ir_graph *irg = env->irg;
3520 dbg_info *dbgi = NULL;
3521 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3526 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3527 ir_node *block = transform_node(env, get_nodes_block(node));
3528 ir_node *call = get_Proj_pred(node);
3529 ir_node *new_call = transform_node(env, call);
3530 ir_graph *irg = env->irg;
3531 dbg_info *dbgi = get_irn_dbg_info(node);
3532 long proj = get_Proj_proj(node);
3533 ir_mode *mode = get_irn_mode(node);
3535 const arch_register_class_t *cls;
3537 /* The following is kinda tricky: If we're using SSE, then we have to
3538 * move the result value of the call in floating point registers to an
3539 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3540 * after the call, we have to make sure to correctly make the
3541 * MemProj and the result Proj use these 2 nodes
3543 if (proj == pn_be_Call_M_regular) {
3544 // get new node for result, are we doing the sse load/store hack?
3545 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3546 ir_node *call_res_new;
3547 ir_node *call_res_pred = NULL;
3549 if (call_res != NULL) {
3550 call_res_new = transform_node(env, call_res);
3551 call_res_pred = get_Proj_pred(call_res_new);
3554 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3555 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3557 assert(is_ia32_xLoad(call_res_pred));
3558 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3561 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env->cg)) {
3563 ir_node *frame = get_irg_frame(irg);
3564 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3566 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3568 const arch_register_class_t *cls;
3570 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3571 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3573 /* store st(0) onto stack */
3574 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3576 set_ia32_ls_mode(fstp, mode);
3577 set_ia32_op_type(fstp, ia32_AddrModeD);
3578 set_ia32_use_frame(fstp);
3579 set_ia32_am_flavour(fstp, ia32_am_B);
3580 set_ia32_am_support(fstp, ia32_am_Dest);
3582 /* load into SSE register */
3583 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3584 set_ia32_ls_mode(sse_load, mode);
3585 set_ia32_op_type(sse_load, ia32_AddrModeS);
3586 set_ia32_use_frame(sse_load);
3587 set_ia32_am_flavour(sse_load, ia32_am_B);
3588 set_ia32_am_support(sse_load, ia32_am_Source);
3590 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3592 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3594 /* get a Proj representing a caller save register */
3595 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3596 assert(is_Proj(p) && "Proj expected.");
3598 /* user of the the proj is the Keep */
3599 p = get_edge_src_irn(get_irn_out_edge_first(p));
3600 assert(be_is_Keep(p) && "Keep expected.");
3602 /* keep the result */
3603 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3604 keepin[0] = sse_load;
3605 be_new_Keep(cls, irg, block, 1, keepin);
3610 /* transform call modes */
3611 if (mode_is_data(mode)) {
3612 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3616 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3619 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3620 ir_graph *irg = env->irg;
3621 dbg_info *dbgi = get_irn_dbg_info(node);
3622 ir_node *pred = get_Proj_pred(node);
3623 long proj = get_Proj_proj(node);
3625 if (is_Store(pred) || be_is_FrameStore(pred)) {
3626 if (proj == pn_Store_M) {
3627 return transform_node(env, pred);
3630 return new_r_Bad(irg);
3632 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3633 return gen_Proj_Load(env, node);
3634 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3635 return gen_Proj_DivMod(env, node);
3636 } else if (is_CopyB(pred)) {
3637 return gen_Proj_CopyB(env, node);
3638 } else if (is_Quot(pred)) {
3639 return gen_Proj_Quot(env, node);
3640 } else if (is_ia32_l_vfdiv(pred)) {
3641 return gen_Proj_l_vfdiv(env, node);
3642 } else if (be_is_SubSP(pred)) {
3643 return gen_Proj_be_SubSP(env, node);
3644 } else if (be_is_AddSP(pred)) {
3645 return gen_Proj_be_AddSP(env, node);
3646 } else if (be_is_Call(pred)) {
3647 return gen_Proj_be_Call(env, node);
3648 } else if (get_irn_op(pred) == op_Start) {
3649 if (proj == pn_Start_X_initial_exec) {
3650 ir_node *block = get_nodes_block(pred);
3653 /* we exchange the ProjX with a jump */
3654 block = transform_node(env, block);
3655 jump = new_rd_Jmp(dbgi, irg, block);
3656 ir_fprintf(stderr, "created jump: %+F\n", jump);
3659 if (node == env->old_anchors[anchor_tls]) {
3660 return gen_Proj_tls(env, node);
3663 ir_node *new_pred = transform_node(env, pred);
3664 ir_node *block = transform_node(env, get_nodes_block(node));
3665 ir_mode *mode = get_irn_mode(node);
3666 if (mode_needs_gp_reg(mode)) {
3667 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3668 get_Proj_proj(node));
3669 #ifdef DEBUG_libfirm
3670 new_proj->node_nr = node->node_nr;
3676 return duplicate_node(env, node);
3680 * Enters all transform functions into the generic pointer
3682 static void register_transformers(void) {
3683 ir_op *op_Max, *op_Min, *op_Mulh;
3685 /* first clear the generic function pointer for all ops */
3686 clear_irp_opcodes_generic_func();
3688 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3689 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3728 /* transform ops from intrinsic lowering */
3748 /* GEN(ia32_l_vfist); TODO */
3750 GEN(ia32_l_X87toSSE);
3751 GEN(ia32_l_SSEtoX87);
3756 /* we should never see these nodes */
3771 /* handle generic backend nodes */
3781 /* set the register for all Unknown nodes */
3784 op_Max = get_op_Max();
3787 op_Min = get_op_Min();
3790 op_Mulh = get_op_Mulh();
3798 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3802 int deps = get_irn_deps(old_node);
3804 for (i = 0; i < deps; ++i) {
3805 ir_node *dep = get_irn_dep(old_node, i);
3806 ir_node *new_dep = transform_node(env, dep);
3808 add_irn_dep(new_node, new_dep);
3812 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3814 ir_node *block = transform_node(env, get_nodes_block(node));
3815 ir_graph *irg = env->irg;
3816 dbg_info *dbgi = get_irn_dbg_info(node);
3817 ir_mode *mode = get_irn_mode(node);
3818 ir_op *op = get_irn_op(node);
3822 arity = get_irn_arity(node);
3823 if (op->opar == oparity_dynamic) {
3824 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3825 for (i = 0; i < arity; ++i) {
3826 ir_node *in = get_irn_n(node, i);
3827 in = transform_node(env, in);
3828 add_irn_n(new_node, in);
3831 ir_node **ins = alloca(arity * sizeof(ins[0]));
3832 for (i = 0; i < arity; ++i) {
3833 ir_node *in = get_irn_n(node, i);
3834 ins[i] = transform_node(env, in);
3837 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3840 copy_node_attr(node, new_node);
3841 duplicate_deps(env, node, new_node);
3843 #ifdef DEBUG_libfirm
3844 new_node->node_nr = node->node_nr;
3851 * Calls transformation function for given node and marks it visited.
3853 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) {
3855 ir_op *op = get_irn_op(node);
3857 if (irn_visited(node)) {
3858 assert(get_new_node(node) != NULL);
3859 return get_new_node(node);
3862 mark_irn_visited(node);
3863 DEBUG_ONLY(set_new_node(node, NULL));
3865 if (op->ops.generic) {
3866 transform_func *transform = (transform_func *)op->ops.generic;
3868 new_node = (*transform)(env, node);
3869 assert(new_node != NULL);
3871 new_node = duplicate_node(env, node);
3873 DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
3875 set_new_node(node, new_node);
3876 mark_irn_visited(new_node);
3877 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3882 * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
3884 static void fix_loops(ia32_transform_env_t *env, ir_node *node) {
3887 if (irn_visited(node))
3890 mark_irn_visited(node);
3892 assert(node_is_in_irgs_storage(env->irg, node));
3894 if (! is_Block(node)) {
3895 ir_node *block = get_nodes_block(node);
3896 ir_node *new_block = (ir_node *)get_irn_link(block);
3898 if (new_block != NULL) {
3899 set_nodes_block(node, new_block);
3903 fix_loops(env, block);
3906 arity = get_irn_arity(node);
3907 for (i = 0; i < arity; ++i) {
3908 ir_node *in = get_irn_n(node, i);
3909 ir_node *nw = (ir_node *)get_irn_link(in);
3911 if (nw != NULL && nw != in) {
3912 set_irn_n(node, i, nw);
3919 arity = get_irn_deps(node);
3920 for (i = 0; i < arity; ++i) {
3921 ir_node *in = get_irn_dep(node, i);
3922 ir_node *nw = (ir_node *)get_irn_link(in);
3924 if (nw != NULL && nw != in) {
3925 set_irn_dep(node, i, nw);
3933 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3938 *place = transform_node(env, *place);
3942 * Transforms all nodes. Deletes the old obstack and creates a new one.
3944 static void transform_nodes(ia32_code_gen_t *cg) {
3946 ir_graph *irg = cg->irg;
3948 ia32_transform_env_t env;
3950 hook_dead_node_elim(irg, 1);
3952 inc_irg_visited(irg);
3956 env.visited = get_irg_visited(irg);
3957 env.worklist = new_pdeq();
3958 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3960 old_end = get_irg_end(irg);
3962 /* put all anchor nodes in the worklist */
3963 for (i = 0; i < anchor_max; ++i) {
3964 ir_node *anchor = irg->anchors[i];
3968 pdeq_putr(env.worklist, anchor);
3970 /* remember anchor */
3971 env.old_anchors[i] = anchor;
3972 /* and set it to NULL to make sure we don't accidently use it */
3973 irg->anchors[i] = NULL;
3976 /* pre transform some anchors (so they are available in the other transform
3978 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3979 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3980 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3981 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3982 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3984 pre_transform_node(&cg->unknown_gp, &env);
3985 pre_transform_node(&cg->unknown_vfp, &env);
3986 pre_transform_node(&cg->unknown_xmm, &env);
3987 pre_transform_node(&cg->noreg_gp, &env);
3988 pre_transform_node(&cg->noreg_vfp, &env);
3989 pre_transform_node(&cg->noreg_xmm, &env);
3991 /* process worklist (this should transform all nodes in the graph) */
3992 while (! pdeq_empty(env.worklist)) {
3993 ir_node *node = pdeq_getl(env.worklist);
3994 transform_node(&env, node);
3997 /* fix loops and set new anchors*/
3998 inc_irg_visited(irg);
3999 for (i = 0; i < anchor_max; ++i) {
4000 ir_node *anchor = env.old_anchors[i];
4005 anchor = get_irn_link(anchor);
4006 fix_loops(&env, anchor);
4007 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4008 irg->anchors[i] = anchor;
4011 del_pdeq(env.worklist);
4013 hook_dead_node_elim(irg, 0);
4016 void ia32_transform_graph(ia32_code_gen_t *cg)
4018 ir_graph *irg = cg->irg;
4019 be_irg_t *birg = cg->birg;
4020 ir_graph *old_current_ir_graph = current_ir_graph;
4021 int old_interprocedural_view = get_interprocedural_view();
4022 struct obstack *old_obst = NULL;
4023 struct obstack *new_obst = NULL;
4025 current_ir_graph = irg;
4026 set_interprocedural_view(0);
4027 register_transformers();
4029 /* most analysis info is wrong after transformation */
4030 free_callee_info(irg);
4032 irg->outs_state = outs_none;
4034 free_loop_information(irg);
4035 set_irg_doms_inconsistent(irg);
4036 be_invalidate_liveness(birg);
4037 be_invalidate_dom_front(birg);
4039 /* create a new obstack */
4040 old_obst = irg->obst;
4041 new_obst = xmalloc(sizeof(*new_obst));
4042 obstack_init(new_obst);
4043 irg->obst = new_obst;
4044 irg->last_node_idx = 0;
4046 /* create new value table for CSE */
4047 del_identities(irg->value_table);
4048 irg->value_table = new_identities();
4050 /* do the main transformation */
4051 transform_nodes(cg);
4053 /* we don't want the globals anchor anymore */
4054 set_irg_globals(irg, new_r_Bad(irg));
4056 /* free the old obstack */
4057 obstack_free(old_obst, 0);
4061 current_ir_graph = old_current_ir_graph;
4062 set_interprocedural_view(old_interprocedural_view);
4064 /* recalculate edges */
4065 edges_deactivate(irg);
4066 edges_activate(irg);
4070 * Transforms a psi condition.
4072 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4075 /* if the mode is target mode, we have already seen this part of the tree */
4076 if (get_irn_mode(cond) == mode)
4079 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4081 set_irn_mode(cond, mode);
4083 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4084 ir_node *in = get_irn_n(cond, i);
4086 /* if in is a compare: transform into Set/xCmp */
4088 ir_node *new_op = NULL;
4089 ir_node *cmp = get_Proj_pred(in);
4090 ir_node *cmp_a = get_Cmp_left(cmp);
4091 ir_node *cmp_b = get_Cmp_right(cmp);
4092 dbg_info *dbgi = get_irn_dbg_info(cmp);
4093 ir_graph *irg = get_irn_irg(cmp);
4094 ir_node *block = get_nodes_block(cmp);
4095 ir_node *noreg = ia32_new_NoReg_gp(cg);
4096 ir_node *nomem = new_rd_NoMem(irg);
4097 int pnc = get_Proj_proj(in);
4099 /* this is a compare */
4100 if (mode_is_float(mode)) {
4101 /* Psi is float, we need a floating point compare */
4104 ir_mode *m = get_irn_mode(cmp_a);
4106 if (! mode_is_float(m)) {
4107 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4108 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4109 } else if (m == mode_F) {
4110 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4111 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4112 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4115 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4116 set_ia32_pncode(new_op, pnc);
4117 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4124 construct_binop_func *set_func = NULL;
4126 if (mode_is_float(get_irn_mode(cmp_a))) {
4127 /* 1st case: compare operands are floats */
4132 set_func = new_rd_ia32_xCmpSet;
4135 set_func = new_rd_ia32_vfCmpSet;
4138 pnc &= 7; /* fp compare -> int compare */
4140 /* 2nd case: compare operand are integer too */
4141 set_func = new_rd_ia32_CmpSet;
4144 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4145 if (! mode_is_signed(mode))
4146 pnc |= ia32_pn_Cmp_Unsigned;
4148 set_ia32_pncode(new_op, pnc);
4149 set_ia32_am_support(new_op, ia32_am_Source);
4152 /* the the new compare as in */
4153 set_irn_n(cond, i, new_op);
4155 /* another complex condition */
4156 transform_psi_cond(in, mode, cg);
4162 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4163 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4164 * each compare, which causes the compare result to be stored in a register. The
4165 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4167 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4168 ia32_code_gen_t *cg = env;
4169 ir_node *psi_sel, *new_cmp, *block;
4174 if (get_irn_opcode(node) != iro_Psi)
4177 psi_sel = get_Psi_cond(node, 0);
4179 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4180 if (is_Proj(psi_sel)) {
4181 assert(is_Cmp(get_Proj_pred(psi_sel)));
4185 //mode = get_irn_mode(node);
4186 // TODO probably wrong...
4189 transform_psi_cond(psi_sel, mode, cg);
4191 irg = get_irn_irg(node);
4192 block = get_nodes_block(node);
4194 /* we need to compare the evaluated condition tree with 0 */
4195 mode = get_irn_mode(node);
4196 if (mode_is_float(mode)) {
4197 /* BEWARE: new_r_Const_long works for floating point as well */
4198 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4200 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4201 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4202 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4204 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4205 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4206 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4209 set_Psi_cond(node, 0, new_cmp);
4212 void ia32_init_transform(void)
4214 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");