2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
563 * Construct a standard binary operation, set AM and immediate if required.
565 * @param op1 The first operand
566 * @param op2 The second operand
567 * @param func The node constructor function
568 * @return The constructed ia32 node.
570 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
571 construct_binop_float_func *func)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_node *new_node = NULL;
577 dbg_info *dbgi = get_irn_dbg_info(node);
578 ir_graph *irg = current_ir_graph;
579 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
580 ir_node *nomem = new_NoMem();
581 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
582 &ia32_fp_cw_regs[REG_FPCW]);
584 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
586 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
587 if (is_op_commutative(get_irn_op(node))) {
588 set_ia32_commutative(new_node);
591 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
597 * Construct a shift/rotate binary operation, sets AM and immediate if required.
599 * @param op1 The first operand
600 * @param op2 The second operand
601 * @param func The node constructor function
602 * @return The constructed ia32 node.
604 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
605 construct_binop_func *func)
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *new_op1 = be_transform_node(op1);
610 ir_node *new_op = NULL;
611 dbg_info *dbgi = get_irn_dbg_info(node);
612 ir_graph *irg = current_ir_graph;
613 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
614 ir_node *nomem = new_NoMem();
616 assert(! mode_is_float(get_irn_mode(node))
617 && "Shift/Rotate with float not supported");
619 new_op2 = create_immediate_or_transform(op2, 'N');
621 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
624 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
626 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
628 set_ia32_emit_cl(new_op);
635 * Construct a standard unary operation, set AM and immediate if required.
637 * @param op The operand
638 * @param func The node constructor function
639 * @return The constructed ia32 node.
641 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
643 ir_node *block = be_transform_node(get_nodes_block(node));
644 ir_node *new_op = be_transform_node(op);
645 ir_node *new_node = NULL;
646 ir_graph *irg = current_ir_graph;
647 dbg_info *dbgi = get_irn_dbg_info(node);
648 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
649 ir_node *nomem = new_NoMem();
651 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
652 DB((dbg, LEVEL_1, "INT unop ..."));
653 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
661 * Creates an ia32 Add.
663 * @return the created ia32 Add node
665 static ir_node *gen_Add(ir_node *node) {
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *op1 = get_Add_left(node);
668 ir_node *new_op1 = be_transform_node(op1);
669 ir_node *op2 = get_Add_right(node);
670 ir_node *new_op2 = be_transform_node(op2);
671 ir_node *new_op = NULL;
672 ir_graph *irg = current_ir_graph;
673 dbg_info *dbgi = get_irn_dbg_info(node);
674 ir_mode *mode = get_irn_mode(node);
675 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
676 ir_node *nomem = new_NoMem();
677 ir_node *expr_op, *imm_op;
679 /* Check if immediate optimization is on and */
680 /* if it's an operation with immediate. */
681 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
682 expr_op = get_expr_op(new_op1, new_op2);
684 assert((expr_op || imm_op) && "invalid operands");
686 if (mode_is_float(mode)) {
688 if (USE_SSE2(env_cg))
689 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
691 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
696 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
697 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
699 /* No expr_op means, that we have two const - one symconst and */
700 /* one tarval or another symconst - because this case is not */
701 /* covered by constant folding */
702 /* We need to check for: */
703 /* 1) symconst + const -> becomes a LEA */
704 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
705 /* linker doesn't support two symconsts */
707 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
708 /* this is the 2nd case */
709 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
710 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
711 set_ia32_am_flavour(new_op, ia32_am_B);
712 set_ia32_op_type(new_op, ia32_AddrModeS);
714 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
715 } else if (tp1 == ia32_ImmSymConst) {
716 tarval *tv = get_ia32_Immop_tarval(new_op2);
717 long offs = get_tarval_long(tv);
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
720 add_irn_dep(new_op, get_irg_frame(irg));
721 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
723 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
724 add_ia32_am_offs_int(new_op, offs);
725 set_ia32_am_flavour(new_op, ia32_am_OB);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
727 } else if (tp2 == ia32_ImmSymConst) {
728 tarval *tv = get_ia32_Immop_tarval(new_op1);
729 long offs = get_tarval_long(tv);
731 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
732 add_irn_dep(new_op, get_irg_frame(irg));
733 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
735 add_ia32_am_offs_int(new_op, offs);
736 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
737 set_ia32_am_flavour(new_op, ia32_am_OB);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
741 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
742 tarval *restv = tarval_add(tv1, tv2);
744 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
746 new_op = new_rd_ia32_Const(dbgi, irg, block);
747 set_ia32_Const_tarval(new_op, restv);
748 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
754 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
755 tarval_classification_t class_tv, class_negtv;
756 tarval *tv = get_ia32_Immop_tarval(imm_op);
758 /* optimize tarvals */
759 class_tv = classify_tarval(tv);
760 class_negtv = classify_tarval(tarval_neg(tv));
762 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
763 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
764 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
767 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
768 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
769 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
770 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
776 /* This is a normal add */
777 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
780 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
781 set_ia32_commutative(new_op);
783 fold_immediate(new_op, 2, 3);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
791 * Creates an ia32 Mul.
793 * @return the created ia32 Mul node
795 static ir_node *gen_Mul(ir_node *node) {
796 ir_node *op1 = get_Mul_left(node);
797 ir_node *op2 = get_Mul_right(node);
798 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode)) {
802 if (USE_SSE2(env_cg))
803 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
805 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
809 for the lower 32bit of the result it doesn't matter whether we use
810 signed or unsigned multiplication so we use IMul as it has fewer
813 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
817 * Creates an ia32 Mulh.
818 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
819 * this result while Mul returns the lower 32 bit.
821 * @return the created ia32 Mulh node
823 static ir_node *gen_Mulh(ir_node *node) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *op1 = get_irn_n(node, 0);
826 ir_node *new_op1 = be_transform_node(op1);
827 ir_node *op2 = get_irn_n(node, 1);
828 ir_node *new_op2 = be_transform_node(op2);
829 ir_graph *irg = current_ir_graph;
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
832 ir_mode *mode = get_irn_mode(node);
833 ir_node *proj_EAX, *proj_EDX, *res;
836 assert(!mode_is_float(mode) && "Mulh with float not supported");
837 if (mode_is_signed(mode)) {
838 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
840 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
843 set_ia32_commutative(res);
844 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
846 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
847 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
851 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
859 * Creates an ia32 And.
861 * @return The created ia32 And node
863 static ir_node *gen_And(ir_node *node) {
864 ir_node *op1 = get_And_left(node);
865 ir_node *op2 = get_And_right(node);
867 assert (! mode_is_float(get_irn_mode(node)));
868 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
874 * Creates an ia32 Or.
876 * @return The created ia32 Or node
878 static ir_node *gen_Or(ir_node *node) {
879 ir_node *op1 = get_Or_left(node);
880 ir_node *op2 = get_Or_right(node);
882 assert (! mode_is_float(get_irn_mode(node)));
883 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
889 * Creates an ia32 Eor.
891 * @return The created ia32 Eor node
893 static ir_node *gen_Eor(ir_node *node) {
894 ir_node *op1 = get_Eor_left(node);
895 ir_node *op2 = get_Eor_right(node);
897 assert(! mode_is_float(get_irn_mode(node)));
898 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
903 * Creates an ia32 Sub.
905 * @return The created ia32 Sub node
907 static ir_node *gen_Sub(ir_node *node) {
908 ir_node *block = be_transform_node(get_nodes_block(node));
909 ir_node *op1 = get_Sub_left(node);
910 ir_node *new_op1 = be_transform_node(op1);
911 ir_node *op2 = get_Sub_right(node);
912 ir_node *new_op2 = be_transform_node(op2);
913 ir_node *new_op = NULL;
914 ir_graph *irg = current_ir_graph;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_mode *mode = get_irn_mode(node);
917 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
918 ir_node *nomem = new_NoMem();
919 ir_node *expr_op, *imm_op;
921 /* Check if immediate optimization is on and */
922 /* if it's an operation with immediate. */
923 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
924 expr_op = get_expr_op(new_op1, new_op2);
926 assert((expr_op || imm_op) && "invalid operands");
928 if (mode_is_float(mode)) {
930 if (USE_SSE2(env_cg))
931 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
933 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
938 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
939 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
941 /* No expr_op means, that we have two const - one symconst and */
942 /* one tarval or another symconst - because this case is not */
943 /* covered by constant folding */
944 /* We need to check for: */
945 /* 1) symconst - const -> becomes a LEA */
946 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
947 /* linker doesn't support two symconsts */
948 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
949 /* this is the 2nd case */
950 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
951 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
952 set_ia32_am_sc_sign(new_op);
953 set_ia32_am_flavour(new_op, ia32_am_B);
955 DBG_OPT_LEA3(op1, op2, node, new_op);
956 } else if (tp1 == ia32_ImmSymConst) {
957 tarval *tv = get_ia32_Immop_tarval(new_op2);
958 long offs = get_tarval_long(tv);
960 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
961 add_irn_dep(new_op, get_irg_frame(irg));
962 DBG_OPT_LEA3(op1, op2, node, new_op);
964 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
965 add_ia32_am_offs_int(new_op, -offs);
966 set_ia32_am_flavour(new_op, ia32_am_OB);
967 set_ia32_op_type(new_op, ia32_AddrModeS);
968 } else if (tp2 == ia32_ImmSymConst) {
969 tarval *tv = get_ia32_Immop_tarval(new_op1);
970 long offs = get_tarval_long(tv);
972 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
973 add_irn_dep(new_op, get_irg_frame(irg));
974 DBG_OPT_LEA3(op1, op2, node, new_op);
976 add_ia32_am_offs_int(new_op, offs);
977 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
978 set_ia32_am_sc_sign(new_op);
979 set_ia32_am_flavour(new_op, ia32_am_OB);
980 set_ia32_op_type(new_op, ia32_AddrModeS);
982 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
983 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
984 tarval *restv = tarval_sub(tv1, tv2);
986 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
988 new_op = new_rd_ia32_Const(dbgi, irg, block);
989 set_ia32_Const_tarval(new_op, restv);
990 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
993 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
996 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
997 tarval_classification_t class_tv, class_negtv;
998 tarval *tv = get_ia32_Immop_tarval(imm_op);
1000 /* optimize tarvals */
1001 class_tv = classify_tarval(tv);
1002 class_negtv = classify_tarval(tarval_neg(tv));
1004 if (class_tv == TV_CLASSIFY_ONE) {
1005 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1006 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1007 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1009 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1010 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1011 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1018 /* This is a normal sub */
1019 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1021 /* set AM support */
1022 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1024 fold_immediate(new_op, 2, 3);
1026 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1034 * Generates an ia32 DivMod with additional infrastructure for the
1035 * register allocator if needed.
1037 * @param dividend -no comment- :)
1038 * @param divisor -no comment- :)
1039 * @param dm_flav flavour_Div/Mod/DivMod
1040 * @return The created ia32 DivMod node
1042 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1043 ir_node *divisor, ia32_op_flavour_t dm_flav)
1045 ir_node *block = be_transform_node(get_nodes_block(node));
1046 ir_node *new_dividend = be_transform_node(dividend);
1047 ir_node *new_divisor = be_transform_node(divisor);
1048 ir_graph *irg = current_ir_graph;
1049 dbg_info *dbgi = get_irn_dbg_info(node);
1050 ir_mode *mode = get_irn_mode(node);
1051 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1052 ir_node *res, *proj_div, *proj_mod;
1053 ir_node *sign_extension;
1054 ir_node *in_keep[2];
1055 ir_node *mem, *new_mem;
1056 ir_node *projs[pn_DivMod_max];
1059 ia32_collect_Projs(node, projs, pn_DivMod_max);
1061 proj_div = proj_mod = NULL;
1065 mem = get_Div_mem(node);
1066 mode = get_Div_resmode(node);
1067 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1068 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1071 mem = get_Mod_mem(node);
1072 mode = get_Mod_resmode(node);
1073 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1074 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1076 case flavour_DivMod:
1077 mem = get_DivMod_mem(node);
1078 mode = get_DivMod_resmode(node);
1079 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1080 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1081 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1084 panic("invalid divmod flavour!");
1086 new_mem = be_transform_node(mem);
1088 if (mode_is_signed(mode)) {
1089 /* in signed mode, we need to sign extend the dividend */
1090 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1092 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1093 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1095 add_irn_dep(sign_extension, get_irg_frame(irg));
1098 if (mode_is_signed(mode)) {
1099 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1100 sign_extension, new_divisor, new_mem, dm_flav);
1102 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1103 sign_extension, new_divisor, new_mem, dm_flav);
1106 set_ia32_exc_label(res, has_exc);
1107 set_irn_pinned(res, get_irn_pinned(node));
1109 /* Matze: code can't handle this at the moment... */
1111 /* set AM support */
1112 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1115 /* check, which Proj-Keep, we need to add */
1117 if (proj_div == NULL) {
1118 /* We have only mod result: add div res Proj-Keep */
1119 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1122 if (proj_mod == NULL) {
1123 /* We have only div result: add mod res Proj-Keep */
1124 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1128 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1130 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1137 * Wrapper for generate_DivMod. Sets flavour_Mod.
1140 static ir_node *gen_Mod(ir_node *node) {
1141 return generate_DivMod(node, get_Mod_left(node),
1142 get_Mod_right(node), flavour_Mod);
1146 * Wrapper for generate_DivMod. Sets flavour_Div.
1149 static ir_node *gen_Div(ir_node *node) {
1150 return generate_DivMod(node, get_Div_left(node),
1151 get_Div_right(node), flavour_Div);
1155 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1157 static ir_node *gen_DivMod(ir_node *node) {
1158 return generate_DivMod(node, get_DivMod_left(node),
1159 get_DivMod_right(node), flavour_DivMod);
1165 * Creates an ia32 floating Div.
1167 * @return The created ia32 xDiv node
1169 static ir_node *gen_Quot(ir_node *node) {
1170 ir_node *block = be_transform_node(get_nodes_block(node));
1171 ir_node *op1 = get_Quot_left(node);
1172 ir_node *new_op1 = be_transform_node(op1);
1173 ir_node *op2 = get_Quot_right(node);
1174 ir_node *new_op2 = be_transform_node(op2);
1175 ir_graph *irg = current_ir_graph;
1176 dbg_info *dbgi = get_irn_dbg_info(node);
1177 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1178 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1182 if (USE_SSE2(env_cg)) {
1183 ir_mode *mode = get_irn_mode(op1);
1184 if (is_ia32_xConst(new_op2)) {
1185 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1186 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1187 copy_ia32_Immop_attr(new_op, new_op2);
1189 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1190 // Matze: disabled for now, spillslot coalescer fails
1191 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1193 set_ia32_ls_mode(new_op, mode);
1195 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1196 &ia32_fp_cw_regs[REG_FPCW]);
1197 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1198 new_op2, nomem, fpcw);
1199 // Matze: disabled for now (spillslot coalescer fails)
1200 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1202 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1208 * Creates an ia32 Shl.
1210 * @return The created ia32 Shl node
1212 static ir_node *gen_Shl(ir_node *node) {
1213 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1220 * Creates an ia32 Shr.
1222 * @return The created ia32 Shr node
1224 static ir_node *gen_Shr(ir_node *node) {
1225 return gen_shift_binop(node, get_Shr_left(node),
1226 get_Shr_right(node), new_rd_ia32_Shr);
1232 * Creates an ia32 Sar.
1234 * @return The created ia32 Shrs node
1236 static ir_node *gen_Shrs(ir_node *node) {
1237 ir_node *left = get_Shrs_left(node);
1238 ir_node *right = get_Shrs_right(node);
1239 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1240 tarval *tv = get_Const_tarval(right);
1241 long val = get_tarval_long(tv);
1243 /* this is a sign extension */
1244 ir_graph *irg = current_ir_graph;
1245 dbg_info *dbgi = get_irn_dbg_info(node);
1246 ir_node *block = be_transform_node(get_nodes_block(node));
1248 ir_node *new_op = be_transform_node(op);
1250 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1254 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1260 * Creates an ia32 RotL.
1262 * @param op1 The first operator
1263 * @param op2 The second operator
1264 * @return The created ia32 RotL node
1266 static ir_node *gen_RotL(ir_node *node,
1267 ir_node *op1, ir_node *op2) {
1268 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1274 * Creates an ia32 RotR.
1275 * NOTE: There is no RotR with immediate because this would always be a RotL
1276 * "imm-mode_size_bits" which can be pre-calculated.
1278 * @param op1 The first operator
1279 * @param op2 The second operator
1280 * @return The created ia32 RotR node
1282 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1284 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1290 * Creates an ia32 RotR or RotL (depending on the found pattern).
1292 * @return The created ia32 RotL or RotR node
1294 static ir_node *gen_Rot(ir_node *node) {
1295 ir_node *rotate = NULL;
1296 ir_node *op1 = get_Rot_left(node);
1297 ir_node *op2 = get_Rot_right(node);
1299 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1300 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1301 that means we can create a RotR instead of an Add and a RotL */
1303 if (get_irn_op(op2) == op_Add) {
1305 ir_node *left = get_Add_left(add);
1306 ir_node *right = get_Add_right(add);
1307 if (is_Const(right)) {
1308 tarval *tv = get_Const_tarval(right);
1309 ir_mode *mode = get_irn_mode(node);
1310 long bits = get_mode_size_bits(mode);
1312 if (get_irn_op(left) == op_Minus &&
1313 tarval_is_long(tv) &&
1314 get_tarval_long(tv) == bits)
1316 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1317 rotate = gen_RotR(node, op1, get_Minus_op(left));
1322 if (rotate == NULL) {
1323 rotate = gen_RotL(node, op1, op2);
1332 * Transforms a Minus node.
1334 * @param op The Minus operand
1335 * @return The created ia32 Minus node
1337 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1338 ir_node *block = be_transform_node(get_nodes_block(node));
1339 ir_graph *irg = current_ir_graph;
1340 dbg_info *dbgi = get_irn_dbg_info(node);
1341 ir_mode *mode = get_irn_mode(node);
1346 if (mode_is_float(mode)) {
1347 ir_node *new_op = be_transform_node(op);
1349 if (USE_SSE2(env_cg)) {
1350 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1351 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1352 ir_node *nomem = new_rd_NoMem(irg);
1354 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1356 size = get_mode_size_bits(mode);
1357 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1359 set_ia32_am_sc(res, ent);
1360 set_ia32_op_type(res, ia32_AddrModeS);
1361 set_ia32_ls_mode(res, mode);
1363 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1366 res = gen_unop(node, op, new_rd_ia32_Neg);
1369 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1375 * Transforms a Minus node.
1377 * @return The created ia32 Minus node
1379 static ir_node *gen_Minus(ir_node *node) {
1380 return gen_Minus_ex(node, get_Minus_op(node));
1385 * Transforms a Not node.
1387 * @return The created ia32 Not node
1389 static ir_node *gen_Not(ir_node *node) {
1390 ir_node *op = get_Not_op(node);
1392 assert (! mode_is_float(get_irn_mode(node)));
1393 return gen_unop(node, op, new_rd_ia32_Not);
1399 * Transforms an Abs node.
1401 * @return The created ia32 Abs node
1403 static ir_node *gen_Abs(ir_node *node) {
1404 ir_node *block = be_transform_node(get_nodes_block(node));
1405 ir_node *op = get_Abs_op(node);
1406 ir_node *new_op = be_transform_node(op);
1407 ir_graph *irg = current_ir_graph;
1408 dbg_info *dbgi = get_irn_dbg_info(node);
1409 ir_mode *mode = get_irn_mode(node);
1410 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1411 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1412 ir_node *nomem = new_NoMem();
1417 if (mode_is_float(mode)) {
1419 if (USE_SSE2(env_cg)) {
1420 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1422 size = get_mode_size_bits(mode);
1423 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1425 set_ia32_am_sc(res, ent);
1427 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1429 set_ia32_op_type(res, ia32_AddrModeS);
1430 set_ia32_ls_mode(res, mode);
1433 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1434 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1438 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1439 SET_IA32_ORIG_NODE(sign_extension,
1440 ia32_get_old_node_name(env_cg, node));
1442 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1443 sign_extension, nomem);
1444 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1446 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1447 sign_extension, nomem);
1448 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1457 * Transforms a Load.
1459 * @return the created ia32 Load node
1461 static ir_node *gen_Load(ir_node *node) {
1462 ir_node *block = be_transform_node(get_nodes_block(node));
1463 ir_node *ptr = get_Load_ptr(node);
1464 ir_node *new_ptr = be_transform_node(ptr);
1465 ir_node *mem = get_Load_mem(node);
1466 ir_node *new_mem = be_transform_node(mem);
1467 ir_graph *irg = current_ir_graph;
1468 dbg_info *dbgi = get_irn_dbg_info(node);
1469 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1470 ir_mode *mode = get_Load_mode(node);
1472 ir_node *lptr = new_ptr;
1475 ir_node *projs[pn_Load_max];
1476 ia32_am_flavour_t am_flav = ia32_am_B;
1478 ia32_collect_Projs(node, projs, pn_Load_max);
1480 /* address might be a constant (symconst or absolute address) */
1481 if (is_ia32_Const(new_ptr)) {
1486 if (mode_is_float(mode)) {
1488 if (USE_SSE2(env_cg)) {
1489 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1490 res_mode = mode_xmm;
1492 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1493 res_mode = mode_vfp;
1496 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1501 check for special case: the loaded value might not be used
1503 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1504 /* add a result proj and a Keep to produce a pseudo use */
1505 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1507 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1510 /* base is a constant address */
1512 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1513 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1514 am_flav = ia32_am_N;
1516 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1517 long offs = get_tarval_long(tv);
1519 add_ia32_am_offs_int(new_op, offs);
1520 am_flav = ia32_am_O;
1524 set_irn_pinned(new_op, get_irn_pinned(node));
1525 set_ia32_op_type(new_op, ia32_AddrModeS);
1526 set_ia32_am_flavour(new_op, am_flav);
1527 set_ia32_ls_mode(new_op, mode);
1529 /* make sure we are scheduled behind the initial IncSP/Barrier
1530 * to avoid spills being placed before it
1532 if (block == get_irg_start_block(irg)) {
1533 add_irn_dep(new_op, get_irg_frame(irg));
1536 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1537 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1545 * Transforms a Store.
1547 * @return the created ia32 Store node
1549 static ir_node *gen_Store(ir_node *node) {
1550 ir_node *block = be_transform_node(get_nodes_block(node));
1551 ir_node *ptr = get_Store_ptr(node);
1552 ir_node *new_ptr = be_transform_node(ptr);
1553 ir_node *val = get_Store_value(node);
1555 ir_node *mem = get_Store_mem(node);
1556 ir_node *new_mem = be_transform_node(mem);
1557 ir_graph *irg = current_ir_graph;
1558 dbg_info *dbgi = get_irn_dbg_info(node);
1559 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1560 ir_node *sptr = new_ptr;
1561 ir_mode *mode = get_irn_mode(val);
1564 ia32_am_flavour_t am_flav = ia32_am_B;
1566 /* address might be a constant (symconst or absolute address) */
1567 if (is_ia32_Const(new_ptr)) {
1572 if (mode_is_float(mode)) {
1575 new_val = be_transform_node(val);
1576 if (USE_SSE2(env_cg)) {
1577 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1580 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1584 new_val = create_immediate_or_transform(val, 0);
1586 if (get_mode_size_bits(mode) == 8) {
1587 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1590 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1595 /* base is an constant address */
1597 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1598 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1599 am_flav = ia32_am_N;
1601 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1602 long offs = get_tarval_long(tv);
1604 add_ia32_am_offs_int(new_op, offs);
1605 am_flav = ia32_am_O;
1609 set_irn_pinned(new_op, get_irn_pinned(node));
1610 set_ia32_op_type(new_op, ia32_AddrModeD);
1611 set_ia32_am_flavour(new_op, am_flav);
1612 set_ia32_ls_mode(new_op, mode);
1614 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1615 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1620 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1622 ir_node *cmp_left = get_Cmp_left(node);
1623 ir_node *new_cmp_left;
1624 ir_node *cmp_right = get_Cmp_right(node);
1625 ir_node *new_cmp_right;
1632 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1634 if(!is_Const_0(cmp_right))
1637 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1638 and_left = get_And_left(cmp_left);
1639 and_right = get_And_right(cmp_left);
1641 new_cmp_left = be_transform_node(and_left);
1642 new_cmp_right = create_immediate_or_transform(and_right, 0);
1644 new_cmp_left = be_transform_node(cmp_left);
1645 new_cmp_right = be_transform_node(cmp_left);
1648 dbgi = get_irn_dbg_info(node);
1649 noreg = ia32_new_NoReg_gp(env_cg);
1650 nomem = new_NoMem();
1652 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1653 new_cmp_left, new_cmp_right, nomem, pnc);
1654 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1655 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1660 static ir_node *create_Switch(ir_node *node)
1662 ir_graph *irg = current_ir_graph;
1663 dbg_info *dbgi = get_irn_dbg_info(node);
1664 ir_node *block = be_transform_node(get_nodes_block(node));
1665 ir_node *sel = get_Cond_selector(node);
1666 ir_node *new_sel = be_transform_node(sel);
1668 int switch_min = INT_MAX;
1669 const ir_edge_t *edge;
1671 /* determine the smallest switch case value */
1672 foreach_out_edge(node, edge) {
1673 ir_node *proj = get_edge_src_irn(edge);
1674 int pn = get_Proj_proj(proj);
1679 if (switch_min != 0) {
1680 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1682 /* if smallest switch case is not 0 we need an additional sub */
1683 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1684 add_ia32_am_offs_int(new_sel, -switch_min);
1685 set_ia32_am_flavour(new_sel, ia32_am_OB);
1686 set_ia32_op_type(new_sel, ia32_AddrModeS);
1688 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1691 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1692 set_ia32_pncode(res, get_Cond_defaultProj(node));
1694 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1700 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1702 * @return The transformed node.
1704 static ir_node *gen_Cond(ir_node *node) {
1705 ir_node *block = be_transform_node(get_nodes_block(node));
1706 ir_graph *irg = current_ir_graph;
1707 dbg_info *dbgi = get_irn_dbg_info(node);
1708 ir_node *sel = get_Cond_selector(node);
1709 ir_mode *sel_mode = get_irn_mode(sel);
1710 ir_node *res = NULL;
1711 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1718 ir_node *nomem = new_NoMem();
1721 if (sel_mode != mode_b) {
1722 return create_Switch(node);
1725 cmp = get_Proj_pred(sel);
1726 cmp_a = get_Cmp_left(cmp);
1727 cmp_b = get_Cmp_right(cmp);
1728 cmp_mode = get_irn_mode(cmp_a);
1729 pnc = get_Proj_proj(sel);
1730 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1731 pnc |= ia32_pn_Cmp_Unsigned;
1734 if(mode_needs_gp_reg(cmp_mode)) {
1735 res = try_create_TestJmp(block, cmp, pnc);
1740 new_cmp_a = be_transform_node(cmp_a);
1741 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1743 if (mode_is_float(cmp_mode)) {
1745 if (USE_SSE2(env_cg)) {
1746 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1748 set_ia32_commutative(res);
1749 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1750 set_ia32_ls_mode(res, cmp_mode);
1753 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1754 set_ia32_commutative(res);
1755 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1756 pn_ia32_vfCondJmp_temp_reg_eax);
1757 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1761 assert(get_mode_size_bits(cmp_mode) == 32);
1762 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1763 new_cmp_a, new_cmp_b, nomem, pnc);
1764 set_ia32_commutative(res);
1765 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1768 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1776 * Transforms a CopyB node.
1778 * @return The transformed node.
1780 static ir_node *gen_CopyB(ir_node *node) {
1781 ir_node *block = be_transform_node(get_nodes_block(node));
1782 ir_node *src = get_CopyB_src(node);
1783 ir_node *new_src = be_transform_node(src);
1784 ir_node *dst = get_CopyB_dst(node);
1785 ir_node *new_dst = be_transform_node(dst);
1786 ir_node *mem = get_CopyB_mem(node);
1787 ir_node *new_mem = be_transform_node(mem);
1788 ir_node *res = NULL;
1789 ir_graph *irg = current_ir_graph;
1790 dbg_info *dbgi = get_irn_dbg_info(node);
1791 int size = get_type_size_bytes(get_CopyB_type(node));
1792 ir_mode *dst_mode = get_irn_mode(dst);
1793 ir_mode *src_mode = get_irn_mode(src);
1797 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1798 /* then we need the size explicitly in ECX. */
1799 if (size >= 32 * 4) {
1800 rem = size & 0x3; /* size % 4 */
1803 res = new_rd_ia32_Const(dbgi, irg, block);
1804 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1805 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1807 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1808 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1810 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1811 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1812 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1813 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1814 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1817 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1818 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1820 /* ok: now attach Proj's because movsd will destroy esi and edi */
1821 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1822 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1823 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1826 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1832 ir_node *gen_be_Copy(ir_node *node)
1834 ir_node *result = be_duplicate_node(node);
1835 ir_mode *mode = get_irn_mode(result);
1837 if (mode_needs_gp_reg(mode)) {
1838 set_irn_mode(result, mode_Iu);
1847 * Transforms a Mux node into CMov.
1849 * @return The transformed node.
1851 static ir_node *gen_Mux(ir_node *node) {
1852 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1853 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1855 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1861 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1862 dbg_info *dbgi, ir_node *block)
1864 ir_graph *irg = current_ir_graph;
1865 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1866 ir_node *nomem = new_rd_NoMem(irg);
1867 ir_node *new_cmp_left;
1868 ir_node *new_cmp_right;
1871 /* can we use a test instruction? */
1872 if(is_Const_0(cmp_right)) {
1873 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1874 if(is_And(cmp_left) &&
1875 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1876 ir_node *and_left = get_And_left(cmp_left);
1877 ir_node *and_right = get_And_right(cmp_left);
1879 new_cmp_left = be_transform_node(and_left);
1880 new_cmp_right = create_immediate_or_transform(and_right, 0);
1882 new_cmp_left = be_transform_node(cmp_left);
1883 new_cmp_right = be_transform_node(cmp_left);
1886 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1887 new_cmp_left, new_cmp_right, nomem, pnc);
1888 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1893 new_cmp_left = be_transform_node(cmp_left);
1894 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1895 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1896 new_cmp_left, new_cmp_right, nomem, pnc);
1901 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1902 ir_node *val_true, ir_node *val_false,
1903 dbg_info *dbgi, ir_node *block)
1905 ir_graph *irg = current_ir_graph;
1906 ir_node *new_val_true = be_transform_node(val_true);
1907 ir_node *new_val_false = be_transform_node(val_false);
1908 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1909 ir_node *nomem = new_NoMem();
1910 ir_node *new_cmp_left;
1911 ir_node *new_cmp_right;
1914 /* can we use a test instruction? */
1915 if(is_Const_0(cmp_right)) {
1916 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1917 if(is_And(cmp_left) &&
1918 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1919 ir_node *and_left = get_And_left(cmp_left);
1920 ir_node *and_right = get_And_right(cmp_left);
1922 new_cmp_left = be_transform_node(and_left);
1923 new_cmp_right = create_immediate_or_transform(and_right, 0);
1925 new_cmp_left = be_transform_node(cmp_left);
1926 new_cmp_right = be_transform_node(cmp_left);
1929 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1930 new_cmp_left, new_cmp_right, nomem,
1931 new_val_true, new_val_false, pnc);
1932 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1937 new_cmp_left = be_transform_node(cmp_left);
1938 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1940 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1941 new_cmp_right, nomem, new_val_true, new_val_false,
1943 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1950 * Transforms a Psi node into CMov.
1952 * @return The transformed node.
1954 static ir_node *gen_Psi(ir_node *node) {
1955 ir_node *psi_true = get_Psi_val(node, 0);
1956 ir_node *psi_default = get_Psi_default(node);
1957 ia32_code_gen_t *cg = env_cg;
1958 ir_node *cond = get_Psi_cond(node, 0);
1959 ir_node *block = be_transform_node(get_nodes_block(node));
1960 dbg_info *dbgi = get_irn_dbg_info(node);
1967 assert(get_Psi_n_conds(node) == 1);
1968 assert(get_irn_mode(cond) == mode_b);
1970 if(is_And(cond) || is_Or(cond)) {
1971 /* this is a psi with a complicated condition, we have to compare it
1974 cmp_right = new_Const_long(mode_Iu, 0);
1978 ir_node *cmp = get_Proj_pred(cond);
1980 cmp_left = get_Cmp_left(cmp);
1981 cmp_right = get_Cmp_right(cmp);
1982 cmp_mode = get_irn_mode(cmp_left);
1983 pnc = get_Proj_proj(cond);
1985 assert(!mode_is_float(cmp_mode));
1987 if (!mode_is_signed(cmp_mode)) {
1988 pnc |= ia32_pn_Cmp_Unsigned;
1993 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1994 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1995 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1996 pnc = get_negated_pnc(pnc, cmp_mode);
1997 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2000 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2003 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2009 * Following conversion rules apply:
2013 * 1) n bit -> m bit n > m (downscale)
2015 * 2) n bit -> m bit n == m (sign change)
2017 * 3) n bit -> m bit n < m (upscale)
2018 * a) source is signed: movsx
2019 * b) source is unsigned: and with lower bits sets
2023 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2027 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2031 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2032 * x87 is mode_E internally, conversions happen only at load and store
2033 * in non-strict semantic
2037 * Create a conversion from x87 state register to general purpose.
2039 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2040 ir_node *block = be_transform_node(get_nodes_block(node));
2041 ir_node *op = get_Conv_op(node);
2042 ir_node *new_op = be_transform_node(op);
2043 ia32_code_gen_t *cg = env_cg;
2044 ir_graph *irg = current_ir_graph;
2045 dbg_info *dbgi = get_irn_dbg_info(node);
2046 ir_node *noreg = ia32_new_NoReg_gp(cg);
2047 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2048 ir_node *fist, *load;
2051 fist = new_rd_ia32_vfist(dbgi, irg, block,
2052 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2054 set_irn_pinned(fist, op_pin_state_floats);
2055 set_ia32_use_frame(fist);
2056 set_ia32_op_type(fist, ia32_AddrModeD);
2057 set_ia32_am_flavour(fist, ia32_am_B);
2058 set_ia32_ls_mode(fist, mode_Iu);
2059 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2062 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2064 set_irn_pinned(load, op_pin_state_floats);
2065 set_ia32_use_frame(load);
2066 set_ia32_op_type(load, ia32_AddrModeS);
2067 set_ia32_am_flavour(load, ia32_am_B);
2068 set_ia32_ls_mode(load, mode_Iu);
2069 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2071 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2075 * Create a conversion from general purpose to x87 register
2077 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2078 ir_node *block = be_transform_node(get_nodes_block(node));
2079 ir_node *op = get_Conv_op(node);
2080 ir_node *new_op = be_transform_node(op);
2081 ir_graph *irg = current_ir_graph;
2082 dbg_info *dbgi = get_irn_dbg_info(node);
2083 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2084 ir_node *nomem = new_NoMem();
2085 ir_node *fild, *store;
2088 /* first convert to 32 bit if necessary */
2089 src_bits = get_mode_size_bits(src_mode);
2090 if (src_bits == 8) {
2091 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2092 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2093 set_ia32_ls_mode(new_op, src_mode);
2094 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2095 } else if (src_bits < 32) {
2096 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2097 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2098 set_ia32_ls_mode(new_op, src_mode);
2099 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2103 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2105 set_ia32_use_frame(store);
2106 set_ia32_op_type(store, ia32_AddrModeD);
2107 set_ia32_am_flavour(store, ia32_am_OB);
2108 set_ia32_ls_mode(store, mode_Iu);
2111 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2113 set_ia32_use_frame(fild);
2114 set_ia32_op_type(fild, ia32_AddrModeS);
2115 set_ia32_am_flavour(fild, ia32_am_OB);
2116 set_ia32_ls_mode(fild, mode_Iu);
2118 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2121 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2124 ir_node *block = get_nodes_block(node);
2125 ir_graph *irg = current_ir_graph;
2126 dbg_info *dbgi = get_irn_dbg_info(node);
2127 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2128 ir_node *nomem = new_NoMem();
2129 int src_bits = get_mode_size_bits(src_mode);
2130 int tgt_bits = get_mode_size_bits(tgt_mode);
2131 ir_node *frame = get_irg_frame(irg);
2132 ir_mode *smaller_mode;
2133 ir_node *store, *load;
2136 if(src_bits <= tgt_bits)
2137 smaller_mode = src_mode;
2139 smaller_mode = tgt_mode;
2141 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2143 set_ia32_use_frame(store);
2144 set_ia32_op_type(store, ia32_AddrModeD);
2145 set_ia32_am_flavour(store, ia32_am_OB);
2147 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2149 set_ia32_use_frame(load);
2150 set_ia32_op_type(load, ia32_AddrModeS);
2151 set_ia32_am_flavour(load, ia32_am_OB);
2153 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2158 * Transforms a Conv node.
2160 * @return The created ia32 Conv node
2162 static ir_node *gen_Conv(ir_node *node) {
2163 ir_node *block = be_transform_node(get_nodes_block(node));
2164 ir_node *op = get_Conv_op(node);
2165 ir_node *new_op = be_transform_node(op);
2166 ir_graph *irg = current_ir_graph;
2167 dbg_info *dbgi = get_irn_dbg_info(node);
2168 ir_mode *src_mode = get_irn_mode(op);
2169 ir_mode *tgt_mode = get_irn_mode(node);
2170 int src_bits = get_mode_size_bits(src_mode);
2171 int tgt_bits = get_mode_size_bits(tgt_mode);
2172 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2173 ir_node *nomem = new_rd_NoMem(irg);
2176 if (src_mode == tgt_mode) {
2177 if (get_Conv_strict(node)) {
2178 if (USE_SSE2(env_cg)) {
2179 /* when we are in SSE mode, we can kill all strict no-op conversion */
2183 /* this should be optimized already, but who knows... */
2184 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2185 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2190 if (mode_is_float(src_mode)) {
2191 /* we convert from float ... */
2192 if (mode_is_float(tgt_mode)) {
2193 if(src_mode == mode_E && tgt_mode == mode_D
2194 && !get_Conv_strict(node)) {
2195 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2200 if (USE_SSE2(env_cg)) {
2201 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2202 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2203 set_ia32_ls_mode(res, tgt_mode);
2205 // Matze: TODO what about strict convs?
2206 if(get_Conv_strict(node)) {
2207 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2208 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2211 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2216 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2217 if (USE_SSE2(env_cg)) {
2218 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2219 set_ia32_ls_mode(res, src_mode);
2221 return gen_x87_fp_to_gp(node);
2225 /* we convert from int ... */
2226 if (mode_is_float(tgt_mode)) {
2229 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2230 if (USE_SSE2(env_cg)) {
2231 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2232 set_ia32_ls_mode(res, tgt_mode);
2233 if(src_bits == 32) {
2234 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2237 return gen_x87_gp_to_fp(node, src_mode);
2241 ir_mode *smaller_mode;
2244 if (src_bits == tgt_bits) {
2245 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2249 if (src_bits < tgt_bits) {
2250 smaller_mode = src_mode;
2251 smaller_bits = src_bits;
2253 smaller_mode = tgt_mode;
2254 smaller_bits = tgt_bits;
2257 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2258 if (smaller_bits == 8) {
2259 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2260 set_ia32_ls_mode(res, smaller_mode);
2262 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2263 set_ia32_ls_mode(res, smaller_mode);
2265 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2269 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2275 int check_immediate_constraint(long val, char immediate_constraint_type)
2277 switch (immediate_constraint_type) {
2281 return val >= 0 && val <= 32;
2283 return val >= 0 && val <= 63;
2285 return val >= -128 && val <= 127;
2287 return val == 0xff || val == 0xffff;
2289 return val >= 0 && val <= 3;
2291 return val >= 0 && val <= 255;
2293 return val >= 0 && val <= 127;
2297 panic("Invalid immediate constraint found");
2302 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2305 tarval *offset = NULL;
2306 int offset_sign = 0;
2308 ir_entity *symconst_ent = NULL;
2309 int symconst_sign = 0;
2311 ir_node *cnst = NULL;
2312 ir_node *symconst = NULL;
2318 mode = get_irn_mode(node);
2319 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2320 !mode_is_reference(mode)) {
2324 if(is_Minus(node)) {
2326 node = get_Minus_op(node);
2329 if(is_Const(node)) {
2332 offset_sign = minus;
2333 } else if(is_SymConst(node)) {
2336 symconst_sign = minus;
2337 } else if(is_Add(node)) {
2338 ir_node *left = get_Add_left(node);
2339 ir_node *right = get_Add_right(node);
2340 if(is_Const(left) && is_SymConst(right)) {
2343 symconst_sign = minus;
2344 offset_sign = minus;
2345 } else if(is_SymConst(left) && is_Const(right)) {
2348 symconst_sign = minus;
2349 offset_sign = minus;
2351 } else if(is_Sub(node)) {
2352 ir_node *left = get_Sub_left(node);
2353 ir_node *right = get_Sub_right(node);
2354 if(is_Const(left) && is_SymConst(right)) {
2357 symconst_sign = !minus;
2358 offset_sign = minus;
2359 } else if(is_SymConst(left) && is_Const(right)) {
2362 symconst_sign = minus;
2363 offset_sign = !minus;
2370 offset = get_Const_tarval(cnst);
2371 if(tarval_is_long(offset)) {
2372 val = get_tarval_long(offset);
2373 } else if(tarval_is_null(offset)) {
2376 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2381 if(!check_immediate_constraint(val, immediate_constraint_type))
2384 if(symconst != NULL) {
2385 if(immediate_constraint_type != 0) {
2386 /* we need full 32bits for symconsts */
2390 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2392 symconst_ent = get_SymConst_entity(symconst);
2394 if(cnst == NULL && symconst == NULL)
2397 if(offset_sign && offset != NULL) {
2398 offset = tarval_neg(offset);
2401 irg = current_ir_graph;
2402 dbgi = get_irn_dbg_info(node);
2403 block = get_irg_start_block(irg);
2404 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2406 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2408 /* make sure we don't schedule stuff before the barrier */
2409 add_irn_dep(res, get_irg_frame(irg));
2415 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2417 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2418 if (new_node == NULL) {
2419 new_node = be_transform_node(node);
2424 typedef struct constraint_t constraint_t;
2425 struct constraint_t {
2428 const arch_register_req_t **out_reqs;
2430 const arch_register_req_t *req;
2431 unsigned immediate_possible;
2432 char immediate_type;
2435 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2437 int immediate_possible = 0;
2438 char immediate_type = 0;
2439 unsigned limited = 0;
2440 const arch_register_class_t *cls = NULL;
2442 struct obstack *obst;
2443 arch_register_req_t *req;
2444 unsigned *limited_ptr;
2448 /* TODO: replace all the asserts with nice error messages */
2450 printf("Constraint: %s\n", c);
2460 assert(cls == NULL ||
2461 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2462 cls = &ia32_reg_classes[CLASS_ia32_gp];
2463 limited |= 1 << REG_EAX;
2466 assert(cls == NULL ||
2467 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2468 cls = &ia32_reg_classes[CLASS_ia32_gp];
2469 limited |= 1 << REG_EBX;
2472 assert(cls == NULL ||
2473 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2474 cls = &ia32_reg_classes[CLASS_ia32_gp];
2475 limited |= 1 << REG_ECX;
2478 assert(cls == NULL ||
2479 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2480 cls = &ia32_reg_classes[CLASS_ia32_gp];
2481 limited |= 1 << REG_EDX;
2484 assert(cls == NULL ||
2485 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2486 cls = &ia32_reg_classes[CLASS_ia32_gp];
2487 limited |= 1 << REG_EDI;
2490 assert(cls == NULL ||
2491 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2492 cls = &ia32_reg_classes[CLASS_ia32_gp];
2493 limited |= 1 << REG_ESI;
2496 case 'q': /* q means lower part of the regs only, this makes no
2497 * difference to Q for us (we only assigne whole registers) */
2498 assert(cls == NULL ||
2499 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2500 cls = &ia32_reg_classes[CLASS_ia32_gp];
2501 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2505 assert(cls == NULL ||
2506 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2507 cls = &ia32_reg_classes[CLASS_ia32_gp];
2508 limited |= 1 << REG_EAX | 1 << REG_EDX;
2511 assert(cls == NULL ||
2512 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2513 cls = &ia32_reg_classes[CLASS_ia32_gp];
2514 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2515 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2522 assert(cls == NULL);
2523 cls = &ia32_reg_classes[CLASS_ia32_gp];
2529 /* TODO: mark values so the x87 simulator knows about t and u */
2530 assert(cls == NULL);
2531 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2536 assert(cls == NULL);
2537 /* TODO: check that sse2 is supported */
2538 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2548 assert(!immediate_possible);
2549 immediate_possible = 1;
2550 immediate_type = *c;
2554 assert(!immediate_possible);
2555 immediate_possible = 1;
2559 assert(!immediate_possible && cls == NULL);
2560 immediate_possible = 1;
2561 cls = &ia32_reg_classes[CLASS_ia32_gp];
2574 assert(constraint->is_in && "can only specify same constraint "
2577 sscanf(c, "%d%n", &same_as, &p);
2584 case 'E': /* no float consts yet */
2585 case 'F': /* no float consts yet */
2586 case 's': /* makes no sense on x86 */
2587 case 'X': /* we can't support that in firm */
2591 case '<': /* no autodecrement on x86 */
2592 case '>': /* no autoincrement on x86 */
2593 case 'C': /* sse constant not supported yet */
2594 case 'G': /* 80387 constant not supported yet */
2595 case 'y': /* we don't support mmx registers yet */
2596 case 'Z': /* not available in 32 bit mode */
2597 case 'e': /* not available in 32 bit mode */
2598 assert(0 && "asm constraint not supported");
2601 assert(0 && "unknown asm constraint found");
2608 const arch_register_req_t *other_constr;
2610 assert(cls == NULL && "same as and register constraint not supported");
2611 assert(!immediate_possible && "same as and immediate constraint not "
2613 assert(same_as < constraint->n_outs && "wrong constraint number in "
2614 "same_as constraint");
2616 other_constr = constraint->out_reqs[same_as];
2618 req = obstack_alloc(obst, sizeof(req[0]));
2619 req->cls = other_constr->cls;
2620 req->type = arch_register_req_type_should_be_same;
2621 req->limited = NULL;
2622 req->other_same = pos;
2623 req->other_different = -1;
2625 /* switch constraints. This is because in firm we have same_as
2626 * constraints on the output constraints while in the gcc asm syntax
2627 * they are specified on the input constraints */
2628 constraint->req = other_constr;
2629 constraint->out_reqs[same_as] = req;
2630 constraint->immediate_possible = 0;
2634 if(immediate_possible && cls == NULL) {
2635 cls = &ia32_reg_classes[CLASS_ia32_gp];
2637 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2638 assert(cls != NULL);
2640 if(immediate_possible) {
2641 assert(constraint->is_in
2642 && "imeediates make no sense for output constraints");
2644 /* todo: check types (no float input on 'r' constrainted in and such... */
2646 irg = current_ir_graph;
2647 obst = get_irg_obstack(irg);
2650 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2651 limited_ptr = (unsigned*) (req+1);
2653 req = obstack_alloc(obst, sizeof(req[0]));
2655 memset(req, 0, sizeof(req[0]));
2658 req->type = arch_register_req_type_limited;
2659 *limited_ptr = limited;
2660 req->limited = limited_ptr;
2662 req->type = arch_register_req_type_normal;
2666 constraint->req = req;
2667 constraint->immediate_possible = immediate_possible;
2668 constraint->immediate_type = immediate_type;
2672 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2679 panic("Clobbers not supported yet");
2682 ir_node *gen_ASM(ir_node *node)
2685 ir_graph *irg = current_ir_graph;
2686 ir_node *block = be_transform_node(get_nodes_block(node));
2687 dbg_info *dbgi = get_irn_dbg_info(node);
2694 ia32_asm_attr_t *attr;
2695 const arch_register_req_t **out_reqs;
2696 const arch_register_req_t **in_reqs;
2697 struct obstack *obst;
2698 constraint_t parsed_constraint;
2700 /* assembler could contain float statements */
2703 /* transform inputs */
2704 arity = get_irn_arity(node);
2705 in = alloca(arity * sizeof(in[0]));
2706 memset(in, 0, arity * sizeof(in[0]));
2708 n_outs = get_ASM_n_output_constraints(node);
2709 n_clobbers = get_ASM_n_clobbers(node);
2710 out_arity = n_outs + n_clobbers;
2712 /* construct register constraints */
2713 obst = get_irg_obstack(irg);
2714 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2715 parsed_constraint.out_reqs = out_reqs;
2716 parsed_constraint.n_outs = n_outs;
2717 parsed_constraint.is_in = 0;
2718 for(i = 0; i < out_arity; ++i) {
2722 const ir_asm_constraint *constraint;
2723 constraint = & get_ASM_output_constraints(node) [i];
2724 c = get_id_str(constraint->constraint);
2725 parse_asm_constraint(i, &parsed_constraint, c);
2727 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2728 c = get_id_str(glob_id);
2729 parse_clobber(node, i, &parsed_constraint, c);
2731 out_reqs[i] = parsed_constraint.req;
2734 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2735 parsed_constraint.is_in = 1;
2736 for(i = 0; i < arity; ++i) {
2737 const ir_asm_constraint *constraint;
2741 constraint = & get_ASM_input_constraints(node) [i];
2742 constr_id = constraint->constraint;
2743 c = get_id_str(constr_id);
2744 parse_asm_constraint(i, &parsed_constraint, c);
2745 in_reqs[i] = parsed_constraint.req;
2747 if(parsed_constraint.immediate_possible) {
2748 ir_node *pred = get_irn_n(node, i);
2749 char imm_type = parsed_constraint.immediate_type;
2750 ir_node *immediate = try_create_Immediate(pred, imm_type);
2752 if(immediate != NULL) {
2758 /* transform inputs */
2759 for(i = 0; i < arity; ++i) {
2761 ir_node *transformed;
2766 pred = get_irn_n(node, i);
2767 transformed = be_transform_node(pred);
2768 in[i] = transformed;
2771 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2773 generic_attr = get_irn_generic_attr(res);
2774 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2775 attr->asm_text = get_ASM_text(node);
2776 set_ia32_out_req_all(res, out_reqs);
2777 set_ia32_in_req_all(res, in_reqs);
2779 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2784 /********************************************
2787 * | |__ ___ _ __ ___ __| | ___ ___
2788 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2789 * | |_) | __/ | | | (_) | (_| | __/\__ \
2790 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2792 ********************************************/
2794 static ir_node *gen_be_StackParam(ir_node *node) {
2795 ir_node *block = be_transform_node(get_nodes_block(node));
2796 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2797 ir_node *new_ptr = be_transform_node(ptr);
2798 ir_node *new_op = NULL;
2799 ir_graph *irg = current_ir_graph;
2800 dbg_info *dbgi = get_irn_dbg_info(node);
2801 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2802 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2803 ir_mode *load_mode = get_irn_mode(node);
2804 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2808 if (mode_is_float(load_mode)) {
2810 if (USE_SSE2(env_cg)) {
2811 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2812 pn_res = pn_ia32_xLoad_res;
2813 proj_mode = mode_xmm;
2815 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2816 pn_res = pn_ia32_vfld_res;
2817 proj_mode = mode_vfp;
2820 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2821 proj_mode = mode_Iu;
2822 pn_res = pn_ia32_Load_res;
2825 set_irn_pinned(new_op, op_pin_state_floats);
2826 set_ia32_frame_ent(new_op, ent);
2827 set_ia32_use_frame(new_op);
2829 set_ia32_op_type(new_op, ia32_AddrModeS);
2830 set_ia32_am_flavour(new_op, ia32_am_B);
2831 set_ia32_ls_mode(new_op, load_mode);
2832 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2834 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2836 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2840 * Transforms a FrameAddr into an ia32 Add.
2842 static ir_node *gen_be_FrameAddr(ir_node *node) {
2843 ir_node *block = be_transform_node(get_nodes_block(node));
2844 ir_node *op = be_get_FrameAddr_frame(node);
2845 ir_node *new_op = be_transform_node(op);
2846 ir_graph *irg = current_ir_graph;
2847 dbg_info *dbgi = get_irn_dbg_info(node);
2848 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2851 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2852 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2853 set_ia32_use_frame(res);
2854 set_ia32_am_flavour(res, ia32_am_OB);
2856 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2862 * Transforms a FrameLoad into an ia32 Load.
2864 static ir_node *gen_be_FrameLoad(ir_node *node) {
2865 ir_node *block = be_transform_node(get_nodes_block(node));
2866 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2867 ir_node *new_mem = be_transform_node(mem);
2868 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2869 ir_node *new_ptr = be_transform_node(ptr);
2870 ir_node *new_op = NULL;
2871 ir_graph *irg = current_ir_graph;
2872 dbg_info *dbgi = get_irn_dbg_info(node);
2873 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2874 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2875 ir_mode *mode = get_type_mode(get_entity_type(ent));
2876 ir_node *projs[pn_Load_max];
2878 ia32_collect_Projs(node, projs, pn_Load_max);
2880 if (mode_is_float(mode)) {
2882 if (USE_SSE2(env_cg)) {
2883 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2886 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2890 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2893 set_irn_pinned(new_op, op_pin_state_floats);
2894 set_ia32_frame_ent(new_op, ent);
2895 set_ia32_use_frame(new_op);
2897 set_ia32_op_type(new_op, ia32_AddrModeS);
2898 set_ia32_am_flavour(new_op, ia32_am_B);
2899 set_ia32_ls_mode(new_op, mode);
2900 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2902 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2909 * Transforms a FrameStore into an ia32 Store.
2911 static ir_node *gen_be_FrameStore(ir_node *node) {
2912 ir_node *block = be_transform_node(get_nodes_block(node));
2913 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2914 ir_node *new_mem = be_transform_node(mem);
2915 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2916 ir_node *new_ptr = be_transform_node(ptr);
2917 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2918 ir_node *new_val = be_transform_node(val);
2919 ir_node *new_op = NULL;
2920 ir_graph *irg = current_ir_graph;
2921 dbg_info *dbgi = get_irn_dbg_info(node);
2922 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2923 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2924 ir_mode *mode = get_irn_mode(val);
2926 if (mode_is_float(mode)) {
2928 if (USE_SSE2(env_cg)) {
2929 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2931 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2933 } else if (get_mode_size_bits(mode) == 8) {
2934 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2936 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2939 set_ia32_frame_ent(new_op, ent);
2940 set_ia32_use_frame(new_op);
2942 set_ia32_op_type(new_op, ia32_AddrModeD);
2943 set_ia32_am_flavour(new_op, ia32_am_B);
2944 set_ia32_ls_mode(new_op, mode);
2946 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2952 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2954 static ir_node *gen_be_Return(ir_node *node) {
2955 ir_graph *irg = current_ir_graph;
2956 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2957 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2958 ir_entity *ent = get_irg_entity(irg);
2959 ir_type *tp = get_entity_type(ent);
2964 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2965 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2968 int pn_ret_val, pn_ret_mem, arity, i;
2970 assert(ret_val != NULL);
2971 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2972 return be_duplicate_node(node);
2975 res_type = get_method_res_type(tp, 0);
2977 if (! is_Primitive_type(res_type)) {
2978 return be_duplicate_node(node);
2981 mode = get_type_mode(res_type);
2982 if (! mode_is_float(mode)) {
2983 return be_duplicate_node(node);
2986 assert(get_method_n_ress(tp) == 1);
2988 pn_ret_val = get_Proj_proj(ret_val);
2989 pn_ret_mem = get_Proj_proj(ret_mem);
2991 /* get the Barrier */
2992 barrier = get_Proj_pred(ret_val);
2994 /* get result input of the Barrier */
2995 ret_val = get_irn_n(barrier, pn_ret_val);
2996 new_ret_val = be_transform_node(ret_val);
2998 /* get memory input of the Barrier */
2999 ret_mem = get_irn_n(barrier, pn_ret_mem);
3000 new_ret_mem = be_transform_node(ret_mem);
3002 frame = get_irg_frame(irg);
3004 dbgi = get_irn_dbg_info(barrier);
3005 block = be_transform_node(get_nodes_block(barrier));
3007 noreg = ia32_new_NoReg_gp(env_cg);
3009 /* store xmm0 onto stack */
3010 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3011 set_ia32_ls_mode(sse_store, mode);
3012 set_ia32_op_type(sse_store, ia32_AddrModeD);
3013 set_ia32_use_frame(sse_store);
3014 set_ia32_am_flavour(sse_store, ia32_am_B);
3017 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3018 set_ia32_ls_mode(fld, mode);
3019 set_ia32_op_type(fld, ia32_AddrModeS);
3020 set_ia32_use_frame(fld);
3021 set_ia32_am_flavour(fld, ia32_am_B);
3023 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3024 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3025 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3027 /* create a new barrier */
3028 arity = get_irn_arity(barrier);
3029 in = alloca(arity * sizeof(in[0]));
3030 for (i = 0; i < arity; ++i) {
3033 if (i == pn_ret_val) {
3035 } else if (i == pn_ret_mem) {
3038 ir_node *in = get_irn_n(barrier, i);
3039 new_in = be_transform_node(in);
3044 new_barrier = new_ir_node(dbgi, irg, block,
3045 get_irn_op(barrier), get_irn_mode(barrier),
3047 copy_node_attr(barrier, new_barrier);
3048 be_duplicate_deps(barrier, new_barrier);
3049 be_set_transformed_node(barrier, new_barrier);
3050 mark_irn_visited(barrier);
3052 /* transform normally */
3053 return be_duplicate_node(node);
3057 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3059 static ir_node *gen_be_AddSP(ir_node *node) {
3060 ir_node *block = be_transform_node(get_nodes_block(node));
3061 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3063 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3064 ir_node *new_sp = be_transform_node(sp);
3065 ir_graph *irg = current_ir_graph;
3066 dbg_info *dbgi = get_irn_dbg_info(node);
3067 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3068 ir_node *nomem = new_NoMem();
3071 new_sz = create_immediate_or_transform(sz, 0);
3073 /* ia32 stack grows in reverse direction, make a SubSP */
3074 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3076 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3077 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3083 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3085 static ir_node *gen_be_SubSP(ir_node *node) {
3086 ir_node *block = be_transform_node(get_nodes_block(node));
3087 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3089 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3090 ir_node *new_sp = be_transform_node(sp);
3091 ir_graph *irg = current_ir_graph;
3092 dbg_info *dbgi = get_irn_dbg_info(node);
3093 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3094 ir_node *nomem = new_NoMem();
3097 new_sz = create_immediate_or_transform(sz, 0);
3099 /* ia32 stack grows in reverse direction, make an AddSP */
3100 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3101 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3108 * This function just sets the register for the Unknown node
3109 * as this is not done during register allocation because Unknown
3110 * is an "ignore" node.
3112 static ir_node *gen_Unknown(ir_node *node) {
3113 ir_mode *mode = get_irn_mode(node);
3115 if (mode_is_float(mode)) {
3117 if (USE_SSE2(env_cg))
3118 return ia32_new_Unknown_xmm(env_cg);
3120 return ia32_new_Unknown_vfp(env_cg);
3121 } else if (mode_needs_gp_reg(mode)) {
3122 return ia32_new_Unknown_gp(env_cg);
3124 assert(0 && "unsupported Unknown-Mode");
3131 * Change some phi modes
3133 static ir_node *gen_Phi(ir_node *node) {
3134 ir_node *block = be_transform_node(get_nodes_block(node));
3135 ir_graph *irg = current_ir_graph;
3136 dbg_info *dbgi = get_irn_dbg_info(node);
3137 ir_mode *mode = get_irn_mode(node);
3140 if(mode_needs_gp_reg(mode)) {
3141 /* we shouldn't have any 64bit stuff around anymore */
3142 assert(get_mode_size_bits(mode) <= 32);
3143 /* all integer operations are on 32bit registers now */
3145 } else if(mode_is_float(mode)) {
3146 if (USE_SSE2(env_cg)) {
3153 /* phi nodes allow loops, so we use the old arguments for now
3154 * and fix this later */
3155 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3156 copy_node_attr(node, phi);
3157 be_duplicate_deps(node, phi);
3159 be_set_transformed_node(node, phi);
3160 be_enqueue_preds(node);
3165 /**********************************************************************
3168 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3169 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3170 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3171 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3173 **********************************************************************/
3175 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3177 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3180 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3181 ir_node *val, ir_node *mem);
3184 * Transforms a lowered Load into a "real" one.
3186 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3187 ir_node *block = be_transform_node(get_nodes_block(node));
3188 ir_node *ptr = get_irn_n(node, 0);
3189 ir_node *new_ptr = be_transform_node(ptr);
3190 ir_node *mem = get_irn_n(node, 1);
3191 ir_node *new_mem = be_transform_node(mem);
3192 ir_graph *irg = current_ir_graph;
3193 dbg_info *dbgi = get_irn_dbg_info(node);
3194 ir_mode *mode = get_ia32_ls_mode(node);
3195 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3199 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3200 lowering we have x87 nodes, so we need to enforce simulation.
3202 if (mode_is_float(mode)) {
3204 if (fp_unit == fp_x87)
3208 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3210 set_ia32_op_type(new_op, ia32_AddrModeS);
3211 set_ia32_am_flavour(new_op, ia32_am_OB);
3212 set_ia32_am_offs_int(new_op, 0);
3213 set_ia32_am_scale(new_op, 1);
3214 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3215 if (is_ia32_am_sc_sign(node))
3216 set_ia32_am_sc_sign(new_op);
3217 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3218 if (is_ia32_use_frame(node)) {
3219 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3220 set_ia32_use_frame(new_op);
3223 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3229 * Transforms a lowered Store into a "real" one.
3231 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3232 ir_node *block = be_transform_node(get_nodes_block(node));
3233 ir_node *ptr = get_irn_n(node, 0);
3234 ir_node *new_ptr = be_transform_node(ptr);
3235 ir_node *val = get_irn_n(node, 1);
3236 ir_node *new_val = be_transform_node(val);
3237 ir_node *mem = get_irn_n(node, 2);
3238 ir_node *new_mem = be_transform_node(mem);
3239 ir_graph *irg = current_ir_graph;
3240 dbg_info *dbgi = get_irn_dbg_info(node);
3241 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3242 ir_mode *mode = get_ia32_ls_mode(node);
3245 ia32_am_flavour_t am_flav = ia32_B;
3248 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3249 lowering we have x87 nodes, so we need to enforce simulation.
3251 if (mode_is_float(mode)) {
3253 if (fp_unit == fp_x87)
3257 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3259 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3261 add_ia32_am_offs_int(new_op, am_offs);
3264 set_ia32_op_type(new_op, ia32_AddrModeD);
3265 set_ia32_am_flavour(new_op, am_flav);
3266 set_ia32_ls_mode(new_op, mode);
3267 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3268 set_ia32_use_frame(new_op);
3270 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3277 * Transforms an ia32_l_XXX into a "real" XXX node
3279 * @param env The transformation environment
3280 * @return the created ia32 XXX node
3282 #define GEN_LOWERED_OP(op) \
3283 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3284 ir_mode *mode = get_irn_mode(node); \
3285 if (mode_is_float(mode)) \
3287 return gen_binop(node, get_binop_left(node), \
3288 get_binop_right(node), new_rd_ia32_##op,0); \
3291 #define GEN_LOWERED_x87_OP(op) \
3292 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3294 FORCE_x87(env_cg); \
3295 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3296 get_binop_right(node), new_rd_ia32_##op); \
3300 #define GEN_LOWERED_UNOP(op) \
3301 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3302 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3305 #define GEN_LOWERED_SHIFT_OP(op) \
3306 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3307 return gen_shift_binop(node, get_binop_left(node), \
3308 get_binop_right(node), new_rd_ia32_##op); \
3311 #define GEN_LOWERED_LOAD(op, fp_unit) \
3312 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3313 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3316 #define GEN_LOWERED_STORE(op, fp_unit) \
3317 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3318 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3325 GEN_LOWERED_OP(IMul)
3327 GEN_LOWERED_x87_OP(vfprem)
3328 GEN_LOWERED_x87_OP(vfmul)
3329 GEN_LOWERED_x87_OP(vfsub)
3331 GEN_LOWERED_UNOP(Neg)
3333 GEN_LOWERED_LOAD(vfild, fp_x87)
3334 GEN_LOWERED_LOAD(Load, fp_none)
3335 /*GEN_LOWERED_STORE(vfist, fp_x87)
3338 GEN_LOWERED_STORE(Store, fp_none)
3340 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3341 ir_node *block = be_transform_node(get_nodes_block(node));
3342 ir_node *left = get_binop_left(node);
3343 ir_node *new_left = be_transform_node(left);
3344 ir_node *right = get_binop_right(node);
3345 ir_node *new_right = be_transform_node(right);
3346 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3347 ir_graph *irg = current_ir_graph;
3348 dbg_info *dbgi = get_irn_dbg_info(node);
3349 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3350 &ia32_fp_cw_regs[REG_FPCW]);
3353 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3354 new_right, new_NoMem(), fpcw);
3355 clear_ia32_commutative(vfdiv);
3356 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3358 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3366 * Transforms a l_MulS into a "real" MulS node.
3368 * @param env The transformation environment
3369 * @return the created ia32 Mul node
3371 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3372 ir_node *block = be_transform_node(get_nodes_block(node));
3373 ir_node *left = get_binop_left(node);
3374 ir_node *new_left = be_transform_node(left);
3375 ir_node *right = get_binop_right(node);
3376 ir_node *new_right = be_transform_node(right);
3377 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3378 ir_graph *irg = current_ir_graph;
3379 dbg_info *dbgi = get_irn_dbg_info(node);
3382 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3383 /* and then skip the result Proj, because all needed Projs are already there. */
3384 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3385 new_right, new_NoMem());
3386 clear_ia32_commutative(muls);
3387 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3389 /* check if EAX and EDX proj exist, add missing one */
3390 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3391 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3392 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3394 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3399 GEN_LOWERED_SHIFT_OP(Shl)
3400 GEN_LOWERED_SHIFT_OP(Shr)
3401 GEN_LOWERED_SHIFT_OP(Sar)
3404 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3405 * op1 - target to be shifted
3406 * op2 - contains bits to be shifted into target
3408 * Only op3 can be an immediate.
3410 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3411 ir_node *op2, ir_node *count)
3413 ir_node *block = be_transform_node(get_nodes_block(node));
3414 ir_node *new_op1 = be_transform_node(op1);
3415 ir_node *new_op2 = be_transform_node(op2);
3416 ir_node *new_count = be_transform_node(count);
3417 ir_node *new_op = NULL;
3418 ir_graph *irg = current_ir_graph;
3419 dbg_info *dbgi = get_irn_dbg_info(node);
3420 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3421 ir_node *nomem = new_NoMem();
3425 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3427 /* Check if immediate optimization is on and */
3428 /* if it's an operation with immediate. */
3429 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3431 /* Limit imm_op within range imm8 */
3433 tv = get_ia32_Immop_tarval(imm_op);
3436 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3437 set_ia32_Immop_tarval(imm_op, tv);
3444 /* integer operations */
3446 /* This is ShiftD with const */
3447 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3449 if (is_ia32_l_ShlD(node))
3450 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3451 new_op1, new_op2, noreg, nomem);
3453 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3454 new_op1, new_op2, noreg, nomem);
3455 copy_ia32_Immop_attr(new_op, imm_op);
3458 /* This is a normal ShiftD */
3459 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3460 if (is_ia32_l_ShlD(node))
3461 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3462 new_op1, new_op2, new_count, nomem);
3464 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3465 new_op1, new_op2, new_count, nomem);
3468 /* set AM support */
3469 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3471 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3473 set_ia32_emit_cl(new_op);
3478 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3479 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3480 get_irn_n(node, 1), get_irn_n(node, 2));
3483 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3484 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3485 get_irn_n(node, 1), get_irn_n(node, 2));
3489 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3491 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3492 ir_node *block = be_transform_node(get_nodes_block(node));
3493 ir_node *val = get_irn_n(node, 1);
3494 ir_node *new_val = be_transform_node(val);
3495 ia32_code_gen_t *cg = env_cg;
3496 ir_node *res = NULL;
3497 ir_graph *irg = current_ir_graph;
3499 ir_node *noreg, *new_ptr, *new_mem;
3506 mem = get_irn_n(node, 2);
3507 new_mem = be_transform_node(mem);
3508 ptr = get_irn_n(node, 0);
3509 new_ptr = be_transform_node(ptr);
3510 noreg = ia32_new_NoReg_gp(cg);
3511 dbgi = get_irn_dbg_info(node);
3513 /* Store x87 -> MEM */
3514 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3515 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3516 set_ia32_use_frame(res);
3517 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3518 set_ia32_am_flavour(res, ia32_B);
3519 set_ia32_op_type(res, ia32_AddrModeD);
3521 /* Load MEM -> SSE */
3522 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3523 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3524 set_ia32_use_frame(res);
3525 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3526 set_ia32_am_flavour(res, ia32_B);
3527 set_ia32_op_type(res, ia32_AddrModeS);
3528 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3534 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3536 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3537 ir_node *block = be_transform_node(get_nodes_block(node));
3538 ir_node *val = get_irn_n(node, 1);
3539 ir_node *new_val = be_transform_node(val);
3540 ia32_code_gen_t *cg = env_cg;
3541 ir_graph *irg = current_ir_graph;
3542 ir_node *res = NULL;
3543 ir_entity *fent = get_ia32_frame_ent(node);
3544 ir_mode *lsmode = get_ia32_ls_mode(node);
3546 ir_node *noreg, *new_ptr, *new_mem;
3550 if (! USE_SSE2(cg)) {
3551 /* SSE unit is not used -> skip this node. */
3555 ptr = get_irn_n(node, 0);
3556 new_ptr = be_transform_node(ptr);
3557 mem = get_irn_n(node, 2);
3558 new_mem = be_transform_node(mem);
3559 noreg = ia32_new_NoReg_gp(cg);
3560 dbgi = get_irn_dbg_info(node);
3562 /* Store SSE -> MEM */
3563 if (is_ia32_xLoad(skip_Proj(new_val))) {
3564 ir_node *ld = skip_Proj(new_val);
3566 /* we can vfld the value directly into the fpu */
3567 fent = get_ia32_frame_ent(ld);
3568 ptr = get_irn_n(ld, 0);
3569 offs = get_ia32_am_offs_int(ld);
3571 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3572 set_ia32_frame_ent(res, fent);
3573 set_ia32_use_frame(res);
3574 set_ia32_ls_mode(res, lsmode);
3575 set_ia32_am_flavour(res, ia32_B);
3576 set_ia32_op_type(res, ia32_AddrModeD);
3580 /* Load MEM -> x87 */
3581 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3582 set_ia32_frame_ent(res, fent);
3583 set_ia32_use_frame(res);
3584 add_ia32_am_offs_int(res, offs);
3585 set_ia32_am_flavour(res, ia32_B);
3586 set_ia32_op_type(res, ia32_AddrModeS);
3587 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3592 /*********************************************************
3595 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3596 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3597 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3598 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3600 *********************************************************/
3603 * the BAD transformer.
3605 static ir_node *bad_transform(ir_node *node) {
3606 panic("No transform function for %+F available.\n", node);
3611 * Transform the Projs of an AddSP.
3613 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3614 ir_node *block = be_transform_node(get_nodes_block(node));
3615 ir_node *pred = get_Proj_pred(node);
3616 ir_node *new_pred = be_transform_node(pred);
3617 ir_graph *irg = current_ir_graph;
3618 dbg_info *dbgi = get_irn_dbg_info(node);
3619 long proj = get_Proj_proj(node);
3621 if (proj == pn_be_AddSP_res) {
3622 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3623 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3625 } else if (proj == pn_be_AddSP_M) {
3626 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3630 return new_rd_Unknown(irg, get_irn_mode(node));
3634 * Transform the Projs of a SubSP.
3636 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3637 ir_node *block = be_transform_node(get_nodes_block(node));
3638 ir_node *pred = get_Proj_pred(node);
3639 ir_node *new_pred = be_transform_node(pred);
3640 ir_graph *irg = current_ir_graph;
3641 dbg_info *dbgi = get_irn_dbg_info(node);
3642 long proj = get_Proj_proj(node);
3644 if (proj == pn_be_SubSP_res) {
3645 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3646 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3648 } else if (proj == pn_be_SubSP_M) {
3649 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3653 return new_rd_Unknown(irg, get_irn_mode(node));
3657 * Transform and renumber the Projs from a Load.
3659 static ir_node *gen_Proj_Load(ir_node *node) {
3660 ir_node *block = be_transform_node(get_nodes_block(node));
3661 ir_node *pred = get_Proj_pred(node);
3662 ir_node *new_pred = be_transform_node(pred);
3663 ir_graph *irg = current_ir_graph;
3664 dbg_info *dbgi = get_irn_dbg_info(node);
3665 long proj = get_Proj_proj(node);
3667 /* renumber the proj */
3668 if (is_ia32_Load(new_pred)) {
3669 if (proj == pn_Load_res) {
3670 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3671 } else if (proj == pn_Load_M) {
3672 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3674 } else if (is_ia32_xLoad(new_pred)) {
3675 if (proj == pn_Load_res) {
3676 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3677 } else if (proj == pn_Load_M) {
3678 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3680 } else if (is_ia32_vfld(new_pred)) {
3681 if (proj == pn_Load_res) {
3682 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3683 } else if (proj == pn_Load_M) {
3684 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3689 return new_rd_Unknown(irg, get_irn_mode(node));
3693 * Transform and renumber the Projs from a DivMod like instruction.
3695 static ir_node *gen_Proj_DivMod(ir_node *node) {
3696 ir_node *block = be_transform_node(get_nodes_block(node));
3697 ir_node *pred = get_Proj_pred(node);
3698 ir_node *new_pred = be_transform_node(pred);
3699 ir_graph *irg = current_ir_graph;
3700 dbg_info *dbgi = get_irn_dbg_info(node);
3701 ir_mode *mode = get_irn_mode(node);
3702 long proj = get_Proj_proj(node);
3704 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3706 switch (get_irn_opcode(pred)) {
3710 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3712 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3720 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3722 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3730 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3731 case pn_DivMod_res_div:
3732 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3733 case pn_DivMod_res_mod:
3734 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3744 return new_rd_Unknown(irg, mode);
3748 * Transform and renumber the Projs from a CopyB.
3750 static ir_node *gen_Proj_CopyB(ir_node *node) {
3751 ir_node *block = be_transform_node(get_nodes_block(node));
3752 ir_node *pred = get_Proj_pred(node);
3753 ir_node *new_pred = be_transform_node(pred);
3754 ir_graph *irg = current_ir_graph;
3755 dbg_info *dbgi = get_irn_dbg_info(node);
3756 ir_mode *mode = get_irn_mode(node);
3757 long proj = get_Proj_proj(node);
3760 case pn_CopyB_M_regular:
3761 if (is_ia32_CopyB_i(new_pred)) {
3762 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3763 } else if (is_ia32_CopyB(new_pred)) {
3764 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3772 return new_rd_Unknown(irg, mode);
3776 * Transform and renumber the Projs from a vfdiv.
3778 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3779 ir_node *block = be_transform_node(get_nodes_block(node));
3780 ir_node *pred = get_Proj_pred(node);
3781 ir_node *new_pred = be_transform_node(pred);
3782 ir_graph *irg = current_ir_graph;
3783 dbg_info *dbgi = get_irn_dbg_info(node);
3784 ir_mode *mode = get_irn_mode(node);
3785 long proj = get_Proj_proj(node);
3788 case pn_ia32_l_vfdiv_M:
3789 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3790 case pn_ia32_l_vfdiv_res:
3791 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3796 return new_rd_Unknown(irg, mode);
3800 * Transform and renumber the Projs from a Quot.
3802 static ir_node *gen_Proj_Quot(ir_node *node) {
3803 ir_node *block = be_transform_node(get_nodes_block(node));
3804 ir_node *pred = get_Proj_pred(node);
3805 ir_node *new_pred = be_transform_node(pred);
3806 ir_graph *irg = current_ir_graph;
3807 dbg_info *dbgi = get_irn_dbg_info(node);
3808 ir_mode *mode = get_irn_mode(node);
3809 long proj = get_Proj_proj(node);
3813 if (is_ia32_xDiv(new_pred)) {
3814 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3815 } else if (is_ia32_vfdiv(new_pred)) {
3816 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3820 if (is_ia32_xDiv(new_pred)) {
3821 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3822 } else if (is_ia32_vfdiv(new_pred)) {
3823 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3831 return new_rd_Unknown(irg, mode);
3835 * Transform the Thread Local Storage Proj.
3837 static ir_node *gen_Proj_tls(ir_node *node) {
3838 ir_node *block = be_transform_node(get_nodes_block(node));
3839 ir_graph *irg = current_ir_graph;
3840 dbg_info *dbgi = NULL;
3841 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3847 * Transform the Projs from a be_Call.
3849 static ir_node *gen_Proj_be_Call(ir_node *node) {
3850 ir_node *block = be_transform_node(get_nodes_block(node));
3851 ir_node *call = get_Proj_pred(node);
3852 ir_node *new_call = be_transform_node(call);
3853 ir_graph *irg = current_ir_graph;
3854 dbg_info *dbgi = get_irn_dbg_info(node);
3855 long proj = get_Proj_proj(node);
3856 ir_mode *mode = get_irn_mode(node);
3858 const arch_register_class_t *cls;
3860 /* The following is kinda tricky: If we're using SSE, then we have to
3861 * move the result value of the call in floating point registers to an
3862 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3863 * after the call, we have to make sure to correctly make the
3864 * MemProj and the result Proj use these 2 nodes
3866 if (proj == pn_be_Call_M_regular) {
3867 // get new node for result, are we doing the sse load/store hack?
3868 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3869 ir_node *call_res_new;
3870 ir_node *call_res_pred = NULL;
3872 if (call_res != NULL) {
3873 call_res_new = be_transform_node(call_res);
3874 call_res_pred = get_Proj_pred(call_res_new);
3877 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3878 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3880 assert(is_ia32_xLoad(call_res_pred));
3881 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3884 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3886 ir_node *frame = get_irg_frame(irg);
3887 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3889 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3891 const arch_register_class_t *cls;
3893 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3894 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3896 /* store st(0) onto stack */
3897 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3899 set_ia32_ls_mode(fstp, mode);
3900 set_ia32_op_type(fstp, ia32_AddrModeD);
3901 set_ia32_use_frame(fstp);
3902 set_ia32_am_flavour(fstp, ia32_am_B);
3904 /* load into SSE register */
3905 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3906 set_ia32_ls_mode(sse_load, mode);
3907 set_ia32_op_type(sse_load, ia32_AddrModeS);
3908 set_ia32_use_frame(sse_load);
3909 set_ia32_am_flavour(sse_load, ia32_am_B);
3911 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3913 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3915 /* get a Proj representing a caller save register */
3916 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3917 assert(is_Proj(p) && "Proj expected.");
3919 /* user of the the proj is the Keep */
3920 p = get_edge_src_irn(get_irn_out_edge_first(p));
3921 assert(be_is_Keep(p) && "Keep expected.");
3923 /* keep the result */
3924 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3925 keepin[0] = sse_load;
3926 be_new_Keep(cls, irg, block, 1, keepin);
3931 /* transform call modes */
3932 if (mode_is_data(mode)) {
3933 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3937 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3941 * Transform the Projs from a Cmp.
3943 static ir_node *gen_Proj_Cmp(ir_node *node)
3945 /* normally Cmps are processed when looking at Cond nodes, but this case
3946 * can happen in complicated Psi conditions */
3948 ir_node *cmp = get_Proj_pred(node);
3949 long pnc = get_Proj_proj(node);
3950 ir_node *cmp_left = get_Cmp_left(cmp);
3951 ir_node *cmp_right = get_Cmp_right(cmp);
3952 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3953 dbg_info *dbgi = get_irn_dbg_info(cmp);
3954 ir_node *block = be_transform_node(get_nodes_block(node));
3957 assert(!mode_is_float(cmp_mode));
3959 if(!mode_is_signed(cmp_mode)) {
3960 pnc |= ia32_pn_Cmp_Unsigned;
3963 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3964 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3970 * Transform and potentially renumber Proj nodes.
3972 static ir_node *gen_Proj(ir_node *node) {
3973 ir_graph *irg = current_ir_graph;
3974 dbg_info *dbgi = get_irn_dbg_info(node);
3975 ir_node *pred = get_Proj_pred(node);
3976 long proj = get_Proj_proj(node);
3978 if (is_Store(pred) || be_is_FrameStore(pred)) {
3979 if (proj == pn_Store_M) {
3980 return be_transform_node(pred);
3983 return new_r_Bad(irg);
3985 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3986 return gen_Proj_Load(node);
3987 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3988 return gen_Proj_DivMod(node);
3989 } else if (is_CopyB(pred)) {
3990 return gen_Proj_CopyB(node);
3991 } else if (is_Quot(pred)) {
3992 return gen_Proj_Quot(node);
3993 } else if (is_ia32_l_vfdiv(pred)) {
3994 return gen_Proj_l_vfdiv(node);
3995 } else if (be_is_SubSP(pred)) {
3996 return gen_Proj_be_SubSP(node);
3997 } else if (be_is_AddSP(pred)) {
3998 return gen_Proj_be_AddSP(node);
3999 } else if (be_is_Call(pred)) {
4000 return gen_Proj_be_Call(node);
4001 } else if (is_Cmp(pred)) {
4002 return gen_Proj_Cmp(node);
4003 } else if (get_irn_op(pred) == op_Start) {
4004 if (proj == pn_Start_X_initial_exec) {
4005 ir_node *block = get_nodes_block(pred);
4008 /* we exchange the ProjX with a jump */
4009 block = be_transform_node(block);
4010 jump = new_rd_Jmp(dbgi, irg, block);
4013 if (node == be_get_old_anchor(anchor_tls)) {
4014 return gen_Proj_tls(node);
4017 ir_node *new_pred = be_transform_node(pred);
4018 ir_node *block = be_transform_node(get_nodes_block(node));
4019 ir_mode *mode = get_irn_mode(node);
4020 if (mode_needs_gp_reg(mode)) {
4021 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4022 get_Proj_proj(node));
4023 #ifdef DEBUG_libfirm
4024 new_proj->node_nr = node->node_nr;
4030 return be_duplicate_node(node);
4034 * Enters all transform functions into the generic pointer
4036 static void register_transformers(void)
4040 /* first clear the generic function pointer for all ops */
4041 clear_irp_opcodes_generic_func();
4043 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4044 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4081 /* transform ops from intrinsic lowering */
4101 /* GEN(ia32_l_vfist); TODO */
4103 GEN(ia32_l_X87toSSE);
4104 GEN(ia32_l_SSEtoX87);
4109 /* we should never see these nodes */
4124 /* handle generic backend nodes */
4135 /* set the register for all Unknown nodes */
4138 op_Mulh = get_op_Mulh();
4147 * Pre-transform all unknown and noreg nodes.
4149 static void ia32_pretransform_node(void *arch_cg) {
4150 ia32_code_gen_t *cg = arch_cg;
4152 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4153 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4154 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4155 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4156 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4157 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4160 /* do the transformation */
4161 void ia32_transform_graph(ia32_code_gen_t *cg) {
4162 register_transformers();
4164 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4167 void ia32_init_transform(void)
4169 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");