2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** holdd the current code generator during transformation */
90 static ia32_code_gen_t *env_cg;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
120 * Return true if a mode can be stored in the GP register set
122 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
123 if(mode == mode_fpcw)
125 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
129 * Returns 1 if irn is a Const representing 0, 0 otherwise
131 static INLINE int is_ia32_Const_0(ir_node *irn) {
132 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
133 && tarval_is_null(get_ia32_Immop_tarval(irn));
137 * Returns 1 if irn is a Const representing 1, 0 otherwise
139 static INLINE int is_ia32_Const_1(ir_node *irn) {
140 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
141 && tarval_is_one(get_ia32_Immop_tarval(irn));
145 * Collects all Projs of a node into the node array. Index is the projnum.
146 * BEWARE: The caller has to assure the appropriate array size!
148 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
149 const ir_edge_t *edge;
150 assert(get_irn_mode(irn) == mode_T && "need mode_T");
152 memset(projs, 0, size * sizeof(projs[0]));
154 foreach_out_edge(irn, edge) {
155 ir_node *proj = get_edge_src_irn(edge);
156 int proj_proj = get_Proj_proj(proj);
157 assert(proj_proj < size);
158 projs[proj_proj] = proj;
163 * Renumbers the proj having pn_old in the array tp pn_new
164 * and removes the proj from the array.
166 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
167 fprintf(stderr, "Warning: renumber_Proj used!\n");
169 set_Proj_proj(projs[pn_old], pn_new);
170 projs[pn_old] = NULL;
175 * creates a unique ident by adding a number to a tag
177 * @param tag the tag string, must contain a %d if a number
180 static ident *unique_id(const char *tag)
182 static unsigned id = 0;
185 snprintf(str, sizeof(str), tag, ++id);
186 return new_id_from_str(str);
190 * Get a primitive type for a mode.
192 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
194 pmap_entry *e = pmap_find(types, mode);
199 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
200 res = new_type_primitive(new_id_from_str(buf), mode);
201 set_type_alignment_bytes(res, 16);
202 pmap_insert(types, mode, res);
210 * Get an entity that is initialized with a tarval
212 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
214 tarval *tv = get_Const_tarval(cnst);
215 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
220 ir_mode *mode = get_irn_mode(cnst);
221 ir_type *tp = get_Const_type(cnst);
222 if (tp == firm_unknown_type)
223 tp = get_prim_type(cg->isa->types, mode);
225 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
227 set_entity_ld_ident(res, get_entity_ident(res));
228 set_entity_visibility(res, visibility_local);
229 set_entity_variability(res, variability_constant);
230 set_entity_allocation(res, allocation_static);
232 /* we create a new entity here: It's initialization must resist on the
234 rem = current_ir_graph;
235 current_ir_graph = get_const_code_irg();
236 set_atomic_ent_value(res, new_Const_type(tv, tp));
237 current_ir_graph = rem;
239 pmap_insert(cg->isa->tv_ent, tv, res);
247 static int is_Const_0(ir_node *node) {
251 return classify_Const(node) == CNST_NULL;
254 static int is_Const_1(ir_node *node) {
258 return classify_Const(node) == CNST_ONE;
262 * Transforms a Const.
264 static ir_node *gen_Const(ir_node *node) {
265 ir_graph *irg = current_ir_graph;
266 ir_node *block = be_transform_node(get_nodes_block(node));
267 dbg_info *dbgi = get_irn_dbg_info(node);
268 ir_mode *mode = get_irn_mode(node);
270 if (mode_is_float(mode)) {
272 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
273 ir_node *nomem = new_NoMem();
278 if (! USE_SSE2(env_cg)) {
279 cnst_classify_t clss = classify_Const(node);
281 if (clss == CNST_NULL) {
282 load = new_rd_ia32_vfldz(dbgi, irg, block);
284 } else if (clss == CNST_ONE) {
285 load = new_rd_ia32_vfld1(dbgi, irg, block);
288 floatent = get_entity_for_tv(env_cg, node);
290 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
291 set_ia32_op_type(load, ia32_AddrModeS);
292 set_ia32_am_flavour(load, ia32_am_N);
293 set_ia32_am_sc(load, floatent);
294 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
296 set_ia32_ls_mode(load, mode);
298 floatent = get_entity_for_tv(env_cg, node);
300 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_flavour(load, ia32_am_N);
303 set_ia32_am_sc(load, floatent);
304 set_ia32_ls_mode(load, mode);
306 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
323 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
326 if (get_irg_start_block(irg) == block) {
327 add_irn_dep(cnst, get_irg_frame(irg));
330 set_ia32_Const_attr(cnst, node);
331 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
336 return new_r_Bad(irg);
340 * Transforms a SymConst.
342 static ir_node *gen_SymConst(ir_node *node) {
343 ir_graph *irg = current_ir_graph;
344 ir_node *block = be_transform_node(get_nodes_block(node));
345 dbg_info *dbgi = get_irn_dbg_info(node);
346 ir_mode *mode = get_irn_mode(node);
349 if (mode_is_float(mode)) {
351 if (USE_SSE2(env_cg))
352 cnst = new_rd_ia32_xConst(dbgi, irg, block);
354 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
355 //set_ia32_ls_mode(cnst, mode);
356 set_ia32_ls_mode(cnst, mode_E);
358 cnst = new_rd_ia32_Const(dbgi, irg, block);
361 /* Const Nodes before the initial IncSP are a bad idea, because
362 * they could be spilled and we have no SP ready at that point yet
364 if (get_irg_start_block(irg) == block) {
365 add_irn_dep(cnst, get_irg_frame(irg));
368 set_ia32_Const_attr(cnst, node);
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
375 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
376 static const struct {
378 const char *ent_name;
379 const char *cnst_str;
380 } names [ia32_known_const_max] = {
381 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
382 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
383 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
384 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
386 static ir_entity *ent_cache[ia32_known_const_max];
388 const char *tp_name, *ent_name, *cnst_str;
396 ent_name = names[kct].ent_name;
397 if (! ent_cache[kct]) {
398 tp_name = names[kct].tp_name;
399 cnst_str = names[kct].cnst_str;
401 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
403 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
404 tp = new_type_primitive(new_id_from_str(tp_name), mode);
405 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
407 set_entity_ld_ident(ent, get_entity_ident(ent));
408 set_entity_visibility(ent, visibility_local);
409 set_entity_variability(ent, variability_constant);
410 set_entity_allocation(ent, allocation_static);
412 /* we create a new entity here: It's initialization must resist on the
414 rem = current_ir_graph;
415 current_ir_graph = get_const_code_irg();
416 cnst = new_Const(mode, tv);
417 current_ir_graph = rem;
419 set_atomic_ent_value(ent, cnst);
421 /* cache the entry */
422 ent_cache[kct] = ent;
425 return ent_cache[kct];
430 * Prints the old node name on cg obst and returns a pointer to it.
432 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
433 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
435 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
436 obstack_1grow(isa->name_obst, 0);
437 return obstack_finish(isa->name_obst);
441 /* determine if one operator is an Imm */
442 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
444 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
446 return is_ia32_Cnst(op2) ? op2 : NULL;
450 /* determine if one operator is not an Imm */
451 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
452 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
455 static void fold_immediate(ir_node *node, int in1, int in2) {
459 if (!(env_cg->opt & IA32_OPT_IMMOPS))
462 left = get_irn_n(node, in1);
463 right = get_irn_n(node, in2);
464 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
465 /* we can only set right operand to immediate */
466 if(!is_ia32_commutative(node))
468 /* exchange left/right */
469 set_irn_n(node, in1, right);
470 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
471 copy_ia32_Immop_attr(node, left);
472 } else if(is_ia32_Cnst(right)) {
473 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
474 copy_ia32_Immop_attr(node, right);
479 clear_ia32_commutative(node);
480 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
481 get_ia32_am_arity(node));
485 * Construct a standard binary operation, set AM and immediate if required.
487 * @param op1 The first operand
488 * @param op2 The second operand
489 * @param func The node constructor function
490 * @return The constructed ia32 node.
492 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
493 construct_binop_func *func, int commutative)
495 ir_node *block = be_transform_node(get_nodes_block(node));
496 ir_node *new_op1 = NULL;
497 ir_node *new_op2 = NULL;
498 ir_node *new_node = NULL;
499 ir_graph *irg = current_ir_graph;
500 dbg_info *dbgi = get_irn_dbg_info(node);
501 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
502 ir_node *nomem = new_NoMem();
505 new_op2 = try_create_Immediate(op1, 0);
506 if(new_op2 != NULL) {
507 new_op1 = be_transform_node(op2);
512 if(new_op2 == NULL) {
513 new_op2 = try_create_Immediate(op2, 0);
514 if(new_op2 != NULL) {
515 new_op1 = be_transform_node(op1);
520 if(new_op2 == NULL) {
521 new_op1 = be_transform_node(op1);
522 new_op2 = be_transform_node(op2);
525 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
526 if (func == new_rd_ia32_IMul) {
527 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
529 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
532 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
534 set_ia32_commutative(new_node);
541 * Construct a standard binary operation, set AM and immediate if required.
543 * @param op1 The first operand
544 * @param op2 The second operand
545 * @param func The node constructor function
546 * @return The constructed ia32 node.
548 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
549 construct_binop_func *func)
551 ir_node *block = be_transform_node(get_nodes_block(node));
552 ir_node *new_op1 = be_transform_node(op1);
553 ir_node *new_op2 = be_transform_node(op2);
554 ir_node *new_node = NULL;
555 dbg_info *dbgi = get_irn_dbg_info(node);
556 ir_graph *irg = current_ir_graph;
557 ir_mode *mode = get_irn_mode(node);
558 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
559 ir_node *nomem = new_NoMem();
561 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
563 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
564 if (is_op_commutative(get_irn_op(node))) {
565 set_ia32_commutative(new_node);
567 if (USE_SSE2(env_cg)) {
568 set_ia32_ls_mode(new_node, mode);
571 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
577 * Construct a standard binary operation, set AM and immediate if required.
579 * @param op1 The first operand
580 * @param op2 The second operand
581 * @param func The node constructor function
582 * @return The constructed ia32 node.
584 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
585 construct_binop_float_func *func)
587 ir_node *block = be_transform_node(get_nodes_block(node));
588 ir_node *new_op1 = be_transform_node(op1);
589 ir_node *new_op2 = be_transform_node(op2);
590 ir_node *new_node = NULL;
591 dbg_info *dbgi = get_irn_dbg_info(node);
592 ir_graph *irg = current_ir_graph;
593 ir_mode *mode = get_irn_mode(node);
594 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
595 ir_node *nomem = new_NoMem();
596 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
597 &ia32_fp_cw_regs[REG_FPCW]);
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
601 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
602 if (is_op_commutative(get_irn_op(node))) {
603 set_ia32_commutative(new_node);
605 if (USE_SSE2(env_cg)) {
606 set_ia32_ls_mode(new_node, mode);
609 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
615 * Construct a shift/rotate binary operation, sets AM and immediate if required.
617 * @param op1 The first operand
618 * @param op2 The second operand
619 * @param func The node constructor function
620 * @return The constructed ia32 node.
622 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
623 construct_binop_func *func)
625 ir_node *block = be_transform_node(get_nodes_block(node));
626 ir_node *new_op1 = be_transform_node(op1);
627 ir_node *new_op2 = be_transform_node(op2);
628 ir_node *new_op = NULL;
629 dbg_info *dbgi = get_irn_dbg_info(node);
630 ir_graph *irg = current_ir_graph;
631 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
632 ir_node *nomem = new_NoMem();
637 assert(! mode_is_float(get_irn_mode(node))
638 && "Shift/Rotate with float not supported");
640 /* Check if immediate optimization is on and */
641 /* if it's an operation with immediate. */
642 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
643 expr_op = get_expr_op(new_op1, new_op2);
645 assert((expr_op || imm_op) && "invalid operands");
648 /* We have two consts here: not yet supported */
652 /* Limit imm_op within range imm8 */
654 tv = get_ia32_Immop_tarval(imm_op);
657 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
658 set_ia32_Immop_tarval(imm_op, tv);
665 /* integer operations */
667 /* This is shift/rot with const */
668 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
670 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
671 copy_ia32_Immop_attr(new_op, imm_op);
673 /* This is a normal shift/rot */
674 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
675 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
679 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
681 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
683 set_ia32_emit_cl(new_op);
690 * Construct a standard unary operation, set AM and immediate if required.
692 * @param op The operand
693 * @param func The node constructor function
694 * @return The constructed ia32 node.
696 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
698 ir_node *block = be_transform_node(get_nodes_block(node));
699 ir_node *new_op = be_transform_node(op);
700 ir_node *new_node = NULL;
701 ir_graph *irg = current_ir_graph;
702 dbg_info *dbgi = get_irn_dbg_info(node);
703 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
704 ir_node *nomem = new_NoMem();
706 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
707 DB((dbg, LEVEL_1, "INT unop ..."));
708 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
710 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
716 * Creates an ia32 Add.
718 * @return the created ia32 Add node
720 static ir_node *gen_Add(ir_node *node) {
721 ir_node *block = be_transform_node(get_nodes_block(node));
722 ir_node *op1 = get_Add_left(node);
723 ir_node *new_op1 = be_transform_node(op1);
724 ir_node *op2 = get_Add_right(node);
725 ir_node *new_op2 = be_transform_node(op2);
726 ir_node *new_op = NULL;
727 ir_graph *irg = current_ir_graph;
728 dbg_info *dbgi = get_irn_dbg_info(node);
729 ir_mode *mode = get_irn_mode(node);
730 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
731 ir_node *nomem = new_NoMem();
732 ir_node *expr_op, *imm_op;
734 /* Check if immediate optimization is on and */
735 /* if it's an operation with immediate. */
736 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
737 expr_op = get_expr_op(new_op1, new_op2);
739 assert((expr_op || imm_op) && "invalid operands");
741 if (mode_is_float(mode)) {
743 if (USE_SSE2(env_cg))
744 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
746 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
751 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
752 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
754 /* No expr_op means, that we have two const - one symconst and */
755 /* one tarval or another symconst - because this case is not */
756 /* covered by constant folding */
757 /* We need to check for: */
758 /* 1) symconst + const -> becomes a LEA */
759 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
760 /* linker doesn't support two symconsts */
762 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
763 /* this is the 2nd case */
764 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
765 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
766 set_ia32_am_flavour(new_op, ia32_am_B);
767 set_ia32_op_type(new_op, ia32_AddrModeS);
769 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
770 } else if (tp1 == ia32_ImmSymConst) {
771 tarval *tv = get_ia32_Immop_tarval(new_op2);
772 long offs = get_tarval_long(tv);
774 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
775 add_irn_dep(new_op, get_irg_frame(irg));
776 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
778 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
779 add_ia32_am_offs_int(new_op, offs);
780 set_ia32_am_flavour(new_op, ia32_am_OB);
781 set_ia32_op_type(new_op, ia32_AddrModeS);
782 } else if (tp2 == ia32_ImmSymConst) {
783 tarval *tv = get_ia32_Immop_tarval(new_op1);
784 long offs = get_tarval_long(tv);
786 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
787 add_irn_dep(new_op, get_irg_frame(irg));
788 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
790 add_ia32_am_offs_int(new_op, offs);
791 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
792 set_ia32_am_flavour(new_op, ia32_am_OB);
793 set_ia32_op_type(new_op, ia32_AddrModeS);
795 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
796 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
797 tarval *restv = tarval_add(tv1, tv2);
799 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
801 new_op = new_rd_ia32_Const(dbgi, irg, block);
802 set_ia32_Const_tarval(new_op, restv);
803 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
806 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
809 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
810 tarval_classification_t class_tv, class_negtv;
811 tarval *tv = get_ia32_Immop_tarval(imm_op);
813 /* optimize tarvals */
814 class_tv = classify_tarval(tv);
815 class_negtv = classify_tarval(tarval_neg(tv));
817 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
818 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
819 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
820 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
822 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
823 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
824 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
825 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
831 /* This is a normal add */
832 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
835 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
836 set_ia32_commutative(new_op);
838 fold_immediate(new_op, 2, 3);
840 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
846 static ir_node *create_ia32_Mul(ir_node *node) {
847 ir_graph *irg = current_ir_graph;
848 dbg_info *dbgi = get_irn_dbg_info(node);
849 ir_node *block = be_transform_node(get_nodes_block(node));
850 ir_node *op1 = get_Mul_left(node);
851 ir_node *op2 = get_Mul_right(node);
852 ir_node *new_op1 = be_transform_node(op1);
853 ir_node *new_op2 = be_transform_node(op2);
854 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
855 ir_node *proj_EAX, *proj_EDX, *res;
858 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
859 set_ia32_commutative(res);
860 set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
862 /* imediates are not supported, so no fold_immediate */
863 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
864 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
868 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
876 * Creates an ia32 Mul.
878 * @return the created ia32 Mul node
880 static ir_node *gen_Mul(ir_node *node) {
881 ir_node *op1 = get_Mul_left(node);
882 ir_node *op2 = get_Mul_right(node);
883 ir_mode *mode = get_irn_mode(node);
885 if (mode_is_float(mode)) {
887 if (USE_SSE2(env_cg))
888 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
890 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
894 for the lower 32bit of the result it doesn't matter whether we use
895 signed or unsigned multiplication so we use IMul as it has fewer
898 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
902 * Creates an ia32 Mulh.
903 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
904 * this result while Mul returns the lower 32 bit.
906 * @return the created ia32 Mulh node
908 static ir_node *gen_Mulh(ir_node *node) {
909 ir_node *block = be_transform_node(get_nodes_block(node));
910 ir_node *op1 = get_irn_n(node, 0);
911 ir_node *new_op1 = be_transform_node(op1);
912 ir_node *op2 = get_irn_n(node, 1);
913 ir_node *new_op2 = be_transform_node(op2);
914 ir_graph *irg = current_ir_graph;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
917 ir_mode *mode = get_irn_mode(node);
918 ir_node *proj_EAX, *proj_EDX, *res;
921 assert(!mode_is_float(mode) && "Mulh with float not supported");
922 if (mode_is_signed(mode)) {
923 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
925 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
928 set_ia32_commutative(res);
929 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
931 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
932 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
936 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
944 * Creates an ia32 And.
946 * @return The created ia32 And node
948 static ir_node *gen_And(ir_node *node) {
949 ir_node *op1 = get_And_left(node);
950 ir_node *op2 = get_And_right(node);
952 assert (! mode_is_float(get_irn_mode(node)));
953 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
959 * Creates an ia32 Or.
961 * @return The created ia32 Or node
963 static ir_node *gen_Or(ir_node *node) {
964 ir_node *op1 = get_Or_left(node);
965 ir_node *op2 = get_Or_right(node);
967 assert (! mode_is_float(get_irn_mode(node)));
968 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
974 * Creates an ia32 Eor.
976 * @return The created ia32 Eor node
978 static ir_node *gen_Eor(ir_node *node) {
979 ir_node *op1 = get_Eor_left(node);
980 ir_node *op2 = get_Eor_right(node);
982 assert(! mode_is_float(get_irn_mode(node)));
983 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
989 * Creates an ia32 Max.
991 * @return the created ia32 Max node
993 static ir_node *gen_Max(ir_node *node) {
994 ir_node *block = be_transform_node(get_nodes_block(node));
995 ir_node *op1 = get_irn_n(node, 0);
996 ir_node *new_op1 = be_transform_node(op1);
997 ir_node *op2 = get_irn_n(node, 1);
998 ir_node *new_op2 = be_transform_node(op2);
999 ir_graph *irg = current_ir_graph;
1000 ir_mode *mode = get_irn_mode(node);
1001 dbg_info *dbgi = get_irn_dbg_info(node);
1002 ir_mode *op_mode = get_irn_mode(op1);
1005 assert(get_mode_size_bits(mode) == 32);
1007 if (mode_is_float(mode)) {
1009 if (USE_SSE2(env_cg)) {
1010 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
1012 panic("Can't create Max node");
1015 long pnc = pn_Cmp_Gt;
1016 if (! mode_is_signed(op_mode)) {
1017 pnc |= ia32_pn_Cmp_Unsigned;
1019 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1020 new_op1, new_op2, pnc);
1022 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1028 * Creates an ia32 Min.
1030 * @return the created ia32 Min node
1032 static ir_node *gen_Min(ir_node *node) {
1033 ir_node *block = be_transform_node(get_nodes_block(node));
1034 ir_node *op1 = get_irn_n(node, 0);
1035 ir_node *new_op1 = be_transform_node(op1);
1036 ir_node *op2 = get_irn_n(node, 1);
1037 ir_node *new_op2 = be_transform_node(op2);
1038 ir_graph *irg = current_ir_graph;
1039 ir_mode *mode = get_irn_mode(node);
1040 dbg_info *dbgi = get_irn_dbg_info(node);
1041 ir_mode *op_mode = get_irn_mode(op1);
1044 assert(get_mode_size_bits(mode) == 32);
1046 if (mode_is_float(mode)) {
1048 if (USE_SSE2(env_cg)) {
1049 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
1051 panic("can't create Min node");
1054 long pnc = pn_Cmp_Lt;
1055 if (! mode_is_signed(op_mode)) {
1056 pnc |= ia32_pn_Cmp_Unsigned;
1058 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1059 new_op1, new_op2, pnc);
1061 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1068 * Creates an ia32 Sub.
1070 * @return The created ia32 Sub node
1072 static ir_node *gen_Sub(ir_node *node) {
1073 ir_node *block = be_transform_node(get_nodes_block(node));
1074 ir_node *op1 = get_Sub_left(node);
1075 ir_node *new_op1 = be_transform_node(op1);
1076 ir_node *op2 = get_Sub_right(node);
1077 ir_node *new_op2 = be_transform_node(op2);
1078 ir_node *new_op = NULL;
1079 ir_graph *irg = current_ir_graph;
1080 dbg_info *dbgi = get_irn_dbg_info(node);
1081 ir_mode *mode = get_irn_mode(node);
1082 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1083 ir_node *nomem = new_NoMem();
1084 ir_node *expr_op, *imm_op;
1086 /* Check if immediate optimization is on and */
1087 /* if it's an operation with immediate. */
1088 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1089 expr_op = get_expr_op(new_op1, new_op2);
1091 assert((expr_op || imm_op) && "invalid operands");
1093 if (mode_is_float(mode)) {
1095 if (USE_SSE2(env_cg))
1096 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1098 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1103 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1104 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1106 /* No expr_op means, that we have two const - one symconst and */
1107 /* one tarval or another symconst - because this case is not */
1108 /* covered by constant folding */
1109 /* We need to check for: */
1110 /* 1) symconst - const -> becomes a LEA */
1111 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1112 /* linker doesn't support two symconsts */
1113 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1114 /* this is the 2nd case */
1115 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1116 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1117 set_ia32_am_sc_sign(new_op);
1118 set_ia32_am_flavour(new_op, ia32_am_B);
1120 DBG_OPT_LEA3(op1, op2, node, new_op);
1121 } else if (tp1 == ia32_ImmSymConst) {
1122 tarval *tv = get_ia32_Immop_tarval(new_op2);
1123 long offs = get_tarval_long(tv);
1125 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1126 add_irn_dep(new_op, get_irg_frame(irg));
1127 DBG_OPT_LEA3(op1, op2, node, new_op);
1129 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1130 add_ia32_am_offs_int(new_op, -offs);
1131 set_ia32_am_flavour(new_op, ia32_am_OB);
1132 set_ia32_op_type(new_op, ia32_AddrModeS);
1133 } else if (tp2 == ia32_ImmSymConst) {
1134 tarval *tv = get_ia32_Immop_tarval(new_op1);
1135 long offs = get_tarval_long(tv);
1137 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1138 add_irn_dep(new_op, get_irg_frame(irg));
1139 DBG_OPT_LEA3(op1, op2, node, new_op);
1141 add_ia32_am_offs_int(new_op, offs);
1142 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1143 set_ia32_am_sc_sign(new_op);
1144 set_ia32_am_flavour(new_op, ia32_am_OB);
1145 set_ia32_op_type(new_op, ia32_AddrModeS);
1147 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1148 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1149 tarval *restv = tarval_sub(tv1, tv2);
1151 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1153 new_op = new_rd_ia32_Const(dbgi, irg, block);
1154 set_ia32_Const_tarval(new_op, restv);
1155 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1158 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1160 } else if (imm_op) {
1161 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1162 tarval_classification_t class_tv, class_negtv;
1163 tarval *tv = get_ia32_Immop_tarval(imm_op);
1165 /* optimize tarvals */
1166 class_tv = classify_tarval(tv);
1167 class_negtv = classify_tarval(tarval_neg(tv));
1169 if (class_tv == TV_CLASSIFY_ONE) {
1170 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1171 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1172 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1174 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1175 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1176 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1183 /* This is a normal sub */
1184 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1186 /* set AM support */
1187 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1189 fold_immediate(new_op, 2, 3);
1191 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1199 * Generates an ia32 DivMod with additional infrastructure for the
1200 * register allocator if needed.
1202 * @param dividend -no comment- :)
1203 * @param divisor -no comment- :)
1204 * @param dm_flav flavour_Div/Mod/DivMod
1205 * @return The created ia32 DivMod node
1207 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1208 ir_node *divisor, ia32_op_flavour_t dm_flav)
1210 ir_node *block = be_transform_node(get_nodes_block(node));
1211 ir_node *new_dividend = be_transform_node(dividend);
1212 ir_node *new_divisor = be_transform_node(divisor);
1213 ir_graph *irg = current_ir_graph;
1214 dbg_info *dbgi = get_irn_dbg_info(node);
1215 ir_mode *mode = get_irn_mode(node);
1216 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1217 ir_node *res, *proj_div, *proj_mod;
1218 ir_node *edx_node, *cltd;
1219 ir_node *in_keep[2];
1220 ir_node *mem, *new_mem;
1221 ir_node *projs[pn_DivMod_max];
1224 ia32_collect_Projs(node, projs, pn_DivMod_max);
1226 proj_div = proj_mod = NULL;
1230 mem = get_Div_mem(node);
1231 mode = get_Div_resmode(node);
1232 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1233 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1236 mem = get_Mod_mem(node);
1237 mode = get_Mod_resmode(node);
1238 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1239 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1241 case flavour_DivMod:
1242 mem = get_DivMod_mem(node);
1243 mode = get_DivMod_resmode(node);
1244 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1245 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1246 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1249 panic("invalid divmod flavour!");
1251 new_mem = be_transform_node(mem);
1253 if (mode_is_signed(mode)) {
1254 /* in signed mode, we need to sign extend the dividend */
1255 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1256 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1257 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1259 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1260 add_irn_dep(edx_node, be_abi_get_start_barrier(env_cg->birg->abi));
1261 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1264 if (mode_is_signed(mode)) {
1265 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1267 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1270 set_ia32_exc_label(res, has_exc);
1271 set_irn_pinned(res, get_irn_pinned(node));
1273 /* Matze: code can't handle this at the moment... */
1275 /* set AM support */
1276 set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
1279 /* check, which Proj-Keep, we need to add */
1281 if (proj_div == NULL) {
1282 /* We have only mod result: add div res Proj-Keep */
1283 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1286 if (proj_mod == NULL) {
1287 /* We have only div result: add mod res Proj-Keep */
1288 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1292 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1294 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1301 * Wrapper for generate_DivMod. Sets flavour_Mod.
1304 static ir_node *gen_Mod(ir_node *node) {
1305 return generate_DivMod(node, get_Mod_left(node),
1306 get_Mod_right(node), flavour_Mod);
1310 * Wrapper for generate_DivMod. Sets flavour_Div.
1313 static ir_node *gen_Div(ir_node *node) {
1314 return generate_DivMod(node, get_Div_left(node),
1315 get_Div_right(node), flavour_Div);
1319 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1321 static ir_node *gen_DivMod(ir_node *node) {
1322 return generate_DivMod(node, get_DivMod_left(node),
1323 get_DivMod_right(node), flavour_DivMod);
1329 * Creates an ia32 floating Div.
1331 * @return The created ia32 xDiv node
1333 static ir_node *gen_Quot(ir_node *node) {
1334 ir_node *block = be_transform_node(get_nodes_block(node));
1335 ir_node *op1 = get_Quot_left(node);
1336 ir_node *new_op1 = be_transform_node(op1);
1337 ir_node *op2 = get_Quot_right(node);
1338 ir_node *new_op2 = be_transform_node(op2);
1339 ir_graph *irg = current_ir_graph;
1340 dbg_info *dbgi = get_irn_dbg_info(node);
1341 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1342 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1346 if (USE_SSE2(env_cg)) {
1347 ir_mode *mode = get_irn_mode(op1);
1348 if (is_ia32_xConst(new_op2)) {
1349 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1350 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1351 copy_ia32_Immop_attr(new_op, new_op2);
1353 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1354 // Matze: disabled for now, spillslot coalescer fails
1355 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1357 set_ia32_ls_mode(new_op, mode);
1359 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1360 &ia32_fp_cw_regs[REG_FPCW]);
1361 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1362 new_op2, nomem, fpcw);
1363 // Matze: disabled for now (spillslot coalescer fails)
1364 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1366 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1372 * Creates an ia32 Shl.
1374 * @return The created ia32 Shl node
1376 static ir_node *gen_Shl(ir_node *node) {
1377 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1384 * Creates an ia32 Shr.
1386 * @return The created ia32 Shr node
1388 static ir_node *gen_Shr(ir_node *node) {
1389 return gen_shift_binop(node, get_Shr_left(node),
1390 get_Shr_right(node), new_rd_ia32_Shr);
1396 * Creates an ia32 Sar.
1398 * @return The created ia32 Shrs node
1400 static ir_node *gen_Shrs(ir_node *node) {
1401 return gen_shift_binop(node, get_Shrs_left(node),
1402 get_Shrs_right(node), new_rd_ia32_Sar);
1408 * Creates an ia32 RotL.
1410 * @param op1 The first operator
1411 * @param op2 The second operator
1412 * @return The created ia32 RotL node
1414 static ir_node *gen_RotL(ir_node *node,
1415 ir_node *op1, ir_node *op2) {
1416 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1422 * Creates an ia32 RotR.
1423 * NOTE: There is no RotR with immediate because this would always be a RotL
1424 * "imm-mode_size_bits" which can be pre-calculated.
1426 * @param op1 The first operator
1427 * @param op2 The second operator
1428 * @return The created ia32 RotR node
1430 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1432 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1438 * Creates an ia32 RotR or RotL (depending on the found pattern).
1440 * @return The created ia32 RotL or RotR node
1442 static ir_node *gen_Rot(ir_node *node) {
1443 ir_node *rotate = NULL;
1444 ir_node *op1 = get_Rot_left(node);
1445 ir_node *op2 = get_Rot_right(node);
1447 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1448 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1449 that means we can create a RotR instead of an Add and a RotL */
1451 if (get_irn_op(op2) == op_Add) {
1453 ir_node *left = get_Add_left(add);
1454 ir_node *right = get_Add_right(add);
1455 if (is_Const(right)) {
1456 tarval *tv = get_Const_tarval(right);
1457 ir_mode *mode = get_irn_mode(node);
1458 long bits = get_mode_size_bits(mode);
1460 if (get_irn_op(left) == op_Minus &&
1461 tarval_is_long(tv) &&
1462 get_tarval_long(tv) == bits)
1464 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1465 rotate = gen_RotR(node, op1, get_Minus_op(left));
1470 if (rotate == NULL) {
1471 rotate = gen_RotL(node, op1, op2);
1480 * Transforms a Minus node.
1482 * @param op The Minus operand
1483 * @return The created ia32 Minus node
1485 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1486 ir_node *block = be_transform_node(get_nodes_block(node));
1487 ir_graph *irg = current_ir_graph;
1488 dbg_info *dbgi = get_irn_dbg_info(node);
1489 ir_mode *mode = get_irn_mode(node);
1494 if (mode_is_float(mode)) {
1495 ir_node *new_op = be_transform_node(op);
1497 if (USE_SSE2(env_cg)) {
1498 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1499 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1500 ir_node *nomem = new_rd_NoMem(irg);
1502 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1504 size = get_mode_size_bits(mode);
1505 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1507 set_ia32_am_sc(res, ent);
1508 set_ia32_op_type(res, ia32_AddrModeS);
1509 set_ia32_ls_mode(res, mode);
1511 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1514 res = gen_unop(node, op, new_rd_ia32_Neg);
1517 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1523 * Transforms a Minus node.
1525 * @return The created ia32 Minus node
1527 static ir_node *gen_Minus(ir_node *node) {
1528 return gen_Minus_ex(node, get_Minus_op(node));
1533 * Transforms a Not node.
1535 * @return The created ia32 Not node
1537 static ir_node *gen_Not(ir_node *node) {
1538 ir_node *op = get_Not_op(node);
1540 assert (! mode_is_float(get_irn_mode(node)));
1541 return gen_unop(node, op, new_rd_ia32_Not);
1547 * Transforms an Abs node.
1549 * @return The created ia32 Abs node
1551 static ir_node *gen_Abs(ir_node *node) {
1552 ir_node *block = be_transform_node(get_nodes_block(node));
1553 ir_node *op = get_Abs_op(node);
1554 ir_node *new_op = be_transform_node(op);
1555 ir_graph *irg = current_ir_graph;
1556 dbg_info *dbgi = get_irn_dbg_info(node);
1557 ir_mode *mode = get_irn_mode(node);
1558 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1559 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1560 ir_node *nomem = new_NoMem();
1561 ir_node *res, *p_eax, *p_edx;
1565 if (mode_is_float(mode)) {
1567 if (USE_SSE2(env_cg)) {
1568 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1570 size = get_mode_size_bits(mode);
1571 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1573 set_ia32_am_sc(res, ent);
1575 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1577 set_ia32_op_type(res, ia32_AddrModeS);
1578 set_ia32_ls_mode(res, mode);
1581 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1582 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1586 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1587 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1589 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1590 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1592 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1593 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1595 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1596 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1605 * Transforms a Load.
1607 * @return the created ia32 Load node
1609 static ir_node *gen_Load(ir_node *node) {
1610 ir_node *block = be_transform_node(get_nodes_block(node));
1611 ir_node *ptr = get_Load_ptr(node);
1612 ir_node *new_ptr = be_transform_node(ptr);
1613 ir_node *mem = get_Load_mem(node);
1614 ir_node *new_mem = be_transform_node(mem);
1615 ir_graph *irg = current_ir_graph;
1616 dbg_info *dbgi = get_irn_dbg_info(node);
1617 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1618 ir_mode *mode = get_Load_mode(node);
1620 ir_node *lptr = new_ptr;
1623 ir_node *projs[pn_Load_max];
1624 ia32_am_flavour_t am_flav = ia32_am_B;
1626 ia32_collect_Projs(node, projs, pn_Load_max);
1628 /* address might be a constant (symconst or absolute address) */
1629 if (is_ia32_Const(new_ptr)) {
1634 if (mode_is_float(mode)) {
1636 if (USE_SSE2(env_cg)) {
1637 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1638 res_mode = mode_xmm;
1640 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1641 res_mode = mode_vfp;
1644 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1649 check for special case: the loaded value might not be used
1651 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1652 /* add a result proj and a Keep to produce a pseudo use */
1653 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1655 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1658 /* base is a constant address */
1660 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1661 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1662 am_flav = ia32_am_N;
1664 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1665 long offs = get_tarval_long(tv);
1667 add_ia32_am_offs_int(new_op, offs);
1668 am_flav = ia32_am_O;
1672 set_irn_pinned(new_op, get_irn_pinned(node));
1673 set_ia32_op_type(new_op, ia32_AddrModeS);
1674 set_ia32_am_flavour(new_op, am_flav);
1675 set_ia32_ls_mode(new_op, mode);
1677 /* make sure we are scheduled behind the initial IncSP/Barrier
1678 * to avoid spills being placed before it
1680 if (block == get_irg_start_block(irg)) {
1681 add_irn_dep(new_op, get_irg_frame(irg));
1684 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1685 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1693 * Transforms a Store.
1695 * @return the created ia32 Store node
1697 static ir_node *gen_Store(ir_node *node) {
1698 ir_node *block = be_transform_node(get_nodes_block(node));
1699 ir_node *ptr = get_Store_ptr(node);
1700 ir_node *new_ptr = be_transform_node(ptr);
1701 ir_node *val = get_Store_value(node);
1702 ir_node *new_val = be_transform_node(val);
1703 ir_node *mem = get_Store_mem(node);
1704 ir_node *new_mem = be_transform_node(mem);
1705 ir_graph *irg = current_ir_graph;
1706 dbg_info *dbgi = get_irn_dbg_info(node);
1707 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1708 ir_node *sptr = new_ptr;
1709 ir_mode *mode = get_irn_mode(val);
1710 ir_node *sval = new_val;
1713 ia32_am_flavour_t am_flav = ia32_am_B;
1715 if (is_ia32_Const(new_val)) {
1716 assert(!mode_is_float(mode));
1720 /* address might be a constant (symconst or absolute address) */
1721 if (is_ia32_Const(new_ptr)) {
1726 if (mode_is_float(mode)) {
1728 if (USE_SSE2(env_cg)) {
1729 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1731 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem, mode);
1733 } else if (get_mode_size_bits(mode) == 8) {
1734 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1736 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1739 /* stored const is an immediate value */
1740 if (is_ia32_Const(new_val)) {
1741 assert(!mode_is_float(mode));
1742 copy_ia32_Immop_attr(new_op, new_val);
1745 /* base is an constant address */
1747 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1748 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1749 am_flav = ia32_am_N;
1751 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1752 long offs = get_tarval_long(tv);
1754 add_ia32_am_offs_int(new_op, offs);
1755 am_flav = ia32_am_O;
1759 set_irn_pinned(new_op, get_irn_pinned(node));
1760 set_ia32_op_type(new_op, ia32_AddrModeD);
1761 set_ia32_am_flavour(new_op, am_flav);
1762 set_ia32_ls_mode(new_op, mode);
1764 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1773 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1775 * @return The transformed node.
1777 static ir_node *gen_Cond(ir_node *node) {
1778 ir_node *block = be_transform_node(get_nodes_block(node));
1779 ir_graph *irg = current_ir_graph;
1780 dbg_info *dbgi = get_irn_dbg_info(node);
1781 ir_node *sel = get_Cond_selector(node);
1782 ir_mode *sel_mode = get_irn_mode(sel);
1783 ir_node *res = NULL;
1784 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1785 ir_node *cnst, *expr;
1787 if (is_Proj(sel) && sel_mode == mode_b) {
1788 ir_node *pred = get_Proj_pred(sel);
1789 ir_node *cmp_a = get_Cmp_left(pred);
1790 ir_node *new_cmp_a = be_transform_node(cmp_a);
1791 ir_node *cmp_b = get_Cmp_right(pred);
1792 ir_node *new_cmp_b = be_transform_node(cmp_b);
1793 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1794 ir_node *nomem = new_NoMem();
1796 int pnc = get_Proj_proj(sel);
1797 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1798 pnc |= ia32_pn_Cmp_Unsigned;
1801 /* check if we can use a CondJmp with immediate */
1802 cnst = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1803 expr = get_expr_op(new_cmp_a, new_cmp_b);
1805 if (cnst != NULL && expr != NULL) {
1806 /* immop has to be the right operand, we might need to flip pnc */
1807 if(cnst != new_cmp_b) {
1808 pnc = get_inversed_pnc(pnc);
1811 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1812 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1813 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1815 /* a Cmp A =/!= 0 */
1816 ir_node *op1 = expr;
1817 ir_node *op2 = expr;
1820 /* check, if expr is an only once used And operation */
1821 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1822 op1 = get_irn_n(expr, 2);
1823 op2 = get_irn_n(expr, 3);
1825 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1827 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1828 set_ia32_pncode(res, pnc);
1831 copy_ia32_Immop_attr(res, expr);
1834 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1839 if (mode_is_float(cmp_mode)) {
1841 if (USE_SSE2(env_cg)) {
1842 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1843 set_ia32_ls_mode(res, cmp_mode);
1849 assert(get_mode_size_bits(cmp_mode) == 32);
1850 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1852 copy_ia32_Immop_attr(res, cnst);
1855 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1857 if (mode_is_float(cmp_mode)) {
1859 if (USE_SSE2(env_cg)) {
1860 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1861 set_ia32_ls_mode(res, cmp_mode);
1864 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1865 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1866 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1870 assert(get_mode_size_bits(cmp_mode) == 32);
1871 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 set_ia32_commutative(res);
1876 set_ia32_pncode(res, pnc);
1877 // Matze: disabled for now, because the default collect_spills_walker
1878 // is not able to detect the mode of the spilled value
1879 // moreover, the lea optimize phase freely exchanges left/right
1880 // without updating the pnc
1881 //set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
1884 /* determine the smallest switch case value */
1885 ir_node *new_sel = be_transform_node(sel);
1886 int switch_min = INT_MAX;
1887 const ir_edge_t *edge;
1889 foreach_out_edge(node, edge) {
1890 int pn = get_Proj_proj(get_edge_src_irn(edge));
1891 switch_min = pn < switch_min ? pn : switch_min;
1895 /* if smallest switch case is not 0 we need an additional sub */
1896 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1897 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1898 add_ia32_am_offs_int(res, -switch_min);
1899 set_ia32_am_flavour(res, ia32_am_OB);
1900 set_ia32_op_type(res, ia32_AddrModeS);
1903 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1904 set_ia32_pncode(res, get_Cond_defaultProj(node));
1907 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1914 * Transforms a CopyB node.
1916 * @return The transformed node.
1918 static ir_node *gen_CopyB(ir_node *node) {
1919 ir_node *block = be_transform_node(get_nodes_block(node));
1920 ir_node *src = get_CopyB_src(node);
1921 ir_node *new_src = be_transform_node(src);
1922 ir_node *dst = get_CopyB_dst(node);
1923 ir_node *new_dst = be_transform_node(dst);
1924 ir_node *mem = get_CopyB_mem(node);
1925 ir_node *new_mem = be_transform_node(mem);
1926 ir_node *res = NULL;
1927 ir_graph *irg = current_ir_graph;
1928 dbg_info *dbgi = get_irn_dbg_info(node);
1929 int size = get_type_size_bytes(get_CopyB_type(node));
1930 ir_mode *dst_mode = get_irn_mode(dst);
1931 ir_mode *src_mode = get_irn_mode(src);
1935 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1936 /* then we need the size explicitly in ECX. */
1937 if (size >= 32 * 4) {
1938 rem = size & 0x3; /* size % 4 */
1941 res = new_rd_ia32_Const(dbgi, irg, block);
1942 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1943 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1945 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1946 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1948 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1949 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1950 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1951 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1952 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1955 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1956 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1958 /* ok: now attach Proj's because movsd will destroy esi and edi */
1959 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1960 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1961 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1964 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1970 ir_node *gen_be_Copy(ir_node *node)
1972 ir_node *result = be_duplicate_node(node);
1973 ir_mode *mode = get_irn_mode(result);
1975 if (mode_needs_gp_reg(mode)) {
1976 set_irn_mode(result, mode_Iu);
1985 * Transforms a Mux node into CMov.
1987 * @return The transformed node.
1989 static ir_node *gen_Mux(ir_node *node) {
1990 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1991 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1993 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1999 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2000 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2001 ir_node *psi_default);
2004 * Transforms a Psi node into CMov.
2006 * @return The transformed node.
2008 static ir_node *gen_Psi(ir_node *node) {
2009 ir_node *block = be_transform_node(get_nodes_block(node));
2010 ir_node *psi_true = get_Psi_val(node, 0);
2011 ir_node *psi_default = get_Psi_default(node);
2012 ia32_code_gen_t *cg = env_cg;
2013 ir_graph *irg = current_ir_graph;
2014 dbg_info *dbgi = get_irn_dbg_info(node);
2015 ir_node *cond = get_Psi_cond(node, 0);
2016 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2017 ir_node *nomem = new_NoMem();
2019 ir_node *cmp, *cmp_a, *cmp_b;
2020 ir_node *new_cmp_a, *new_cmp_b;
2024 assert(get_Psi_n_conds(node) == 1);
2025 assert(get_irn_mode(cond) == mode_b);
2027 if(is_And(cond) || is_Or(cond)) {
2028 ir_node *new_cond = be_transform_node(cond);
2029 tarval *tv_zero = new_tarval_from_long(0, mode_Iu);
2030 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0,
2032 arch_set_irn_register(env_cg->arch_env, zero,
2033 &ia32_gp_regs[REG_GP_NOREG]);
2035 /* we have to compare the result against zero */
2036 new_cmp_a = new_cond;
2041 cmp = get_Proj_pred(cond);
2042 cmp_a = get_Cmp_left(cmp);
2043 cmp_b = get_Cmp_right(cmp);
2044 cmp_mode = get_irn_mode(cmp_a);
2045 pnc = get_Proj_proj(cond);
2047 new_cmp_b = try_create_Immediate(cmp_b, 0);
2048 if(new_cmp_b == NULL) {
2049 new_cmp_b = try_create_Immediate(cmp_a, 0);
2050 if(new_cmp_b != NULL) {
2051 pnc = get_inversed_pnc(pnc);
2052 new_cmp_a = be_transform_node(cmp_b);
2055 new_cmp_a = be_transform_node(cmp_a);
2057 if(new_cmp_b == NULL) {
2058 new_cmp_a = be_transform_node(cmp_a);
2059 new_cmp_b = be_transform_node(cmp_b);
2062 if (!mode_is_signed(cmp_mode)) {
2063 pnc |= ia32_pn_Cmp_Unsigned;
2067 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2068 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2069 new_cmp_a, new_cmp_b, nomem, pnc);
2070 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2071 pnc = get_negated_pnc(pnc, cmp_mode);
2072 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2073 new_cmp_a, new_cmp_b, nomem, pnc);
2075 ir_node *new_psi_true = be_transform_node(psi_true);
2076 ir_node *new_psi_default = be_transform_node(psi_default);
2077 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2078 new_psi_true, new_psi_default, pnc);
2080 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2086 * Following conversion rules apply:
2090 * 1) n bit -> m bit n > m (downscale)
2092 * 2) n bit -> m bit n == m (sign change)
2094 * 3) n bit -> m bit n < m (upscale)
2095 * a) source is signed: movsx
2096 * b) source is unsigned: and with lower bits sets
2100 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2104 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2108 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2109 * x87 is mode_E internally, conversions happen only at load and store
2110 * in non-strict semantic
2114 * Create a conversion from x87 state register to general purpose.
2116 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2117 ir_node *block = be_transform_node(get_nodes_block(node));
2118 ir_node *op = get_Conv_op(node);
2119 ir_node *new_op = be_transform_node(op);
2120 ia32_code_gen_t *cg = env_cg;
2121 ir_graph *irg = current_ir_graph;
2122 dbg_info *dbgi = get_irn_dbg_info(node);
2123 ir_node *noreg = ia32_new_NoReg_gp(cg);
2124 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2125 ir_node *fist, *load;
2128 fist = new_rd_ia32_vfist(dbgi, irg, block,
2129 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2131 set_irn_pinned(fist, op_pin_state_floats);
2132 set_ia32_use_frame(fist);
2133 set_ia32_op_type(fist, ia32_AddrModeD);
2134 set_ia32_am_flavour(fist, ia32_am_B);
2135 set_ia32_ls_mode(fist, mode_Iu);
2136 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2139 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2141 set_irn_pinned(load, op_pin_state_floats);
2142 set_ia32_use_frame(load);
2143 set_ia32_op_type(load, ia32_AddrModeS);
2144 set_ia32_am_flavour(load, ia32_am_B);
2145 set_ia32_ls_mode(load, mode_Iu);
2146 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2148 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2152 * Create a conversion from general purpose to x87 register
2154 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2155 ir_node *block = be_transform_node(get_nodes_block(node));
2156 ir_node *op = get_Conv_op(node);
2157 ir_node *new_op = be_transform_node(op);
2158 ir_graph *irg = current_ir_graph;
2159 dbg_info *dbgi = get_irn_dbg_info(node);
2160 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2161 ir_node *nomem = new_NoMem();
2162 ir_node *fild, *store;
2165 /* first convert to 32 bit if necessary */
2166 src_bits = get_mode_size_bits(src_mode);
2167 if (src_bits == 8) {
2168 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2169 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2170 set_ia32_ls_mode(new_op, src_mode);
2171 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2172 } else if (src_bits < 32) {
2173 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2174 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2175 set_ia32_ls_mode(new_op, src_mode);
2176 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2180 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2182 set_ia32_use_frame(store);
2183 set_ia32_op_type(store, ia32_AddrModeD);
2184 set_ia32_am_flavour(store, ia32_am_OB);
2185 set_ia32_ls_mode(store, mode_Iu);
2188 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2190 set_ia32_use_frame(fild);
2191 set_ia32_op_type(fild, ia32_AddrModeS);
2192 set_ia32_am_flavour(fild, ia32_am_OB);
2193 set_ia32_ls_mode(fild, mode_Iu);
2195 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2198 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2201 ir_node *block = get_nodes_block(node);
2202 ir_graph *irg = current_ir_graph;
2203 dbg_info *dbgi = get_irn_dbg_info(node);
2204 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2205 ir_node *nomem = new_NoMem();
2206 int src_bits = get_mode_size_bits(src_mode);
2207 int tgt_bits = get_mode_size_bits(tgt_mode);
2208 ir_node *frame = get_irg_frame(irg);
2209 ir_mode *smaller_mode;
2210 ir_node *store, *load;
2213 if(src_bits <= tgt_bits)
2214 smaller_mode = src_mode;
2216 smaller_mode = tgt_mode;
2218 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2220 set_ia32_use_frame(store);
2221 set_ia32_op_type(store, ia32_AddrModeD);
2222 set_ia32_am_flavour(store, ia32_am_OB);
2224 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2226 set_ia32_use_frame(load);
2227 set_ia32_op_type(load, ia32_AddrModeS);
2228 set_ia32_am_flavour(load, ia32_am_OB);
2230 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2235 * Transforms a Conv node.
2237 * @return The created ia32 Conv node
2239 static ir_node *gen_Conv(ir_node *node) {
2240 ir_node *block = be_transform_node(get_nodes_block(node));
2241 ir_node *op = get_Conv_op(node);
2242 ir_node *new_op = be_transform_node(op);
2243 ir_graph *irg = current_ir_graph;
2244 dbg_info *dbgi = get_irn_dbg_info(node);
2245 ir_mode *src_mode = get_irn_mode(op);
2246 ir_mode *tgt_mode = get_irn_mode(node);
2247 int src_bits = get_mode_size_bits(src_mode);
2248 int tgt_bits = get_mode_size_bits(tgt_mode);
2249 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2250 ir_node *nomem = new_rd_NoMem(irg);
2253 if (src_mode == tgt_mode) {
2254 if (get_Conv_strict(node)) {
2255 if (USE_SSE2(env_cg)) {
2256 /* when we are in SSE mode, we can kill all strict no-op conversion */
2260 /* this should be optimized already, but who knows... */
2261 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2262 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2267 if (mode_is_float(src_mode)) {
2268 /* we convert from float ... */
2269 if (mode_is_float(tgt_mode)) {
2270 if(src_mode == mode_E && tgt_mode == mode_D
2271 && !get_Conv_strict(node)) {
2272 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2277 if (USE_SSE2(env_cg)) {
2278 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2279 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2280 set_ia32_ls_mode(res, tgt_mode);
2282 // Matze: TODO what about strict convs?
2283 if(get_Conv_strict(node)) {
2284 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2285 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2288 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2293 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2294 if (USE_SSE2(env_cg)) {
2295 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2296 set_ia32_ls_mode(res, src_mode);
2298 return gen_x87_fp_to_gp(node);
2302 /* we convert from int ... */
2303 if (mode_is_float(tgt_mode)) {
2306 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2307 if (USE_SSE2(env_cg)) {
2308 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2309 set_ia32_ls_mode(res, tgt_mode);
2310 if(src_bits == 32) {
2311 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2314 return gen_x87_gp_to_fp(node, src_mode);
2318 ir_mode *smaller_mode;
2321 if (src_bits == tgt_bits) {
2322 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2326 if (src_bits < tgt_bits) {
2327 smaller_mode = src_mode;
2328 smaller_bits = src_bits;
2330 smaller_mode = tgt_mode;
2331 smaller_bits = tgt_bits;
2334 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2335 if (smaller_bits == 8) {
2336 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2337 set_ia32_ls_mode(res, smaller_mode);
2339 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2340 set_ia32_ls_mode(res, smaller_mode);
2342 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2346 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2352 int check_immediate_constraint(tarval *tv, char immediate_constraint_type)
2356 assert(tarval_is_long(tv));
2357 val = get_tarval_long(tv);
2359 switch (immediate_constraint_type) {
2363 return val >= 0 && val <= 32;
2365 return val >= 0 && val <= 63;
2367 return val >= -128 && val <= 127;
2369 return val == 0xff || val == 0xffff;
2371 return val >= 0 && val <= 3;
2373 return val >= 0 && val <= 255;
2375 return val >= 0 && val <= 127;
2379 panic("Invalid immediate constraint found");
2384 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2387 tarval *offset = NULL;
2388 int offset_sign = 0;
2389 ir_entity *symconst_ent = NULL;
2390 int symconst_sign = 0;
2392 ir_node *cnst = NULL;
2393 ir_node *symconst = NULL;
2399 mode = get_irn_mode(node);
2400 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2401 !mode_is_reference(mode)) {
2405 if(is_Minus(node)) {
2407 node = get_Minus_op(node);
2410 if(is_Const(node)) {
2413 offset_sign = minus;
2414 } else if(is_SymConst(node)) {
2417 symconst_sign = minus;
2418 } else if(is_Add(node)) {
2419 ir_node *left = get_Add_left(node);
2420 ir_node *right = get_Add_right(node);
2421 if(is_Const(left) && is_SymConst(right)) {
2424 symconst_sign = minus;
2425 offset_sign = minus;
2426 } else if(is_SymConst(left) && is_Const(right)) {
2429 symconst_sign = minus;
2430 offset_sign = minus;
2432 } else if(is_Sub(node)) {
2433 ir_node *left = get_Sub_left(node);
2434 ir_node *right = get_Sub_right(node);
2435 if(is_Const(left) && is_SymConst(right)) {
2438 symconst_sign = !minus;
2439 offset_sign = minus;
2440 } else if(is_SymConst(left) && is_Const(right)) {
2443 symconst_sign = minus;
2444 offset_sign = !minus;
2451 offset = get_Const_tarval(cnst);
2452 if(!tarval_is_long(offset)) {
2453 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2458 if(!check_immediate_constraint(offset, immediate_constraint_type))
2461 if(symconst != NULL) {
2462 if(immediate_constraint_type != 0) {
2463 /* we need full 32bits for symconsts */
2467 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2469 symconst_ent = get_SymConst_entity(symconst);
2471 if(cnst == NULL && symconst == NULL)
2474 if(offset_sign && offset != NULL) {
2475 offset = tarval_neg(offset);
2478 irg = current_ir_graph;
2479 dbgi = get_irn_dbg_info(node);
2480 block = get_irg_start_block(irg);
2481 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2483 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2485 /* make sure we don't schedule stuff before the barrier */
2486 add_irn_dep(res, get_irg_frame(irg));
2491 typedef struct constraint_t constraint_t;
2492 struct constraint_t {
2495 const arch_register_req_t **out_reqs;
2497 const arch_register_req_t *req;
2498 unsigned immediate_possible;
2499 char immediate_type;
2502 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2504 int immediate_possible = 0;
2505 char immediate_type = 0;
2506 unsigned limited = 0;
2507 const arch_register_class_t *cls = NULL;
2509 struct obstack *obst;
2510 arch_register_req_t *req;
2511 unsigned *limited_ptr;
2515 /* TODO: replace all the asserts with nice error messages */
2517 printf("Constraint: %s\n", c);
2527 assert(cls == NULL ||
2528 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2529 cls = &ia32_reg_classes[CLASS_ia32_gp];
2530 limited |= 1 << REG_EAX;
2533 assert(cls == NULL ||
2534 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2535 cls = &ia32_reg_classes[CLASS_ia32_gp];
2536 limited |= 1 << REG_EBX;
2539 assert(cls == NULL ||
2540 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2541 cls = &ia32_reg_classes[CLASS_ia32_gp];
2542 limited |= 1 << REG_ECX;
2545 assert(cls == NULL ||
2546 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2547 cls = &ia32_reg_classes[CLASS_ia32_gp];
2548 limited |= 1 << REG_EDX;
2551 assert(cls == NULL ||
2552 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2553 cls = &ia32_reg_classes[CLASS_ia32_gp];
2554 limited |= 1 << REG_EDI;
2557 assert(cls == NULL ||
2558 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2559 cls = &ia32_reg_classes[CLASS_ia32_gp];
2560 limited |= 1 << REG_ESI;
2563 case 'q': /* q means lower part of the regs only, this makes no
2564 * difference to Q for us (we only assigne whole registers) */
2565 assert(cls == NULL ||
2566 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2567 cls = &ia32_reg_classes[CLASS_ia32_gp];
2568 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2572 assert(cls == NULL ||
2573 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2574 cls = &ia32_reg_classes[CLASS_ia32_gp];
2575 limited |= 1 << REG_EAX | 1 << REG_EDX;
2578 assert(cls == NULL ||
2579 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2580 cls = &ia32_reg_classes[CLASS_ia32_gp];
2581 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2582 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2589 assert(cls == NULL);
2590 cls = &ia32_reg_classes[CLASS_ia32_gp];
2596 /* TODO: mark values so the x87 simulator knows about t and u */
2597 assert(cls == NULL);
2598 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2603 assert(cls == NULL);
2604 /* TODO: check that sse2 is supported */
2605 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2615 assert(!immediate_possible);
2616 immediate_possible = 1;
2617 immediate_type = *c;
2621 assert(!immediate_possible);
2622 immediate_possible = 1;
2626 assert(!immediate_possible && cls == NULL);
2627 immediate_possible = 1;
2628 cls = &ia32_reg_classes[CLASS_ia32_gp];
2641 assert(constraint->is_in && "can only specify same constraint "
2644 sscanf(c, "%d%n", &same_as, &p);
2651 case 'E': /* no float consts yet */
2652 case 'F': /* no float consts yet */
2653 case 's': /* makes no sense on x86 */
2654 case 'X': /* we can't support that in firm */
2658 case '<': /* no autodecrement on x86 */
2659 case '>': /* no autoincrement on x86 */
2660 case 'C': /* sse constant not supported yet */
2661 case 'G': /* 80387 constant not supported yet */
2662 case 'y': /* we don't support mmx registers yet */
2663 case 'Z': /* not available in 32 bit mode */
2664 case 'e': /* not available in 32 bit mode */
2665 assert(0 && "asm constraint not supported");
2668 assert(0 && "unknown asm constraint found");
2675 const arch_register_req_t *other_constr;
2677 assert(cls == NULL && "same as and register constraint not supported");
2678 assert(!immediate_possible && "same as and immediate constraint not "
2680 assert(same_as < constraint->n_outs && "wrong constraint number in "
2681 "same_as constraint");
2683 other_constr = constraint->out_reqs[same_as];
2685 req = obstack_alloc(obst, sizeof(req[0]));
2686 req->cls = other_constr->cls;
2687 req->type = arch_register_req_type_should_be_same;
2688 req->limited = NULL;
2689 req->other_same = pos;
2690 req->other_different = -1;
2692 /* switch constraints. This is because in firm we have same_as
2693 * constraints on the output constraints while in the gcc asm syntax
2694 * they are specified on the input constraints */
2695 constraint->req = other_constr;
2696 constraint->out_reqs[same_as] = req;
2697 constraint->immediate_possible = 0;
2701 if(immediate_possible && cls == NULL) {
2702 cls = &ia32_reg_classes[CLASS_ia32_gp];
2704 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2705 assert(cls != NULL);
2707 if(immediate_possible) {
2708 assert(constraint->is_in
2709 && "imeediates make no sense for output constraints");
2711 /* todo: check types (no float input on 'r' constrainted in and such... */
2713 irg = current_ir_graph;
2714 obst = get_irg_obstack(irg);
2717 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2718 limited_ptr = (unsigned*) (req+1);
2720 req = obstack_alloc(obst, sizeof(req[0]));
2722 memset(req, 0, sizeof(req[0]));
2725 req->type = arch_register_req_type_limited;
2726 *limited_ptr = limited;
2727 req->limited = limited_ptr;
2729 req->type = arch_register_req_type_normal;
2733 constraint->req = req;
2734 constraint->immediate_possible = immediate_possible;
2735 constraint->immediate_type = immediate_type;
2739 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2746 panic("Clobbers not supported yet");
2749 ir_node *gen_ASM(ir_node *node)
2752 ir_graph *irg = current_ir_graph;
2753 ir_node *block = be_transform_node(get_nodes_block(node));
2754 dbg_info *dbgi = get_irn_dbg_info(node);
2761 ia32_asm_attr_t *attr;
2762 const arch_register_req_t **out_reqs;
2763 const arch_register_req_t **in_reqs;
2764 struct obstack *obst;
2765 constraint_t parsed_constraint;
2767 /* assembler could contain float statements */
2770 /* transform inputs */
2771 arity = get_irn_arity(node);
2772 in = alloca(arity * sizeof(in[0]));
2773 memset(in, 0, arity * sizeof(in[0]));
2775 n_outs = get_ASM_n_output_constraints(node);
2776 n_clobbers = get_ASM_n_clobbers(node);
2777 out_arity = n_outs + n_clobbers;
2779 /* construct register constraints */
2780 obst = get_irg_obstack(irg);
2781 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2782 parsed_constraint.out_reqs = out_reqs;
2783 parsed_constraint.n_outs = n_outs;
2784 parsed_constraint.is_in = 0;
2785 for(i = 0; i < out_arity; ++i) {
2789 const ir_asm_constraint *constraint;
2790 constraint = & get_ASM_output_constraints(node) [i];
2791 c = get_id_str(constraint->constraint);
2792 parse_asm_constraint(i, &parsed_constraint, c);
2794 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2795 c = get_id_str(glob_id);
2796 parse_clobber(node, i, &parsed_constraint, c);
2798 out_reqs[i] = parsed_constraint.req;
2801 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2802 parsed_constraint.is_in = 1;
2803 for(i = 0; i < arity; ++i) {
2804 const ir_asm_constraint *constraint;
2808 constraint = & get_ASM_input_constraints(node) [i];
2809 constr_id = constraint->constraint;
2810 c = get_id_str(constr_id);
2811 parse_asm_constraint(i, &parsed_constraint, c);
2812 in_reqs[i] = parsed_constraint.req;
2814 if(parsed_constraint.immediate_possible) {
2815 ir_node *pred = get_irn_n(node, i);
2816 char imm_type = parsed_constraint.immediate_type;
2817 ir_node *immediate = try_create_Immediate(pred, imm_type);
2819 if(immediate != NULL) {
2825 /* transform inputs */
2826 for(i = 0; i < arity; ++i) {
2828 ir_node *transformed;
2833 pred = get_irn_n(node, i);
2834 transformed = be_transform_node(pred);
2835 in[i] = transformed;
2838 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2840 generic_attr = get_irn_generic_attr(res);
2841 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2842 attr->asm_text = get_ASM_text(node);
2843 set_ia32_out_req_all(res, out_reqs);
2844 set_ia32_in_req_all(res, in_reqs);
2846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2851 /********************************************
2854 * | |__ ___ _ __ ___ __| | ___ ___
2855 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2856 * | |_) | __/ | | | (_) | (_| | __/\__ \
2857 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2859 ********************************************/
2861 static ir_node *gen_be_StackParam(ir_node *node) {
2862 ir_node *block = be_transform_node(get_nodes_block(node));
2863 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2864 ir_node *new_ptr = be_transform_node(ptr);
2865 ir_node *new_op = NULL;
2866 ir_graph *irg = current_ir_graph;
2867 dbg_info *dbgi = get_irn_dbg_info(node);
2868 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2869 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2870 ir_mode *load_mode = get_irn_mode(node);
2871 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2875 if (mode_is_float(load_mode)) {
2877 if (USE_SSE2(env_cg)) {
2878 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2879 pn_res = pn_ia32_xLoad_res;
2880 proj_mode = mode_xmm;
2882 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2883 pn_res = pn_ia32_vfld_res;
2884 proj_mode = mode_vfp;
2887 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2888 proj_mode = mode_Iu;
2889 pn_res = pn_ia32_Load_res;
2892 set_irn_pinned(new_op, op_pin_state_floats);
2893 set_ia32_frame_ent(new_op, ent);
2894 set_ia32_use_frame(new_op);
2896 set_ia32_op_type(new_op, ia32_AddrModeS);
2897 set_ia32_am_flavour(new_op, ia32_am_B);
2898 set_ia32_ls_mode(new_op, load_mode);
2899 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2901 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2903 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2907 * Transforms a FrameAddr into an ia32 Add.
2909 static ir_node *gen_be_FrameAddr(ir_node *node) {
2910 ir_node *block = be_transform_node(get_nodes_block(node));
2911 ir_node *op = be_get_FrameAddr_frame(node);
2912 ir_node *new_op = be_transform_node(op);
2913 ir_graph *irg = current_ir_graph;
2914 dbg_info *dbgi = get_irn_dbg_info(node);
2915 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2918 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2919 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2920 set_ia32_use_frame(res);
2921 set_ia32_am_flavour(res, ia32_am_OB);
2923 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2929 * Transforms a FrameLoad into an ia32 Load.
2931 static ir_node *gen_be_FrameLoad(ir_node *node) {
2932 ir_node *block = be_transform_node(get_nodes_block(node));
2933 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2934 ir_node *new_mem = be_transform_node(mem);
2935 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2936 ir_node *new_ptr = be_transform_node(ptr);
2937 ir_node *new_op = NULL;
2938 ir_graph *irg = current_ir_graph;
2939 dbg_info *dbgi = get_irn_dbg_info(node);
2940 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2941 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2942 ir_mode *mode = get_type_mode(get_entity_type(ent));
2943 ir_node *projs[pn_Load_max];
2945 ia32_collect_Projs(node, projs, pn_Load_max);
2947 if (mode_is_float(mode)) {
2949 if (USE_SSE2(env_cg)) {
2950 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2953 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2957 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2960 set_irn_pinned(new_op, op_pin_state_floats);
2961 set_ia32_frame_ent(new_op, ent);
2962 set_ia32_use_frame(new_op);
2964 set_ia32_op_type(new_op, ia32_AddrModeS);
2965 set_ia32_am_flavour(new_op, ia32_am_B);
2966 set_ia32_ls_mode(new_op, mode);
2968 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2975 * Transforms a FrameStore into an ia32 Store.
2977 static ir_node *gen_be_FrameStore(ir_node *node) {
2978 ir_node *block = be_transform_node(get_nodes_block(node));
2979 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2980 ir_node *new_mem = be_transform_node(mem);
2981 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2982 ir_node *new_ptr = be_transform_node(ptr);
2983 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2984 ir_node *new_val = be_transform_node(val);
2985 ir_node *new_op = NULL;
2986 ir_graph *irg = current_ir_graph;
2987 dbg_info *dbgi = get_irn_dbg_info(node);
2988 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2989 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2990 ir_mode *mode = get_irn_mode(val);
2992 if (mode_is_float(mode)) {
2994 if (USE_SSE2(env_cg)) {
2995 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2997 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2999 } else if (get_mode_size_bits(mode) == 8) {
3000 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3002 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3005 set_ia32_frame_ent(new_op, ent);
3006 set_ia32_use_frame(new_op);
3008 set_ia32_op_type(new_op, ia32_AddrModeD);
3009 set_ia32_am_flavour(new_op, ia32_am_B);
3010 set_ia32_ls_mode(new_op, mode);
3012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3018 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3020 static ir_node *gen_be_Return(ir_node *node) {
3021 ir_graph *irg = current_ir_graph;
3022 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3023 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3024 ir_entity *ent = get_irg_entity(irg);
3025 ir_type *tp = get_entity_type(ent);
3030 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3031 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3034 int pn_ret_val, pn_ret_mem, arity, i;
3036 assert(ret_val != NULL);
3037 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3038 return be_duplicate_node(node);
3041 res_type = get_method_res_type(tp, 0);
3043 if (! is_Primitive_type(res_type)) {
3044 return be_duplicate_node(node);
3047 mode = get_type_mode(res_type);
3048 if (! mode_is_float(mode)) {
3049 return be_duplicate_node(node);
3052 assert(get_method_n_ress(tp) == 1);
3054 pn_ret_val = get_Proj_proj(ret_val);
3055 pn_ret_mem = get_Proj_proj(ret_mem);
3057 /* get the Barrier */
3058 barrier = get_Proj_pred(ret_val);
3060 /* get result input of the Barrier */
3061 ret_val = get_irn_n(barrier, pn_ret_val);
3062 new_ret_val = be_transform_node(ret_val);
3064 /* get memory input of the Barrier */
3065 ret_mem = get_irn_n(barrier, pn_ret_mem);
3066 new_ret_mem = be_transform_node(ret_mem);
3068 frame = get_irg_frame(irg);
3070 dbgi = get_irn_dbg_info(barrier);
3071 block = be_transform_node(get_nodes_block(barrier));
3073 noreg = ia32_new_NoReg_gp(env_cg);
3075 /* store xmm0 onto stack */
3076 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3077 set_ia32_ls_mode(sse_store, mode);
3078 set_ia32_op_type(sse_store, ia32_AddrModeD);
3079 set_ia32_use_frame(sse_store);
3080 set_ia32_am_flavour(sse_store, ia32_am_B);
3083 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3084 set_ia32_ls_mode(fld, mode);
3085 set_ia32_op_type(fld, ia32_AddrModeS);
3086 set_ia32_use_frame(fld);
3087 set_ia32_am_flavour(fld, ia32_am_B);
3089 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3090 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3091 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3093 /* create a new barrier */
3094 arity = get_irn_arity(barrier);
3095 in = alloca(arity * sizeof(in[0]));
3096 for (i = 0; i < arity; ++i) {
3099 if (i == pn_ret_val) {
3101 } else if (i == pn_ret_mem) {
3104 ir_node *in = get_irn_n(barrier, i);
3105 new_in = be_transform_node(in);
3110 new_barrier = new_ir_node(dbgi, irg, block,
3111 get_irn_op(barrier), get_irn_mode(barrier),
3113 copy_node_attr(barrier, new_barrier);
3114 be_duplicate_deps(barrier, new_barrier);
3115 be_set_transformed_node(barrier, new_barrier);
3116 mark_irn_visited(barrier);
3118 /* transform normally */
3119 return be_duplicate_node(node);
3123 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3125 static ir_node *gen_be_AddSP(ir_node *node) {
3126 ir_node *block = be_transform_node(get_nodes_block(node));
3127 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3128 ir_node *new_sz = be_transform_node(sz);
3129 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3130 ir_node *new_sp = be_transform_node(sp);
3131 ir_graph *irg = current_ir_graph;
3132 dbg_info *dbgi = get_irn_dbg_info(node);
3133 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3134 ir_node *nomem = new_NoMem();
3137 /* ia32 stack grows in reverse direction, make a SubSP */
3138 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3139 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3140 fold_immediate(new_op, 2, 3);
3142 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3148 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3150 static ir_node *gen_be_SubSP(ir_node *node) {
3151 ir_node *block = be_transform_node(get_nodes_block(node));
3152 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3153 ir_node *new_sz = be_transform_node(sz);
3154 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3155 ir_node *new_sp = be_transform_node(sp);
3156 ir_graph *irg = current_ir_graph;
3157 dbg_info *dbgi = get_irn_dbg_info(node);
3158 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3159 ir_node *nomem = new_NoMem();
3162 /* ia32 stack grows in reverse direction, make an AddSP */
3163 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3164 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3165 fold_immediate(new_op, 2, 3);
3167 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3173 * This function just sets the register for the Unknown node
3174 * as this is not done during register allocation because Unknown
3175 * is an "ignore" node.
3177 static ir_node *gen_Unknown(ir_node *node) {
3178 ir_mode *mode = get_irn_mode(node);
3180 if (mode_is_float(mode)) {
3181 if (USE_SSE2(env_cg))
3182 return ia32_new_Unknown_xmm(env_cg);
3184 return ia32_new_Unknown_vfp(env_cg);
3185 } else if (mode_needs_gp_reg(mode)) {
3186 return ia32_new_Unknown_gp(env_cg);
3188 assert(0 && "unsupported Unknown-Mode");
3195 * Change some phi modes
3197 static ir_node *gen_Phi(ir_node *node) {
3198 ir_node *block = be_transform_node(get_nodes_block(node));
3199 ir_graph *irg = current_ir_graph;
3200 dbg_info *dbgi = get_irn_dbg_info(node);
3201 ir_mode *mode = get_irn_mode(node);
3204 if(mode_needs_gp_reg(mode)) {
3205 /* we shouldn't have any 64bit stuff around anymore */
3206 assert(get_mode_size_bits(mode) <= 32);
3207 /* all integer operations are on 32bit registers now */
3209 } else if(mode_is_float(mode)) {
3210 if (USE_SSE2(env_cg)) {
3217 /* phi nodes allow loops, so we use the old arguments for now
3218 * and fix this later */
3219 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3220 copy_node_attr(node, phi);
3221 be_duplicate_deps(node, phi);
3223 be_set_transformed_node(node, phi);
3224 be_enqueue_preds(node);
3229 /**********************************************************************
3232 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3233 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3234 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3235 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3237 **********************************************************************/
3239 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3241 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3244 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3245 ir_node *val, ir_node *mem);
3248 * Transforms a lowered Load into a "real" one.
3250 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3251 ir_node *block = be_transform_node(get_nodes_block(node));
3252 ir_node *ptr = get_irn_n(node, 0);
3253 ir_node *new_ptr = be_transform_node(ptr);
3254 ir_node *mem = get_irn_n(node, 1);
3255 ir_node *new_mem = be_transform_node(mem);
3256 ir_graph *irg = current_ir_graph;
3257 dbg_info *dbgi = get_irn_dbg_info(node);
3258 ir_mode *mode = get_ia32_ls_mode(node);
3259 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3263 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3264 lowering we have x87 nodes, so we need to enforce simulation.
3266 if (mode_is_float(mode)) {
3268 if (fp_unit == fp_x87)
3272 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3274 set_ia32_op_type(new_op, ia32_AddrModeS);
3275 set_ia32_am_flavour(new_op, ia32_am_OB);
3276 set_ia32_am_offs_int(new_op, 0);
3277 set_ia32_am_scale(new_op, 1);
3278 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3279 if (is_ia32_am_sc_sign(node))
3280 set_ia32_am_sc_sign(new_op);
3281 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3282 if (is_ia32_use_frame(node)) {
3283 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3284 set_ia32_use_frame(new_op);
3287 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3293 * Transforms a lowered Store into a "real" one.
3295 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3296 ir_node *block = be_transform_node(get_nodes_block(node));
3297 ir_node *ptr = get_irn_n(node, 0);
3298 ir_node *new_ptr = be_transform_node(ptr);
3299 ir_node *val = get_irn_n(node, 1);
3300 ir_node *new_val = be_transform_node(val);
3301 ir_node *mem = get_irn_n(node, 2);
3302 ir_node *new_mem = be_transform_node(mem);
3303 ir_graph *irg = current_ir_graph;
3304 dbg_info *dbgi = get_irn_dbg_info(node);
3305 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3306 ir_mode *mode = get_ia32_ls_mode(node);
3309 ia32_am_flavour_t am_flav = ia32_B;
3312 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3313 lowering we have x87 nodes, so we need to enforce simulation.
3315 if (mode_is_float(mode)) {
3317 if (fp_unit == fp_x87)
3321 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3323 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3325 add_ia32_am_offs_int(new_op, am_offs);
3328 set_ia32_op_type(new_op, ia32_AddrModeD);
3329 set_ia32_am_flavour(new_op, am_flav);
3330 set_ia32_ls_mode(new_op, mode);
3331 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3332 set_ia32_use_frame(new_op);
3334 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3341 * Transforms an ia32_l_XXX into a "real" XXX node
3343 * @param env The transformation environment
3344 * @return the created ia32 XXX node
3346 #define GEN_LOWERED_OP(op) \
3347 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3348 ir_mode *mode = get_irn_mode(node); \
3349 if (mode_is_float(mode)) \
3351 return gen_binop(node, get_binop_left(node), \
3352 get_binop_right(node), new_rd_ia32_##op,0); \
3355 #define GEN_LOWERED_x87_OP(op) \
3356 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3358 FORCE_x87(env_cg); \
3359 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3360 get_binop_right(node), new_rd_ia32_##op); \
3364 #define GEN_LOWERED_UNOP(op) \
3365 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3366 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3369 #define GEN_LOWERED_SHIFT_OP(op) \
3370 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3371 return gen_shift_binop(node, get_binop_left(node), \
3372 get_binop_right(node), new_rd_ia32_##op); \
3375 #define GEN_LOWERED_LOAD(op, fp_unit) \
3376 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3377 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3380 #define GEN_LOWERED_STORE(op, fp_unit) \
3381 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3382 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3389 GEN_LOWERED_OP(IMul)
3391 GEN_LOWERED_x87_OP(vfprem)
3392 GEN_LOWERED_x87_OP(vfmul)
3393 GEN_LOWERED_x87_OP(vfsub)
3395 GEN_LOWERED_UNOP(Neg)
3397 GEN_LOWERED_LOAD(vfild, fp_x87)
3398 GEN_LOWERED_LOAD(Load, fp_none)
3399 /*GEN_LOWERED_STORE(vfist, fp_x87)
3402 GEN_LOWERED_STORE(Store, fp_none)
3404 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3405 ir_node *block = be_transform_node(get_nodes_block(node));
3406 ir_node *left = get_binop_left(node);
3407 ir_node *new_left = be_transform_node(left);
3408 ir_node *right = get_binop_right(node);
3409 ir_node *new_right = be_transform_node(right);
3410 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3411 ir_graph *irg = current_ir_graph;
3412 dbg_info *dbgi = get_irn_dbg_info(node);
3413 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3414 &ia32_fp_cw_regs[REG_FPCW]);
3417 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3418 new_right, new_NoMem(), fpcw);
3419 clear_ia32_commutative(vfdiv);
3420 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3421 fold_immediate(vfdiv, 2, 3);
3423 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3431 * Transforms a l_MulS into a "real" MulS node.
3433 * @param env The transformation environment
3434 * @return the created ia32 Mul node
3436 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3437 ir_node *block = be_transform_node(get_nodes_block(node));
3438 ir_node *left = get_binop_left(node);
3439 ir_node *new_left = be_transform_node(left);
3440 ir_node *right = get_binop_right(node);
3441 ir_node *new_right = be_transform_node(right);
3442 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3443 ir_graph *irg = current_ir_graph;
3444 dbg_info *dbgi = get_irn_dbg_info(node);
3447 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3448 /* and then skip the result Proj, because all needed Projs are already there. */
3449 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3450 clear_ia32_commutative(muls);
3451 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3452 fold_immediate(muls, 2, 3);
3454 /* check if EAX and EDX proj exist, add missing one */
3455 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3456 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3457 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3459 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3464 GEN_LOWERED_SHIFT_OP(Shl)
3465 GEN_LOWERED_SHIFT_OP(Shr)
3466 GEN_LOWERED_SHIFT_OP(Sar)
3469 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3470 * op1 - target to be shifted
3471 * op2 - contains bits to be shifted into target
3473 * Only op3 can be an immediate.
3475 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3476 ir_node *op2, ir_node *count)
3478 ir_node *block = be_transform_node(get_nodes_block(node));
3479 ir_node *new_op1 = be_transform_node(op1);
3480 ir_node *new_op2 = be_transform_node(op2);
3481 ir_node *new_count = be_transform_node(count);
3482 ir_node *new_op = NULL;
3483 ir_graph *irg = current_ir_graph;
3484 dbg_info *dbgi = get_irn_dbg_info(node);
3485 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3486 ir_node *nomem = new_NoMem();
3490 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3492 /* Check if immediate optimization is on and */
3493 /* if it's an operation with immediate. */
3494 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3496 /* Limit imm_op within range imm8 */
3498 tv = get_ia32_Immop_tarval(imm_op);
3501 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3502 set_ia32_Immop_tarval(imm_op, tv);
3509 /* integer operations */
3511 /* This is ShiftD with const */
3512 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3514 if (is_ia32_l_ShlD(node))
3515 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3516 new_op1, new_op2, noreg, nomem);
3518 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3519 new_op1, new_op2, noreg, nomem);
3520 copy_ia32_Immop_attr(new_op, imm_op);
3523 /* This is a normal ShiftD */
3524 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3525 if (is_ia32_l_ShlD(node))
3526 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3527 new_op1, new_op2, new_count, nomem);
3529 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3530 new_op1, new_op2, new_count, nomem);
3533 /* set AM support */
3534 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3536 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3538 set_ia32_emit_cl(new_op);
3543 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3544 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3545 get_irn_n(node, 1), get_irn_n(node, 2));
3548 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3549 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3550 get_irn_n(node, 1), get_irn_n(node, 2));
3554 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3556 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3557 ir_node *block = be_transform_node(get_nodes_block(node));
3558 ir_node *val = get_irn_n(node, 1);
3559 ir_node *new_val = be_transform_node(val);
3560 ia32_code_gen_t *cg = env_cg;
3561 ir_node *res = NULL;
3562 ir_graph *irg = current_ir_graph;
3564 ir_node *noreg, *new_ptr, *new_mem;
3571 mem = get_irn_n(node, 2);
3572 new_mem = be_transform_node(mem);
3573 ptr = get_irn_n(node, 0);
3574 new_ptr = be_transform_node(ptr);
3575 noreg = ia32_new_NoReg_gp(cg);
3576 dbgi = get_irn_dbg_info(node);
3578 /* Store x87 -> MEM */
3579 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3580 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3581 set_ia32_use_frame(res);
3582 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3583 set_ia32_am_flavour(res, ia32_B);
3584 set_ia32_op_type(res, ia32_AddrModeD);
3586 /* Load MEM -> SSE */
3587 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3588 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3589 set_ia32_use_frame(res);
3590 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3591 set_ia32_am_flavour(res, ia32_B);
3592 set_ia32_op_type(res, ia32_AddrModeS);
3593 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3599 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3601 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3602 ir_node *block = be_transform_node(get_nodes_block(node));
3603 ir_node *val = get_irn_n(node, 1);
3604 ir_node *new_val = be_transform_node(val);
3605 ia32_code_gen_t *cg = env_cg;
3606 ir_graph *irg = current_ir_graph;
3607 ir_node *res = NULL;
3608 ir_entity *fent = get_ia32_frame_ent(node);
3609 ir_mode *lsmode = get_ia32_ls_mode(node);
3611 ir_node *noreg, *new_ptr, *new_mem;
3615 if (! USE_SSE2(cg)) {
3616 /* SSE unit is not used -> skip this node. */
3620 ptr = get_irn_n(node, 0);
3621 new_ptr = be_transform_node(ptr);
3622 mem = get_irn_n(node, 2);
3623 new_mem = be_transform_node(mem);
3624 noreg = ia32_new_NoReg_gp(cg);
3625 dbgi = get_irn_dbg_info(node);
3627 /* Store SSE -> MEM */
3628 if (is_ia32_xLoad(skip_Proj(new_val))) {
3629 ir_node *ld = skip_Proj(new_val);
3631 /* we can vfld the value directly into the fpu */
3632 fent = get_ia32_frame_ent(ld);
3633 ptr = get_irn_n(ld, 0);
3634 offs = get_ia32_am_offs_int(ld);
3636 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3637 set_ia32_frame_ent(res, fent);
3638 set_ia32_use_frame(res);
3639 set_ia32_ls_mode(res, lsmode);
3640 set_ia32_am_flavour(res, ia32_B);
3641 set_ia32_op_type(res, ia32_AddrModeD);
3645 /* Load MEM -> x87 */
3646 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3647 set_ia32_frame_ent(res, fent);
3648 set_ia32_use_frame(res);
3649 add_ia32_am_offs_int(res, offs);
3650 set_ia32_am_flavour(res, ia32_B);
3651 set_ia32_op_type(res, ia32_AddrModeS);
3652 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3657 /*********************************************************
3660 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3661 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3662 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3663 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3665 *********************************************************/
3668 * the BAD transformer.
3670 static ir_node *bad_transform(ir_node *node) {
3671 panic("No transform function for %+F available.\n", node);
3676 * Transform the Projs of an AddSP.
3678 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3679 ir_node *block = be_transform_node(get_nodes_block(node));
3680 ir_node *pred = get_Proj_pred(node);
3681 ir_node *new_pred = be_transform_node(pred);
3682 ir_graph *irg = current_ir_graph;
3683 dbg_info *dbgi = get_irn_dbg_info(node);
3684 long proj = get_Proj_proj(node);
3686 if (proj == pn_be_AddSP_res) {
3687 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3688 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3690 } else if (proj == pn_be_AddSP_M) {
3691 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3695 return new_rd_Unknown(irg, get_irn_mode(node));
3699 * Transform the Projs of a SubSP.
3701 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3702 ir_node *block = be_transform_node(get_nodes_block(node));
3703 ir_node *pred = get_Proj_pred(node);
3704 ir_node *new_pred = be_transform_node(pred);
3705 ir_graph *irg = current_ir_graph;
3706 dbg_info *dbgi = get_irn_dbg_info(node);
3707 long proj = get_Proj_proj(node);
3709 if (proj == pn_be_SubSP_res) {
3710 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3711 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3713 } else if (proj == pn_be_SubSP_M) {
3714 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3718 return new_rd_Unknown(irg, get_irn_mode(node));
3722 * Transform and renumber the Projs from a Load.
3724 static ir_node *gen_Proj_Load(ir_node *node) {
3725 ir_node *block = be_transform_node(get_nodes_block(node));
3726 ir_node *pred = get_Proj_pred(node);
3727 ir_node *new_pred = be_transform_node(pred);
3728 ir_graph *irg = current_ir_graph;
3729 dbg_info *dbgi = get_irn_dbg_info(node);
3730 long proj = get_Proj_proj(node);
3732 /* renumber the proj */
3733 if (is_ia32_Load(new_pred)) {
3734 if (proj == pn_Load_res) {
3735 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3736 } else if (proj == pn_Load_M) {
3737 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3739 } else if (is_ia32_xLoad(new_pred)) {
3740 if (proj == pn_Load_res) {
3741 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3742 } else if (proj == pn_Load_M) {
3743 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3745 } else if (is_ia32_vfld(new_pred)) {
3746 if (proj == pn_Load_res) {
3747 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3748 } else if (proj == pn_Load_M) {
3749 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3754 return new_rd_Unknown(irg, get_irn_mode(node));
3758 * Transform and renumber the Projs from a DivMod like instruction.
3760 static ir_node *gen_Proj_DivMod(ir_node *node) {
3761 ir_node *block = be_transform_node(get_nodes_block(node));
3762 ir_node *pred = get_Proj_pred(node);
3763 ir_node *new_pred = be_transform_node(pred);
3764 ir_graph *irg = current_ir_graph;
3765 dbg_info *dbgi = get_irn_dbg_info(node);
3766 ir_mode *mode = get_irn_mode(node);
3767 long proj = get_Proj_proj(node);
3769 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3771 switch (get_irn_opcode(pred)) {
3775 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3777 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3785 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3787 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3795 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3796 case pn_DivMod_res_div:
3797 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3798 case pn_DivMod_res_mod:
3799 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3809 return new_rd_Unknown(irg, mode);
3813 * Transform and renumber the Projs from a CopyB.
3815 static ir_node *gen_Proj_CopyB(ir_node *node) {
3816 ir_node *block = be_transform_node(get_nodes_block(node));
3817 ir_node *pred = get_Proj_pred(node);
3818 ir_node *new_pred = be_transform_node(pred);
3819 ir_graph *irg = current_ir_graph;
3820 dbg_info *dbgi = get_irn_dbg_info(node);
3821 ir_mode *mode = get_irn_mode(node);
3822 long proj = get_Proj_proj(node);
3825 case pn_CopyB_M_regular:
3826 if (is_ia32_CopyB_i(new_pred)) {
3827 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3828 } else if (is_ia32_CopyB(new_pred)) {
3829 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3837 return new_rd_Unknown(irg, mode);
3841 * Transform and renumber the Projs from a vfdiv.
3843 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3844 ir_node *block = be_transform_node(get_nodes_block(node));
3845 ir_node *pred = get_Proj_pred(node);
3846 ir_node *new_pred = be_transform_node(pred);
3847 ir_graph *irg = current_ir_graph;
3848 dbg_info *dbgi = get_irn_dbg_info(node);
3849 ir_mode *mode = get_irn_mode(node);
3850 long proj = get_Proj_proj(node);
3853 case pn_ia32_l_vfdiv_M:
3854 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3855 case pn_ia32_l_vfdiv_res:
3856 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3861 return new_rd_Unknown(irg, mode);
3865 * Transform and renumber the Projs from a Quot.
3867 static ir_node *gen_Proj_Quot(ir_node *node) {
3868 ir_node *block = be_transform_node(get_nodes_block(node));
3869 ir_node *pred = get_Proj_pred(node);
3870 ir_node *new_pred = be_transform_node(pred);
3871 ir_graph *irg = current_ir_graph;
3872 dbg_info *dbgi = get_irn_dbg_info(node);
3873 ir_mode *mode = get_irn_mode(node);
3874 long proj = get_Proj_proj(node);
3878 if (is_ia32_xDiv(new_pred)) {
3879 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3880 } else if (is_ia32_vfdiv(new_pred)) {
3881 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3885 if (is_ia32_xDiv(new_pred)) {
3886 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3887 } else if (is_ia32_vfdiv(new_pred)) {
3888 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3896 return new_rd_Unknown(irg, mode);
3900 * Transform the Thread Local Storage Proj.
3902 static ir_node *gen_Proj_tls(ir_node *node) {
3903 ir_node *block = be_transform_node(get_nodes_block(node));
3904 ir_graph *irg = current_ir_graph;
3905 dbg_info *dbgi = NULL;
3906 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3912 * Transform the Projs from a be_Call.
3914 static ir_node *gen_Proj_be_Call(ir_node *node) {
3915 ir_node *block = be_transform_node(get_nodes_block(node));
3916 ir_node *call = get_Proj_pred(node);
3917 ir_node *new_call = be_transform_node(call);
3918 ir_graph *irg = current_ir_graph;
3919 dbg_info *dbgi = get_irn_dbg_info(node);
3920 long proj = get_Proj_proj(node);
3921 ir_mode *mode = get_irn_mode(node);
3923 const arch_register_class_t *cls;
3925 /* The following is kinda tricky: If we're using SSE, then we have to
3926 * move the result value of the call in floating point registers to an
3927 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3928 * after the call, we have to make sure to correctly make the
3929 * MemProj and the result Proj use these 2 nodes
3931 if (proj == pn_be_Call_M_regular) {
3932 // get new node for result, are we doing the sse load/store hack?
3933 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3934 ir_node *call_res_new;
3935 ir_node *call_res_pred = NULL;
3937 if (call_res != NULL) {
3938 call_res_new = be_transform_node(call_res);
3939 call_res_pred = get_Proj_pred(call_res_new);
3942 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3943 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3945 assert(is_ia32_xLoad(call_res_pred));
3946 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3949 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3951 ir_node *frame = get_irg_frame(irg);
3952 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3954 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3956 const arch_register_class_t *cls;
3958 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3959 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3961 /* store st(0) onto stack */
3962 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3964 set_ia32_ls_mode(fstp, mode);
3965 set_ia32_op_type(fstp, ia32_AddrModeD);
3966 set_ia32_use_frame(fstp);
3967 set_ia32_am_flavour(fstp, ia32_am_B);
3969 /* load into SSE register */
3970 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3971 set_ia32_ls_mode(sse_load, mode);
3972 set_ia32_op_type(sse_load, ia32_AddrModeS);
3973 set_ia32_use_frame(sse_load);
3974 set_ia32_am_flavour(sse_load, ia32_am_B);
3976 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3978 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3980 /* get a Proj representing a caller save register */
3981 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3982 assert(is_Proj(p) && "Proj expected.");
3984 /* user of the the proj is the Keep */
3985 p = get_edge_src_irn(get_irn_out_edge_first(p));
3986 assert(be_is_Keep(p) && "Keep expected.");
3988 /* keep the result */
3989 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3990 keepin[0] = sse_load;
3991 be_new_Keep(cls, irg, block, 1, keepin);
3996 /* transform call modes */
3997 if (mode_is_data(mode)) {
3998 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4002 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4006 * Transform the Projs from a Cmp.
4008 static ir_node *gen_Proj_Cmp(ir_node *node)
4010 /* normally Cmps are processed when looking at Cond nodes, but this case
4011 * can happen in complicated Psi conditions */
4013 ir_graph *irg = current_ir_graph;
4014 dbg_info *dbgi = get_irn_dbg_info(node);
4015 ir_node *block = be_transform_node(get_nodes_block(node));
4016 ir_node *cmp = get_Proj_pred(node);
4017 long pnc = get_Proj_proj(node);
4018 ir_node *cmp_left = get_Cmp_left(cmp);
4019 ir_node *cmp_right = get_Cmp_right(cmp);
4020 ir_node *new_cmp_left;
4021 ir_node *new_cmp_right;
4022 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4023 ir_node *nomem = new_rd_NoMem(irg);
4024 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4027 assert(!mode_is_float(cmp_mode));
4029 /* (a != b) -> (a ^ b) */
4030 if(pnc == pn_Cmp_Lg) {
4031 if(is_Const_0(cmp_left)) {
4032 new_op = be_transform_node(cmp_right);
4033 } else if(is_Const_0(cmp_right)) {
4034 new_op = be_transform_node(cmp_left);
4036 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4042 * (a == b) -> !(a ^ b)
4043 * (a < 0) -> (a & 0x80000000) oder a >> 31
4044 * (a >= 0) -> (a >> 31) ^ 1
4047 if(!mode_is_signed(cmp_mode)) {
4048 pnc |= ia32_pn_Cmp_Unsigned;
4051 new_cmp_right = try_create_Immediate(cmp_right, 0);
4052 if(new_cmp_right == NULL) {
4053 new_cmp_right = try_create_Immediate(cmp_left, 0);
4054 if(new_cmp_right != NULL) {
4055 pnc = get_inversed_pnc(pnc);
4056 new_cmp_left = be_transform_node(cmp_right);
4059 new_cmp_left = be_transform_node(cmp_left);
4061 if(new_cmp_right == NULL) {
4062 new_cmp_left = be_transform_node(cmp_left);
4063 new_cmp_right = be_transform_node(cmp_right);
4066 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4067 new_cmp_right, nomem, pnc);
4068 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4074 * Transform and potentially renumber Proj nodes.
4076 static ir_node *gen_Proj(ir_node *node) {
4077 ir_graph *irg = current_ir_graph;
4078 dbg_info *dbgi = get_irn_dbg_info(node);
4079 ir_node *pred = get_Proj_pred(node);
4080 long proj = get_Proj_proj(node);
4082 if (is_Store(pred) || be_is_FrameStore(pred)) {
4083 if (proj == pn_Store_M) {
4084 return be_transform_node(pred);
4087 return new_r_Bad(irg);
4089 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4090 return gen_Proj_Load(node);
4091 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4092 return gen_Proj_DivMod(node);
4093 } else if (is_CopyB(pred)) {
4094 return gen_Proj_CopyB(node);
4095 } else if (is_Quot(pred)) {
4096 return gen_Proj_Quot(node);
4097 } else if (is_ia32_l_vfdiv(pred)) {
4098 return gen_Proj_l_vfdiv(node);
4099 } else if (be_is_SubSP(pred)) {
4100 return gen_Proj_be_SubSP(node);
4101 } else if (be_is_AddSP(pred)) {
4102 return gen_Proj_be_AddSP(node);
4103 } else if (be_is_Call(pred)) {
4104 return gen_Proj_be_Call(node);
4105 } else if (is_Cmp(pred)) {
4106 return gen_Proj_Cmp(node);
4107 } else if (get_irn_op(pred) == op_Start) {
4108 if (proj == pn_Start_X_initial_exec) {
4109 ir_node *block = get_nodes_block(pred);
4112 /* we exchange the ProjX with a jump */
4113 block = be_transform_node(block);
4114 jump = new_rd_Jmp(dbgi, irg, block);
4117 if (node == be_get_old_anchor(anchor_tls)) {
4118 return gen_Proj_tls(node);
4121 ir_node *new_pred = be_transform_node(pred);
4122 ir_node *block = be_transform_node(get_nodes_block(node));
4123 ir_mode *mode = get_irn_mode(node);
4124 if (mode_needs_gp_reg(mode)) {
4125 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4126 get_Proj_proj(node));
4127 #ifdef DEBUG_libfirm
4128 new_proj->node_nr = node->node_nr;
4134 return be_duplicate_node(node);
4138 * Enters all transform functions into the generic pointer
4140 static void register_transformers(void) {
4141 ir_op *op_Max, *op_Min, *op_Mulh;
4143 /* first clear the generic function pointer for all ops */
4144 clear_irp_opcodes_generic_func();
4146 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4147 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4184 /* transform ops from intrinsic lowering */
4204 /* GEN(ia32_l_vfist); TODO */
4206 GEN(ia32_l_X87toSSE);
4207 GEN(ia32_l_SSEtoX87);
4212 /* we should never see these nodes */
4227 /* handle generic backend nodes */
4238 /* set the register for all Unknown nodes */
4241 op_Max = get_op_Max();
4244 op_Min = get_op_Min();
4247 op_Mulh = get_op_Mulh();
4256 * Pre-transform all unknown and noreg nodes.
4258 static void ia32_pretransform_node(void *arch_cg) {
4259 ia32_code_gen_t *cg = arch_cg;
4261 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4262 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4263 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4264 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4265 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4266 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4269 /* do the transformation */
4270 void ia32_transform_graph(ia32_code_gen_t *cg) {
4271 register_transformers();
4273 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4276 void ia32_init_transform(void)
4278 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");