2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define TP_SFP_SIGN "ia32_sfp_sign"
77 #define TP_DFP_SIGN "ia32_dfp_sign"
78 #define TP_SFP_ABS "ia32_sfp_abs"
79 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
82 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
83 #define ENT_SFP_ABS "IA32_SFP_ABS"
84 #define ENT_DFP_ABS "IA32_DFP_ABS"
86 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
87 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
89 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
91 /** hold the current code generator during transformation */
92 static ia32_code_gen_t *env_cg = NULL;
93 static ir_node *initial_fpcw = NULL;
94 static heights_t *heights = NULL;
96 extern ir_op *get_op_Mulh(void);
98 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem);
102 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
109 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
112 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
114 ir_node *op2, ir_node *mem, ir_node *fpcw);
116 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *op);
119 /****************************************************************************************************
121 * | | | | / _| | | (_)
122 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
123 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
124 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
125 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
127 ****************************************************************************************************/
129 static ir_node *try_create_Immediate(ir_node *node,
130 char immediate_constraint_type);
132 static ir_node *create_immediate_or_transform(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
136 dbg_info *dbgi, ir_node *new_block,
140 * Return true if a mode can be stored in the GP register set
142 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
143 if(mode == mode_fpcw)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an entity that is initialized with a tarval
186 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
188 tarval *tv = get_Const_tarval(cnst);
189 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
194 ir_mode *mode = get_irn_mode(cnst);
195 ir_type *tp = get_Const_type(cnst);
196 if (tp == firm_unknown_type)
197 tp = get_prim_type(cg->isa->types, mode);
199 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
201 set_entity_ld_ident(res, get_entity_ident(res));
202 set_entity_visibility(res, visibility_local);
203 set_entity_variability(res, variability_constant);
204 set_entity_allocation(res, allocation_static);
206 /* we create a new entity here: It's initialization must resist on the
208 rem = current_ir_graph;
209 current_ir_graph = get_const_code_irg();
210 set_atomic_ent_value(res, new_Const_type(tv, tp));
211 current_ir_graph = rem;
213 pmap_insert(cg->isa->tv_ent, tv, res);
221 static int is_Const_0(ir_node *node) {
225 return classify_Const(node) == CNST_NULL;
228 static int is_Const_1(ir_node *node) {
232 return classify_Const(node) == CNST_ONE;
235 static int is_Const_Minus_1(ir_node *node) {
241 mode = get_irn_mode(node);
242 if(!mode_is_signed(mode))
245 tv = get_Const_tarval(node);
248 return classify_tarval(tv) == CNST_ONE;
252 * Transforms a Const.
254 static ir_node *gen_Const(ir_node *node) {
255 ir_graph *irg = current_ir_graph;
256 ir_node *old_block = get_nodes_block(node);
257 ir_node *block = be_transform_node(old_block);
258 dbg_info *dbgi = get_irn_dbg_info(node);
259 ir_mode *mode = get_irn_mode(node);
261 if (mode_is_float(mode)) {
263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
264 ir_node *nomem = new_NoMem();
268 if (! USE_SSE2(env_cg)) {
269 cnst_classify_t clss = classify_Const(node);
271 if (clss == CNST_NULL) {
272 load = new_rd_ia32_vfldz(dbgi, irg, block);
274 } else if (clss == CNST_ONE) {
275 load = new_rd_ia32_vfld1(dbgi, irg, block);
278 floatent = get_entity_for_tv(env_cg, node);
280 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
286 set_ia32_ls_mode(load, mode);
288 floatent = get_entity_for_tv(env_cg, node);
290 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
292 set_ia32_op_type(load, ia32_AddrModeS);
293 set_ia32_am_sc(load, floatent);
294 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
296 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
299 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
301 /* Const Nodes before the initial IncSP are a bad idea, because
302 * they could be spilled and we have no SP ready at that point yet.
303 * So add a dependency to the initial frame pointer calculation to
304 * avoid that situation.
306 if (get_irg_start_block(irg) == block) {
307 add_irn_dep(load, get_irg_frame(irg));
310 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
314 tarval *tv = get_Const_tarval(node);
317 tv = tarval_convert_to(tv, mode_Iu);
319 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
321 panic("couldn't convert constant tarval (%+F)", node);
323 val = get_tarval_long(tv);
325 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
326 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
329 if (get_irg_start_block(irg) == block) {
330 add_irn_dep(cnst, get_irg_frame(irg));
338 * Transforms a SymConst.
340 static ir_node *gen_SymConst(ir_node *node) {
341 ir_graph *irg = current_ir_graph;
342 ir_node *old_block = get_nodes_block(node);
343 ir_node *block = be_transform_node(old_block);
344 dbg_info *dbgi = get_irn_dbg_info(node);
345 ir_mode *mode = get_irn_mode(node);
348 if (mode_is_float(mode)) {
349 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
350 ir_node *nomem = new_NoMem();
352 if (USE_SSE2(env_cg))
353 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
355 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
356 set_ia32_am_sc(cnst, get_SymConst_entity(node));
360 if(get_SymConst_kind(node) != symconst_addr_ent) {
361 panic("backend only support symconst_addr_ent (at %+F)", node);
363 entity = get_SymConst_entity(node);
364 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 static int use_source_address_mode(ir_node *block, ir_node *node,
455 load = get_Proj_pred(node);
456 pn = get_Proj_proj(node);
457 if(!is_Load(load) || pn != pn_Load_res)
459 if(get_nodes_block(load) != block)
461 /* we only use address mode if we're the only user of the load */
462 if(get_irn_n_edges(node) > 1)
465 mode = get_irn_mode(node);
466 if(!mode_needs_gp_reg(mode))
468 if(get_mode_size_bits(mode) != 32)
471 /* don't do AM if other node inputs depend on the load (via mem-proj) */
472 if(other != NULL && get_nodes_block(other) == block
473 && heights_reachable_in_block(heights, other, load))
479 typedef struct ia32_address_mode_t ia32_address_mode_t;
480 struct ia32_address_mode_t {
484 ia32_op_type_t op_type;
491 static void build_address(ia32_address_mode_t *am, ir_node *node)
493 ia32_address_t *addr = &am->addr;
494 ir_node *load = get_Proj_pred(node);
495 ir_node *ptr = get_Load_ptr(load);
496 ir_node *mem = get_Load_mem(load);
497 ir_node *new_mem = be_transform_node(mem);
501 am->ls_mode = get_Load_mode(load);
502 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
504 /* construct load address */
505 ia32_create_address_mode(addr, ptr, 0);
510 base = ia32_new_NoReg_gp(env_cg);
512 base = be_transform_node(base);
516 index = ia32_new_NoReg_gp(env_cg);
518 index = be_transform_node(index);
526 static void set_address(ir_node *node, ia32_address_t *addr)
528 set_ia32_am_scale(node, addr->scale);
529 set_ia32_am_sc(node, addr->symconst_ent);
530 set_ia32_am_offs_int(node, addr->offset);
531 if(addr->symconst_sign)
532 set_ia32_am_sc_sign(node);
534 set_ia32_use_frame(node);
535 set_ia32_frame_ent(node, addr->frame_entity);
538 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
540 set_address(node, &am->addr);
542 set_ia32_op_type(node, am->op_type);
543 set_ia32_ls_mode(node, am->ls_mode);
545 set_ia32_commutative(node);
548 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
549 ir_node *op1, ir_node *op2, int commutative,
550 int use_am_and_immediates)
552 ia32_address_t *addr = &am->addr;
553 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
557 memset(am, 0, sizeof(am[0]));
559 new_op2 = try_create_Immediate(op2, 0);
560 if(new_op2 == NULL && use_source_address_mode(block, op2, op1)) {
561 build_address(am, op2);
562 new_op1 = be_transform_node(op1);
564 am->op_type = ia32_AddrModeS;
565 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
566 use_source_address_mode(block, op1, op2)) {
567 build_address(am, op1);
568 if(new_op2 != NULL) {
571 new_op1 = be_transform_node(op2);
575 am->op_type = ia32_AddrModeS;
577 new_op1 = be_transform_node(op1);
579 new_op2 = be_transform_node(op2);
580 am->op_type = ia32_Normal;
582 if(addr->base == NULL)
583 addr->base = noreg_gp;
584 if(addr->index == NULL)
585 addr->index = noreg_gp;
586 if(addr->mem == NULL)
587 addr->mem = new_NoMem();
589 am->new_op1 = new_op1;
590 am->new_op2 = new_op2;
591 am->commutative = commutative;
594 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
596 ir_graph *irg = current_ir_graph;
600 if(am->mem_proj == NULL)
603 /* we have to create a mode_T so the old MemProj can attach to us */
604 mode = get_irn_mode(node);
605 load = get_Proj_pred(am->mem_proj);
607 mark_irn_visited(load);
608 be_set_transformed_node(load, node);
611 set_irn_mode(node, mode_T);
612 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0);
619 * Construct a standard binary operation, set AM and immediate if required.
621 * @param op1 The first operand
622 * @param op2 The second operand
623 * @param func The node constructor function
624 * @return The constructed ia32 node.
626 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
627 construct_binop_func *func, int commutative)
629 ir_node *src_block = get_nodes_block(node);
630 ir_node *block = be_transform_node(src_block);
631 ir_graph *irg = current_ir_graph;
632 dbg_info *dbgi = get_irn_dbg_info(node);
634 ia32_address_mode_t am;
635 ia32_address_t *addr = &am.addr;
637 match_arguments(&am, src_block, op1, op2, commutative, 0);
639 new_node = func(dbgi, irg, block, addr->base, addr->index, am.new_op1,
640 am.new_op2, addr->mem);
641 set_am_attributes(new_node, &am);
642 /* we can't use source address mode anymore when using immediates */
643 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
644 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
645 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
647 new_node = fix_mem_proj(new_node, &am);
653 * Construct a standard binary operation, set AM and immediate if required.
655 * @param op1 The first operand
656 * @param op2 The second operand
657 * @param func The node constructor function
658 * @return The constructed ia32 node.
660 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
661 construct_binop_func *func)
663 ir_node *block = be_transform_node(get_nodes_block(node));
664 ir_node *new_op1 = be_transform_node(op1);
665 ir_node *new_op2 = be_transform_node(op2);
666 ir_node *new_node = NULL;
667 dbg_info *dbgi = get_irn_dbg_info(node);
668 ir_graph *irg = current_ir_graph;
669 ir_mode *mode = get_irn_mode(node);
670 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
671 ir_node *nomem = new_NoMem();
673 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
675 if (is_op_commutative(get_irn_op(node))) {
676 set_ia32_commutative(new_node);
678 set_ia32_ls_mode(new_node, mode);
680 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
685 static ir_node *get_fpcw(void)
688 if(initial_fpcw != NULL)
691 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
692 &ia32_fp_cw_regs[REG_FPCW]);
693 initial_fpcw = be_transform_node(fpcw);
699 * Construct a standard binary operation, set AM and immediate if required.
701 * @param op1 The first operand
702 * @param op2 The second operand
703 * @param func The node constructor function
704 * @return The constructed ia32 node.
706 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
707 construct_binop_float_func *func)
709 ir_node *block = be_transform_node(get_nodes_block(node));
710 ir_node *new_op1 = be_transform_node(op1);
711 ir_node *new_op2 = be_transform_node(op2);
712 ir_node *new_node = NULL;
713 dbg_info *dbgi = get_irn_dbg_info(node);
714 ir_graph *irg = current_ir_graph;
715 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
716 ir_node *nomem = new_NoMem();
718 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
720 if (is_op_commutative(get_irn_op(node))) {
721 set_ia32_commutative(new_node);
724 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
730 * Construct a shift/rotate binary operation, sets AM and immediate if required.
732 * @param op1 The first operand
733 * @param op2 The second operand
734 * @param func The node constructor function
735 * @return The constructed ia32 node.
737 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
738 construct_shift_func *func)
740 dbg_info *dbgi = get_irn_dbg_info(node);
741 ir_graph *irg = current_ir_graph;
742 ir_node *block = get_nodes_block(node);
743 ir_node *new_block = be_transform_node(block);
744 ir_node *new_op1 = be_transform_node(op1);
745 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
748 assert(! mode_is_float(get_irn_mode(node))
749 && "Shift/Rotate with float not supported");
751 res = func(dbgi, irg, new_block, new_op1, new_op2);
752 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
754 /* lowered shift instruction may have a dependency operand, handle it here */
755 if (get_irn_arity(node) == 3) {
756 /* we have a dependency */
757 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
758 add_irn_dep(res, new_dep);
766 * Construct a standard unary operation, set AM and immediate if required.
768 * @param op The operand
769 * @param func The node constructor function
770 * @return The constructed ia32 node.
772 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
774 ir_node *block = be_transform_node(get_nodes_block(node));
775 ir_node *new_op = be_transform_node(op);
776 ir_node *new_node = NULL;
777 ir_graph *irg = current_ir_graph;
778 dbg_info *dbgi = get_irn_dbg_info(node);
780 new_node = func(dbgi, irg, block, new_op);
782 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
787 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
788 ia32_address_t *addr)
790 ir_graph *irg = current_ir_graph;
791 ir_node *base = addr->base;
792 ir_node *index = addr->index;
796 base = ia32_new_NoReg_gp(env_cg);
798 base = be_transform_node(base);
802 index = ia32_new_NoReg_gp(env_cg);
804 index = be_transform_node(index);
807 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
808 set_address(res, addr);
813 static int am_has_immediates(const ia32_address_t *addr)
815 return addr->offset != 0 || addr->symconst_ent != NULL
816 || addr->frame_entity || addr->use_frame;
820 * Creates an ia32 Add.
822 * @return the created ia32 Add node
824 static ir_node *gen_Add(ir_node *node) {
825 ir_node *block = be_transform_node(get_nodes_block(node));
826 ir_node *op1 = get_Add_left(node);
827 ir_node *op2 = get_Add_right(node);
830 ir_graph *irg = current_ir_graph;
831 dbg_info *dbgi = get_irn_dbg_info(node);
832 ir_mode *mode = get_irn_mode(node);
833 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
834 ir_node *src_block = get_nodes_block(node);
835 ir_node *add_immediate_op;
837 ia32_address_mode_t am;
839 if (mode_is_float(mode)) {
840 if (USE_SSE2(env_cg))
841 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
843 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
848 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
849 * 1. Add with immediate -> Lea
850 * 2. Add with possible source address mode -> Add
851 * 3. Otherwise -> Lea
853 memset(&addr, 0, sizeof(addr));
854 ia32_create_address_mode(&addr, node, 1);
855 add_immediate_op = NULL;
857 if(addr.base == NULL && addr.index == NULL) {
858 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
859 addr.symconst_sign, addr.offset);
860 add_irn_dep(new_op, get_irg_frame(irg));
861 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
864 /* add with immediate? */
865 if(addr.index == NULL) {
866 add_immediate_op = addr.base;
867 } else if(addr.base == NULL && addr.scale == 0) {
868 add_immediate_op = addr.index;
871 if(add_immediate_op != NULL) {
872 if(!am_has_immediates(&addr)) {
874 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
877 return be_transform_node(add_immediate_op);
880 new_op = create_lea_from_address(dbgi, block, &addr);
881 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
885 /* test if we can use source address mode */
886 memset(&am, 0, sizeof(am));
888 if(use_source_address_mode(src_block, op2, op1)) {
889 build_address(&am, op2);
890 new_op1 = be_transform_node(op1);
891 } else if(use_source_address_mode(src_block, op1, op2)) {
892 build_address(&am, op1);
893 new_op1 = be_transform_node(op2);
895 /* construct an Add with source address mode */
896 if(new_op1 != NULL) {
897 ia32_address_t *am_addr = &am.addr;
898 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base,
899 am_addr->index, new_op1, noreg, am_addr->mem);
900 set_address(new_op, am_addr);
901 set_ia32_op_type(new_op, ia32_AddrModeS);
902 set_ia32_ls_mode(new_op, am.ls_mode);
903 set_ia32_commutative(new_op);
904 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
906 new_op = fix_mem_proj(new_op, &am);
911 /* otherwise construct a lea */
912 new_op = create_lea_from_address(dbgi, block, &addr);
913 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
918 * Creates an ia32 Mul.
920 * @return the created ia32 Mul node
922 static ir_node *gen_Mul(ir_node *node) {
923 ir_node *op1 = get_Mul_left(node);
924 ir_node *op2 = get_Mul_right(node);
925 ir_mode *mode = get_irn_mode(node);
927 if (mode_is_float(mode)) {
928 if (USE_SSE2(env_cg))
929 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
931 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
935 for the lower 32bit of the result it doesn't matter whether we use
936 signed or unsigned multiplication so we use IMul as it has fewer
939 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
943 * Creates an ia32 Mulh.
944 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
945 * this result while Mul returns the lower 32 bit.
947 * @return the created ia32 Mulh node
949 static ir_node *gen_Mulh(ir_node *node) {
950 ir_node *block = be_transform_node(get_nodes_block(node));
951 ir_node *op1 = get_irn_n(node, 0);
952 ir_node *new_op1 = be_transform_node(op1);
953 ir_node *op2 = get_irn_n(node, 1);
954 ir_node *new_op2 = be_transform_node(op2);
955 ir_graph *irg = current_ir_graph;
956 dbg_info *dbgi = get_irn_dbg_info(node);
957 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
958 ir_mode *mode = get_irn_mode(node);
959 ir_node *proj_EDX, *res;
961 assert(!mode_is_float(mode) && "Mulh with float not supported");
962 if (mode_is_signed(mode)) {
963 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
964 new_op2, new_NoMem());
966 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
970 set_ia32_commutative(res);
972 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
980 * Creates an ia32 And.
982 * @return The created ia32 And node
984 static ir_node *gen_And(ir_node *node) {
985 ir_node *op1 = get_And_left(node);
986 ir_node *op2 = get_And_right(node);
987 assert(! mode_is_float(get_irn_mode(node)));
989 /* is it a zero extension? */
991 tarval *tv = get_Const_tarval(op2);
992 long v = get_tarval_long(tv);
994 if (v == 0xFF || v == 0xFFFF) {
995 dbg_info *dbgi = get_irn_dbg_info(node);
996 ir_node *block = be_transform_node(get_nodes_block(node));
997 ir_node *new_op = be_transform_node(op1);
1004 assert(v == 0xFFFF);
1007 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
1008 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1014 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1020 * Creates an ia32 Or.
1022 * @return The created ia32 Or node
1024 static ir_node *gen_Or(ir_node *node) {
1025 ir_node *op1 = get_Or_left(node);
1026 ir_node *op2 = get_Or_right(node);
1028 assert (! mode_is_float(get_irn_mode(node)));
1029 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1035 * Creates an ia32 Eor.
1037 * @return The created ia32 Eor node
1039 static ir_node *gen_Eor(ir_node *node) {
1040 ir_node *op1 = get_Eor_left(node);
1041 ir_node *op2 = get_Eor_right(node);
1043 assert(! mode_is_float(get_irn_mode(node)));
1044 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1049 * Creates an ia32 Sub.
1051 * @return The created ia32 Sub node
1053 static ir_node *gen_Sub(ir_node *node) {
1054 ir_node *op1 = get_Sub_left(node);
1055 ir_node *op2 = get_Sub_right(node);
1056 ir_mode *mode = get_irn_mode(node);
1058 if (mode_is_float(mode)) {
1059 if (USE_SSE2(env_cg))
1060 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1062 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1066 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1070 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1076 * Generates an ia32 DivMod with additional infrastructure for the
1077 * register allocator if needed.
1079 * @param dividend -no comment- :)
1080 * @param divisor -no comment- :)
1081 * @param dm_flav flavour_Div/Mod/DivMod
1082 * @return The created ia32 DivMod node
1084 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1085 ir_node *divisor, ia32_op_flavour_t dm_flav)
1087 ir_node *block = be_transform_node(get_nodes_block(node));
1088 ir_node *new_dividend = be_transform_node(dividend);
1089 ir_node *new_divisor = be_transform_node(divisor);
1090 ir_graph *irg = current_ir_graph;
1091 dbg_info *dbgi = get_irn_dbg_info(node);
1092 ir_mode *mode = get_irn_mode(node);
1093 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1094 ir_node *res, *proj_div, *proj_mod;
1095 ir_node *sign_extension;
1096 ir_node *mem, *new_mem;
1099 proj_div = proj_mod = NULL;
1103 mem = get_Div_mem(node);
1104 mode = get_Div_resmode(node);
1105 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1106 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1109 mem = get_Mod_mem(node);
1110 mode = get_Mod_resmode(node);
1111 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1112 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1114 case flavour_DivMod:
1115 mem = get_DivMod_mem(node);
1116 mode = get_DivMod_resmode(node);
1117 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1118 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1119 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1122 panic("invalid divmod flavour!");
1124 new_mem = be_transform_node(mem);
1126 if (mode_is_signed(mode)) {
1127 /* in signed mode, we need to sign extend the dividend */
1128 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1129 add_irn_dep(produceval, get_irg_frame(irg));
1130 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1133 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1134 add_irn_dep(sign_extension, get_irg_frame(irg));
1137 if (mode_is_signed(mode)) {
1138 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1139 sign_extension, new_divisor, new_mem, dm_flav);
1141 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1142 sign_extension, new_divisor, new_mem, dm_flav);
1145 set_ia32_exc_label(res, has_exc);
1146 set_irn_pinned(res, get_irn_pinned(node));
1148 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1155 * Wrapper for generate_DivMod. Sets flavour_Mod.
1158 static ir_node *gen_Mod(ir_node *node) {
1159 return generate_DivMod(node, get_Mod_left(node),
1160 get_Mod_right(node), flavour_Mod);
1164 * Wrapper for generate_DivMod. Sets flavour_Div.
1167 static ir_node *gen_Div(ir_node *node) {
1168 return generate_DivMod(node, get_Div_left(node),
1169 get_Div_right(node), flavour_Div);
1173 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1175 static ir_node *gen_DivMod(ir_node *node) {
1176 return generate_DivMod(node, get_DivMod_left(node),
1177 get_DivMod_right(node), flavour_DivMod);
1183 * Creates an ia32 floating Div.
1185 * @return The created ia32 xDiv node
1187 static ir_node *gen_Quot(ir_node *node) {
1188 ir_node *block = be_transform_node(get_nodes_block(node));
1189 ir_node *op1 = get_Quot_left(node);
1190 ir_node *new_op1 = be_transform_node(op1);
1191 ir_node *op2 = get_Quot_right(node);
1192 ir_node *new_op2 = be_transform_node(op2);
1193 ir_graph *irg = current_ir_graph;
1194 dbg_info *dbgi = get_irn_dbg_info(node);
1195 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1196 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1199 if (USE_SSE2(env_cg)) {
1200 ir_mode *mode = get_irn_mode(op1);
1201 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1,
1203 set_ia32_ls_mode(new_op, mode);
1205 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1206 new_op2, nomem, get_fpcw());
1208 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1214 * Creates an ia32 Shl.
1216 * @return The created ia32 Shl node
1218 static ir_node *gen_Shl(ir_node *node) {
1219 ir_node *right = get_Shl_right(node);
1221 /* test wether we can build a lea */
1222 if(is_Const(right)) {
1223 tarval *tv = get_Const_tarval(right);
1224 if(tarval_is_long(tv)) {
1225 long val = get_tarval_long(tv);
1226 if(val >= 0 && val <= 3) {
1227 ir_graph *irg = current_ir_graph;
1228 dbg_info *dbgi = get_irn_dbg_info(node);
1229 ir_node *block = be_transform_node(get_nodes_block(node));
1230 ir_node *base = ia32_new_NoReg_gp(env_cg);
1231 ir_node *index = be_transform_node(get_Shl_left(node));
1234 = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1235 set_ia32_am_scale(res, val);
1236 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1242 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1249 * Creates an ia32 Shr.
1251 * @return The created ia32 Shr node
1253 static ir_node *gen_Shr(ir_node *node) {
1254 return gen_shift_binop(node, get_Shr_left(node),
1255 get_Shr_right(node), new_rd_ia32_Shr);
1261 * Creates an ia32 Sar.
1263 * @return The created ia32 Shrs node
1265 static ir_node *gen_Shrs(ir_node *node) {
1266 ir_node *left = get_Shrs_left(node);
1267 ir_node *right = get_Shrs_right(node);
1268 ir_mode *mode = get_irn_mode(node);
1269 if(is_Const(right) && mode == mode_Is) {
1270 tarval *tv = get_Const_tarval(right);
1271 long val = get_tarval_long(tv);
1273 /* this is a sign extension */
1274 ir_graph *irg = current_ir_graph;
1275 dbg_info *dbgi = get_irn_dbg_info(node);
1276 ir_node *block = be_transform_node(get_nodes_block(node));
1278 ir_node *new_op = be_transform_node(op);
1279 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1280 add_irn_dep(pval, get_irg_frame(irg));
1282 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1286 /* 8 or 16 bit sign extension? */
1287 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1288 ir_node *shl_left = get_Shl_left(left);
1289 ir_node *shl_right = get_Shl_right(left);
1290 if(is_Const(shl_right)) {
1291 tarval *tv1 = get_Const_tarval(right);
1292 tarval *tv2 = get_Const_tarval(shl_right);
1293 if(tv1 == tv2 && tarval_is_long(tv1)) {
1294 long val = get_tarval_long(tv1);
1295 if(val == 16 || val == 24) {
1296 dbg_info *dbgi = get_irn_dbg_info(node);
1297 ir_node *block = be_transform_node(get_nodes_block(node));
1298 ir_node *new_op = be_transform_node(shl_left);
1308 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1310 SET_IA32_ORIG_NODE(res,
1311 ia32_get_old_node_name(env_cg, node));
1319 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1325 * Creates an ia32 RotL.
1327 * @param op1 The first operator
1328 * @param op2 The second operator
1329 * @return The created ia32 RotL node
1331 static ir_node *gen_RotL(ir_node *node,
1332 ir_node *op1, ir_node *op2) {
1333 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1339 * Creates an ia32 RotR.
1340 * NOTE: There is no RotR with immediate because this would always be a RotL
1341 * "imm-mode_size_bits" which can be pre-calculated.
1343 * @param op1 The first operator
1344 * @param op2 The second operator
1345 * @return The created ia32 RotR node
1347 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1349 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1355 * Creates an ia32 RotR or RotL (depending on the found pattern).
1357 * @return The created ia32 RotL or RotR node
1359 static ir_node *gen_Rot(ir_node *node) {
1360 ir_node *rotate = NULL;
1361 ir_node *op1 = get_Rot_left(node);
1362 ir_node *op2 = get_Rot_right(node);
1364 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1365 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1366 that means we can create a RotR instead of an Add and a RotL */
1368 if (get_irn_op(op2) == op_Add) {
1370 ir_node *left = get_Add_left(add);
1371 ir_node *right = get_Add_right(add);
1372 if (is_Const(right)) {
1373 tarval *tv = get_Const_tarval(right);
1374 ir_mode *mode = get_irn_mode(node);
1375 long bits = get_mode_size_bits(mode);
1377 if (get_irn_op(left) == op_Minus &&
1378 tarval_is_long(tv) &&
1379 get_tarval_long(tv) == bits)
1381 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1382 rotate = gen_RotR(node, op1, get_Minus_op(left));
1387 if (rotate == NULL) {
1388 rotate = gen_RotL(node, op1, op2);
1397 * Transforms a Minus node.
1399 * @param op The Minus operand
1400 * @return The created ia32 Minus node
1402 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1403 ir_node *block = be_transform_node(get_nodes_block(node));
1404 ir_graph *irg = current_ir_graph;
1405 dbg_info *dbgi = get_irn_dbg_info(node);
1406 ir_mode *mode = get_irn_mode(node);
1411 if (mode_is_float(mode)) {
1412 ir_node *new_op = be_transform_node(op);
1413 if (USE_SSE2(env_cg)) {
1414 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1415 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1416 ir_node *nomem = new_rd_NoMem(irg);
1418 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1420 size = get_mode_size_bits(mode);
1421 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1423 set_ia32_am_sc(res, ent);
1424 set_ia32_op_type(res, ia32_AddrModeS);
1425 set_ia32_ls_mode(res, mode);
1427 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1430 res = gen_unop(node, op, new_rd_ia32_Neg);
1433 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1439 * Transforms a Minus node.
1441 * @return The created ia32 Minus node
1443 static ir_node *gen_Minus(ir_node *node) {
1444 return gen_Minus_ex(node, get_Minus_op(node));
1447 static ir_node *create_Immediate_from_int(int val)
1449 ir_graph *irg = current_ir_graph;
1450 ir_node *start_block = get_irg_start_block(irg);
1451 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1452 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1457 static ir_node *gen_bin_Not(ir_node *node)
1459 ir_graph *irg = current_ir_graph;
1460 dbg_info *dbgi = get_irn_dbg_info(node);
1461 ir_node *block = be_transform_node(get_nodes_block(node));
1462 ir_node *op = get_Not_op(node);
1463 ir_node *new_op = be_transform_node(op);
1464 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1465 ir_node *nomem = new_NoMem();
1466 ir_node *one = create_Immediate_from_int(1);
1468 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1472 * Transforms a Not node.
1474 * @return The created ia32 Not node
1476 static ir_node *gen_Not(ir_node *node) {
1477 ir_node *op = get_Not_op(node);
1478 ir_mode *mode = get_irn_mode(node);
1480 if(mode == mode_b) {
1481 return gen_bin_Not(node);
1484 assert (! mode_is_float(get_irn_mode(node)));
1485 return gen_unop(node, op, new_rd_ia32_Not);
1491 * Transforms an Abs node.
1493 * @return The created ia32 Abs node
1495 static ir_node *gen_Abs(ir_node *node) {
1496 ir_node *block = be_transform_node(get_nodes_block(node));
1497 ir_node *op = get_Abs_op(node);
1498 ir_node *new_op = be_transform_node(op);
1499 ir_graph *irg = current_ir_graph;
1500 dbg_info *dbgi = get_irn_dbg_info(node);
1501 ir_mode *mode = get_irn_mode(node);
1502 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1503 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1504 ir_node *nomem = new_NoMem();
1509 if (mode_is_float(mode)) {
1510 if (USE_SSE2(env_cg)) {
1511 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1513 size = get_mode_size_bits(mode);
1514 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1516 set_ia32_am_sc(res, ent);
1518 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1520 set_ia32_op_type(res, ia32_AddrModeS);
1521 set_ia32_ls_mode(res, mode);
1524 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1525 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1529 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1530 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1533 add_irn_dep(pval, get_irg_frame(irg));
1534 SET_IA32_ORIG_NODE(sign_extension,
1535 ia32_get_old_node_name(env_cg, node));
1537 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1538 sign_extension, nomem);
1539 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1541 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1542 sign_extension, nomem);
1543 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1550 * Transforms a Load.
1552 * @return the created ia32 Load node
1554 static ir_node *gen_Load(ir_node *node) {
1555 ir_node *old_block = get_nodes_block(node);
1556 ir_node *block = be_transform_node(old_block);
1557 ir_node *ptr = get_Load_ptr(node);
1558 ir_node *mem = get_Load_mem(node);
1559 ir_node *new_mem = be_transform_node(mem);
1562 ir_graph *irg = current_ir_graph;
1563 dbg_info *dbgi = get_irn_dbg_info(node);
1564 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1565 ir_mode *mode = get_Load_mode(node);
1568 ia32_address_t addr;
1570 /* construct load address */
1571 memset(&addr, 0, sizeof(addr));
1572 ia32_create_address_mode(&addr, ptr, 0);
1579 base = be_transform_node(base);
1585 index = be_transform_node(index);
1588 if (mode_is_float(mode)) {
1589 if (USE_SSE2(env_cg)) {
1590 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1592 res_mode = mode_xmm;
1594 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1596 res_mode = mode_vfp;
1602 /* create a conv node with address mode for smaller modes */
1603 if(get_mode_size_bits(mode) < 32) {
1604 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, noreg,
1607 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1612 set_irn_pinned(new_op, get_irn_pinned(node));
1613 set_ia32_op_type(new_op, ia32_AddrModeS);
1614 set_ia32_ls_mode(new_op, mode);
1615 set_address(new_op, &addr);
1617 /* make sure we are scheduled behind the initial IncSP/Barrier
1618 * to avoid spills being placed before it
1620 if (block == get_irg_start_block(irg)) {
1621 add_irn_dep(new_op, get_irg_frame(irg));
1624 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1625 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1630 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1631 ir_node *ptr, ir_mode *mode, ir_node *other)
1638 /* we only use address mode if we're the only user of the load */
1639 if(get_irn_n_edges(node) > 1)
1642 load = get_Proj_pred(node);
1645 if(get_nodes_block(load) != block)
1648 /* Store should be attached to the load */
1649 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1651 /* store should have the same pointer as the load */
1652 if(get_Load_ptr(load) != ptr)
1655 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1656 if(other != NULL && get_nodes_block(other) == block
1657 && heights_reachable_in_block(heights, other, load))
1660 assert(get_Load_mode(load) == mode);
1665 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1666 ir_node *mem, ir_node *ptr, ir_mode *mode,
1667 construct_binop_dest_func *func, int commutative)
1669 ir_node *src_block = get_nodes_block(node);
1671 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1672 ir_graph *irg = current_ir_graph;
1676 ia32_address_mode_t am;
1677 ia32_address_t *addr = &am.addr;
1678 memset(&am, 0, sizeof(am));
1680 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1681 build_address(&am, op1);
1682 new_op = create_immediate_or_transform(op2, 0);
1683 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1684 build_address(&am, op2);
1685 new_op = create_immediate_or_transform(op1, 0);
1690 if(addr->base == NULL)
1691 addr->base = noreg_gp;
1692 if(addr->index == NULL)
1693 addr->index = noreg_gp;
1694 if(addr->mem == NULL)
1695 addr->mem = new_NoMem();
1697 dbgi = get_irn_dbg_info(node);
1698 block = be_transform_node(src_block);
1699 new_node = func(dbgi, irg, block, addr->base, addr->index, new_op,
1701 set_address(new_node, addr);
1702 set_ia32_op_type(new_node, ia32_AddrModeD);
1703 set_ia32_ls_mode(new_node, mode);
1704 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1709 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1710 ir_node *ptr, ir_mode *mode,
1711 construct_unop_dest_func *func)
1713 ir_node *src_block = get_nodes_block(node);
1715 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1716 ir_graph *irg = current_ir_graph;
1719 ia32_address_mode_t am;
1720 ia32_address_t *addr = &am.addr;
1721 memset(&am, 0, sizeof(am));
1723 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1726 build_address(&am, op);
1728 if(addr->base == NULL)
1729 addr->base = noreg_gp;
1730 if(addr->index == NULL)
1731 addr->index = noreg_gp;
1732 if(addr->mem == NULL)
1733 addr->mem = new_NoMem();
1735 dbgi = get_irn_dbg_info(node);
1736 block = be_transform_node(src_block);
1737 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1738 set_address(new_node, addr);
1739 set_ia32_op_type(new_node, ia32_AddrModeD);
1740 set_ia32_ls_mode(new_node, mode);
1741 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1746 static ir_node *try_create_dest_am(ir_node *node) {
1747 ir_node *val = get_Store_value(node);
1748 ir_node *mem = get_Store_mem(node);
1749 ir_node *ptr = get_Store_ptr(node);
1750 ir_mode *mode = get_irn_mode(val);
1755 /* handle only GP modes for now... */
1756 if(!mode_needs_gp_reg(mode))
1758 if(get_mode_size_bits(mode) != 32)
1761 /* store must be the only user of the val node */
1762 if(get_irn_n_edges(val) > 1)
1765 switch(get_irn_opcode(val)) {
1767 op1 = get_Add_left(val);
1768 op2 = get_Add_right(val);
1769 if(is_Const_1(op2)) {
1770 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1771 new_rd_ia32_IncMem);
1773 } else if(is_Const_Minus_1(op2)) {
1774 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1775 new_rd_ia32_DecMem);
1778 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1779 new_rd_ia32_AddMem, 1);
1782 op1 = get_Sub_left(val);
1783 op2 = get_Sub_right(val);
1784 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1785 new_rd_ia32_SubMem, 0);
1788 op1 = get_And_left(val);
1789 op2 = get_And_right(val);
1790 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1791 new_rd_ia32_AndMem, 1);
1794 op1 = get_Or_left(val);
1795 op2 = get_Or_right(val);
1796 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1797 new_rd_ia32_OrMem, 1);
1800 op1 = get_Eor_left(val);
1801 op2 = get_Eor_right(val);
1802 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1803 new_rd_ia32_XorMem, 1);
1806 op1 = get_Shl_left(val);
1807 op2 = get_Shl_right(val);
1808 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1809 new_rd_ia32_ShlMem, 0);
1812 op1 = get_Shr_left(val);
1813 op2 = get_Shr_right(val);
1814 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1815 new_rd_ia32_ShrMem, 0);
1818 op1 = get_Shrs_left(val);
1819 op2 = get_Shrs_right(val);
1820 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1821 new_rd_ia32_SarMem, 0);
1824 op1 = get_Rot_left(val);
1825 op2 = get_Rot_right(val);
1826 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1827 new_rd_ia32_RolMem, 0);
1829 /* TODO: match ROR patterns... */
1831 op1 = get_Minus_op(val);
1832 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1835 /* TODO this would be ^ 1 with DestAM */
1838 op1 = get_Not_op(val);
1839 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1849 * Transforms a Store.
1851 * @return the created ia32 Store node
1853 static ir_node *gen_Store(ir_node *node) {
1854 ir_node *block = be_transform_node(get_nodes_block(node));
1855 ir_node *ptr = get_Store_ptr(node);
1858 ir_node *val = get_Store_value(node);
1860 ir_node *mem = get_Store_mem(node);
1861 ir_node *new_mem = be_transform_node(mem);
1862 ir_graph *irg = current_ir_graph;
1863 dbg_info *dbgi = get_irn_dbg_info(node);
1864 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1865 ir_mode *mode = get_irn_mode(val);
1867 ia32_address_t addr;
1869 /* check for destination address mode */
1870 new_op = try_create_dest_am(node);
1874 /* construct load address */
1875 memset(&addr, 0, sizeof(addr));
1876 ia32_create_address_mode(&addr, ptr, 0);
1883 base = be_transform_node(base);
1889 index = be_transform_node(index);
1892 if (mode_is_float(mode)) {
1893 new_val = be_transform_node(val);
1894 if (USE_SSE2(env_cg)) {
1895 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_val,
1898 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_val,
1902 new_val = create_immediate_or_transform(val, 0);
1906 if (get_mode_size_bits(mode) == 8) {
1907 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
1910 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_val,
1915 set_irn_pinned(new_op, get_irn_pinned(node));
1916 set_ia32_op_type(new_op, ia32_AddrModeD);
1917 set_ia32_ls_mode(new_op, mode);
1919 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1920 set_address(new_op, &addr);
1921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1926 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1927 ir_node *cmp_left, ir_node *cmp_right)
1933 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1934 ia32_address_mode_t am;
1935 ia32_address_t *addr = &am.addr;
1937 if(cmp_right != NULL && !is_Const_0(cmp_right))
1940 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1941 mode = get_irn_mode(cmp_left);
1942 arg_left = get_And_left(cmp_left);
1943 arg_right = get_And_right(cmp_left);
1945 mode = get_irn_mode(cmp_left);
1946 arg_left = cmp_left;
1947 arg_right = cmp_left;
1953 assert(get_mode_size_bits(mode) <= 32);
1954 match_arguments(&am, block, arg_left, arg_right, 1, 1);
1956 pnc = get_inversed_pnc(pnc);
1958 if(get_mode_size_bits(mode) == 8) {
1959 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1960 addr->index, am.new_op1, am.new_op2,
1963 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1964 addr->index, am.new_op1, am.new_op2,
1967 set_am_attributes(res, &am);
1968 set_ia32_ls_mode(res, mode);
1970 res = fix_mem_proj(res, &am);
1975 static ir_node *create_Switch(ir_node *node)
1977 ir_graph *irg = current_ir_graph;
1978 dbg_info *dbgi = get_irn_dbg_info(node);
1979 ir_node *block = be_transform_node(get_nodes_block(node));
1980 ir_node *sel = get_Cond_selector(node);
1981 ir_node *new_sel = be_transform_node(sel);
1983 int switch_min = INT_MAX;
1984 const ir_edge_t *edge;
1986 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1988 /* determine the smallest switch case value */
1989 foreach_out_edge(node, edge) {
1990 ir_node *proj = get_edge_src_irn(edge);
1991 int pn = get_Proj_proj(proj);
1996 if (switch_min != 0) {
1997 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1999 /* if smallest switch case is not 0 we need an additional sub */
2000 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2001 add_ia32_am_offs_int(new_sel, -switch_min);
2002 set_ia32_op_type(new_sel, ia32_AddrModeS);
2004 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2007 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2008 set_ia32_pncode(res, get_Cond_defaultProj(node));
2010 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2016 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2018 * @return The transformed node.
2020 static ir_node *gen_Cond(ir_node *node) {
2021 ir_node *src_block = get_nodes_block(node);
2022 ir_node *block = be_transform_node(src_block);
2023 ir_graph *irg = current_ir_graph;
2024 dbg_info *dbgi = get_irn_dbg_info(node);
2025 ir_node *sel = get_Cond_selector(node);
2026 ir_mode *sel_mode = get_irn_mode(sel);
2027 ir_node *res = NULL;
2028 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2029 ir_node *nomem = new_NoMem();
2038 if (sel_mode != mode_b) {
2039 return create_Switch(node);
2042 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2043 /* it's some mode_b value but not a direct comparison -> create a
2045 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
2046 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2050 cmp = get_Proj_pred(sel);
2051 cmp_a = get_Cmp_left(cmp);
2052 cmp_b = get_Cmp_right(cmp);
2053 cmp_mode = get_irn_mode(cmp_a);
2054 pnc = get_Proj_proj(sel);
2055 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2056 pnc |= ia32_pn_Cmp_Unsigned;
2059 if(mode_needs_gp_reg(cmp_mode)) {
2060 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
2062 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2067 if (mode_is_float(cmp_mode)) {
2068 new_cmp_a = be_transform_node(cmp_a);
2069 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2070 if (USE_SSE2(env_cg)) {
2071 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, cmp_a,
2073 set_ia32_commutative(res);
2074 set_ia32_ls_mode(res, cmp_mode);
2076 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2077 set_ia32_commutative(res);
2080 ia32_address_mode_t am;
2081 ia32_address_t *addr = &am.addr;
2082 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1);
2084 pnc = get_inversed_pnc(pnc);
2086 if(get_mode_size_bits(cmp_mode) == 8) {
2087 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base,
2088 addr->index, am.new_op1, am.new_op2,
2091 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2092 am.new_op1, am.new_op2, addr->mem, pnc);
2094 set_am_attributes(res, &am);
2095 assert(cmp_mode != NULL);
2096 set_ia32_ls_mode(res, cmp_mode);
2098 res = fix_mem_proj(res, &am);
2101 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2109 * Transforms a CopyB node.
2111 * @return The transformed node.
2113 static ir_node *gen_CopyB(ir_node *node) {
2114 ir_node *block = be_transform_node(get_nodes_block(node));
2115 ir_node *src = get_CopyB_src(node);
2116 ir_node *new_src = be_transform_node(src);
2117 ir_node *dst = get_CopyB_dst(node);
2118 ir_node *new_dst = be_transform_node(dst);
2119 ir_node *mem = get_CopyB_mem(node);
2120 ir_node *new_mem = be_transform_node(mem);
2121 ir_node *res = NULL;
2122 ir_graph *irg = current_ir_graph;
2123 dbg_info *dbgi = get_irn_dbg_info(node);
2124 int size = get_type_size_bytes(get_CopyB_type(node));
2127 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2128 /* then we need the size explicitly in ECX. */
2129 if (size >= 32 * 4) {
2130 rem = size & 0x3; /* size % 4 */
2133 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2134 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2136 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2137 /* we misuse the pncode field for the copyb size */
2138 set_ia32_pncode(res, rem);
2140 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2141 set_ia32_pncode(res, size);
2144 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2150 ir_node *gen_be_Copy(ir_node *node)
2152 ir_node *result = be_duplicate_node(node);
2153 ir_mode *mode = get_irn_mode(result);
2155 if (mode_needs_gp_reg(mode)) {
2156 set_irn_mode(result, mode_Iu);
2163 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2164 dbg_info *dbgi, ir_node *block)
2166 ir_graph *irg = current_ir_graph;
2167 ir_node *new_block = be_transform_node(block);
2168 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2169 ir_node *nomem = new_rd_NoMem(irg);
2174 ia32_address_mode_t am;
2175 ia32_address_t *addr = &am.addr;
2177 /* can we use a test instruction? */
2178 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2179 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2180 if(is_And(cmp_left) &&
2181 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2182 ir_node *and_left = get_And_left(cmp_left);
2183 ir_node *and_right = get_And_right(cmp_left);
2185 mode = get_irn_mode(and_left);
2186 arg_left = and_left;
2187 arg_right = and_right;
2189 mode = get_irn_mode(cmp_left);
2190 arg_left = cmp_left;
2191 arg_right = cmp_left;
2194 assert(get_mode_size_bits(mode) <= 32);
2196 match_arguments(&am, block, arg_left, arg_right, 1, 1);
2198 pnc = get_inversed_pnc(pnc);
2200 if(get_mode_size_bits(mode) == 8) {
2201 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2202 addr->index, am.new_op1, am.new_op2,
2205 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base,
2206 addr->index, am.new_op1, am.new_op2,
2209 set_am_attributes(res, &am);
2210 set_ia32_ls_mode(res, mode);
2212 res = fix_mem_proj(res, &am);
2214 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2220 mode = get_irn_mode(cmp_left);
2221 assert(get_mode_size_bits(mode) <= 32);
2223 match_arguments(&am, block, cmp_left, cmp_right, 1, 1);
2225 pnc = get_inversed_pnc(pnc);
2227 if(get_mode_size_bits(mode) == 8) {
2228 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base,
2229 addr->index, am.new_op1, am.new_op2,
2232 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2233 am.new_op1, am.new_op2, addr->mem, pnc);
2235 set_am_attributes(res, &am);
2236 set_ia32_ls_mode(res, mode);
2238 res = fix_mem_proj(res, &am);
2240 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2246 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2247 ir_node *val_true, ir_node *val_false,
2248 dbg_info *dbgi, ir_node *block)
2250 ir_graph *irg = current_ir_graph;
2251 ir_node *new_block = be_transform_node(block);
2252 ir_node *new_val_true = be_transform_node(val_true);
2253 ir_node *new_val_false = be_transform_node(val_false);
2254 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2255 ir_node *nomem = new_NoMem();
2256 ir_node *new_cmp_left;
2257 ir_node *new_cmp_right;
2261 /* cmovs with unknowns are pointless... */
2262 if(is_Unknown(val_true)) {
2263 #ifdef DEBUG_libfirm
2264 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2266 return new_val_false;
2268 if(is_Unknown(val_false)) {
2269 #ifdef DEBUG_libfirm
2270 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2272 return new_val_true;
2275 /* can we use a test instruction? */
2276 if(is_Const_0(cmp_right)) {
2277 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2278 if(is_And(cmp_left) &&
2279 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2280 ir_node *and_left = get_And_left(cmp_left);
2281 ir_node *and_right = get_And_right(cmp_left);
2283 mode = get_irn_mode(and_left);
2284 new_cmp_left = be_transform_node(and_left);
2285 new_cmp_right = create_immediate_or_transform(and_right, 0);
2287 mode = get_irn_mode(cmp_left);
2288 new_cmp_left = be_transform_node(cmp_left);
2289 new_cmp_right = be_transform_node(cmp_left);
2292 assert(get_mode_size_bits(mode) <= 32);
2294 if(get_mode_size_bits(mode) == 8) {
2295 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block,
2296 noreg, noreg, new_cmp_left,
2297 new_cmp_right, nomem, new_val_true,
2298 new_val_false, pnc);
2300 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2301 noreg, new_cmp_left, new_cmp_right,
2302 nomem, new_val_true, new_val_false, pnc);
2304 set_ia32_ls_mode(res, mode);
2309 mode = get_irn_mode(cmp_left);
2310 new_cmp_left = be_transform_node(cmp_left);
2311 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2313 /* no support for 8,16 bit modes yet */
2314 assert(get_mode_size_bits(mode) <= 32);
2316 if(get_mode_size_bits(mode) == 8) {
2317 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg,
2318 new_cmp_left, new_cmp_right, nomem,
2319 new_val_true, new_val_false, pnc);
2321 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg,
2322 new_cmp_left, new_cmp_right, nomem,
2323 new_val_true, new_val_false, pnc);
2325 set_ia32_ls_mode(res, mode);
2332 * Transforms a Psi node into CMov.
2334 * @return The transformed node.
2336 static ir_node *gen_Psi(ir_node *node) {
2337 ir_node *psi_true = get_Psi_val(node, 0);
2338 ir_node *psi_default = get_Psi_default(node);
2339 ia32_code_gen_t *cg = env_cg;
2340 ir_node *cond = get_Psi_cond(node, 0);
2341 ir_node *block = get_nodes_block(node);
2342 dbg_info *dbgi = get_irn_dbg_info(node);
2349 assert(get_Psi_n_conds(node) == 1);
2350 assert(get_irn_mode(cond) == mode_b);
2351 assert(mode_needs_gp_reg(get_irn_mode(node)));
2353 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2354 /* a mode_b value, we have to compare it against 0 */
2356 cmp_right = new_Const_long(mode_Iu, 0);
2360 ir_node *cmp = get_Proj_pred(cond);
2362 cmp_left = get_Cmp_left(cmp);
2363 cmp_right = get_Cmp_right(cmp);
2364 cmp_mode = get_irn_mode(cmp_left);
2365 pnc = get_Proj_proj(cond);
2367 assert(!mode_is_float(cmp_mode));
2369 if (!mode_is_signed(cmp_mode)) {
2370 pnc |= ia32_pn_Cmp_Unsigned;
2374 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2375 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2376 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2377 pnc = get_negated_pnc(pnc, cmp_mode);
2378 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2380 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2383 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2389 * Create a conversion from x87 state register to general purpose.
2391 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2392 ir_node *block = be_transform_node(get_nodes_block(node));
2393 ir_node *op = get_Conv_op(node);
2394 ir_node *new_op = be_transform_node(op);
2395 ia32_code_gen_t *cg = env_cg;
2396 ir_graph *irg = current_ir_graph;
2397 dbg_info *dbgi = get_irn_dbg_info(node);
2398 ir_node *noreg = ia32_new_NoReg_gp(cg);
2399 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2400 ir_mode *mode = get_irn_mode(node);
2401 ir_node *fist, *load;
2404 fist = new_rd_ia32_vfist(dbgi, irg, block,
2405 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2407 set_irn_pinned(fist, op_pin_state_floats);
2408 set_ia32_use_frame(fist);
2409 set_ia32_op_type(fist, ia32_AddrModeD);
2411 assert(get_mode_size_bits(mode) <= 32);
2412 /* exception we can only store signed 32 bit integers, so for unsigned
2413 we store a 64bit (signed) integer and load the lower bits */
2414 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2415 set_ia32_ls_mode(fist, mode_Ls);
2417 set_ia32_ls_mode(fist, mode_Is);
2419 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2422 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2424 set_irn_pinned(load, op_pin_state_floats);
2425 set_ia32_use_frame(load);
2426 set_ia32_op_type(load, ia32_AddrModeS);
2427 set_ia32_ls_mode(load, mode_Is);
2428 if(get_ia32_ls_mode(fist) == mode_Ls) {
2429 ia32_attr_t *attr = get_ia32_attr(load);
2430 attr->data.need_64bit_stackent = 1;
2432 ia32_attr_t *attr = get_ia32_attr(load);
2433 attr->data.need_32bit_stackent = 1;
2435 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2437 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2440 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2442 ir_node *block = get_nodes_block(node);
2443 ir_graph *irg = current_ir_graph;
2444 dbg_info *dbgi = get_irn_dbg_info(node);
2445 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2446 ir_node *nomem = new_NoMem();
2447 ir_node *frame = get_irg_frame(irg);
2448 ir_node *store, *load;
2451 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2453 set_ia32_use_frame(store);
2454 set_ia32_op_type(store, ia32_AddrModeD);
2455 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2457 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2459 set_ia32_use_frame(load);
2460 set_ia32_op_type(load, ia32_AddrModeS);
2461 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2463 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2468 * Create a conversion from general purpose to x87 register
2470 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2471 ir_node *block = be_transform_node(get_nodes_block(node));
2472 ir_node *op = get_Conv_op(node);
2473 ir_node *new_op = be_transform_node(op);
2474 ir_graph *irg = current_ir_graph;
2475 dbg_info *dbgi = get_irn_dbg_info(node);
2476 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2477 ir_node *nomem = new_NoMem();
2478 ir_mode *mode = get_irn_mode(op);
2479 ir_mode *store_mode;
2480 ir_node *fild, *store;
2484 /* first convert to 32 bit signed if necessary */
2485 src_bits = get_mode_size_bits(src_mode);
2486 if (src_bits == 8) {
2487 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2489 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2491 } else if (src_bits < 32) {
2492 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2493 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2497 assert(get_mode_size_bits(mode) == 32);
2500 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2502 set_ia32_use_frame(store);
2503 set_ia32_op_type(store, ia32_AddrModeD);
2504 set_ia32_ls_mode(store, mode_Iu);
2506 /* exception for 32bit unsigned, do a 64bit spill+load */
2507 if(!mode_is_signed(mode)) {
2510 ir_node *zero_const = create_Immediate_from_int(0);
2512 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2515 set_ia32_use_frame(zero_store);
2516 set_ia32_op_type(zero_store, ia32_AddrModeD);
2517 add_ia32_am_offs_int(zero_store, 4);
2518 set_ia32_ls_mode(zero_store, mode_Iu);
2523 store = new_rd_Sync(dbgi, irg, block, 2, in);
2524 store_mode = mode_Ls;
2526 store_mode = mode_Is;
2530 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2532 set_ia32_use_frame(fild);
2533 set_ia32_op_type(fild, ia32_AddrModeS);
2534 set_ia32_ls_mode(fild, store_mode);
2536 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2542 * Crete a conversion from one integer mode into another one
2544 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2545 dbg_info *dbgi, ir_node *new_block,
2548 ir_graph *irg = current_ir_graph;
2549 int src_bits = get_mode_size_bits(src_mode);
2550 int tgt_bits = get_mode_size_bits(tgt_mode);
2551 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2552 ir_node *nomem = new_rd_NoMem(irg);
2554 ir_mode *smaller_mode;
2557 if (src_bits < tgt_bits) {
2558 smaller_mode = src_mode;
2559 smaller_bits = src_bits;
2561 smaller_mode = tgt_mode;
2562 smaller_bits = tgt_bits;
2565 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2566 if (smaller_bits == 8) {
2567 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2568 new_op, nomem, smaller_mode);
2570 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2571 nomem, smaller_mode);
2578 * Transforms a Conv node.
2580 * @return The created ia32 Conv node
2582 static ir_node *gen_Conv(ir_node *node) {
2583 ir_node *block = be_transform_node(get_nodes_block(node));
2584 ir_node *op = get_Conv_op(node);
2585 ir_node *new_op = be_transform_node(op);
2586 ir_graph *irg = current_ir_graph;
2587 dbg_info *dbgi = get_irn_dbg_info(node);
2588 ir_mode *src_mode = get_irn_mode(op);
2589 ir_mode *tgt_mode = get_irn_mode(node);
2590 int src_bits = get_mode_size_bits(src_mode);
2591 int tgt_bits = get_mode_size_bits(tgt_mode);
2592 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2593 ir_node *nomem = new_rd_NoMem(irg);
2596 if (src_mode == mode_b) {
2597 assert(mode_is_int(tgt_mode));
2598 /* nothing to do, we already model bools as 0/1 ints */
2602 if (src_mode == tgt_mode) {
2603 if (get_Conv_strict(node)) {
2604 if (USE_SSE2(env_cg)) {
2605 /* when we are in SSE mode, we can kill all strict no-op conversion */
2609 /* this should be optimized already, but who knows... */
2610 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2611 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2616 if (mode_is_float(src_mode)) {
2617 /* we convert from float ... */
2618 if (mode_is_float(tgt_mode)) {
2619 if(src_mode == mode_E && tgt_mode == mode_D
2620 && !get_Conv_strict(node)) {
2621 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2626 if (USE_SSE2(env_cg)) {
2627 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2628 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2629 set_ia32_ls_mode(res, tgt_mode);
2631 if(get_Conv_strict(node)) {
2632 res = create_strict_conv(tgt_mode, new_op);
2633 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2636 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2641 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2642 if (USE_SSE2(env_cg)) {
2643 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2644 set_ia32_ls_mode(res, src_mode);
2646 return gen_x87_fp_to_gp(node);
2650 /* we convert from int ... */
2651 if (mode_is_float(tgt_mode)) {
2653 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2654 if (USE_SSE2(env_cg)) {
2655 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2656 set_ia32_ls_mode(res, tgt_mode);
2658 res = gen_x87_gp_to_fp(node, src_mode);
2659 if(get_Conv_strict(node)) {
2660 res = create_strict_conv(tgt_mode, res);
2661 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2662 ia32_get_old_node_name(env_cg, node));
2666 } else if(tgt_mode == mode_b) {
2667 /* mode_b lowering already took care that we only have 0/1 values */
2668 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2669 src_mode, tgt_mode));
2673 if (src_bits == tgt_bits) {
2674 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2675 src_mode, tgt_mode));
2679 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2683 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2689 int check_immediate_constraint(long val, char immediate_constraint_type)
2691 switch (immediate_constraint_type) {
2695 return val >= 0 && val <= 32;
2697 return val >= 0 && val <= 63;
2699 return val >= -128 && val <= 127;
2701 return val == 0xff || val == 0xffff;
2703 return val >= 0 && val <= 3;
2705 return val >= 0 && val <= 255;
2707 return val >= 0 && val <= 127;
2711 panic("Invalid immediate constraint found");
2716 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2719 tarval *offset = NULL;
2720 int offset_sign = 0;
2722 ir_entity *symconst_ent = NULL;
2723 int symconst_sign = 0;
2725 ir_node *cnst = NULL;
2726 ir_node *symconst = NULL;
2732 mode = get_irn_mode(node);
2733 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2737 if(is_Minus(node)) {
2739 node = get_Minus_op(node);
2742 if(is_Const(node)) {
2745 offset_sign = minus;
2746 } else if(is_SymConst(node)) {
2749 symconst_sign = minus;
2750 } else if(is_Add(node)) {
2751 ir_node *left = get_Add_left(node);
2752 ir_node *right = get_Add_right(node);
2753 if(is_Const(left) && is_SymConst(right)) {
2756 symconst_sign = minus;
2757 offset_sign = minus;
2758 } else if(is_SymConst(left) && is_Const(right)) {
2761 symconst_sign = minus;
2762 offset_sign = minus;
2764 } else if(is_Sub(node)) {
2765 ir_node *left = get_Sub_left(node);
2766 ir_node *right = get_Sub_right(node);
2767 if(is_Const(left) && is_SymConst(right)) {
2770 symconst_sign = !minus;
2771 offset_sign = minus;
2772 } else if(is_SymConst(left) && is_Const(right)) {
2775 symconst_sign = minus;
2776 offset_sign = !minus;
2783 offset = get_Const_tarval(cnst);
2784 if(tarval_is_long(offset)) {
2785 val = get_tarval_long(offset);
2786 } else if(tarval_is_null(offset)) {
2789 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2794 if(!check_immediate_constraint(val, immediate_constraint_type))
2797 if(symconst != NULL) {
2798 if(immediate_constraint_type != 0) {
2799 /* we need full 32bits for symconsts */
2803 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2805 symconst_ent = get_SymConst_entity(symconst);
2807 if(cnst == NULL && symconst == NULL)
2810 if(offset_sign && offset != NULL) {
2811 offset = tarval_neg(offset);
2814 irg = current_ir_graph;
2815 dbgi = get_irn_dbg_info(node);
2816 block = get_irg_start_block(irg);
2817 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2818 symconst_sign, val);
2819 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2825 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2827 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2828 if (new_node == NULL) {
2829 new_node = be_transform_node(node);
2834 typedef struct constraint_t constraint_t;
2835 struct constraint_t {
2838 const arch_register_req_t **out_reqs;
2840 const arch_register_req_t *req;
2841 unsigned immediate_possible;
2842 char immediate_type;
2845 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2847 int immediate_possible = 0;
2848 char immediate_type = 0;
2849 unsigned limited = 0;
2850 const arch_register_class_t *cls = NULL;
2851 ir_graph *irg = current_ir_graph;
2852 struct obstack *obst = get_irg_obstack(irg);
2853 arch_register_req_t *req;
2854 unsigned *limited_ptr;
2858 /* TODO: replace all the asserts with nice error messages */
2860 printf("Constraint: %s\n", c);
2870 assert(cls == NULL ||
2871 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2872 cls = &ia32_reg_classes[CLASS_ia32_gp];
2873 limited |= 1 << REG_EAX;
2876 assert(cls == NULL ||
2877 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2878 cls = &ia32_reg_classes[CLASS_ia32_gp];
2879 limited |= 1 << REG_EBX;
2882 assert(cls == NULL ||
2883 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2884 cls = &ia32_reg_classes[CLASS_ia32_gp];
2885 limited |= 1 << REG_ECX;
2888 assert(cls == NULL ||
2889 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2890 cls = &ia32_reg_classes[CLASS_ia32_gp];
2891 limited |= 1 << REG_EDX;
2894 assert(cls == NULL ||
2895 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2896 cls = &ia32_reg_classes[CLASS_ia32_gp];
2897 limited |= 1 << REG_EDI;
2900 assert(cls == NULL ||
2901 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2902 cls = &ia32_reg_classes[CLASS_ia32_gp];
2903 limited |= 1 << REG_ESI;
2906 case 'q': /* q means lower part of the regs only, this makes no
2907 * difference to Q for us (we only assigne whole registers) */
2908 assert(cls == NULL ||
2909 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2910 cls = &ia32_reg_classes[CLASS_ia32_gp];
2911 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2915 assert(cls == NULL ||
2916 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2917 cls = &ia32_reg_classes[CLASS_ia32_gp];
2918 limited |= 1 << REG_EAX | 1 << REG_EDX;
2921 assert(cls == NULL ||
2922 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2923 cls = &ia32_reg_classes[CLASS_ia32_gp];
2924 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2925 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2932 assert(cls == NULL);
2933 cls = &ia32_reg_classes[CLASS_ia32_gp];
2939 /* TODO: mark values so the x87 simulator knows about t and u */
2940 assert(cls == NULL);
2941 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2946 assert(cls == NULL);
2947 /* TODO: check that sse2 is supported */
2948 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2958 assert(!immediate_possible);
2959 immediate_possible = 1;
2960 immediate_type = *c;
2964 assert(!immediate_possible);
2965 immediate_possible = 1;
2969 assert(!immediate_possible && cls == NULL);
2970 immediate_possible = 1;
2971 cls = &ia32_reg_classes[CLASS_ia32_gp];
2984 assert(constraint->is_in && "can only specify same constraint "
2987 sscanf(c, "%d%n", &same_as, &p);
2994 case 'E': /* no float consts yet */
2995 case 'F': /* no float consts yet */
2996 case 's': /* makes no sense on x86 */
2997 case 'X': /* we can't support that in firm */
3001 case '<': /* no autodecrement on x86 */
3002 case '>': /* no autoincrement on x86 */
3003 case 'C': /* sse constant not supported yet */
3004 case 'G': /* 80387 constant not supported yet */
3005 case 'y': /* we don't support mmx registers yet */
3006 case 'Z': /* not available in 32 bit mode */
3007 case 'e': /* not available in 32 bit mode */
3008 assert(0 && "asm constraint not supported");
3011 assert(0 && "unknown asm constraint found");
3018 const arch_register_req_t *other_constr;
3020 assert(cls == NULL && "same as and register constraint not supported");
3021 assert(!immediate_possible && "same as and immediate constraint not "
3023 assert(same_as < constraint->n_outs && "wrong constraint number in "
3024 "same_as constraint");
3026 other_constr = constraint->out_reqs[same_as];
3028 req = obstack_alloc(obst, sizeof(req[0]));
3029 req->cls = other_constr->cls;
3030 req->type = arch_register_req_type_should_be_same;
3031 req->limited = NULL;
3032 req->other_same = pos;
3033 req->other_different = -1;
3035 /* switch constraints. This is because in firm we have same_as
3036 * constraints on the output constraints while in the gcc asm syntax
3037 * they are specified on the input constraints */
3038 constraint->req = other_constr;
3039 constraint->out_reqs[same_as] = req;
3040 constraint->immediate_possible = 0;
3044 if(immediate_possible && cls == NULL) {
3045 cls = &ia32_reg_classes[CLASS_ia32_gp];
3047 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3048 assert(cls != NULL);
3050 if(immediate_possible) {
3051 assert(constraint->is_in
3052 && "imeediates make no sense for output constraints");
3054 /* todo: check types (no float input on 'r' constrained in and such... */
3057 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3058 limited_ptr = (unsigned*) (req+1);
3060 req = obstack_alloc(obst, sizeof(req[0]));
3062 memset(req, 0, sizeof(req[0]));
3065 req->type = arch_register_req_type_limited;
3066 *limited_ptr = limited;
3067 req->limited = limited_ptr;
3069 req->type = arch_register_req_type_normal;
3073 constraint->req = req;
3074 constraint->immediate_possible = immediate_possible;
3075 constraint->immediate_type = immediate_type;
3079 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3086 panic("Clobbers not supported yet");
3089 ir_node *gen_ASM(ir_node *node)
3092 ir_graph *irg = current_ir_graph;
3093 ir_node *block = be_transform_node(get_nodes_block(node));
3094 dbg_info *dbgi = get_irn_dbg_info(node);
3101 ia32_asm_attr_t *attr;
3102 const arch_register_req_t **out_reqs;
3103 const arch_register_req_t **in_reqs;
3104 struct obstack *obst;
3105 constraint_t parsed_constraint;
3107 /* transform inputs */
3108 arity = get_irn_arity(node);
3109 in = alloca(arity * sizeof(in[0]));
3110 memset(in, 0, arity * sizeof(in[0]));
3112 n_outs = get_ASM_n_output_constraints(node);
3113 n_clobbers = get_ASM_n_clobbers(node);
3114 out_arity = n_outs + n_clobbers;
3116 /* construct register constraints */
3117 obst = get_irg_obstack(irg);
3118 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3119 parsed_constraint.out_reqs = out_reqs;
3120 parsed_constraint.n_outs = n_outs;
3121 parsed_constraint.is_in = 0;
3122 for(i = 0; i < out_arity; ++i) {
3126 const ir_asm_constraint *constraint;
3127 constraint = & get_ASM_output_constraints(node) [i];
3128 c = get_id_str(constraint->constraint);
3129 parse_asm_constraint(i, &parsed_constraint, c);
3131 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3132 c = get_id_str(glob_id);
3133 parse_clobber(node, i, &parsed_constraint, c);
3135 out_reqs[i] = parsed_constraint.req;
3138 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3139 parsed_constraint.is_in = 1;
3140 for(i = 0; i < arity; ++i) {
3141 const ir_asm_constraint *constraint;
3145 constraint = & get_ASM_input_constraints(node) [i];
3146 constr_id = constraint->constraint;
3147 c = get_id_str(constr_id);
3148 parse_asm_constraint(i, &parsed_constraint, c);
3149 in_reqs[i] = parsed_constraint.req;
3151 if(parsed_constraint.immediate_possible) {
3152 ir_node *pred = get_irn_n(node, i);
3153 char imm_type = parsed_constraint.immediate_type;
3154 ir_node *immediate = try_create_Immediate(pred, imm_type);
3156 if(immediate != NULL) {
3162 /* transform inputs */
3163 for(i = 0; i < arity; ++i) {
3165 ir_node *transformed;
3170 pred = get_irn_n(node, i);
3171 transformed = be_transform_node(pred);
3172 in[i] = transformed;
3175 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3177 generic_attr = get_irn_generic_attr(res);
3178 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3179 attr->asm_text = get_ASM_text(node);
3180 set_ia32_out_req_all(res, out_reqs);
3181 set_ia32_in_req_all(res, in_reqs);
3183 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3188 /********************************************
3191 * | |__ ___ _ __ ___ __| | ___ ___
3192 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3193 * | |_) | __/ | | | (_) | (_| | __/\__ \
3194 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3196 ********************************************/
3199 * Transforms a FrameAddr into an ia32 Add.
3201 static ir_node *gen_be_FrameAddr(ir_node *node) {
3202 ir_node *block = be_transform_node(get_nodes_block(node));
3203 ir_node *op = be_get_FrameAddr_frame(node);
3204 ir_node *new_op = be_transform_node(op);
3205 ir_graph *irg = current_ir_graph;
3206 dbg_info *dbgi = get_irn_dbg_info(node);
3207 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3210 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3211 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3212 set_ia32_use_frame(res);
3214 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3220 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3222 static ir_node *gen_be_Return(ir_node *node) {
3223 ir_graph *irg = current_ir_graph;
3224 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3225 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3226 ir_entity *ent = get_irg_entity(irg);
3227 ir_type *tp = get_entity_type(ent);
3232 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3233 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3236 int pn_ret_val, pn_ret_mem, arity, i;
3238 assert(ret_val != NULL);
3239 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3240 return be_duplicate_node(node);
3243 res_type = get_method_res_type(tp, 0);
3245 if (! is_Primitive_type(res_type)) {
3246 return be_duplicate_node(node);
3249 mode = get_type_mode(res_type);
3250 if (! mode_is_float(mode)) {
3251 return be_duplicate_node(node);
3254 assert(get_method_n_ress(tp) == 1);
3256 pn_ret_val = get_Proj_proj(ret_val);
3257 pn_ret_mem = get_Proj_proj(ret_mem);
3259 /* get the Barrier */
3260 barrier = get_Proj_pred(ret_val);
3262 /* get result input of the Barrier */
3263 ret_val = get_irn_n(barrier, pn_ret_val);
3264 new_ret_val = be_transform_node(ret_val);
3266 /* get memory input of the Barrier */
3267 ret_mem = get_irn_n(barrier, pn_ret_mem);
3268 new_ret_mem = be_transform_node(ret_mem);
3270 frame = get_irg_frame(irg);
3272 dbgi = get_irn_dbg_info(barrier);
3273 block = be_transform_node(get_nodes_block(barrier));
3275 noreg = ia32_new_NoReg_gp(env_cg);
3277 /* store xmm0 onto stack */
3278 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3279 new_ret_val, new_ret_mem);
3280 set_ia32_ls_mode(sse_store, mode);
3281 set_ia32_op_type(sse_store, ia32_AddrModeD);
3282 set_ia32_use_frame(sse_store);
3284 /* load into x87 register */
3285 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3286 set_ia32_op_type(fld, ia32_AddrModeS);
3287 set_ia32_use_frame(fld);
3289 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3290 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3292 /* create a new barrier */
3293 arity = get_irn_arity(barrier);
3294 in = alloca(arity * sizeof(in[0]));
3295 for (i = 0; i < arity; ++i) {
3298 if (i == pn_ret_val) {
3300 } else if (i == pn_ret_mem) {
3303 ir_node *in = get_irn_n(barrier, i);
3304 new_in = be_transform_node(in);
3309 new_barrier = new_ir_node(dbgi, irg, block,
3310 get_irn_op(barrier), get_irn_mode(barrier),
3312 copy_node_attr(barrier, new_barrier);
3313 be_duplicate_deps(barrier, new_barrier);
3314 be_set_transformed_node(barrier, new_barrier);
3315 mark_irn_visited(barrier);
3317 /* transform normally */
3318 return be_duplicate_node(node);
3322 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3324 static ir_node *gen_be_AddSP(ir_node *node) {
3325 ir_node *block = be_transform_node(get_nodes_block(node));
3326 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3328 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3329 ir_node *new_sp = be_transform_node(sp);
3330 ir_graph *irg = current_ir_graph;
3331 dbg_info *dbgi = get_irn_dbg_info(node);
3332 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3333 ir_node *nomem = new_NoMem();
3336 new_sz = create_immediate_or_transform(sz, 0);
3338 /* ia32 stack grows in reverse direction, make a SubSP */
3339 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3341 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3347 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3349 static ir_node *gen_be_SubSP(ir_node *node) {
3350 ir_node *block = be_transform_node(get_nodes_block(node));
3351 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3353 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3354 ir_node *new_sp = be_transform_node(sp);
3355 ir_graph *irg = current_ir_graph;
3356 dbg_info *dbgi = get_irn_dbg_info(node);
3357 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3358 ir_node *nomem = new_NoMem();
3361 new_sz = create_immediate_or_transform(sz, 0);
3363 /* ia32 stack grows in reverse direction, make an AddSP */
3364 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3365 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3371 * This function just sets the register for the Unknown node
3372 * as this is not done during register allocation because Unknown
3373 * is an "ignore" node.
3375 static ir_node *gen_Unknown(ir_node *node) {
3376 ir_mode *mode = get_irn_mode(node);
3378 if (mode_is_float(mode)) {
3379 if (USE_SSE2(env_cg)) {
3380 return ia32_new_Unknown_xmm(env_cg);
3382 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3383 ir_graph *irg = current_ir_graph;
3384 dbg_info *dbgi = get_irn_dbg_info(node);
3385 ir_node *block = get_irg_start_block(irg);
3386 return new_rd_ia32_vfldz(dbgi, irg, block);
3388 } else if (mode_needs_gp_reg(mode)) {
3389 return ia32_new_Unknown_gp(env_cg);
3391 assert(0 && "unsupported Unknown-Mode");
3398 * Change some phi modes
3400 static ir_node *gen_Phi(ir_node *node) {
3401 ir_node *block = be_transform_node(get_nodes_block(node));
3402 ir_graph *irg = current_ir_graph;
3403 dbg_info *dbgi = get_irn_dbg_info(node);
3404 ir_mode *mode = get_irn_mode(node);
3407 if(mode_needs_gp_reg(mode)) {
3408 /* we shouldn't have any 64bit stuff around anymore */
3409 assert(get_mode_size_bits(mode) <= 32);
3410 /* all integer operations are on 32bit registers now */
3412 } else if(mode_is_float(mode)) {
3413 if (USE_SSE2(env_cg)) {
3420 /* phi nodes allow loops, so we use the old arguments for now
3421 * and fix this later */
3422 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3423 get_irn_in(node) + 1);
3424 copy_node_attr(node, phi);
3425 be_duplicate_deps(node, phi);
3427 be_set_transformed_node(node, phi);
3428 be_enqueue_preds(node);
3436 static ir_node *gen_IJmp(ir_node *node) {
3437 /* TODO: support AM */
3438 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3442 /**********************************************************************
3445 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3446 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3447 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3448 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3450 **********************************************************************/
3452 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3454 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3457 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3458 ir_node *val, ir_node *mem);
3461 * Transforms a lowered Load into a "real" one.
3463 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3465 ir_node *block = be_transform_node(get_nodes_block(node));
3466 ir_node *ptr = get_irn_n(node, 0);
3467 ir_node *new_ptr = be_transform_node(ptr);
3468 ir_node *mem = get_irn_n(node, 1);
3469 ir_node *new_mem = be_transform_node(mem);
3470 ir_graph *irg = current_ir_graph;
3471 dbg_info *dbgi = get_irn_dbg_info(node);
3472 ir_mode *mode = get_ia32_ls_mode(node);
3473 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3476 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3478 set_ia32_op_type(new_op, ia32_AddrModeS);
3479 set_ia32_am_offs_int(new_op, 0);
3480 set_ia32_am_scale(new_op, 1);
3481 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3482 if (is_ia32_am_sc_sign(node))
3483 set_ia32_am_sc_sign(new_op);
3484 set_ia32_ls_mode(new_op, mode);
3485 if (is_ia32_use_frame(node)) {
3486 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3487 set_ia32_use_frame(new_op);
3490 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3496 * Transforms a lowered Store into a "real" one.
3498 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3500 ir_node *block = be_transform_node(get_nodes_block(node));
3501 ir_node *ptr = get_irn_n(node, 0);
3502 ir_node *new_ptr = be_transform_node(ptr);
3503 ir_node *val = get_irn_n(node, 1);
3504 ir_node *new_val = be_transform_node(val);
3505 ir_node *mem = get_irn_n(node, 2);
3506 ir_node *new_mem = be_transform_node(mem);
3507 ir_graph *irg = current_ir_graph;
3508 dbg_info *dbgi = get_irn_dbg_info(node);
3509 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3510 ir_mode *mode = get_ia32_ls_mode(node);
3514 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3516 am_offs = get_ia32_am_offs_int(node);
3517 add_ia32_am_offs_int(new_op, am_offs);
3519 set_ia32_op_type(new_op, ia32_AddrModeD);
3520 set_ia32_ls_mode(new_op, mode);
3521 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3522 set_ia32_use_frame(new_op);
3524 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3531 * Transforms an ia32_l_XXX into a "real" XXX node
3533 * @param env The transformation environment
3534 * @return the created ia32 XXX node
3536 #define GEN_LOWERED_OP(op) \
3537 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3538 return gen_binop(node, get_binop_left(node), \
3539 get_binop_right(node), new_rd_ia32_##op,0); \
3542 #define GEN_LOWERED_x87_OP(op) \
3543 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3545 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3546 get_binop_right(node), new_rd_ia32_##op); \
3550 #define GEN_LOWERED_UNOP(op) \
3551 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3552 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3555 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3556 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3557 return gen_shift_binop(node, get_irn_n(node, 0), \
3558 get_irn_n(node, 1), new_rd_ia32_##op); \
3561 #define GEN_LOWERED_LOAD(op) \
3562 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3563 return gen_lowered_Load(node, new_rd_ia32_##op); \
3566 #define GEN_LOWERED_STORE(op) \
3567 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3568 return gen_lowered_Store(node, new_rd_ia32_##op); \
3576 GEN_LOWERED_x87_OP(vfprem)
3577 GEN_LOWERED_x87_OP(vfmul)
3578 GEN_LOWERED_x87_OP(vfsub)
3580 GEN_LOWERED_UNOP(Neg)
3582 GEN_LOWERED_LOAD(vfild)
3583 GEN_LOWERED_LOAD(Load)
3584 GEN_LOWERED_STORE(Store)
3587 * Transforms a l_vfist into a "real" vfist node.
3589 * @param env The transformation environment
3590 * @return the created ia32 vfist node
3592 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3593 ir_node *block = be_transform_node(get_nodes_block(node));
3594 ir_node *ptr = get_irn_n(node, 0);
3595 ir_node *new_ptr = be_transform_node(ptr);
3596 ir_node *val = get_irn_n(node, 1);
3597 ir_node *new_val = be_transform_node(val);
3598 ir_node *mem = get_irn_n(node, 2);
3599 ir_node *new_mem = be_transform_node(mem);
3600 ir_graph *irg = current_ir_graph;
3601 dbg_info *dbgi = get_irn_dbg_info(node);
3602 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3603 ir_mode *mode = get_ia32_ls_mode(node);
3604 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3608 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
3609 trunc_mode, new_mem);
3611 am_offs = get_ia32_am_offs_int(node);
3612 add_ia32_am_offs_int(new_op, am_offs);
3614 set_ia32_op_type(new_op, ia32_AddrModeD);
3615 set_ia32_ls_mode(new_op, mode);
3616 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3617 set_ia32_use_frame(new_op);
3619 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3625 * Transforms a l_vfdiv into a "real" vfdiv node.
3627 * @param env The transformation environment
3628 * @return the created ia32 vfdiv node
3630 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3631 ir_node *block = be_transform_node(get_nodes_block(node));
3632 ir_node *left = get_binop_left(node);
3633 ir_node *new_left = be_transform_node(left);
3634 ir_node *right = get_binop_right(node);
3635 ir_node *new_right = be_transform_node(right);
3636 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3637 ir_graph *irg = current_ir_graph;
3638 dbg_info *dbgi = get_irn_dbg_info(node);
3639 ir_node *fpcw = get_fpcw();
3642 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3643 new_right, new_NoMem(), fpcw);
3644 clear_ia32_commutative(vfdiv);
3646 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3652 * Transforms a l_MulS into a "real" MulS node.
3654 * @param env The transformation environment
3655 * @return the created ia32 Mul node
3657 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3658 ir_node *block = be_transform_node(get_nodes_block(node));
3659 ir_node *left = get_binop_left(node);
3660 ir_node *new_left = be_transform_node(left);
3661 ir_node *right = get_binop_right(node);
3662 ir_node *new_right = be_transform_node(right);
3663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3664 ir_graph *irg = current_ir_graph;
3665 dbg_info *dbgi = get_irn_dbg_info(node);
3667 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3668 /* and then skip the result Proj, because all needed Projs are already there. */
3669 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3670 new_right, new_NoMem());
3671 clear_ia32_commutative(muls);
3673 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3679 * Transforms a l_IMulS into a "real" IMul1OPS node.
3681 * @param env The transformation environment
3682 * @return the created ia32 IMul1OP node
3684 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3685 ir_node *block = be_transform_node(get_nodes_block(node));
3686 ir_node *left = get_binop_left(node);
3687 ir_node *new_left = be_transform_node(left);
3688 ir_node *right = get_binop_right(node);
3689 ir_node *new_right = be_transform_node(right);
3690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3691 ir_graph *irg = current_ir_graph;
3692 dbg_info *dbgi = get_irn_dbg_info(node);
3694 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3695 /* and then skip the result Proj, because all needed Projs are already there. */
3696 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_left,
3697 new_right, new_NoMem());
3698 clear_ia32_commutative(muls);
3699 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3701 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3706 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3707 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3708 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3709 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3712 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3713 * op1 - target to be shifted
3714 * op2 - contains bits to be shifted into target
3716 * Only op3 can be an immediate.
3718 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3719 ir_node *op2, ir_node *count)
3721 ir_node *block = be_transform_node(get_nodes_block(node));
3722 ir_node *new_op = NULL;
3723 ir_graph *irg = current_ir_graph;
3724 dbg_info *dbgi = get_irn_dbg_info(node);
3725 ir_node *new_op1 = be_transform_node(op1);
3726 ir_node *new_op2 = create_immediate_or_transform(op2, 'I');
3727 ir_node *new_count = be_transform_node(count);
3729 /* TODO proper AM support */
3731 if (is_ia32_l_ShlD(node))
3732 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3734 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3736 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3741 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3742 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3743 get_irn_n(node, 1), get_irn_n(node, 2));
3746 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3747 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3748 get_irn_n(node, 1), get_irn_n(node, 2));
3752 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3754 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3755 ir_node *block = be_transform_node(get_nodes_block(node));
3756 ir_node *val = get_irn_n(node, 1);
3757 ir_node *new_val = be_transform_node(val);
3758 ia32_code_gen_t *cg = env_cg;
3759 ir_node *res = NULL;
3760 ir_graph *irg = current_ir_graph;
3762 ir_node *noreg, *new_ptr, *new_mem;
3769 mem = get_irn_n(node, 2);
3770 new_mem = be_transform_node(mem);
3771 ptr = get_irn_n(node, 0);
3772 new_ptr = be_transform_node(ptr);
3773 noreg = ia32_new_NoReg_gp(cg);
3774 dbgi = get_irn_dbg_info(node);
3776 /* Store x87 -> MEM */
3777 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3778 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3779 set_ia32_use_frame(res);
3780 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3781 set_ia32_op_type(res, ia32_AddrModeD);
3783 /* Load MEM -> SSE */
3784 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3785 get_ia32_ls_mode(node));
3786 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3787 set_ia32_use_frame(res);
3788 set_ia32_op_type(res, ia32_AddrModeS);
3789 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3795 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3797 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3798 ir_node *block = be_transform_node(get_nodes_block(node));
3799 ir_node *val = get_irn_n(node, 1);
3800 ir_node *new_val = be_transform_node(val);
3801 ia32_code_gen_t *cg = env_cg;
3802 ir_graph *irg = current_ir_graph;
3803 ir_node *res = NULL;
3804 ir_entity *fent = get_ia32_frame_ent(node);
3805 ir_mode *lsmode = get_ia32_ls_mode(node);
3807 ir_node *noreg, *new_ptr, *new_mem;
3811 if (! USE_SSE2(cg)) {
3812 /* SSE unit is not used -> skip this node. */
3816 ptr = get_irn_n(node, 0);
3817 new_ptr = be_transform_node(ptr);
3818 mem = get_irn_n(node, 2);
3819 new_mem = be_transform_node(mem);
3820 noreg = ia32_new_NoReg_gp(cg);
3821 dbgi = get_irn_dbg_info(node);
3823 /* Store SSE -> MEM */
3824 if (is_ia32_xLoad(skip_Proj(new_val))) {
3825 ir_node *ld = skip_Proj(new_val);
3827 /* we can vfld the value directly into the fpu */
3828 fent = get_ia32_frame_ent(ld);
3829 ptr = get_irn_n(ld, 0);
3830 offs = get_ia32_am_offs_int(ld);
3832 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3833 set_ia32_frame_ent(res, fent);
3834 set_ia32_use_frame(res);
3835 set_ia32_ls_mode(res, lsmode);
3836 set_ia32_op_type(res, ia32_AddrModeD);
3840 /* Load MEM -> x87 */
3841 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3842 set_ia32_frame_ent(res, fent);
3843 set_ia32_use_frame(res);
3844 add_ia32_am_offs_int(res, offs);
3845 set_ia32_op_type(res, ia32_AddrModeS);
3846 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3851 /*********************************************************
3854 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3855 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3856 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3857 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3859 *********************************************************/
3862 * the BAD transformer.
3864 static ir_node *bad_transform(ir_node *node) {
3865 panic("No transform function for %+F available.\n", node);
3870 * Transform the Projs of an AddSP.
3872 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3873 ir_node *block = be_transform_node(get_nodes_block(node));
3874 ir_node *pred = get_Proj_pred(node);
3875 ir_node *new_pred = be_transform_node(pred);
3876 ir_graph *irg = current_ir_graph;
3877 dbg_info *dbgi = get_irn_dbg_info(node);
3878 long proj = get_Proj_proj(node);
3880 if (proj == pn_be_AddSP_sp) {
3881 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3882 pn_ia32_SubSP_stack);
3883 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3885 } else if(proj == pn_be_AddSP_res) {
3886 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3887 pn_ia32_SubSP_addr);
3888 } else if (proj == pn_be_AddSP_M) {
3889 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3893 return new_rd_Unknown(irg, get_irn_mode(node));
3897 * Transform the Projs of a SubSP.
3899 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3900 ir_node *block = be_transform_node(get_nodes_block(node));
3901 ir_node *pred = get_Proj_pred(node);
3902 ir_node *new_pred = be_transform_node(pred);
3903 ir_graph *irg = current_ir_graph;
3904 dbg_info *dbgi = get_irn_dbg_info(node);
3905 long proj = get_Proj_proj(node);
3907 if (proj == pn_be_SubSP_sp) {
3908 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3909 pn_ia32_AddSP_stack);
3910 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3912 } else if (proj == pn_be_SubSP_M) {
3913 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3917 return new_rd_Unknown(irg, get_irn_mode(node));
3921 * Transform and renumber the Projs from a Load.
3923 static ir_node *gen_Proj_Load(ir_node *node) {
3925 ir_node *block = be_transform_node(get_nodes_block(node));
3926 ir_node *pred = get_Proj_pred(node);
3927 ir_graph *irg = current_ir_graph;
3928 dbg_info *dbgi = get_irn_dbg_info(node);
3929 long proj = get_Proj_proj(node);
3932 /* loads might be part of source address mode matches, so we don't
3933 transform the ProjMs yet (with the exception of loads whose result is
3936 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
3939 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
3941 /* this is needed, because sometimes we have loops that are only
3942 reachable through the ProjM */
3943 be_enqueue_preds(node);
3944 /* do it in 2 steps, to silence firm verifier */
3945 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
3946 set_Proj_proj(res, pn_ia32_Load_M);
3950 /* renumber the proj */
3951 new_pred = be_transform_node(pred);
3952 if (is_ia32_Load(new_pred)) {
3953 if (proj == pn_Load_res) {
3954 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3956 } else if (proj == pn_Load_M) {
3957 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3960 } else if(is_ia32_Conv_I2I(new_pred)) {
3961 set_irn_mode(new_pred, mode_T);
3962 if (proj == pn_Load_res) {
3963 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
3964 } else if (proj == pn_Load_M) {
3965 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
3967 } else if (is_ia32_xLoad(new_pred)) {
3968 if (proj == pn_Load_res) {
3969 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3971 } else if (proj == pn_Load_M) {
3972 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3975 } else if (is_ia32_vfld(new_pred)) {
3976 if (proj == pn_Load_res) {
3977 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3979 } else if (proj == pn_Load_M) {
3980 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3984 /* can happen for ProJMs when source address mode happened for the
3987 /* however it should not be the result proj, as that would mean the
3988 load had multiple users and should not have been used for
3990 if(proj != pn_Load_M) {
3991 panic("internal error: transformed node not a Load");
3993 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
3997 return new_rd_Unknown(irg, get_irn_mode(node));
4001 * Transform and renumber the Projs from a DivMod like instruction.
4003 static ir_node *gen_Proj_DivMod(ir_node *node) {
4004 ir_node *block = be_transform_node(get_nodes_block(node));
4005 ir_node *pred = get_Proj_pred(node);
4006 ir_node *new_pred = be_transform_node(pred);
4007 ir_graph *irg = current_ir_graph;
4008 dbg_info *dbgi = get_irn_dbg_info(node);
4009 ir_mode *mode = get_irn_mode(node);
4010 long proj = get_Proj_proj(node);
4012 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4014 switch (get_irn_opcode(pred)) {
4018 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4020 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4028 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4030 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4038 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4039 case pn_DivMod_res_div:
4040 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4041 case pn_DivMod_res_mod:
4042 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4052 return new_rd_Unknown(irg, mode);
4056 * Transform and renumber the Projs from a CopyB.
4058 static ir_node *gen_Proj_CopyB(ir_node *node) {
4059 ir_node *block = be_transform_node(get_nodes_block(node));
4060 ir_node *pred = get_Proj_pred(node);
4061 ir_node *new_pred = be_transform_node(pred);
4062 ir_graph *irg = current_ir_graph;
4063 dbg_info *dbgi = get_irn_dbg_info(node);
4064 ir_mode *mode = get_irn_mode(node);
4065 long proj = get_Proj_proj(node);
4068 case pn_CopyB_M_regular:
4069 if (is_ia32_CopyB_i(new_pred)) {
4070 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4071 } else if (is_ia32_CopyB(new_pred)) {
4072 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4080 return new_rd_Unknown(irg, mode);
4084 * Transform and renumber the Projs from a vfdiv.
4086 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4087 ir_node *block = be_transform_node(get_nodes_block(node));
4088 ir_node *pred = get_Proj_pred(node);
4089 ir_node *new_pred = be_transform_node(pred);
4090 ir_graph *irg = current_ir_graph;
4091 dbg_info *dbgi = get_irn_dbg_info(node);
4092 ir_mode *mode = get_irn_mode(node);
4093 long proj = get_Proj_proj(node);
4096 case pn_ia32_l_vfdiv_M:
4097 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4098 case pn_ia32_l_vfdiv_res:
4099 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4104 return new_rd_Unknown(irg, mode);
4108 * Transform and renumber the Projs from a Quot.
4110 static ir_node *gen_Proj_Quot(ir_node *node) {
4111 ir_node *block = be_transform_node(get_nodes_block(node));
4112 ir_node *pred = get_Proj_pred(node);
4113 ir_node *new_pred = be_transform_node(pred);
4114 ir_graph *irg = current_ir_graph;
4115 dbg_info *dbgi = get_irn_dbg_info(node);
4116 ir_mode *mode = get_irn_mode(node);
4117 long proj = get_Proj_proj(node);
4121 if (is_ia32_xDiv(new_pred)) {
4122 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4123 } else if (is_ia32_vfdiv(new_pred)) {
4124 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4128 if (is_ia32_xDiv(new_pred)) {
4129 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4130 } else if (is_ia32_vfdiv(new_pred)) {
4131 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4139 return new_rd_Unknown(irg, mode);
4143 * Transform the Thread Local Storage Proj.
4145 static ir_node *gen_Proj_tls(ir_node *node) {
4146 ir_node *block = be_transform_node(get_nodes_block(node));
4147 ir_graph *irg = current_ir_graph;
4148 dbg_info *dbgi = NULL;
4149 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4155 * Transform the Projs from a be_Call.
4157 static ir_node *gen_Proj_be_Call(ir_node *node) {
4158 ir_node *block = be_transform_node(get_nodes_block(node));
4159 ir_node *call = get_Proj_pred(node);
4160 ir_node *new_call = be_transform_node(call);
4161 ir_graph *irg = current_ir_graph;
4162 dbg_info *dbgi = get_irn_dbg_info(node);
4163 ir_type *method_type = be_Call_get_type(call);
4164 int n_res = get_method_n_ress(method_type);
4165 long proj = get_Proj_proj(node);
4166 ir_mode *mode = get_irn_mode(node);
4168 const arch_register_class_t *cls;
4170 /* The following is kinda tricky: If we're using SSE, then we have to
4171 * move the result value of the call in floating point registers to an
4172 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4173 * after the call, we have to make sure to correctly make the
4174 * MemProj and the result Proj use these 2 nodes
4176 if (proj == pn_be_Call_M_regular) {
4177 // get new node for result, are we doing the sse load/store hack?
4178 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4179 ir_node *call_res_new;
4180 ir_node *call_res_pred = NULL;
4182 if (call_res != NULL) {
4183 call_res_new = be_transform_node(call_res);
4184 call_res_pred = get_Proj_pred(call_res_new);
4187 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4188 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4189 pn_be_Call_M_regular);
4191 assert(is_ia32_xLoad(call_res_pred));
4192 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4196 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4197 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4198 && USE_SSE2(env_cg)) {
4200 ir_node *frame = get_irg_frame(irg);
4201 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4203 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4206 /* in case there is no memory output: create one to serialize the copy
4208 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4209 pn_be_Call_M_regular);
4210 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4211 pn_be_Call_first_res);
4213 /* store st(0) onto stack */
4214 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
4216 set_ia32_op_type(fstp, ia32_AddrModeD);
4217 set_ia32_use_frame(fstp);
4219 /* load into SSE register */
4220 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4222 set_ia32_op_type(sse_load, ia32_AddrModeS);
4223 set_ia32_use_frame(sse_load);
4225 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4231 /* transform call modes */
4232 if (mode_is_data(mode)) {
4233 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4237 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4241 * Transform the Projs from a Cmp.
4243 static ir_node *gen_Proj_Cmp(ir_node *node)
4245 /* normally Cmps are processed when looking at Cond nodes, but this case
4246 * can happen in complicated Psi conditions */
4248 ir_node *cmp = get_Proj_pred(node);
4249 long pnc = get_Proj_proj(node);
4250 ir_node *cmp_left = get_Cmp_left(cmp);
4251 ir_node *cmp_right = get_Cmp_right(cmp);
4252 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4253 dbg_info *dbgi = get_irn_dbg_info(cmp);
4254 ir_node *block = get_nodes_block(node);
4257 assert(!mode_is_float(cmp_mode));
4259 if(!mode_is_signed(cmp_mode)) {
4260 pnc |= ia32_pn_Cmp_Unsigned;
4263 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4264 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4270 * Transform and potentially renumber Proj nodes.
4272 static ir_node *gen_Proj(ir_node *node) {
4273 ir_graph *irg = current_ir_graph;
4274 dbg_info *dbgi = get_irn_dbg_info(node);
4275 ir_node *pred = get_Proj_pred(node);
4276 long proj = get_Proj_proj(node);
4278 if (is_Store(pred)) {
4279 if (proj == pn_Store_M) {
4280 return be_transform_node(pred);
4283 return new_r_Bad(irg);
4285 } else if (is_Load(pred)) {
4286 return gen_Proj_Load(node);
4287 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4288 return gen_Proj_DivMod(node);
4289 } else if (is_CopyB(pred)) {
4290 return gen_Proj_CopyB(node);
4291 } else if (is_Quot(pred)) {
4292 return gen_Proj_Quot(node);
4293 } else if (is_ia32_l_vfdiv(pred)) {
4294 return gen_Proj_l_vfdiv(node);
4295 } else if (be_is_SubSP(pred)) {
4296 return gen_Proj_be_SubSP(node);
4297 } else if (be_is_AddSP(pred)) {
4298 return gen_Proj_be_AddSP(node);
4299 } else if (be_is_Call(pred)) {
4300 return gen_Proj_be_Call(node);
4301 } else if (is_Cmp(pred)) {
4302 return gen_Proj_Cmp(node);
4303 } else if (get_irn_op(pred) == op_Start) {
4304 if (proj == pn_Start_X_initial_exec) {
4305 ir_node *block = get_nodes_block(pred);
4308 /* we exchange the ProjX with a jump */
4309 block = be_transform_node(block);
4310 jump = new_rd_Jmp(dbgi, irg, block);
4313 if (node == be_get_old_anchor(anchor_tls)) {
4314 return gen_Proj_tls(node);
4317 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4321 ir_node *new_pred = be_transform_node(pred);
4322 ir_node *block = be_transform_node(get_nodes_block(node));
4323 ir_mode *mode = get_irn_mode(node);
4324 if (mode_needs_gp_reg(mode)) {
4325 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4326 get_Proj_proj(node));
4327 #ifdef DEBUG_libfirm
4328 new_proj->node_nr = node->node_nr;
4334 return be_duplicate_node(node);
4338 * Enters all transform functions into the generic pointer
4340 static void register_transformers(void)
4344 /* first clear the generic function pointer for all ops */
4345 clear_irp_opcodes_generic_func();
4347 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4348 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4385 /* transform ops from intrinsic lowering */
4408 GEN(ia32_l_X87toSSE);
4409 GEN(ia32_l_SSEtoX87);
4415 /* we should never see these nodes */
4430 /* handle generic backend nodes */
4438 op_Mulh = get_op_Mulh();
4447 * Pre-transform all unknown and noreg nodes.
4449 static void ia32_pretransform_node(void *arch_cg) {
4450 ia32_code_gen_t *cg = arch_cg;
4452 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4453 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4454 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4455 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4456 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4457 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4462 * Walker, checks if all ia32 nodes producing more than one result have
4463 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4466 void add_missing_keep_walker(ir_node *node, void *data)
4469 unsigned found_projs = 0;
4470 const ir_edge_t *edge;
4471 ir_mode *mode = get_irn_mode(node);
4476 if(!is_ia32_irn(node))
4479 n_outs = get_ia32_n_res(node);
4482 if(is_ia32_SwitchJmp(node))
4485 assert(n_outs < (int) sizeof(unsigned) * 8);
4486 foreach_out_edge(node, edge) {
4487 ir_node *proj = get_edge_src_irn(edge);
4488 int pn = get_Proj_proj(proj);
4490 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4491 found_projs |= 1 << pn;
4495 /* are keeps missing? */
4497 for(i = 0; i < n_outs; ++i) {
4500 const arch_register_req_t *req;
4501 const arch_register_class_t *class;
4503 if(found_projs & (1 << i)) {
4507 req = get_ia32_out_req(node, i);
4513 block = get_nodes_block(node);
4514 in[0] = new_r_Proj(current_ir_graph, block, node,
4515 arch_register_class_mode(class), i);
4516 if(last_keep != NULL) {
4517 be_Keep_add_node(last_keep, class, in[0]);
4519 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4525 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4529 void add_missing_keeps(ia32_code_gen_t *cg)
4531 ir_graph *irg = be_get_birg_irg(cg->birg);
4532 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4535 /* do the transformation */
4536 void ia32_transform_graph(ia32_code_gen_t *cg) {
4537 register_transformers();
4539 initial_fpcw = NULL;
4541 heights = heights_new(cg->irg);
4543 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4545 heights_free(heights);
4547 add_missing_keeps(cg);
4550 void ia32_init_transform(void)
4552 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");