2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
68 #include "ia32_architecture.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define DFP_INTMAX "9223372036854775807"
78 #define TP_SFP_SIGN "ia32_sfp_sign"
79 #define TP_DFP_SIGN "ia32_dfp_sign"
80 #define TP_SFP_ABS "ia32_sfp_abs"
81 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define TP_INT_MAX "ia32_int_max"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
88 #define ENT_INT_MAX "IA32_INT_MAX"
90 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
91 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
93 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
95 /** hold the current code generator during transformation */
96 static ia32_code_gen_t *env_cg = NULL;
97 static ir_node *initial_fpcw = NULL;
98 static heights_t *heights = NULL;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 static ir_node *try_create_Immediate(ir_node *node,
128 char immediate_constraint_type);
130 static ir_node *create_immediate_or_transform(ir_node *node,
131 char immediate_constraint_type);
133 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
134 dbg_info *dbgi, ir_node *block,
135 ir_node *op, ir_node *orig_node);
138 * Return true if a mode can be stored in the GP register set
140 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
141 if(mode == mode_fpcw)
143 if(get_mode_size_bits(mode) > 32)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an atomic entity that is initialized with a tarval
186 static ir_entity *create_float_const_entity(ir_node *cnst)
188 ia32_isa_t *isa = env_cg->isa;
189 tarval *tv = get_Const_tarval(cnst);
190 pmap_entry *e = pmap_find(isa->tv_ent, tv);
195 ir_mode *mode = get_irn_mode(cnst);
196 ir_type *tp = get_Const_type(cnst);
197 if (tp == firm_unknown_type)
198 tp = get_prim_type(isa->types, mode);
200 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
202 set_entity_ld_ident(res, get_entity_ident(res));
203 set_entity_visibility(res, visibility_local);
204 set_entity_variability(res, variability_constant);
205 set_entity_allocation(res, allocation_static);
207 /* we create a new entity here: It's initialization must resist on the
209 rem = current_ir_graph;
210 current_ir_graph = get_const_code_irg();
211 set_atomic_ent_value(res, new_Const_type(tv, tp));
212 current_ir_graph = rem;
214 pmap_insert(isa->tv_ent, tv, res);
222 static int is_Const_0(ir_node *node) {
223 return is_Const(node) && is_Const_null(node);
226 static int is_Const_1(ir_node *node) {
227 return is_Const(node) && is_Const_one(node);
230 static int is_Const_Minus_1(ir_node *node) {
231 return is_Const(node) && is_Const_all_one(node);
235 * returns true if constant can be created with a simple float command
237 static int is_simple_x87_Const(ir_node *node)
239 tarval *tv = get_Const_tarval(node);
241 if(tarval_is_null(tv) || tarval_is_one(tv))
244 /* TODO: match all the other float constants */
249 * Transforms a Const.
251 static ir_node *gen_Const(ir_node *node) {
252 ir_graph *irg = current_ir_graph;
253 ir_node *old_block = get_nodes_block(node);
254 ir_node *block = be_transform_node(old_block);
255 dbg_info *dbgi = get_irn_dbg_info(node);
256 ir_mode *mode = get_irn_mode(node);
258 if (mode_is_float(mode)) {
260 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
261 ir_node *nomem = new_NoMem();
265 if (ia32_cg_config.use_sse2) {
266 if (is_Const_null(node)) {
267 load = new_rd_ia32_xZero(dbgi, irg, block);
268 set_ia32_ls_mode(load, mode);
271 floatent = create_float_const_entity(node);
273 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
275 set_ia32_op_type(load, ia32_AddrModeS);
276 set_ia32_am_sc(load, floatent);
277 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
278 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
281 if (is_Const_null(node)) {
282 load = new_rd_ia32_vfldz(dbgi, irg, block);
284 } else if (is_Const_one(node)) {
285 load = new_rd_ia32_vfld1(dbgi, irg, block);
288 floatent = create_float_const_entity(node);
290 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
291 set_ia32_op_type(load, ia32_AddrModeS);
292 set_ia32_am_sc(load, floatent);
293 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
294 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
296 set_ia32_ls_mode(load, mode);
299 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
301 /* Const Nodes before the initial IncSP are a bad idea, because
302 * they could be spilled and we have no SP ready at that point yet.
303 * So add a dependency to the initial frame pointer calculation to
304 * avoid that situation.
306 if (get_irg_start_block(irg) == block) {
307 add_irn_dep(load, get_irg_frame(irg));
310 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
314 tarval *tv = get_Const_tarval(node);
317 tv = tarval_convert_to(tv, mode_Iu);
319 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
321 panic("couldn't convert constant tarval (%+F)", node);
323 val = get_tarval_long(tv);
325 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
326 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
329 if (get_irg_start_block(irg) == block) {
330 add_irn_dep(cnst, get_irg_frame(irg));
338 * Transforms a SymConst.
340 static ir_node *gen_SymConst(ir_node *node) {
341 ir_graph *irg = current_ir_graph;
342 ir_node *old_block = get_nodes_block(node);
343 ir_node *block = be_transform_node(old_block);
344 dbg_info *dbgi = get_irn_dbg_info(node);
345 ir_mode *mode = get_irn_mode(node);
348 if (mode_is_float(mode)) {
349 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
350 ir_node *nomem = new_NoMem();
352 if (ia32_cg_config.use_sse2)
353 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
355 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
356 set_ia32_am_sc(cnst, get_SymConst_entity(node));
357 set_ia32_use_frame(cnst);
361 if(get_SymConst_kind(node) != symconst_addr_ent) {
362 panic("backend only support symconst_addr_ent (at %+F)", node);
364 entity = get_SymConst_entity(node);
365 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
368 /* Const Nodes before the initial IncSP are a bad idea, because
369 * they could be spilled and we have no SP ready at that point yet
371 if (get_irg_start_block(irg) == block) {
372 add_irn_dep(cnst, get_irg_frame(irg));
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
380 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
381 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
382 static const struct {
384 const char *ent_name;
385 const char *cnst_str;
388 } names [ia32_known_const_max] = {
389 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
390 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
391 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
392 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
393 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 switch (names[kct].mode) {
411 case 0: mode = mode_Iu; break;
412 case 1: mode = mode_Lu; break;
413 default: mode = mode_F; break;
415 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
416 tp = new_type_primitive(new_id_from_str(tp_name), mode);
417 /* set the specified alignment */
418 set_type_alignment_bytes(tp, names[kct].align);
420 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
422 set_entity_ld_ident(ent, get_entity_ident(ent));
423 set_entity_visibility(ent, visibility_local);
424 set_entity_variability(ent, variability_constant);
425 set_entity_allocation(ent, allocation_static);
427 /* we create a new entity here: It's initialization must resist on the
429 rem = current_ir_graph;
430 current_ir_graph = get_const_code_irg();
431 cnst = new_Const(mode, tv);
432 current_ir_graph = rem;
434 set_atomic_ent_value(ent, cnst);
436 /* cache the entry */
437 ent_cache[kct] = ent;
440 return ent_cache[kct];
445 * Prints the old node name on cg obst and returns a pointer to it.
447 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
448 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
450 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
451 obstack_1grow(isa->name_obst, 0);
452 return obstack_finish(isa->name_obst);
457 * return true if the node is a Proj(Load) and could be used in source address
458 * mode for another node. Will return only true if the @p other node is not
459 * dependent on the memory of the Load (for binary operations use the other
460 * input here, for unary operations use NULL).
462 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
463 ir_node *other, ir_node *other2)
465 ir_mode *mode = get_irn_mode(node);
469 /* float constants are always available */
470 if(is_Const(node) && mode_is_float(mode)) {
471 if(!is_simple_x87_Const(node))
473 if(get_irn_n_edges(node) > 1)
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
489 /* in some edge cases with address mode we might reach the load normally
490 * and through some AM sequence, if it is already materialized then we
491 * can't create an AM node from it */
492 if(be_is_transformed(node))
495 /* don't do AM if other node inputs depend on the load (via mem-proj) */
496 if(other != NULL && get_nodes_block(other) == block
497 && heights_reachable_in_block(heights, other, load))
499 if(other2 != NULL && get_nodes_block(other2) == block
500 && heights_reachable_in_block(heights, other2, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative : 1;
516 unsigned ins_permuted : 1;
519 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
523 /* construct load address */
524 memset(addr, 0, sizeof(addr[0]));
525 ia32_create_address_mode(addr, ptr, /*force=*/0);
527 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
528 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
529 addr->mem = be_transform_node(mem);
532 static void build_address(ia32_address_mode_t *am, ir_node *node)
534 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
535 ia32_address_t *addr = &am->addr;
542 ir_entity *entity = create_float_const_entity(node);
543 addr->base = noreg_gp;
544 addr->index = noreg_gp;
545 addr->mem = new_NoMem();
546 addr->symconst_ent = entity;
548 am->ls_mode = get_irn_mode(node);
549 am->pinned = op_pin_state_floats;
553 load = get_Proj_pred(node);
554 ptr = get_Load_ptr(load);
555 mem = get_Load_mem(load);
556 new_mem = be_transform_node(mem);
557 am->pinned = get_irn_pinned(load);
558 am->ls_mode = get_Load_mode(load);
559 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
561 /* construct load address */
562 ia32_create_address_mode(addr, ptr, /*force=*/0);
564 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
565 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
569 static void set_address(ir_node *node, const ia32_address_t *addr)
571 set_ia32_am_scale(node, addr->scale);
572 set_ia32_am_sc(node, addr->symconst_ent);
573 set_ia32_am_offs_int(node, addr->offset);
574 if(addr->symconst_sign)
575 set_ia32_am_sc_sign(node);
577 set_ia32_use_frame(node);
578 set_ia32_frame_ent(node, addr->frame_entity);
581 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
583 set_address(node, &am->addr);
585 set_ia32_op_type(node, am->op_type);
586 set_ia32_ls_mode(node, am->ls_mode);
587 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
588 set_irn_pinned(node, am->pinned);
591 set_ia32_commutative(node);
595 * Check, if a given node is a Down-Conv, ie. a integer Conv
596 * from a mode with a mode with more bits to a mode with lesser bits.
597 * Moreover, we return only true if the node has not more than 1 user.
599 * @param node the node
600 * @return non-zero if node is a Down-Conv
602 static int is_downconv(const ir_node *node)
610 /* we only want to skip the conv when we're the only user
611 * (not optimal but for now...)
613 if(get_irn_n_edges(node) > 1)
616 src_mode = get_irn_mode(get_Conv_op(node));
617 dest_mode = get_irn_mode(node);
618 return mode_needs_gp_reg(src_mode)
619 && mode_needs_gp_reg(dest_mode)
620 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
623 /* Skip all Down-Conv's on a given node and return the resulting node. */
624 ir_node *ia32_skip_downconv(ir_node *node) {
625 while (is_downconv(node))
626 node = get_Conv_op(node);
632 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
634 ir_mode *mode = get_irn_mode(node);
639 if(mode_is_signed(mode)) {
644 block = get_nodes_block(node);
645 dbgi = get_irn_dbg_info(node);
647 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
652 * matches operands of a node into ia32 addressing/operand modes. This covers
653 * usage of source address mode, immediates, operations with non 32-bit modes,
655 * The resulting data is filled into the @p am struct. block is the block
656 * of the node whose arguments are matched. op1, op2 are the first and second
657 * input that are matched (op1 may be NULL). other_op is another unrelated
658 * input that is not matched! but which is needed sometimes to check if AM
659 * for op1/op2 is legal.
660 * @p flags describes the supported modes of the operation in detail.
662 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
663 ir_node *op1, ir_node *op2, ir_node *other_op,
666 ia32_address_t *addr = &am->addr;
667 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
670 ir_mode *mode = get_irn_mode(op2);
672 unsigned commutative;
673 int use_am_and_immediates;
675 int mode_bits = get_mode_size_bits(mode);
677 memset(am, 0, sizeof(am[0]));
679 commutative = (flags & match_commutative) != 0;
680 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
681 use_am = (flags & match_am) != 0;
682 use_immediate = (flags & match_immediate) != 0;
683 assert(!use_am_and_immediates || use_immediate);
686 assert(!commutative || op1 != NULL);
687 assert(use_am || !(flags & match_8bit_am));
688 assert(use_am || !(flags & match_16bit_am));
691 if (! (flags & match_8bit_am))
693 /* we don't automatically add upconvs yet */
694 assert((flags & match_mode_neutral) || (flags & match_8bit));
695 } else if(mode_bits == 16) {
696 if(! (flags & match_16bit_am))
698 /* we don't automatically add upconvs yet */
699 assert((flags & match_mode_neutral) || (flags & match_16bit));
702 /* we can simply skip downconvs for mode neutral nodes: the upper bits
703 * can be random for these operations */
704 if(flags & match_mode_neutral) {
705 op2 = ia32_skip_downconv(op2);
707 op1 = ia32_skip_downconv(op1);
711 /* match immediates. firm nodes are normalized: constants are always on the
714 if(! (flags & match_try_am) && use_immediate) {
715 new_op2 = try_create_Immediate(op2, 0);
719 && use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
720 build_address(am, op2);
721 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
722 if(mode_is_float(mode)) {
723 new_op2 = ia32_new_NoReg_vfp(env_cg);
727 am->op_type = ia32_AddrModeS;
728 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
730 && ia32_use_source_address_mode(block, op1, op2, other_op)) {
732 build_address(am, op1);
734 if(mode_is_float(mode)) {
735 noreg = ia32_new_NoReg_vfp(env_cg);
740 if(new_op2 != NULL) {
743 new_op1 = be_transform_node(op2);
745 am->ins_permuted = 1;
747 am->op_type = ia32_AddrModeS;
749 if(flags & match_try_am) {
752 am->op_type = ia32_Normal;
756 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
758 new_op2 = be_transform_node(op2);
759 am->op_type = ia32_Normal;
760 am->ls_mode = get_irn_mode(op2);
761 if(flags & match_mode_neutral)
762 am->ls_mode = mode_Iu;
764 if(addr->base == NULL)
765 addr->base = noreg_gp;
766 if(addr->index == NULL)
767 addr->index = noreg_gp;
768 if(addr->mem == NULL)
769 addr->mem = new_NoMem();
771 am->new_op1 = new_op1;
772 am->new_op2 = new_op2;
773 am->commutative = commutative;
776 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
778 ir_graph *irg = current_ir_graph;
782 if(am->mem_proj == NULL)
785 /* we have to create a mode_T so the old MemProj can attach to us */
786 mode = get_irn_mode(node);
787 load = get_Proj_pred(am->mem_proj);
789 mark_irn_visited(load);
790 be_set_transformed_node(load, node);
793 set_irn_mode(node, mode_T);
794 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
801 * Construct a standard binary operation, set AM and immediate if required.
803 * @param op1 The first operand
804 * @param op2 The second operand
805 * @param func The node constructor function
806 * @return The constructed ia32 node.
808 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
809 construct_binop_func *func, match_flags_t flags)
811 ir_node *block = get_nodes_block(node);
812 ir_node *new_block = be_transform_node(block);
813 ir_graph *irg = current_ir_graph;
814 dbg_info *dbgi = get_irn_dbg_info(node);
816 ia32_address_mode_t am;
817 ia32_address_t *addr = &am.addr;
819 match_arguments(&am, block, op1, op2, NULL, flags);
821 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
822 am.new_op1, am.new_op2);
823 set_am_attributes(new_node, &am);
824 /* we can't use source address mode anymore when using immediates */
825 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
826 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
827 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
829 new_node = fix_mem_proj(new_node, &am);
836 n_ia32_l_binop_right,
837 n_ia32_l_binop_eflags
839 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
840 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
841 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
842 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
843 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
844 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
847 * Construct a binary operation which also consumes the eflags.
849 * @param node The node to transform
850 * @param func The node constructor function
851 * @param flags The match flags
852 * @return The constructor ia32 node
854 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
857 ir_node *src_block = get_nodes_block(node);
858 ir_node *block = be_transform_node(src_block);
859 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
860 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
861 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
862 ir_node *new_eflags = be_transform_node(eflags);
863 ir_graph *irg = current_ir_graph;
864 dbg_info *dbgi = get_irn_dbg_info(node);
866 ia32_address_mode_t am;
867 ia32_address_t *addr = &am.addr;
869 match_arguments(&am, src_block, op1, op2, NULL, flags);
871 new_node = func(dbgi, irg, block, addr->base, addr->index,
872 addr->mem, am.new_op1, am.new_op2, new_eflags);
873 set_am_attributes(new_node, &am);
874 /* we can't use source address mode anymore when using immediates */
875 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
876 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
877 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
879 new_node = fix_mem_proj(new_node, &am);
884 static ir_node *get_fpcw(void)
887 if(initial_fpcw != NULL)
890 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
891 &ia32_fp_cw_regs[REG_FPCW]);
892 initial_fpcw = be_transform_node(fpcw);
898 * Construct a standard binary operation, set AM and immediate if required.
900 * @param op1 The first operand
901 * @param op2 The second operand
902 * @param func The node constructor function
903 * @return The constructed ia32 node.
905 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
906 construct_binop_float_func *func,
909 ir_graph *irg = current_ir_graph;
910 dbg_info *dbgi = get_irn_dbg_info(node);
911 ir_node *block = get_nodes_block(node);
912 ir_node *new_block = be_transform_node(block);
913 ir_mode *mode = get_irn_mode(node);
915 ia32_address_mode_t am;
916 ia32_address_t *addr = &am.addr;
918 /* cannot use addresmode with long double on x87 */
919 if (get_mode_size_bits(mode) > 64)
922 match_arguments(&am, block, op1, op2, NULL, flags);
924 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
925 am.new_op1, am.new_op2, get_fpcw());
926 set_am_attributes(new_node, &am);
928 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
930 new_node = fix_mem_proj(new_node, &am);
936 * Construct a shift/rotate binary operation, sets AM and immediate if required.
938 * @param op1 The first operand
939 * @param op2 The second operand
940 * @param func The node constructor function
941 * @return The constructed ia32 node.
943 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
944 construct_shift_func *func,
947 dbg_info *dbgi = get_irn_dbg_info(node);
948 ir_graph *irg = current_ir_graph;
949 ir_node *block = get_nodes_block(node);
950 ir_node *new_block = be_transform_node(block);
951 ir_mode *mode = get_irn_mode(node);
956 assert(! mode_is_float(mode));
957 assert(flags & match_immediate);
958 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
960 if(flags & match_mode_neutral) {
961 op1 = ia32_skip_downconv(op1);
963 new_op1 = be_transform_node(op1);
965 /* the shift amount can be any mode that is bigger than 5 bits, since all
966 * other bits are ignored anyway */
967 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
968 op2 = get_Conv_op(op2);
969 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
971 new_op2 = create_immediate_or_transform(op2, 0);
973 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
974 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
976 /* lowered shift instruction may have a dependency operand, handle it here */
977 if (get_irn_arity(node) == 3) {
978 /* we have a dependency */
979 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
980 add_irn_dep(new_node, new_dep);
988 * Construct a standard unary operation, set AM and immediate if required.
990 * @param op The operand
991 * @param func The node constructor function
992 * @return The constructed ia32 node.
994 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
997 ir_graph *irg = current_ir_graph;
998 dbg_info *dbgi = get_irn_dbg_info(node);
999 ir_node *block = get_nodes_block(node);
1000 ir_node *new_block = be_transform_node(block);
1004 assert(flags == 0 || flags == match_mode_neutral);
1005 if(flags & match_mode_neutral) {
1006 op = ia32_skip_downconv(op);
1009 new_op = be_transform_node(op);
1010 new_node = func(dbgi, irg, new_block, new_op);
1012 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1017 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1018 ia32_address_t *addr)
1020 ir_graph *irg = current_ir_graph;
1021 ir_node *base = addr->base;
1022 ir_node *index = addr->index;
1026 base = ia32_new_NoReg_gp(env_cg);
1028 base = be_transform_node(base);
1032 index = ia32_new_NoReg_gp(env_cg);
1034 index = be_transform_node(index);
1037 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1038 set_address(res, addr);
1043 static int am_has_immediates(const ia32_address_t *addr)
1045 return addr->offset != 0 || addr->symconst_ent != NULL
1046 || addr->frame_entity || addr->use_frame;
1050 * Creates an ia32 Add.
1052 * @return the created ia32 Add node
1054 static ir_node *gen_Add(ir_node *node) {
1055 ir_graph *irg = current_ir_graph;
1056 dbg_info *dbgi = get_irn_dbg_info(node);
1057 ir_node *block = get_nodes_block(node);
1058 ir_node *new_block = be_transform_node(block);
1059 ir_node *op1 = get_Add_left(node);
1060 ir_node *op2 = get_Add_right(node);
1061 ir_mode *mode = get_irn_mode(node);
1063 ir_node *add_immediate_op;
1064 ia32_address_t addr;
1065 ia32_address_mode_t am;
1067 if (mode_is_float(mode)) {
1068 if (ia32_cg_config.use_sse2)
1069 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1070 match_commutative | match_am);
1072 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1073 match_commutative | match_am);
1076 ia32_mark_non_am(node);
1078 op2 = ia32_skip_downconv(op2);
1079 op1 = ia32_skip_downconv(op1);
1083 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1084 * 1. Add with immediate -> Lea
1085 * 2. Add with possible source address mode -> Add
1086 * 3. Otherwise -> Lea
1088 memset(&addr, 0, sizeof(addr));
1089 ia32_create_address_mode(&addr, node, /*force=*/1);
1090 add_immediate_op = NULL;
1092 if(addr.base == NULL && addr.index == NULL) {
1093 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1094 addr.symconst_sign, addr.offset);
1095 add_irn_dep(new_node, get_irg_frame(irg));
1096 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1099 /* add with immediate? */
1100 if(addr.index == NULL) {
1101 add_immediate_op = addr.base;
1102 } else if(addr.base == NULL && addr.scale == 0) {
1103 add_immediate_op = addr.index;
1106 if(add_immediate_op != NULL) {
1107 if(!am_has_immediates(&addr)) {
1108 #ifdef DEBUG_libfirm
1109 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1112 return be_transform_node(add_immediate_op);
1115 new_node = create_lea_from_address(dbgi, new_block, &addr);
1116 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1120 /* test if we can use source address mode */
1121 match_arguments(&am, block, op1, op2, NULL, match_commutative
1122 | match_mode_neutral | match_am | match_immediate | match_try_am);
1124 /* construct an Add with source address mode */
1125 if (am.op_type == ia32_AddrModeS) {
1126 ia32_address_t *am_addr = &am.addr;
1127 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1128 am_addr->index, am_addr->mem, am.new_op1,
1130 set_am_attributes(new_node, &am);
1131 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1133 new_node = fix_mem_proj(new_node, &am);
1138 /* otherwise construct a lea */
1139 new_node = create_lea_from_address(dbgi, new_block, &addr);
1140 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1145 * Creates an ia32 Mul.
1147 * @return the created ia32 Mul node
1149 static ir_node *gen_Mul(ir_node *node) {
1150 ir_node *op1 = get_Mul_left(node);
1151 ir_node *op2 = get_Mul_right(node);
1152 ir_mode *mode = get_irn_mode(node);
1154 if (mode_is_float(mode)) {
1155 if (ia32_cg_config.use_sse2)
1156 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1157 match_commutative | match_am);
1159 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1160 match_commutative | match_am);
1163 /* for the lower 32bit of the result it doesn't matter whether we use
1164 * signed or unsigned multiplication so we use IMul as it has fewer
1166 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1167 match_commutative | match_am | match_mode_neutral |
1168 match_immediate | match_am_and_immediates);
1172 * Creates an ia32 Mulh.
1173 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1174 * this result while Mul returns the lower 32 bit.
1176 * @return the created ia32 Mulh node
1178 static ir_node *gen_Mulh(ir_node *node)
1180 ir_node *block = get_nodes_block(node);
1181 ir_node *new_block = be_transform_node(block);
1182 ir_graph *irg = current_ir_graph;
1183 dbg_info *dbgi = get_irn_dbg_info(node);
1184 ir_mode *mode = get_irn_mode(node);
1185 ir_node *op1 = get_Mulh_left(node);
1186 ir_node *op2 = get_Mulh_right(node);
1187 ir_node *proj_res_high;
1189 ia32_address_mode_t am;
1190 ia32_address_t *addr = &am.addr;
1192 assert(!mode_is_float(mode) && "Mulh with float not supported");
1193 assert(get_mode_size_bits(mode) == 32);
1195 match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am);
1197 if (mode_is_signed(mode)) {
1198 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1199 addr->index, addr->mem, am.new_op1,
1202 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1203 addr->index, addr->mem, am.new_op1,
1207 set_am_attributes(new_node, &am);
1208 /* we can't use source address mode anymore when using immediates */
1209 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1210 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1211 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1213 assert(get_irn_mode(new_node) == mode_T);
1215 fix_mem_proj(new_node, &am);
1217 assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high);
1218 proj_res_high = new_rd_Proj(dbgi, irg, block, new_node,
1219 mode_Iu, pn_ia32_IMul1OP_res_high);
1221 return proj_res_high;
1227 * Creates an ia32 And.
1229 * @return The created ia32 And node
1231 static ir_node *gen_And(ir_node *node) {
1232 ir_node *op1 = get_And_left(node);
1233 ir_node *op2 = get_And_right(node);
1234 assert(! mode_is_float(get_irn_mode(node)));
1236 /* is it a zero extension? */
1237 if (is_Const(op2)) {
1238 tarval *tv = get_Const_tarval(op2);
1239 long v = get_tarval_long(tv);
1241 if (v == 0xFF || v == 0xFFFF) {
1242 dbg_info *dbgi = get_irn_dbg_info(node);
1243 ir_node *block = get_nodes_block(node);
1250 assert(v == 0xFFFF);
1253 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1259 return gen_binop(node, op1, op2, new_rd_ia32_And,
1260 match_commutative | match_mode_neutral | match_am
1267 * Creates an ia32 Or.
1269 * @return The created ia32 Or node
1271 static ir_node *gen_Or(ir_node *node) {
1272 ir_node *op1 = get_Or_left(node);
1273 ir_node *op2 = get_Or_right(node);
1275 assert (! mode_is_float(get_irn_mode(node)));
1276 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1277 | match_mode_neutral | match_am | match_immediate);
1283 * Creates an ia32 Eor.
1285 * @return The created ia32 Eor node
1287 static ir_node *gen_Eor(ir_node *node) {
1288 ir_node *op1 = get_Eor_left(node);
1289 ir_node *op2 = get_Eor_right(node);
1291 assert(! mode_is_float(get_irn_mode(node)));
1292 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1293 | match_mode_neutral | match_am | match_immediate);
1298 * Creates an ia32 Sub.
1300 * @return The created ia32 Sub node
1302 static ir_node *gen_Sub(ir_node *node) {
1303 ir_node *op1 = get_Sub_left(node);
1304 ir_node *op2 = get_Sub_right(node);
1305 ir_mode *mode = get_irn_mode(node);
1307 if (mode_is_float(mode)) {
1308 if (ia32_cg_config.use_sse2)
1309 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1311 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1316 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1320 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1321 | match_am | match_immediate);
1325 * Generates an ia32 DivMod with additional infrastructure for the
1326 * register allocator if needed.
1328 static ir_node *create_Div(ir_node *node)
1330 ir_graph *irg = current_ir_graph;
1331 dbg_info *dbgi = get_irn_dbg_info(node);
1332 ir_node *block = get_nodes_block(node);
1333 ir_node *new_block = be_transform_node(block);
1340 ir_node *sign_extension;
1342 ia32_address_mode_t am;
1343 ia32_address_t *addr = &am.addr;
1345 /* the upper bits have random contents for smaller modes */
1347 switch (get_irn_opcode(node)) {
1349 op1 = get_Div_left(node);
1350 op2 = get_Div_right(node);
1351 mem = get_Div_mem(node);
1352 mode = get_Div_resmode(node);
1353 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1356 op1 = get_Mod_left(node);
1357 op2 = get_Mod_right(node);
1358 mem = get_Mod_mem(node);
1359 mode = get_Mod_resmode(node);
1360 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1363 op1 = get_DivMod_left(node);
1364 op2 = get_DivMod_right(node);
1365 mem = get_DivMod_mem(node);
1366 mode = get_DivMod_resmode(node);
1367 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1370 panic("invalid divmod node %+F", node);
1373 match_arguments(&am, block, op1, op2, NULL, match_am);
1375 if(!is_NoMem(mem)) {
1376 new_mem = be_transform_node(mem);
1377 if(!is_NoMem(addr->mem)) {
1381 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1384 new_mem = addr->mem;
1387 if (mode_is_signed(mode)) {
1388 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1389 add_irn_dep(produceval, get_irg_frame(irg));
1390 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1393 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1394 addr->index, new_mem, am.new_op1,
1395 sign_extension, am.new_op2);
1397 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1398 add_irn_dep(sign_extension, get_irg_frame(irg));
1400 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1401 addr->index, new_mem, am.new_op1,
1402 sign_extension, am.new_op2);
1405 set_ia32_exc_label(new_node, has_exc);
1406 set_irn_pinned(new_node, get_irn_pinned(node));
1408 set_am_attributes(new_node, &am);
1409 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1411 new_node = fix_mem_proj(new_node, &am);
1417 static ir_node *gen_Mod(ir_node *node) {
1418 return create_Div(node);
1421 static ir_node *gen_Div(ir_node *node) {
1422 return create_Div(node);
1425 static ir_node *gen_DivMod(ir_node *node) {
1426 return create_Div(node);
1432 * Creates an ia32 floating Div.
1434 * @return The created ia32 xDiv node
1436 static ir_node *gen_Quot(ir_node *node)
1438 ir_node *op1 = get_Quot_left(node);
1439 ir_node *op2 = get_Quot_right(node);
1441 if (ia32_cg_config.use_sse2) {
1442 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1444 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1450 * Creates an ia32 Shl.
1452 * @return The created ia32 Shl node
1454 static ir_node *gen_Shl(ir_node *node) {
1455 ir_node *left = get_Shl_left(node);
1456 ir_node *right = get_Shl_right(node);
1458 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1459 match_mode_neutral | match_immediate);
1463 * Creates an ia32 Shr.
1465 * @return The created ia32 Shr node
1467 static ir_node *gen_Shr(ir_node *node) {
1468 ir_node *left = get_Shr_left(node);
1469 ir_node *right = get_Shr_right(node);
1471 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1477 * Creates an ia32 Sar.
1479 * @return The created ia32 Shrs node
1481 static ir_node *gen_Shrs(ir_node *node) {
1482 ir_node *left = get_Shrs_left(node);
1483 ir_node *right = get_Shrs_right(node);
1484 ir_mode *mode = get_irn_mode(node);
1486 if(is_Const(right) && mode == mode_Is) {
1487 tarval *tv = get_Const_tarval(right);
1488 long val = get_tarval_long(tv);
1490 /* this is a sign extension */
1491 ir_graph *irg = current_ir_graph;
1492 dbg_info *dbgi = get_irn_dbg_info(node);
1493 ir_node *block = be_transform_node(get_nodes_block(node));
1495 ir_node *new_op = be_transform_node(op);
1496 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1497 add_irn_dep(pval, get_irg_frame(irg));
1499 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1503 /* 8 or 16 bit sign extension? */
1504 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1505 ir_node *shl_left = get_Shl_left(left);
1506 ir_node *shl_right = get_Shl_right(left);
1507 if(is_Const(shl_right)) {
1508 tarval *tv1 = get_Const_tarval(right);
1509 tarval *tv2 = get_Const_tarval(shl_right);
1510 if(tv1 == tv2 && tarval_is_long(tv1)) {
1511 long val = get_tarval_long(tv1);
1512 if(val == 16 || val == 24) {
1513 dbg_info *dbgi = get_irn_dbg_info(node);
1514 ir_node *block = get_nodes_block(node);
1524 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1533 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1539 * Creates an ia32 RotL.
1541 * @param op1 The first operator
1542 * @param op2 The second operator
1543 * @return The created ia32 RotL node
1545 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1546 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1552 * Creates an ia32 RotR.
1553 * NOTE: There is no RotR with immediate because this would always be a RotL
1554 * "imm-mode_size_bits" which can be pre-calculated.
1556 * @param op1 The first operator
1557 * @param op2 The second operator
1558 * @return The created ia32 RotR node
1560 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1561 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1567 * Creates an ia32 RotR or RotL (depending on the found pattern).
1569 * @return The created ia32 RotL or RotR node
1571 static ir_node *gen_Rot(ir_node *node) {
1572 ir_node *rotate = NULL;
1573 ir_node *op1 = get_Rot_left(node);
1574 ir_node *op2 = get_Rot_right(node);
1576 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1577 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1578 that means we can create a RotR instead of an Add and a RotL */
1580 if (get_irn_op(op2) == op_Add) {
1582 ir_node *left = get_Add_left(add);
1583 ir_node *right = get_Add_right(add);
1584 if (is_Const(right)) {
1585 tarval *tv = get_Const_tarval(right);
1586 ir_mode *mode = get_irn_mode(node);
1587 long bits = get_mode_size_bits(mode);
1589 if (get_irn_op(left) == op_Minus &&
1590 tarval_is_long(tv) &&
1591 get_tarval_long(tv) == bits &&
1594 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1595 rotate = gen_RotR(node, op1, get_Minus_op(left));
1600 if (rotate == NULL) {
1601 rotate = gen_RotL(node, op1, op2);
1610 * Transforms a Minus node.
1612 * @return The created ia32 Minus node
1614 static ir_node *gen_Minus(ir_node *node)
1616 ir_node *op = get_Minus_op(node);
1617 ir_node *block = be_transform_node(get_nodes_block(node));
1618 ir_graph *irg = current_ir_graph;
1619 dbg_info *dbgi = get_irn_dbg_info(node);
1620 ir_mode *mode = get_irn_mode(node);
1625 if (mode_is_float(mode)) {
1626 ir_node *new_op = be_transform_node(op);
1627 if (ia32_cg_config.use_sse2) {
1628 /* TODO: non-optimal... if we have many xXors, then we should
1629 * rather create a load for the const and use that instead of
1630 * several AM nodes... */
1631 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1632 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1633 ir_node *nomem = new_rd_NoMem(irg);
1635 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1636 nomem, new_op, noreg_xmm);
1638 size = get_mode_size_bits(mode);
1639 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1641 set_ia32_am_sc(new_node, ent);
1642 set_ia32_op_type(new_node, ia32_AddrModeS);
1643 set_ia32_ls_mode(new_node, mode);
1645 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1648 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1651 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1657 * Transforms a Not node.
1659 * @return The created ia32 Not node
1661 static ir_node *gen_Not(ir_node *node) {
1662 ir_node *op = get_Not_op(node);
1664 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1665 assert (! mode_is_float(get_irn_mode(node)));
1667 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1673 * Transforms an Abs node.
1675 * @return The created ia32 Abs node
1677 static ir_node *gen_Abs(ir_node *node)
1679 ir_node *block = get_nodes_block(node);
1680 ir_node *new_block = be_transform_node(block);
1681 ir_node *op = get_Abs_op(node);
1682 ir_graph *irg = current_ir_graph;
1683 dbg_info *dbgi = get_irn_dbg_info(node);
1684 ir_mode *mode = get_irn_mode(node);
1685 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1686 ir_node *nomem = new_NoMem();
1692 if (mode_is_float(mode)) {
1693 new_op = be_transform_node(op);
1695 if (ia32_cg_config.use_sse2) {
1696 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1697 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1698 nomem, new_op, noreg_fp);
1700 size = get_mode_size_bits(mode);
1701 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1703 set_ia32_am_sc(new_node, ent);
1705 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1707 set_ia32_op_type(new_node, ia32_AddrModeS);
1708 set_ia32_ls_mode(new_node, mode);
1710 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1714 ir_node *xor, *pval, *sign_extension;
1716 if (get_mode_size_bits(mode) == 32) {
1717 new_op = be_transform_node(op);
1719 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1722 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1723 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1726 add_irn_dep(pval, get_irg_frame(irg));
1727 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1729 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1730 nomem, new_op, sign_extension);
1731 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1733 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1734 nomem, xor, sign_extension);
1735 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1741 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1743 ir_graph *irg = current_ir_graph;
1751 /* we have a Cmp as input */
1753 ir_node *pred = get_Proj_pred(node);
1755 flags = be_transform_node(pred);
1756 *pnc_out = get_Proj_proj(node);
1761 /* a mode_b value, we have to compare it against 0 */
1762 dbgi = get_irn_dbg_info(node);
1763 new_block = be_transform_node(get_nodes_block(node));
1764 new_op = be_transform_node(node);
1765 noreg = ia32_new_NoReg_gp(env_cg);
1766 nomem = new_NoMem();
1767 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1768 new_op, new_op, 0, 0);
1769 *pnc_out = pn_Cmp_Lg;
1774 * Transforms a Load.
1776 * @return the created ia32 Load node
1778 static ir_node *gen_Load(ir_node *node) {
1779 ir_node *old_block = get_nodes_block(node);
1780 ir_node *block = be_transform_node(old_block);
1781 ir_node *ptr = get_Load_ptr(node);
1782 ir_node *mem = get_Load_mem(node);
1783 ir_node *new_mem = be_transform_node(mem);
1786 ir_graph *irg = current_ir_graph;
1787 dbg_info *dbgi = get_irn_dbg_info(node);
1788 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1789 ir_mode *mode = get_Load_mode(node);
1792 ia32_address_t addr;
1794 /* construct load address */
1795 memset(&addr, 0, sizeof(addr));
1796 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1803 base = be_transform_node(base);
1809 index = be_transform_node(index);
1812 if (mode_is_float(mode)) {
1813 if (ia32_cg_config.use_sse2) {
1814 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1816 res_mode = mode_xmm;
1818 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1820 res_mode = mode_vfp;
1823 assert(mode != mode_b);
1825 /* create a conv node with address mode for smaller modes */
1826 if(get_mode_size_bits(mode) < 32) {
1827 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1828 new_mem, noreg, mode);
1830 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1835 set_irn_pinned(new_node, get_irn_pinned(node));
1836 set_ia32_op_type(new_node, ia32_AddrModeS);
1837 set_ia32_ls_mode(new_node, mode);
1838 set_address(new_node, &addr);
1840 if(get_irn_pinned(node) == op_pin_state_floats) {
1841 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1844 /* make sure we are scheduled behind the initial IncSP/Barrier
1845 * to avoid spills being placed before it
1847 if (block == get_irg_start_block(irg)) {
1848 add_irn_dep(new_node, get_irg_frame(irg));
1851 set_ia32_exc_label(new_node,
1852 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1853 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1858 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1859 ir_node *ptr, ir_node *other)
1866 /* we only use address mode if we're the only user of the load */
1867 if(get_irn_n_edges(node) > 1)
1870 load = get_Proj_pred(node);
1873 if(get_nodes_block(load) != block)
1876 /* Store should be attached to the load */
1877 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1879 /* store should have the same pointer as the load */
1880 if(get_Load_ptr(load) != ptr)
1883 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1884 if(other != NULL && get_nodes_block(other) == block
1885 && heights_reachable_in_block(heights, other, load))
1891 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1892 ir_node *mem, ir_node *ptr, ir_mode *mode,
1893 construct_binop_dest_func *func,
1894 construct_binop_dest_func *func8bit,
1895 match_flags_t flags)
1897 ir_node *src_block = get_nodes_block(node);
1899 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1900 ir_graph *irg = current_ir_graph;
1905 ia32_address_mode_t am;
1906 ia32_address_t *addr = &am.addr;
1907 memset(&am, 0, sizeof(am));
1909 assert(flags & match_dest_am);
1910 assert(flags & match_immediate); /* there is no destam node without... */
1911 commutative = (flags & match_commutative) != 0;
1913 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1914 build_address(&am, op1);
1915 new_op = create_immediate_or_transform(op2, 0);
1916 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1917 build_address(&am, op2);
1918 new_op = create_immediate_or_transform(op1, 0);
1923 if(addr->base == NULL)
1924 addr->base = noreg_gp;
1925 if(addr->index == NULL)
1926 addr->index = noreg_gp;
1927 if(addr->mem == NULL)
1928 addr->mem = new_NoMem();
1930 dbgi = get_irn_dbg_info(node);
1931 block = be_transform_node(src_block);
1932 if(get_mode_size_bits(mode) == 8) {
1933 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1936 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1939 set_address(new_node, addr);
1940 set_ia32_op_type(new_node, ia32_AddrModeD);
1941 set_ia32_ls_mode(new_node, mode);
1942 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1947 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1948 ir_node *ptr, ir_mode *mode,
1949 construct_unop_dest_func *func)
1951 ir_graph *irg = current_ir_graph;
1952 ir_node *src_block = get_nodes_block(node);
1956 ia32_address_mode_t am;
1957 ia32_address_t *addr = &am.addr;
1958 memset(&am, 0, sizeof(am));
1960 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1963 build_address(&am, op);
1965 dbgi = get_irn_dbg_info(node);
1966 block = be_transform_node(src_block);
1967 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1968 set_address(new_node, addr);
1969 set_ia32_op_type(new_node, ia32_AddrModeD);
1970 set_ia32_ls_mode(new_node, mode);
1971 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1976 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1977 ir_mode *mode = get_irn_mode(node);
1978 ir_node *psi_true = get_Psi_val(node, 0);
1979 ir_node *psi_default = get_Psi_default(node);
1990 ia32_address_t addr;
1992 if(get_mode_size_bits(mode) != 8)
1995 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1997 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2003 build_address_ptr(&addr, ptr, mem);
2005 irg = current_ir_graph;
2006 dbgi = get_irn_dbg_info(node);
2007 block = get_nodes_block(node);
2008 new_block = be_transform_node(block);
2009 cond = get_Psi_cond(node, 0);
2010 flags = get_flags_node(cond, &pnc);
2011 new_mem = be_transform_node(mem);
2012 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2013 addr.index, addr.mem, flags, pnc, negated);
2014 set_address(new_node, &addr);
2015 set_ia32_op_type(new_node, ia32_AddrModeD);
2016 set_ia32_ls_mode(new_node, mode);
2017 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2022 static ir_node *try_create_dest_am(ir_node *node) {
2023 ir_node *val = get_Store_value(node);
2024 ir_node *mem = get_Store_mem(node);
2025 ir_node *ptr = get_Store_ptr(node);
2026 ir_mode *mode = get_irn_mode(val);
2027 int bits = get_mode_size_bits(mode);
2032 /* handle only GP modes for now... */
2033 if(!mode_needs_gp_reg(mode))
2037 /* store must be the only user of the val node */
2038 if(get_irn_n_edges(val) > 1)
2040 /* skip pointless convs */
2042 ir_node *conv_op = get_Conv_op(val);
2043 ir_mode *pred_mode = get_irn_mode(conv_op);
2044 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2052 /* value must be in the same block */
2053 if(get_nodes_block(node) != get_nodes_block(val))
2056 switch(get_irn_opcode(val)) {
2058 op1 = get_Add_left(val);
2059 op2 = get_Add_right(val);
2060 if(is_Const_1(op2)) {
2061 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2062 new_rd_ia32_IncMem);
2064 } else if(is_Const_Minus_1(op2)) {
2065 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2066 new_rd_ia32_DecMem);
2069 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2070 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2071 match_dest_am | match_commutative |
2075 op1 = get_Sub_left(val);
2076 op2 = get_Sub_right(val);
2078 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2081 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2082 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2083 match_dest_am | match_immediate |
2087 op1 = get_And_left(val);
2088 op2 = get_And_right(val);
2089 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2090 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2091 match_dest_am | match_commutative |
2095 op1 = get_Or_left(val);
2096 op2 = get_Or_right(val);
2097 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2098 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2099 match_dest_am | match_commutative |
2103 op1 = get_Eor_left(val);
2104 op2 = get_Eor_right(val);
2105 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2106 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2107 match_dest_am | match_commutative |
2111 op1 = get_Shl_left(val);
2112 op2 = get_Shl_right(val);
2113 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2114 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2115 match_dest_am | match_immediate);
2118 op1 = get_Shr_left(val);
2119 op2 = get_Shr_right(val);
2120 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2121 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2122 match_dest_am | match_immediate);
2125 op1 = get_Shrs_left(val);
2126 op2 = get_Shrs_right(val);
2127 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2128 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2129 match_dest_am | match_immediate);
2132 op1 = get_Rot_left(val);
2133 op2 = get_Rot_right(val);
2134 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2135 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2136 match_dest_am | match_immediate);
2138 /* TODO: match ROR patterns... */
2140 new_node = try_create_SetMem(val, ptr, mem);
2143 op1 = get_Minus_op(val);
2144 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2147 /* should be lowered already */
2148 assert(mode != mode_b);
2149 op1 = get_Not_op(val);
2150 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2156 if(new_node != NULL) {
2157 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2158 get_irn_pinned(node) == op_pin_state_pinned) {
2159 set_irn_pinned(new_node, op_pin_state_pinned);
2166 static int is_float_to_int32_conv(const ir_node *node)
2168 ir_mode *mode = get_irn_mode(node);
2172 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2177 conv_op = get_Conv_op(node);
2178 conv_mode = get_irn_mode(conv_op);
2180 if(!mode_is_float(conv_mode))
2187 * Transforms a Store.
2189 * @return the created ia32 Store node
2191 static ir_node *gen_Store(ir_node *node)
2193 ir_node *block = get_nodes_block(node);
2194 ir_node *new_block = be_transform_node(block);
2195 ir_node *ptr = get_Store_ptr(node);
2196 ir_node *val = get_Store_value(node);
2197 ir_node *mem = get_Store_mem(node);
2198 ir_graph *irg = current_ir_graph;
2199 dbg_info *dbgi = get_irn_dbg_info(node);
2200 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2201 ir_mode *mode = get_irn_mode(val);
2204 ia32_address_t addr;
2206 /* check for destination address mode */
2207 new_node = try_create_dest_am(node);
2208 if(new_node != NULL)
2211 /* construct store address */
2212 memset(&addr, 0, sizeof(addr));
2213 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2215 if(addr.base == NULL) {
2218 addr.base = be_transform_node(addr.base);
2221 if(addr.index == NULL) {
2224 addr.index = be_transform_node(addr.index);
2226 addr.mem = be_transform_node(mem);
2228 if (mode_is_float(mode)) {
2229 /* convs (and strict-convs) before stores are unnecessary if the mode
2231 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2232 val = get_Conv_op(val);
2234 new_val = be_transform_node(val);
2235 if (ia32_cg_config.use_sse2) {
2236 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2237 addr.index, addr.mem, new_val);
2239 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2240 addr.index, addr.mem, new_val, mode);
2242 } else if(is_float_to_int32_conv(val)) {
2243 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2244 val = get_Conv_op(val);
2246 /* convs (and strict-convs) before stores are unnecessary if the mode
2248 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2249 val = get_Conv_op(val);
2251 new_val = be_transform_node(val);
2253 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2254 addr.index, addr.mem, new_val, trunc_mode);
2256 new_val = create_immediate_or_transform(val, 0);
2257 assert(mode != mode_b);
2259 if (get_mode_size_bits(mode) == 8) {
2260 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2261 addr.index, addr.mem, new_val);
2263 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2264 addr.index, addr.mem, new_val);
2268 set_irn_pinned(new_node, get_irn_pinned(node));
2269 set_ia32_op_type(new_node, ia32_AddrModeD);
2270 set_ia32_ls_mode(new_node, mode);
2272 set_ia32_exc_label(new_node,
2273 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2274 set_address(new_node, &addr);
2275 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2280 static ir_node *create_Switch(ir_node *node)
2282 ir_graph *irg = current_ir_graph;
2283 dbg_info *dbgi = get_irn_dbg_info(node);
2284 ir_node *block = be_transform_node(get_nodes_block(node));
2285 ir_node *sel = get_Cond_selector(node);
2286 ir_node *new_sel = be_transform_node(sel);
2287 int switch_min = INT_MAX;
2289 const ir_edge_t *edge;
2291 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2293 /* determine the smallest switch case value */
2294 foreach_out_edge(node, edge) {
2295 ir_node *proj = get_edge_src_irn(edge);
2296 int pn = get_Proj_proj(proj);
2301 if (switch_min != 0) {
2302 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2304 /* if smallest switch case is not 0 we need an additional sub */
2305 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2306 add_ia32_am_offs_int(new_sel, -switch_min);
2307 set_ia32_op_type(new_sel, ia32_AddrModeS);
2309 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2312 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2313 get_Cond_defaultProj(node));
2314 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2319 static ir_node *gen_Cond(ir_node *node) {
2320 ir_node *block = get_nodes_block(node);
2321 ir_node *new_block = be_transform_node(block);
2322 ir_graph *irg = current_ir_graph;
2323 dbg_info *dbgi = get_irn_dbg_info(node);
2324 ir_node *sel = get_Cond_selector(node);
2325 ir_mode *sel_mode = get_irn_mode(sel);
2326 ir_node *flags = NULL;
2330 if (sel_mode != mode_b) {
2331 return create_Switch(node);
2334 /* we get flags from a cmp */
2335 flags = get_flags_node(sel, &pnc);
2337 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2338 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2346 * Transforms a CopyB node.
2348 * @return The transformed node.
2350 static ir_node *gen_CopyB(ir_node *node) {
2351 ir_node *block = be_transform_node(get_nodes_block(node));
2352 ir_node *src = get_CopyB_src(node);
2353 ir_node *new_src = be_transform_node(src);
2354 ir_node *dst = get_CopyB_dst(node);
2355 ir_node *new_dst = be_transform_node(dst);
2356 ir_node *mem = get_CopyB_mem(node);
2357 ir_node *new_mem = be_transform_node(mem);
2358 ir_node *res = NULL;
2359 ir_graph *irg = current_ir_graph;
2360 dbg_info *dbgi = get_irn_dbg_info(node);
2361 int size = get_type_size_bytes(get_CopyB_type(node));
2364 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2365 /* then we need the size explicitly in ECX. */
2366 if (size >= 32 * 4) {
2367 rem = size & 0x3; /* size % 4 */
2370 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2371 add_irn_dep(res, get_irg_frame(irg));
2373 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2376 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2379 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2382 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2387 static ir_node *gen_be_Copy(ir_node *node)
2389 ir_node *new_node = be_duplicate_node(node);
2390 ir_mode *mode = get_irn_mode(new_node);
2392 if (mode_needs_gp_reg(mode)) {
2393 set_irn_mode(new_node, mode_Iu);
2399 static ir_node *create_Fucom(ir_node *node)
2401 ir_graph *irg = current_ir_graph;
2402 dbg_info *dbgi = get_irn_dbg_info(node);
2403 ir_node *block = get_nodes_block(node);
2404 ir_node *new_block = be_transform_node(block);
2405 ir_node *left = get_Cmp_left(node);
2406 ir_node *new_left = be_transform_node(left);
2407 ir_node *right = get_Cmp_right(node);
2411 if(ia32_cg_config.use_fucomi) {
2412 new_right = be_transform_node(right);
2413 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2415 set_ia32_commutative(new_node);
2416 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2418 if(ia32_cg_config.use_ftst && is_Const_null(right)) {
2419 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2422 new_right = be_transform_node(right);
2423 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2427 set_ia32_commutative(new_node);
2429 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2431 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2432 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2438 static ir_node *create_Ucomi(ir_node *node)
2440 ir_graph *irg = current_ir_graph;
2441 dbg_info *dbgi = get_irn_dbg_info(node);
2442 ir_node *src_block = get_nodes_block(node);
2443 ir_node *new_block = be_transform_node(src_block);
2444 ir_node *left = get_Cmp_left(node);
2445 ir_node *right = get_Cmp_right(node);
2447 ia32_address_mode_t am;
2448 ia32_address_t *addr = &am.addr;
2450 match_arguments(&am, src_block, left, right, NULL,
2451 match_commutative | match_am);
2453 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2454 addr->mem, am.new_op1, am.new_op2,
2456 set_am_attributes(new_node, &am);
2458 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2460 new_node = fix_mem_proj(new_node, &am);
2466 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2467 * to fold an and into a test node
2469 static int can_fold_test_and(ir_node *node)
2471 const ir_edge_t *edge;
2473 /** we can only have eq and lg projs */
2474 foreach_out_edge(node, edge) {
2475 ir_node *proj = get_edge_src_irn(edge);
2476 pn_Cmp pnc = get_Proj_proj(proj);
2477 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2484 static ir_node *gen_Cmp(ir_node *node)
2486 ir_graph *irg = current_ir_graph;
2487 dbg_info *dbgi = get_irn_dbg_info(node);
2488 ir_node *block = get_nodes_block(node);
2489 ir_node *new_block = be_transform_node(block);
2490 ir_node *left = get_Cmp_left(node);
2491 ir_node *right = get_Cmp_right(node);
2492 ir_mode *cmp_mode = get_irn_mode(left);
2494 ia32_address_mode_t am;
2495 ia32_address_t *addr = &am.addr;
2498 if(mode_is_float(cmp_mode)) {
2499 if (ia32_cg_config.use_sse2) {
2500 return create_Ucomi(node);
2502 return create_Fucom(node);
2506 assert(mode_needs_gp_reg(cmp_mode));
2508 /* we prefer the Test instruction where possible except cases where
2509 * we can use SourceAM */
2510 cmp_unsigned = !mode_is_signed(cmp_mode);
2511 if (is_Const_0(right)) {
2513 get_irn_n_edges(left) == 1 &&
2514 can_fold_test_and(node)) {
2515 /* Test(and_left, and_right) */
2516 ir_node *and_left = get_And_left(left);
2517 ir_node *and_right = get_And_right(left);
2518 ir_mode *mode = get_irn_mode(and_left);
2520 match_arguments(&am, block, and_left, and_right, NULL,
2522 match_am | match_8bit_am | match_16bit_am |
2523 match_am_and_immediates | match_immediate |
2524 match_8bit | match_16bit);
2525 if (get_mode_size_bits(mode) == 8) {
2526 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2527 addr->index, addr->mem, am.new_op1,
2528 am.new_op2, am.ins_permuted,
2531 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2532 addr->index, addr->mem, am.new_op1,
2533 am.new_op2, am.ins_permuted, cmp_unsigned);
2536 match_arguments(&am, block, NULL, left, NULL,
2537 match_am | match_8bit_am | match_16bit_am |
2538 match_8bit | match_16bit);
2539 if (am.op_type == ia32_AddrModeS) {
2541 ir_node *imm_zero = try_create_Immediate(right, 0);
2542 if (get_mode_size_bits(cmp_mode) == 8) {
2543 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2544 addr->index, addr->mem, am.new_op2,
2545 imm_zero, am.ins_permuted,
2548 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2549 addr->index, addr->mem, am.new_op2,
2550 imm_zero, am.ins_permuted, cmp_unsigned);
2553 /* Test(left, left) */
2554 if (get_mode_size_bits(cmp_mode) == 8) {
2555 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2556 addr->index, addr->mem, am.new_op2,
2557 am.new_op2, am.ins_permuted,
2560 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2561 addr->index, addr->mem, am.new_op2,
2562 am.new_op2, am.ins_permuted,
2568 /* Cmp(left, right) */
2569 match_arguments(&am, block, left, right, NULL,
2570 match_commutative | match_am | match_8bit_am |
2571 match_16bit_am | match_am_and_immediates |
2572 match_immediate | match_8bit | match_16bit);
2573 if (get_mode_size_bits(cmp_mode) == 8) {
2574 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2575 addr->index, addr->mem, am.new_op1,
2576 am.new_op2, am.ins_permuted,
2579 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2580 addr->index, addr->mem, am.new_op1,
2581 am.new_op2, am.ins_permuted, cmp_unsigned);
2584 set_am_attributes(new_node, &am);
2585 assert(cmp_mode != NULL);
2586 set_ia32_ls_mode(new_node, cmp_mode);
2588 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2590 new_node = fix_mem_proj(new_node, &am);
2595 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2598 ir_graph *irg = current_ir_graph;
2599 dbg_info *dbgi = get_irn_dbg_info(node);
2600 ir_node *block = get_nodes_block(node);
2601 ir_node *new_block = be_transform_node(block);
2602 ir_node *val_true = get_Psi_val(node, 0);
2603 ir_node *val_false = get_Psi_default(node);
2605 match_flags_t match_flags;
2606 ia32_address_mode_t am;
2607 ia32_address_t *addr;
2609 assert(ia32_cg_config.use_cmov);
2610 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2614 match_flags = match_commutative | match_am | match_16bit_am |
2617 match_arguments(&am, block, val_false, val_true, flags, match_flags);
2619 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2620 addr->mem, am.new_op1, am.new_op2, new_flags,
2621 am.ins_permuted, pnc);
2622 set_am_attributes(new_node, &am);
2624 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2626 new_node = fix_mem_proj(new_node, &am);
2633 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2634 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2637 ir_graph *irg = current_ir_graph;
2638 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2639 ir_node *nomem = new_NoMem();
2640 ir_mode *mode = get_irn_mode(orig_node);
2643 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2644 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2646 /* we might need to conv the result up */
2647 if(get_mode_size_bits(mode) > 8) {
2648 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2649 nomem, new_node, mode_Bu);
2650 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2657 * Transforms a Psi node into CMov.
2659 * @return The transformed node.
2661 static ir_node *gen_Psi(ir_node *node)
2663 dbg_info *dbgi = get_irn_dbg_info(node);
2664 ir_node *block = get_nodes_block(node);
2665 ir_node *new_block = be_transform_node(block);
2666 ir_node *psi_true = get_Psi_val(node, 0);
2667 ir_node *psi_default = get_Psi_default(node);
2668 ir_node *cond = get_Psi_cond(node, 0);
2669 ir_node *flags = NULL;
2673 assert(get_Psi_n_conds(node) == 1);
2674 assert(get_irn_mode(cond) == mode_b);
2675 assert(mode_needs_gp_reg(get_irn_mode(node)));
2677 flags = get_flags_node(cond, &pnc);
2679 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2680 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2681 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2682 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2684 new_node = create_CMov(node, cond, flags, pnc);
2691 * Create a conversion from x87 state register to general purpose.
2693 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2694 ir_node *block = be_transform_node(get_nodes_block(node));
2695 ir_node *op = get_Conv_op(node);
2696 ir_node *new_op = be_transform_node(op);
2697 ia32_code_gen_t *cg = env_cg;
2698 ir_graph *irg = current_ir_graph;
2699 dbg_info *dbgi = get_irn_dbg_info(node);
2700 ir_node *noreg = ia32_new_NoReg_gp(cg);
2701 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2702 ir_mode *mode = get_irn_mode(node);
2703 ir_node *fist, *load;
2706 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2707 new_NoMem(), new_op, trunc_mode);
2709 set_irn_pinned(fist, op_pin_state_floats);
2710 set_ia32_use_frame(fist);
2711 set_ia32_op_type(fist, ia32_AddrModeD);
2713 assert(get_mode_size_bits(mode) <= 32);
2714 /* exception we can only store signed 32 bit integers, so for unsigned
2715 we store a 64bit (signed) integer and load the lower bits */
2716 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2717 set_ia32_ls_mode(fist, mode_Ls);
2719 set_ia32_ls_mode(fist, mode_Is);
2721 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2724 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2726 set_irn_pinned(load, op_pin_state_floats);
2727 set_ia32_use_frame(load);
2728 set_ia32_op_type(load, ia32_AddrModeS);
2729 set_ia32_ls_mode(load, mode_Is);
2730 if(get_ia32_ls_mode(fist) == mode_Ls) {
2731 ia32_attr_t *attr = get_ia32_attr(load);
2732 attr->data.need_64bit_stackent = 1;
2734 ia32_attr_t *attr = get_ia32_attr(load);
2735 attr->data.need_32bit_stackent = 1;
2737 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2739 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2743 * Creates a x87 strict Conv by placing a Sore and a Load
2745 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2747 ir_node *block = get_nodes_block(node);
2748 ir_graph *irg = current_ir_graph;
2749 dbg_info *dbgi = get_irn_dbg_info(node);
2750 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2751 ir_node *nomem = new_NoMem();
2752 ir_node *frame = get_irg_frame(irg);
2753 ir_node *store, *load;
2756 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2758 set_ia32_use_frame(store);
2759 set_ia32_op_type(store, ia32_AddrModeD);
2760 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2762 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2764 set_ia32_use_frame(load);
2765 set_ia32_op_type(load, ia32_AddrModeS);
2766 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2768 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2772 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2774 ir_graph *irg = current_ir_graph;
2775 ir_node *start_block = get_irg_start_block(irg);
2776 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2777 symconst, symconst_sign, val);
2778 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2784 * Create a conversion from general purpose to x87 register
2786 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2787 ir_node *src_block = get_nodes_block(node);
2788 ir_node *block = be_transform_node(src_block);
2789 ir_graph *irg = current_ir_graph;
2790 dbg_info *dbgi = get_irn_dbg_info(node);
2791 ir_node *op = get_Conv_op(node);
2792 ir_node *new_op = NULL;
2796 ir_mode *store_mode;
2802 /* fild can use source AM if the operand is a signed 32bit integer */
2803 if (src_mode == mode_Is) {
2804 ia32_address_mode_t am;
2806 match_arguments(&am, src_block, NULL, op, NULL,
2807 match_am | match_try_am);
2808 if (am.op_type == ia32_AddrModeS) {
2809 ia32_address_t *addr = &am.addr;
2811 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2812 addr->index, addr->mem);
2813 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2816 set_am_attributes(fild, &am);
2817 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2819 fix_mem_proj(fild, &am);
2824 if(new_op == NULL) {
2825 new_op = be_transform_node(op);
2828 noreg = ia32_new_NoReg_gp(env_cg);
2829 nomem = new_NoMem();
2830 mode = get_irn_mode(op);
2832 /* first convert to 32 bit signed if necessary */
2833 src_bits = get_mode_size_bits(src_mode);
2834 if (src_bits == 8) {
2835 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2837 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2839 } else if (src_bits < 32) {
2840 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2842 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2846 assert(get_mode_size_bits(mode) == 32);
2849 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2852 set_ia32_use_frame(store);
2853 set_ia32_op_type(store, ia32_AddrModeD);
2854 set_ia32_ls_mode(store, mode_Iu);
2856 /* exception for 32bit unsigned, do a 64bit spill+load */
2857 if(!mode_is_signed(mode)) {
2860 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2862 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2863 get_irg_frame(irg), noreg, nomem,
2866 set_ia32_use_frame(zero_store);
2867 set_ia32_op_type(zero_store, ia32_AddrModeD);
2868 add_ia32_am_offs_int(zero_store, 4);
2869 set_ia32_ls_mode(zero_store, mode_Iu);
2874 store = new_rd_Sync(dbgi, irg, block, 2, in);
2875 store_mode = mode_Ls;
2877 store_mode = mode_Is;
2881 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2883 set_ia32_use_frame(fild);
2884 set_ia32_op_type(fild, ia32_AddrModeS);
2885 set_ia32_ls_mode(fild, store_mode);
2887 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2893 * Create a conversion from one integer mode into another one
2895 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2896 dbg_info *dbgi, ir_node *block, ir_node *op,
2899 ir_graph *irg = current_ir_graph;
2900 int src_bits = get_mode_size_bits(src_mode);
2901 int tgt_bits = get_mode_size_bits(tgt_mode);
2902 ir_node *new_block = be_transform_node(block);
2904 ir_mode *smaller_mode;
2906 ia32_address_mode_t am;
2907 ia32_address_t *addr = &am.addr;
2909 if (src_bits < tgt_bits) {
2910 smaller_mode = src_mode;
2911 smaller_bits = src_bits;
2913 smaller_mode = tgt_mode;
2914 smaller_bits = tgt_bits;
2917 #ifdef DEBUG_libfirm
2919 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2924 match_arguments(&am, block, NULL, op, NULL,
2925 match_8bit | match_16bit |
2926 match_am | match_8bit_am | match_16bit_am);
2927 if (smaller_bits == 8) {
2928 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2929 addr->index, addr->mem, am.new_op2,
2932 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2933 addr->index, addr->mem, am.new_op2,
2936 set_am_attributes(new_node, &am);
2937 /* match_arguments assume that out-mode = in-mode, this isn't true here
2939 set_ia32_ls_mode(new_node, smaller_mode);
2940 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2941 new_node = fix_mem_proj(new_node, &am);
2946 * Transforms a Conv node.
2948 * @return The created ia32 Conv node
2950 static ir_node *gen_Conv(ir_node *node) {
2951 ir_node *block = get_nodes_block(node);
2952 ir_node *new_block = be_transform_node(block);
2953 ir_node *op = get_Conv_op(node);
2954 ir_node *new_op = NULL;
2955 ir_graph *irg = current_ir_graph;
2956 dbg_info *dbgi = get_irn_dbg_info(node);
2957 ir_mode *src_mode = get_irn_mode(op);
2958 ir_mode *tgt_mode = get_irn_mode(node);
2959 int src_bits = get_mode_size_bits(src_mode);
2960 int tgt_bits = get_mode_size_bits(tgt_mode);
2961 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2962 ir_node *nomem = new_rd_NoMem(irg);
2963 ir_node *res = NULL;
2965 if (src_mode == mode_b) {
2966 assert(mode_is_int(tgt_mode));
2967 /* nothing to do, we already model bools as 0/1 ints */
2968 return be_transform_node(op);
2971 if (src_mode == tgt_mode) {
2972 if (get_Conv_strict(node)) {
2973 if (ia32_cg_config.use_sse2) {
2974 /* when we are in SSE mode, we can kill all strict no-op conversion */
2975 return be_transform_node(op);
2978 /* this should be optimized already, but who knows... */
2979 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2980 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2981 return be_transform_node(op);
2985 if (mode_is_float(src_mode)) {
2986 new_op = be_transform_node(op);
2987 /* we convert from float ... */
2988 if (mode_is_float(tgt_mode)) {
2989 if(src_mode == mode_E && tgt_mode == mode_D
2990 && !get_Conv_strict(node)) {
2991 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2996 if (ia32_cg_config.use_sse2) {
2997 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2998 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3000 set_ia32_ls_mode(res, tgt_mode);
3002 if(get_Conv_strict(node)) {
3003 res = gen_x87_strict_conv(tgt_mode, new_op);
3004 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3007 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3012 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3013 if (ia32_cg_config.use_sse2) {
3014 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3016 set_ia32_ls_mode(res, src_mode);
3018 return gen_x87_fp_to_gp(node);
3022 /* we convert from int ... */
3023 if (mode_is_float(tgt_mode)) {
3025 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3026 if (ia32_cg_config.use_sse2) {
3027 new_op = be_transform_node(op);
3028 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3030 set_ia32_ls_mode(res, tgt_mode);
3032 res = gen_x87_gp_to_fp(node, src_mode);
3033 if(get_Conv_strict(node)) {
3034 res = gen_x87_strict_conv(tgt_mode, res);
3035 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3036 ia32_get_old_node_name(env_cg, node));
3040 } else if(tgt_mode == mode_b) {
3041 /* mode_b lowering already took care that we only have 0/1 values */
3042 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3043 src_mode, tgt_mode));
3044 return be_transform_node(op);
3047 if (src_bits == tgt_bits) {
3048 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3049 src_mode, tgt_mode));
3050 return be_transform_node(op);
3053 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3061 static int check_immediate_constraint(long val, char immediate_constraint_type)
3063 switch (immediate_constraint_type) {
3067 return val >= 0 && val <= 32;
3069 return val >= 0 && val <= 63;
3071 return val >= -128 && val <= 127;
3073 return val == 0xff || val == 0xffff;
3075 return val >= 0 && val <= 3;
3077 return val >= 0 && val <= 255;
3079 return val >= 0 && val <= 127;
3083 panic("Invalid immediate constraint found");
3087 static ir_node *try_create_Immediate(ir_node *node,
3088 char immediate_constraint_type)
3091 tarval *offset = NULL;
3092 int offset_sign = 0;
3094 ir_entity *symconst_ent = NULL;
3095 int symconst_sign = 0;
3097 ir_node *cnst = NULL;
3098 ir_node *symconst = NULL;
3101 mode = get_irn_mode(node);
3102 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3106 if(is_Minus(node)) {
3108 node = get_Minus_op(node);
3111 if(is_Const(node)) {
3114 offset_sign = minus;
3115 } else if(is_SymConst(node)) {
3118 symconst_sign = minus;
3119 } else if(is_Add(node)) {
3120 ir_node *left = get_Add_left(node);
3121 ir_node *right = get_Add_right(node);
3122 if(is_Const(left) && is_SymConst(right)) {
3125 symconst_sign = minus;
3126 offset_sign = minus;
3127 } else if(is_SymConst(left) && is_Const(right)) {
3130 symconst_sign = minus;
3131 offset_sign = minus;
3133 } else if(is_Sub(node)) {
3134 ir_node *left = get_Sub_left(node);
3135 ir_node *right = get_Sub_right(node);
3136 if(is_Const(left) && is_SymConst(right)) {
3139 symconst_sign = !minus;
3140 offset_sign = minus;
3141 } else if(is_SymConst(left) && is_Const(right)) {
3144 symconst_sign = minus;
3145 offset_sign = !minus;
3152 offset = get_Const_tarval(cnst);
3153 if(tarval_is_long(offset)) {
3154 val = get_tarval_long(offset);
3156 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3161 if(!check_immediate_constraint(val, immediate_constraint_type))
3164 if(symconst != NULL) {
3165 if(immediate_constraint_type != 0) {
3166 /* we need full 32bits for symconsts */
3170 /* unfortunately the assembler/linker doesn't support -symconst */
3174 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3176 symconst_ent = get_SymConst_entity(symconst);
3178 if(cnst == NULL && symconst == NULL)
3181 if(offset_sign && offset != NULL) {
3182 offset = tarval_neg(offset);
3185 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3190 static ir_node *create_immediate_or_transform(ir_node *node,
3191 char immediate_constraint_type)
3193 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3194 if (new_node == NULL) {
3195 new_node = be_transform_node(node);
3200 static const arch_register_req_t no_register_req = {
3201 arch_register_req_type_none,
3202 NULL, /* regclass */
3203 NULL, /* limit bitset */
3205 0 /* different pos */
3209 * An assembler constraint.
3211 typedef struct constraint_t constraint_t;
3212 struct constraint_t {
3215 const arch_register_req_t **out_reqs;
3217 const arch_register_req_t *req;
3218 unsigned immediate_possible;
3219 char immediate_type;
3222 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3224 int immediate_possible = 0;
3225 char immediate_type = 0;
3226 unsigned limited = 0;
3227 const arch_register_class_t *cls = NULL;
3228 ir_graph *irg = current_ir_graph;
3229 struct obstack *obst = get_irg_obstack(irg);
3230 arch_register_req_t *req;
3231 unsigned *limited_ptr = NULL;
3235 /* TODO: replace all the asserts with nice error messages */
3238 /* a memory constraint: no need to do anything in backend about it
3239 * (the dependencies are already respected by the memory edge of
3241 constraint->req = &no_register_req;
3253 assert(cls == NULL ||
3254 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3255 cls = &ia32_reg_classes[CLASS_ia32_gp];
3256 limited |= 1 << REG_EAX;
3259 assert(cls == NULL ||
3260 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3261 cls = &ia32_reg_classes[CLASS_ia32_gp];
3262 limited |= 1 << REG_EBX;
3265 assert(cls == NULL ||
3266 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3267 cls = &ia32_reg_classes[CLASS_ia32_gp];
3268 limited |= 1 << REG_ECX;
3271 assert(cls == NULL ||
3272 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3273 cls = &ia32_reg_classes[CLASS_ia32_gp];
3274 limited |= 1 << REG_EDX;
3277 assert(cls == NULL ||
3278 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3279 cls = &ia32_reg_classes[CLASS_ia32_gp];
3280 limited |= 1 << REG_EDI;
3283 assert(cls == NULL ||
3284 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3285 cls = &ia32_reg_classes[CLASS_ia32_gp];
3286 limited |= 1 << REG_ESI;
3289 case 'q': /* q means lower part of the regs only, this makes no
3290 * difference to Q for us (we only assigne whole registers) */
3291 assert(cls == NULL ||
3292 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3293 cls = &ia32_reg_classes[CLASS_ia32_gp];
3294 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3298 assert(cls == NULL ||
3299 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3300 cls = &ia32_reg_classes[CLASS_ia32_gp];
3301 limited |= 1 << REG_EAX | 1 << REG_EDX;
3304 assert(cls == NULL ||
3305 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3306 cls = &ia32_reg_classes[CLASS_ia32_gp];
3307 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3308 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3315 assert(cls == NULL);
3316 cls = &ia32_reg_classes[CLASS_ia32_gp];
3322 /* TODO: mark values so the x87 simulator knows about t and u */
3323 assert(cls == NULL);
3324 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3329 assert(cls == NULL);
3330 /* TODO: check that sse2 is supported */
3331 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3341 assert(!immediate_possible);
3342 immediate_possible = 1;
3343 immediate_type = *c;
3347 assert(!immediate_possible);
3348 immediate_possible = 1;
3352 assert(!immediate_possible && cls == NULL);
3353 immediate_possible = 1;
3354 cls = &ia32_reg_classes[CLASS_ia32_gp];
3367 assert(constraint->is_in && "can only specify same constraint "
3370 sscanf(c, "%d%n", &same_as, &p);
3378 /* memory constraint no need to do anything in backend about it
3379 * (the dependencies are already respected by the memory edge of
3381 constraint->req = &no_register_req;
3384 case 'E': /* no float consts yet */
3385 case 'F': /* no float consts yet */
3386 case 's': /* makes no sense on x86 */
3387 case 'X': /* we can't support that in firm */
3390 case '<': /* no autodecrement on x86 */
3391 case '>': /* no autoincrement on x86 */
3392 case 'C': /* sse constant not supported yet */
3393 case 'G': /* 80387 constant not supported yet */
3394 case 'y': /* we don't support mmx registers yet */
3395 case 'Z': /* not available in 32 bit mode */
3396 case 'e': /* not available in 32 bit mode */
3397 panic("unsupported asm constraint '%c' found in (%+F)",
3398 *c, current_ir_graph);
3401 panic("unknown asm constraint '%c' found in (%+F)", *c,
3409 const arch_register_req_t *other_constr;
3411 assert(cls == NULL && "same as and register constraint not supported");
3412 assert(!immediate_possible && "same as and immediate constraint not "
3414 assert(same_as < constraint->n_outs && "wrong constraint number in "
3415 "same_as constraint");
3417 other_constr = constraint->out_reqs[same_as];
3419 req = obstack_alloc(obst, sizeof(req[0]));
3420 req->cls = other_constr->cls;
3421 req->type = arch_register_req_type_should_be_same;
3422 req->limited = NULL;
3423 req->other_same = 1U << pos;
3424 req->other_different = 0;
3426 /* switch constraints. This is because in firm we have same_as
3427 * constraints on the output constraints while in the gcc asm syntax
3428 * they are specified on the input constraints */
3429 constraint->req = other_constr;
3430 constraint->out_reqs[same_as] = req;
3431 constraint->immediate_possible = 0;
3435 if(immediate_possible && cls == NULL) {
3436 cls = &ia32_reg_classes[CLASS_ia32_gp];
3438 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3439 assert(cls != NULL);
3441 if(immediate_possible) {
3442 assert(constraint->is_in
3443 && "immediate make no sense for output constraints");
3445 /* todo: check types (no float input on 'r' constrained in and such... */
3448 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3449 limited_ptr = (unsigned*) (req+1);
3451 req = obstack_alloc(obst, sizeof(req[0]));
3453 memset(req, 0, sizeof(req[0]));
3456 req->type = arch_register_req_type_limited;
3457 *limited_ptr = limited;
3458 req->limited = limited_ptr;
3460 req->type = arch_register_req_type_normal;
3464 constraint->req = req;
3465 constraint->immediate_possible = immediate_possible;
3466 constraint->immediate_type = immediate_type;
3469 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3476 panic("Clobbers not supported yet");
3479 static int is_memory_op(const ir_asm_constraint *constraint)
3481 ident *id = constraint->constraint;
3482 const char *str = get_id_str(id);
3485 for(c = str; *c != '\0'; ++c) {
3494 * generates code for a ASM node
3496 static ir_node *gen_ASM(ir_node *node)
3499 ir_graph *irg = current_ir_graph;
3500 ir_node *block = get_nodes_block(node);
3501 ir_node *new_block = be_transform_node(block);
3502 dbg_info *dbgi = get_irn_dbg_info(node);
3506 int n_out_constraints;
3508 const arch_register_req_t **out_reg_reqs;
3509 const arch_register_req_t **in_reg_reqs;
3510 ia32_asm_reg_t *register_map;
3511 unsigned reg_map_size = 0;
3512 struct obstack *obst;
3513 const ir_asm_constraint *in_constraints;
3514 const ir_asm_constraint *out_constraints;
3516 constraint_t parsed_constraint;
3518 arity = get_irn_arity(node);
3519 in = alloca(arity * sizeof(in[0]));
3520 memset(in, 0, arity * sizeof(in[0]));
3522 n_out_constraints = get_ASM_n_output_constraints(node);
3523 n_clobbers = get_ASM_n_clobbers(node);
3524 out_arity = n_out_constraints + n_clobbers;
3526 in_constraints = get_ASM_input_constraints(node);
3527 out_constraints = get_ASM_output_constraints(node);
3528 clobbers = get_ASM_clobbers(node);
3530 /* construct output constraints */
3531 obst = get_irg_obstack(irg);
3532 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3533 parsed_constraint.out_reqs = out_reg_reqs;
3534 parsed_constraint.n_outs = n_out_constraints;
3535 parsed_constraint.is_in = 0;
3537 for(i = 0; i < out_arity; ++i) {
3540 if(i < n_out_constraints) {
3541 const ir_asm_constraint *constraint = &out_constraints[i];
3542 c = get_id_str(constraint->constraint);
3543 parse_asm_constraint(i, &parsed_constraint, c);
3545 if(constraint->pos > reg_map_size)
3546 reg_map_size = constraint->pos;
3548 ident *glob_id = clobbers [i - n_out_constraints];
3549 c = get_id_str(glob_id);
3550 parse_clobber(node, i, &parsed_constraint, c);
3553 out_reg_reqs[i] = parsed_constraint.req;
3556 /* construct input constraints */
3557 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3558 parsed_constraint.is_in = 1;
3559 for(i = 0; i < arity; ++i) {
3560 const ir_asm_constraint *constraint = &in_constraints[i];
3561 ident *constr_id = constraint->constraint;
3562 const char *c = get_id_str(constr_id);
3564 parse_asm_constraint(i, &parsed_constraint, c);
3565 in_reg_reqs[i] = parsed_constraint.req;
3567 if(constraint->pos > reg_map_size)
3568 reg_map_size = constraint->pos;
3570 if(parsed_constraint.immediate_possible) {
3571 ir_node *pred = get_irn_n(node, i);
3572 char imm_type = parsed_constraint.immediate_type;
3573 ir_node *immediate = try_create_Immediate(pred, imm_type);
3575 if(immediate != NULL) {
3582 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3583 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3585 for(i = 0; i < n_out_constraints; ++i) {
3586 const ir_asm_constraint *constraint = &out_constraints[i];
3587 unsigned pos = constraint->pos;
3589 assert(pos < reg_map_size);
3590 register_map[pos].use_input = 0;
3591 register_map[pos].valid = 1;
3592 register_map[pos].memory = is_memory_op(constraint);
3593 register_map[pos].inout_pos = i;
3594 register_map[pos].mode = constraint->mode;
3597 /* transform inputs */
3598 for(i = 0; i < arity; ++i) {
3599 const ir_asm_constraint *constraint = &in_constraints[i];
3600 unsigned pos = constraint->pos;
3601 ir_node *pred = get_irn_n(node, i);
3602 ir_node *transformed;
3604 assert(pos < reg_map_size);
3605 register_map[pos].use_input = 1;
3606 register_map[pos].valid = 1;
3607 register_map[pos].memory = is_memory_op(constraint);
3608 register_map[pos].inout_pos = i;
3609 register_map[pos].mode = constraint->mode;
3614 transformed = be_transform_node(pred);
3615 in[i] = transformed;
3618 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3619 get_ASM_text(node), register_map);
3621 set_ia32_out_req_all(new_node, out_reg_reqs);
3622 set_ia32_in_req_all(new_node, in_reg_reqs);
3624 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3630 * Transforms a FrameAddr into an ia32 Add.
3632 static ir_node *gen_be_FrameAddr(ir_node *node) {
3633 ir_node *block = be_transform_node(get_nodes_block(node));
3634 ir_node *op = be_get_FrameAddr_frame(node);
3635 ir_node *new_op = be_transform_node(op);
3636 ir_graph *irg = current_ir_graph;
3637 dbg_info *dbgi = get_irn_dbg_info(node);
3638 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3641 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3642 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3643 set_ia32_use_frame(new_node);
3645 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3651 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3653 static ir_node *gen_be_Return(ir_node *node) {
3654 ir_graph *irg = current_ir_graph;
3655 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3656 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3657 ir_entity *ent = get_irg_entity(irg);
3658 ir_type *tp = get_entity_type(ent);
3663 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3664 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3667 int pn_ret_val, pn_ret_mem, arity, i;
3669 assert(ret_val != NULL);
3670 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3671 return be_duplicate_node(node);
3674 res_type = get_method_res_type(tp, 0);
3676 if (! is_Primitive_type(res_type)) {
3677 return be_duplicate_node(node);
3680 mode = get_type_mode(res_type);
3681 if (! mode_is_float(mode)) {
3682 return be_duplicate_node(node);
3685 assert(get_method_n_ress(tp) == 1);
3687 pn_ret_val = get_Proj_proj(ret_val);
3688 pn_ret_mem = get_Proj_proj(ret_mem);
3690 /* get the Barrier */
3691 barrier = get_Proj_pred(ret_val);
3693 /* get result input of the Barrier */
3694 ret_val = get_irn_n(barrier, pn_ret_val);
3695 new_ret_val = be_transform_node(ret_val);
3697 /* get memory input of the Barrier */
3698 ret_mem = get_irn_n(barrier, pn_ret_mem);
3699 new_ret_mem = be_transform_node(ret_mem);
3701 frame = get_irg_frame(irg);
3703 dbgi = get_irn_dbg_info(barrier);
3704 block = be_transform_node(get_nodes_block(barrier));
3706 noreg = ia32_new_NoReg_gp(env_cg);
3708 /* store xmm0 onto stack */
3709 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3710 new_ret_mem, new_ret_val);
3711 set_ia32_ls_mode(sse_store, mode);
3712 set_ia32_op_type(sse_store, ia32_AddrModeD);
3713 set_ia32_use_frame(sse_store);
3715 /* load into x87 register */
3716 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3717 set_ia32_op_type(fld, ia32_AddrModeS);
3718 set_ia32_use_frame(fld);
3720 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3721 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3723 /* create a new barrier */
3724 arity = get_irn_arity(barrier);
3725 in = alloca(arity * sizeof(in[0]));
3726 for (i = 0; i < arity; ++i) {
3729 if (i == pn_ret_val) {
3731 } else if (i == pn_ret_mem) {
3734 ir_node *in = get_irn_n(barrier, i);
3735 new_in = be_transform_node(in);
3740 new_barrier = new_ir_node(dbgi, irg, block,
3741 get_irn_op(barrier), get_irn_mode(barrier),
3743 copy_node_attr(barrier, new_barrier);
3744 be_duplicate_deps(barrier, new_barrier);
3745 be_set_transformed_node(barrier, new_barrier);
3746 mark_irn_visited(barrier);
3748 /* transform normally */
3749 return be_duplicate_node(node);
3753 * Transform a be_AddSP into an ia32_SubSP.
3755 static ir_node *gen_be_AddSP(ir_node *node)
3757 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3758 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3760 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3764 * Transform a be_SubSP into an ia32_AddSP
3766 static ir_node *gen_be_SubSP(ir_node *node)
3768 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3769 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3771 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3775 * This function just sets the register for the Unknown node
3776 * as this is not done during register allocation because Unknown
3777 * is an "ignore" node.
3779 static ir_node *gen_Unknown(ir_node *node) {
3780 ir_mode *mode = get_irn_mode(node);
3782 if (mode_is_float(mode)) {
3783 if (ia32_cg_config.use_sse2) {
3784 return ia32_new_Unknown_xmm(env_cg);
3786 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3787 ir_graph *irg = current_ir_graph;
3788 dbg_info *dbgi = get_irn_dbg_info(node);
3789 ir_node *block = get_irg_start_block(irg);
3790 return new_rd_ia32_vfldz(dbgi, irg, block);
3792 } else if (mode_needs_gp_reg(mode)) {
3793 return ia32_new_Unknown_gp(env_cg);
3795 panic("unsupported Unknown-Mode");
3801 * Change some phi modes
3803 static ir_node *gen_Phi(ir_node *node) {
3804 ir_node *block = be_transform_node(get_nodes_block(node));
3805 ir_graph *irg = current_ir_graph;
3806 dbg_info *dbgi = get_irn_dbg_info(node);
3807 ir_mode *mode = get_irn_mode(node);
3810 if(mode_needs_gp_reg(mode)) {
3811 /* we shouldn't have any 64bit stuff around anymore */
3812 assert(get_mode_size_bits(mode) <= 32);
3813 /* all integer operations are on 32bit registers now */
3815 } else if(mode_is_float(mode)) {
3816 if (ia32_cg_config.use_sse2) {
3823 /* phi nodes allow loops, so we use the old arguments for now
3824 * and fix this later */
3825 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3826 get_irn_in(node) + 1);
3827 copy_node_attr(node, phi);
3828 be_duplicate_deps(node, phi);
3830 be_set_transformed_node(node, phi);
3831 be_enqueue_preds(node);
3839 static ir_node *gen_IJmp(ir_node *node)
3841 ir_node *block = get_nodes_block(node);
3842 ir_node *new_block = be_transform_node(block);
3843 ir_graph *irg = current_ir_graph;
3844 dbg_info *dbgi = get_irn_dbg_info(node);
3845 ir_node *op = get_IJmp_target(node);
3847 ia32_address_mode_t am;
3848 ia32_address_t *addr = &am.addr;
3850 assert(get_irn_mode(op) == mode_P);
3852 match_arguments(&am, block, NULL, op, NULL,
3853 match_am | match_8bit_am | match_16bit_am |
3854 match_immediate | match_8bit | match_16bit);
3856 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3857 addr->mem, am.new_op2);
3858 set_am_attributes(new_node, &am);
3859 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3861 new_node = fix_mem_proj(new_node, &am);
3866 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3869 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3870 ir_node *val, ir_node *mem);
3873 * Transforms a lowered Load into a "real" one.
3875 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3877 ir_node *block = be_transform_node(get_nodes_block(node));
3878 ir_node *ptr = get_irn_n(node, 0);
3879 ir_node *new_ptr = be_transform_node(ptr);
3880 ir_node *mem = get_irn_n(node, 1);
3881 ir_node *new_mem = be_transform_node(mem);
3882 ir_graph *irg = current_ir_graph;
3883 dbg_info *dbgi = get_irn_dbg_info(node);
3884 ir_mode *mode = get_ia32_ls_mode(node);
3885 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3888 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3890 set_ia32_op_type(new_op, ia32_AddrModeS);
3891 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3892 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3893 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3894 if (is_ia32_am_sc_sign(node))
3895 set_ia32_am_sc_sign(new_op);
3896 set_ia32_ls_mode(new_op, mode);
3897 if (is_ia32_use_frame(node)) {
3898 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3899 set_ia32_use_frame(new_op);
3902 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3908 * Transforms a lowered Store into a "real" one.
3910 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3912 ir_node *block = be_transform_node(get_nodes_block(node));
3913 ir_node *ptr = get_irn_n(node, 0);
3914 ir_node *new_ptr = be_transform_node(ptr);
3915 ir_node *val = get_irn_n(node, 1);
3916 ir_node *new_val = be_transform_node(val);
3917 ir_node *mem = get_irn_n(node, 2);
3918 ir_node *new_mem = be_transform_node(mem);
3919 ir_graph *irg = current_ir_graph;
3920 dbg_info *dbgi = get_irn_dbg_info(node);
3921 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3922 ir_mode *mode = get_ia32_ls_mode(node);
3926 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3928 am_offs = get_ia32_am_offs_int(node);
3929 add_ia32_am_offs_int(new_op, am_offs);
3931 set_ia32_op_type(new_op, ia32_AddrModeD);
3932 set_ia32_ls_mode(new_op, mode);
3933 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3934 set_ia32_use_frame(new_op);
3936 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3941 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3943 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
3944 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
3946 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3947 match_immediate | match_mode_neutral);
3950 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3952 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
3953 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
3954 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3958 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3960 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
3961 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
3962 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3966 static ir_node *gen_ia32_l_Add(ir_node *node) {
3967 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3968 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3969 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3970 match_commutative | match_am | match_immediate |
3971 match_mode_neutral);
3973 if(is_Proj(lowered)) {
3974 lowered = get_Proj_pred(lowered);
3976 assert(is_ia32_Add(lowered));
3977 set_irn_mode(lowered, mode_T);
3983 static ir_node *gen_ia32_l_Adc(ir_node *node)
3985 return gen_binop_flags(node, new_rd_ia32_Adc,
3986 match_commutative | match_am | match_immediate |
3987 match_mode_neutral);
3991 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3993 * @param node The node to transform
3994 * @return the created ia32 vfild node
3996 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3997 return gen_lowered_Load(node, new_rd_ia32_vfild);
4001 * Transforms an ia32_l_Load into a "real" ia32_Load node
4003 * @param node The node to transform
4004 * @return the created ia32 Load node
4006 static ir_node *gen_ia32_l_Load(ir_node *node) {
4007 return gen_lowered_Load(node, new_rd_ia32_Load);
4011 * Transforms an ia32_l_Store into a "real" ia32_Store node
4013 * @param node The node to transform
4014 * @return the created ia32 Store node
4016 static ir_node *gen_ia32_l_Store(ir_node *node) {
4017 return gen_lowered_Store(node, new_rd_ia32_Store);
4021 * Transforms a l_vfist into a "real" vfist node.
4023 * @param node The node to transform
4024 * @return the created ia32 vfist node
4026 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4027 ir_node *block = be_transform_node(get_nodes_block(node));
4028 ir_node *ptr = get_irn_n(node, 0);
4029 ir_node *new_ptr = be_transform_node(ptr);
4030 ir_node *val = get_irn_n(node, 1);
4031 ir_node *new_val = be_transform_node(val);
4032 ir_node *mem = get_irn_n(node, 2);
4033 ir_node *new_mem = be_transform_node(mem);
4034 ir_graph *irg = current_ir_graph;
4035 dbg_info *dbgi = get_irn_dbg_info(node);
4036 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4037 ir_mode *mode = get_ia32_ls_mode(node);
4038 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4042 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4043 new_val, trunc_mode);
4045 am_offs = get_ia32_am_offs_int(node);
4046 add_ia32_am_offs_int(new_op, am_offs);
4048 set_ia32_op_type(new_op, ia32_AddrModeD);
4049 set_ia32_ls_mode(new_op, mode);
4050 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4051 set_ia32_use_frame(new_op);
4053 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4059 * Transforms a l_MulS into a "real" MulS node.
4061 * @return the created ia32 Mul node
4063 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4064 ir_node *left = get_binop_left(node);
4065 ir_node *right = get_binop_right(node);
4067 return gen_binop(node, left, right, new_rd_ia32_Mul,
4068 match_commutative | match_am | match_mode_neutral);
4072 * Transforms a l_IMulS into a "real" IMul1OPS node.
4074 * @return the created ia32 IMul1OP node
4076 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4077 ir_node *left = get_binop_left(node);
4078 ir_node *right = get_binop_right(node);
4080 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4081 match_commutative | match_am | match_mode_neutral);
4084 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4085 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4086 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4087 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4088 match_am | match_immediate | match_mode_neutral);
4090 if(is_Proj(lowered)) {
4091 lowered = get_Proj_pred(lowered);
4093 assert(is_ia32_Sub(lowered));
4094 set_irn_mode(lowered, mode_T);
4100 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4101 return gen_binop_flags(node, new_rd_ia32_Sbb,
4102 match_am | match_immediate | match_mode_neutral);
4106 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4107 * op1 - target to be shifted
4108 * op2 - contains bits to be shifted into target
4110 * Only op3 can be an immediate.
4112 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4113 ir_node *low, ir_node *count)
4115 ir_node *block = get_nodes_block(node);
4116 ir_node *new_block = be_transform_node(block);
4117 ir_graph *irg = current_ir_graph;
4118 dbg_info *dbgi = get_irn_dbg_info(node);
4119 ir_node *new_high = be_transform_node(high);
4120 ir_node *new_low = be_transform_node(low);
4124 /* the shift amount can be any mode that is bigger than 5 bits, since all
4125 * other bits are ignored anyway */
4126 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4127 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4128 count = get_Conv_op(count);
4130 new_count = create_immediate_or_transform(count, 0);
4132 if (is_ia32_l_ShlD(node)) {
4133 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4136 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4139 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4144 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4146 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4147 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4148 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4149 return gen_lowered_64bit_shifts(node, high, low, count);
4152 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4154 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4155 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4156 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4157 return gen_lowered_64bit_shifts(node, high, low, count);
4161 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4163 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4164 ir_node *block = be_transform_node(get_nodes_block(node));
4165 ir_node *val = get_irn_n(node, 1);
4166 ir_node *new_val = be_transform_node(val);
4167 ir_node *res = NULL;
4168 ir_graph *irg = current_ir_graph;
4170 ir_node *noreg, *new_ptr, *new_mem;
4173 if (ia32_cg_config.use_sse2) {
4177 mem = get_irn_n(node, 2);
4178 new_mem = be_transform_node(mem);
4179 ptr = get_irn_n(node, 0);
4180 new_ptr = be_transform_node(ptr);
4181 noreg = ia32_new_NoReg_gp(env_cg);
4182 dbgi = get_irn_dbg_info(node);
4184 /* Store x87 -> MEM */
4185 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4186 get_ia32_ls_mode(node));
4187 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4188 set_ia32_use_frame(res);
4189 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4190 set_ia32_op_type(res, ia32_AddrModeD);
4192 /* Load MEM -> SSE */
4193 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4194 get_ia32_ls_mode(node));
4195 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4196 set_ia32_use_frame(res);
4197 set_ia32_op_type(res, ia32_AddrModeS);
4198 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4204 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4206 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4207 ir_node *block = be_transform_node(get_nodes_block(node));
4208 ir_node *val = get_irn_n(node, 1);
4209 ir_node *new_val = be_transform_node(val);
4210 ir_graph *irg = current_ir_graph;
4211 ir_node *res = NULL;
4212 ir_entity *fent = get_ia32_frame_ent(node);
4213 ir_mode *lsmode = get_ia32_ls_mode(node);
4215 ir_node *noreg, *new_ptr, *new_mem;
4219 if (! ia32_cg_config.use_sse2) {
4220 /* SSE unit is not used -> skip this node. */
4224 ptr = get_irn_n(node, 0);
4225 new_ptr = be_transform_node(ptr);
4226 mem = get_irn_n(node, 2);
4227 new_mem = be_transform_node(mem);
4228 noreg = ia32_new_NoReg_gp(env_cg);
4229 dbgi = get_irn_dbg_info(node);
4231 /* Store SSE -> MEM */
4232 if (is_ia32_xLoad(skip_Proj(new_val))) {
4233 ir_node *ld = skip_Proj(new_val);
4235 /* we can vfld the value directly into the fpu */
4236 fent = get_ia32_frame_ent(ld);
4237 ptr = get_irn_n(ld, 0);
4238 offs = get_ia32_am_offs_int(ld);
4240 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4242 set_ia32_frame_ent(res, fent);
4243 set_ia32_use_frame(res);
4244 set_ia32_ls_mode(res, lsmode);
4245 set_ia32_op_type(res, ia32_AddrModeD);
4249 /* Load MEM -> x87 */
4250 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4251 set_ia32_frame_ent(res, fent);
4252 set_ia32_use_frame(res);
4253 add_ia32_am_offs_int(res, offs);
4254 set_ia32_op_type(res, ia32_AddrModeS);
4255 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4261 * the BAD transformer.
4263 static ir_node *bad_transform(ir_node *node) {
4264 panic("No transform function for %+F available.\n", node);
4269 * Transform the Projs of an AddSP.
4271 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4272 ir_node *block = be_transform_node(get_nodes_block(node));
4273 ir_node *pred = get_Proj_pred(node);
4274 ir_node *new_pred = be_transform_node(pred);
4275 ir_graph *irg = current_ir_graph;
4276 dbg_info *dbgi = get_irn_dbg_info(node);
4277 long proj = get_Proj_proj(node);
4279 if (proj == pn_be_AddSP_sp) {
4280 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4281 pn_ia32_SubSP_stack);
4282 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4284 } else if(proj == pn_be_AddSP_res) {
4285 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4286 pn_ia32_SubSP_addr);
4287 } else if (proj == pn_be_AddSP_M) {
4288 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4292 return new_rd_Unknown(irg, get_irn_mode(node));
4296 * Transform the Projs of a SubSP.
4298 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4299 ir_node *block = be_transform_node(get_nodes_block(node));
4300 ir_node *pred = get_Proj_pred(node);
4301 ir_node *new_pred = be_transform_node(pred);
4302 ir_graph *irg = current_ir_graph;
4303 dbg_info *dbgi = get_irn_dbg_info(node);
4304 long proj = get_Proj_proj(node);
4306 if (proj == pn_be_SubSP_sp) {
4307 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4308 pn_ia32_AddSP_stack);
4309 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4311 } else if (proj == pn_be_SubSP_M) {
4312 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4316 return new_rd_Unknown(irg, get_irn_mode(node));
4320 * Transform and renumber the Projs from a Load.
4322 static ir_node *gen_Proj_Load(ir_node *node) {
4324 ir_node *block = be_transform_node(get_nodes_block(node));
4325 ir_node *pred = get_Proj_pred(node);
4326 ir_graph *irg = current_ir_graph;
4327 dbg_info *dbgi = get_irn_dbg_info(node);
4328 long proj = get_Proj_proj(node);
4331 /* loads might be part of source address mode matches, so we don't
4332 transform the ProjMs yet (with the exception of loads whose result is
4335 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4338 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4340 /* this is needed, because sometimes we have loops that are only
4341 reachable through the ProjM */
4342 be_enqueue_preds(node);
4343 /* do it in 2 steps, to silence firm verifier */
4344 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4345 set_Proj_proj(res, pn_ia32_Load_M);
4349 /* renumber the proj */
4350 new_pred = be_transform_node(pred);
4351 if (is_ia32_Load(new_pred)) {
4352 if (proj == pn_Load_res) {
4353 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4355 } else if (proj == pn_Load_M) {
4356 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4359 } else if(is_ia32_Conv_I2I(new_pred)
4360 || is_ia32_Conv_I2I8Bit(new_pred)) {
4361 set_irn_mode(new_pred, mode_T);
4362 if (proj == pn_Load_res) {
4363 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4364 } else if (proj == pn_Load_M) {
4365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4367 } else if (is_ia32_xLoad(new_pred)) {
4368 if (proj == pn_Load_res) {
4369 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4371 } else if (proj == pn_Load_M) {
4372 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4375 } else if (is_ia32_vfld(new_pred)) {
4376 if (proj == pn_Load_res) {
4377 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4379 } else if (proj == pn_Load_M) {
4380 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4384 /* can happen for ProJMs when source address mode happened for the
4387 /* however it should not be the result proj, as that would mean the
4388 load had multiple users and should not have been used for
4390 if(proj != pn_Load_M) {
4391 panic("internal error: transformed node not a Load");
4393 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4397 return new_rd_Unknown(irg, get_irn_mode(node));
4401 * Transform and renumber the Projs from a DivMod like instruction.
4403 static ir_node *gen_Proj_DivMod(ir_node *node) {
4404 ir_node *block = be_transform_node(get_nodes_block(node));
4405 ir_node *pred = get_Proj_pred(node);
4406 ir_node *new_pred = be_transform_node(pred);
4407 ir_graph *irg = current_ir_graph;
4408 dbg_info *dbgi = get_irn_dbg_info(node);
4409 ir_mode *mode = get_irn_mode(node);
4410 long proj = get_Proj_proj(node);
4412 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4414 switch (get_irn_opcode(pred)) {
4418 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4420 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4428 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4430 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4438 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4439 case pn_DivMod_res_div:
4440 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4441 case pn_DivMod_res_mod:
4442 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4452 return new_rd_Unknown(irg, mode);
4456 * Transform and renumber the Projs from a CopyB.
4458 static ir_node *gen_Proj_CopyB(ir_node *node) {
4459 ir_node *block = be_transform_node(get_nodes_block(node));
4460 ir_node *pred = get_Proj_pred(node);
4461 ir_node *new_pred = be_transform_node(pred);
4462 ir_graph *irg = current_ir_graph;
4463 dbg_info *dbgi = get_irn_dbg_info(node);
4464 ir_mode *mode = get_irn_mode(node);
4465 long proj = get_Proj_proj(node);
4468 case pn_CopyB_M_regular:
4469 if (is_ia32_CopyB_i(new_pred)) {
4470 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4471 } else if (is_ia32_CopyB(new_pred)) {
4472 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4480 return new_rd_Unknown(irg, mode);
4484 * Transform and renumber the Projs from a Quot.
4486 static ir_node *gen_Proj_Quot(ir_node *node) {
4487 ir_node *block = be_transform_node(get_nodes_block(node));
4488 ir_node *pred = get_Proj_pred(node);
4489 ir_node *new_pred = be_transform_node(pred);
4490 ir_graph *irg = current_ir_graph;
4491 dbg_info *dbgi = get_irn_dbg_info(node);
4492 ir_mode *mode = get_irn_mode(node);
4493 long proj = get_Proj_proj(node);
4497 if (is_ia32_xDiv(new_pred)) {
4498 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4499 } else if (is_ia32_vfdiv(new_pred)) {
4500 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4504 if (is_ia32_xDiv(new_pred)) {
4505 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4506 } else if (is_ia32_vfdiv(new_pred)) {
4507 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4515 return new_rd_Unknown(irg, mode);
4519 * Transform the Thread Local Storage Proj.
4521 static ir_node *gen_Proj_tls(ir_node *node) {
4522 ir_node *block = be_transform_node(get_nodes_block(node));
4523 ir_graph *irg = current_ir_graph;
4524 dbg_info *dbgi = NULL;
4525 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4530 static ir_node *gen_be_Call(ir_node *node) {
4531 ir_node *res = be_duplicate_node(node);
4532 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4537 static ir_node *gen_be_IncSP(ir_node *node) {
4538 ir_node *res = be_duplicate_node(node);
4539 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4545 * Transform the Projs from a be_Call.
4547 static ir_node *gen_Proj_be_Call(ir_node *node) {
4548 ir_node *block = be_transform_node(get_nodes_block(node));
4549 ir_node *call = get_Proj_pred(node);
4550 ir_node *new_call = be_transform_node(call);
4551 ir_graph *irg = current_ir_graph;
4552 dbg_info *dbgi = get_irn_dbg_info(node);
4553 ir_type *method_type = be_Call_get_type(call);
4554 int n_res = get_method_n_ress(method_type);
4555 long proj = get_Proj_proj(node);
4556 ir_mode *mode = get_irn_mode(node);
4558 const arch_register_class_t *cls;
4560 /* The following is kinda tricky: If we're using SSE, then we have to
4561 * move the result value of the call in floating point registers to an
4562 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4563 * after the call, we have to make sure to correctly make the
4564 * MemProj and the result Proj use these 2 nodes
4566 if (proj == pn_be_Call_M_regular) {
4567 // get new node for result, are we doing the sse load/store hack?
4568 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4569 ir_node *call_res_new;
4570 ir_node *call_res_pred = NULL;
4572 if (call_res != NULL) {
4573 call_res_new = be_transform_node(call_res);
4574 call_res_pred = get_Proj_pred(call_res_new);
4577 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4578 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4579 pn_be_Call_M_regular);
4581 assert(is_ia32_xLoad(call_res_pred));
4582 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4586 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
4587 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
4589 ir_node *frame = get_irg_frame(irg);
4590 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4592 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4595 /* in case there is no memory output: create one to serialize the copy
4597 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4598 pn_be_Call_M_regular);
4599 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4600 pn_be_Call_first_res);
4602 /* store st(0) onto stack */
4603 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4605 set_ia32_op_type(fstp, ia32_AddrModeD);
4606 set_ia32_use_frame(fstp);
4608 /* load into SSE register */
4609 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4611 set_ia32_op_type(sse_load, ia32_AddrModeS);
4612 set_ia32_use_frame(sse_load);
4614 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4620 /* transform call modes */
4621 if (mode_is_data(mode)) {
4622 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4626 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4630 * Transform the Projs from a Cmp.
4632 static ir_node *gen_Proj_Cmp(ir_node *node)
4634 /* this probably means not all mode_b nodes were lowered... */
4635 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
4640 * Transform and potentially renumber Proj nodes.
4642 static ir_node *gen_Proj(ir_node *node) {
4643 ir_graph *irg = current_ir_graph;
4644 dbg_info *dbgi = get_irn_dbg_info(node);
4645 ir_node *pred = get_Proj_pred(node);
4646 long proj = get_Proj_proj(node);
4648 if (is_Store(pred)) {
4649 if (proj == pn_Store_M) {
4650 return be_transform_node(pred);
4653 return new_r_Bad(irg);
4655 } else if (is_Load(pred)) {
4656 return gen_Proj_Load(node);
4657 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4658 return gen_Proj_DivMod(node);
4659 } else if (is_CopyB(pred)) {
4660 return gen_Proj_CopyB(node);
4661 } else if (is_Quot(pred)) {
4662 return gen_Proj_Quot(node);
4663 } else if (be_is_SubSP(pred)) {
4664 return gen_Proj_be_SubSP(node);
4665 } else if (be_is_AddSP(pred)) {
4666 return gen_Proj_be_AddSP(node);
4667 } else if (be_is_Call(pred)) {
4668 return gen_Proj_be_Call(node);
4669 } else if (is_Cmp(pred)) {
4670 return gen_Proj_Cmp(node);
4671 } else if (get_irn_op(pred) == op_Start) {
4672 if (proj == pn_Start_X_initial_exec) {
4673 ir_node *block = get_nodes_block(pred);
4676 /* we exchange the ProjX with a jump */
4677 block = be_transform_node(block);
4678 jump = new_rd_Jmp(dbgi, irg, block);
4681 if (node == be_get_old_anchor(anchor_tls)) {
4682 return gen_Proj_tls(node);
4685 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4689 ir_node *new_pred = be_transform_node(pred);
4690 ir_node *block = be_transform_node(get_nodes_block(node));
4691 ir_mode *mode = get_irn_mode(node);
4692 if (mode_needs_gp_reg(mode)) {
4693 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4694 get_Proj_proj(node));
4695 #ifdef DEBUG_libfirm
4696 new_proj->node_nr = node->node_nr;
4702 return be_duplicate_node(node);
4706 * Enters all transform functions into the generic pointer
4708 static void register_transformers(void)
4712 /* first clear the generic function pointer for all ops */
4713 clear_irp_opcodes_generic_func();
4715 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4716 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4754 /* transform ops from intrinsic lowering */
4770 GEN(ia32_l_X87toSSE);
4771 GEN(ia32_l_SSEtoX87);
4777 /* we should never see these nodes */
4792 /* handle generic backend nodes */
4801 op_Mulh = get_op_Mulh();
4810 * Pre-transform all unknown and noreg nodes.
4812 static void ia32_pretransform_node(void *arch_cg) {
4813 ia32_code_gen_t *cg = arch_cg;
4815 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4816 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4817 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4818 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4819 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4820 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4825 * Walker, checks if all ia32 nodes producing more than one result have
4826 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4828 static void add_missing_keep_walker(ir_node *node, void *data)
4831 unsigned found_projs = 0;
4832 const ir_edge_t *edge;
4833 ir_mode *mode = get_irn_mode(node);
4838 if(!is_ia32_irn(node))
4841 n_outs = get_ia32_n_res(node);
4844 if(is_ia32_SwitchJmp(node))
4847 assert(n_outs < (int) sizeof(unsigned) * 8);
4848 foreach_out_edge(node, edge) {
4849 ir_node *proj = get_edge_src_irn(edge);
4850 int pn = get_Proj_proj(proj);
4852 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4853 found_projs |= 1 << pn;
4857 /* are keeps missing? */
4859 for(i = 0; i < n_outs; ++i) {
4862 const arch_register_req_t *req;
4863 const arch_register_class_t *class;
4865 if(found_projs & (1 << i)) {
4869 req = get_ia32_out_req(node, i);
4874 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4878 block = get_nodes_block(node);
4879 in[0] = new_r_Proj(current_ir_graph, block, node,
4880 arch_register_class_mode(class), i);
4881 if(last_keep != NULL) {
4882 be_Keep_add_node(last_keep, class, in[0]);
4884 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4885 if(sched_is_scheduled(node)) {
4886 sched_add_after(node, last_keep);
4893 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4896 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4898 ir_graph *irg = be_get_birg_irg(cg->birg);
4899 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4902 /* do the transformation */
4903 void ia32_transform_graph(ia32_code_gen_t *cg) {
4905 ir_graph *irg = cg->irg;
4907 register_transformers();
4909 initial_fpcw = NULL;
4911 heights = heights_new(irg);
4912 ia32_calculate_non_address_mode_nodes(cg->birg);
4914 /* the transform phase is not safe for CSE (yet) because several nodes get
4915 * attributes set after their creation */
4916 cse_last = get_opt_cse();
4919 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4921 set_opt_cse(cse_last);
4923 ia32_free_non_address_mode_nodes();
4924 heights_free(heights);
4928 void ia32_init_transform(void)
4930 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");