2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative : 1;
516 unsigned ins_permuted : 1;
519 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
523 /* construct load address */
524 memset(addr, 0, sizeof(addr[0]));
525 ia32_create_address_mode(addr, ptr, /*force=*/0);
527 if(addr->base == NULL) {
528 addr->base = noreg_gp;
530 addr->base = be_transform_node(addr->base);
533 if(addr->index == NULL) {
534 addr->index = noreg_gp;
536 addr->index = be_transform_node(addr->index);
538 addr->mem = be_transform_node(mem);
541 static void build_address(ia32_address_mode_t *am, ir_node *node)
543 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
544 ia32_address_t *addr = &am->addr;
553 ir_entity *entity = create_float_const_entity(node);
554 addr->base = noreg_gp;
555 addr->index = noreg_gp;
556 addr->mem = new_NoMem();
557 addr->symconst_ent = entity;
559 am->ls_mode = get_irn_mode(node);
560 am->pinned = op_pin_state_floats;
564 load = get_Proj_pred(node);
565 ptr = get_Load_ptr(load);
566 mem = get_Load_mem(load);
567 new_mem = be_transform_node(mem);
568 am->pinned = get_irn_pinned(load);
569 am->ls_mode = get_Load_mode(load);
570 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
572 /* construct load address */
573 ia32_create_address_mode(addr, ptr, /*force=*/0);
580 base = be_transform_node(base);
586 index = be_transform_node(index);
594 static void set_address(ir_node *node, const ia32_address_t *addr)
596 set_ia32_am_scale(node, addr->scale);
597 set_ia32_am_sc(node, addr->symconst_ent);
598 set_ia32_am_offs_int(node, addr->offset);
599 if(addr->symconst_sign)
600 set_ia32_am_sc_sign(node);
602 set_ia32_use_frame(node);
603 set_ia32_frame_ent(node, addr->frame_entity);
606 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
608 set_address(node, &am->addr);
610 set_ia32_op_type(node, am->op_type);
611 set_ia32_ls_mode(node, am->ls_mode);
612 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
613 set_irn_pinned(node, am->pinned);
616 set_ia32_commutative(node);
620 * Check, if a given node is a Down-Conv, ie. a integer Conv
621 * from a mode with a mode with more bits to a mode with lesser bits.
622 * Moreover, we return only true if the node has not more than 1 user.
624 * @param node the node
625 * @return non-zero if node is a Down-Conv
627 static int is_downconv(const ir_node *node)
635 /* we only want to skip the conv when we're the only user
636 * (not optimal but for now...)
638 if(get_irn_n_edges(node) > 1)
641 src_mode = get_irn_mode(get_Conv_op(node));
642 dest_mode = get_irn_mode(node);
643 return mode_needs_gp_reg(src_mode)
644 && mode_needs_gp_reg(dest_mode)
645 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
648 /* Skip all Down-Conv's on a given node and return the resulting node. */
649 ir_node *ia32_skip_downconv(ir_node *node) {
650 while (is_downconv(node))
651 node = get_Conv_op(node);
657 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
659 ir_mode *mode = get_irn_mode(node);
664 if(mode_is_signed(mode)) {
669 block = get_nodes_block(node);
670 dbgi = get_irn_dbg_info(node);
672 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
676 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
677 ir_node *op1, ir_node *op2, match_flags_t flags)
679 ia32_address_t *addr = &am->addr;
680 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
683 ir_mode *mode = get_irn_mode(op2);
685 unsigned commutative;
686 int use_am_and_immediates;
688 int mode_bits = get_mode_size_bits(mode);
690 memset(am, 0, sizeof(am[0]));
692 commutative = (flags & match_commutative) != 0;
693 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
694 use_am = (flags & match_am) != 0;
695 use_immediate = (flags & match_immediate) != 0;
696 assert(!use_am_and_immediates || use_immediate);
699 assert(!commutative || op1 != NULL);
702 if (! (flags & match_8bit_am))
704 assert((flags & match_mode_neutral) || (flags & match_8bit));
705 } else if(mode_bits == 16) {
706 if(! (flags & match_16bit_am))
708 assert((flags & match_mode_neutral) || (flags & match_16bit));
711 /* we can simply skip downconvs for mode neutral nodes: the upper bits
712 * can be random for these operations */
713 if(flags & match_mode_neutral) {
714 op2 = ia32_skip_downconv(op2);
716 op1 = ia32_skip_downconv(op1);
720 if(! (flags & match_try_am) && use_immediate)
721 new_op2 = try_create_Immediate(op2, 0);
725 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
726 build_address(am, op2);
727 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
728 if(mode_is_float(mode)) {
729 new_op2 = ia32_new_NoReg_vfp(env_cg);
733 am->op_type = ia32_AddrModeS;
734 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
735 use_am && ia32_use_source_address_mode(block, op1, op2)) {
737 build_address(am, op1);
739 if(mode_is_float(mode)) {
740 noreg = ia32_new_NoReg_vfp(env_cg);
745 if(new_op2 != NULL) {
748 new_op1 = be_transform_node(op2);
750 am->ins_permuted = 1;
752 am->op_type = ia32_AddrModeS;
754 if(flags & match_try_am) {
757 am->op_type = ia32_Normal;
761 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
763 new_op2 = be_transform_node(op2);
764 am->op_type = ia32_Normal;
765 am->ls_mode = get_irn_mode(op2);
766 if(flags & match_mode_neutral)
767 am->ls_mode = mode_Iu;
769 if(addr->base == NULL)
770 addr->base = noreg_gp;
771 if(addr->index == NULL)
772 addr->index = noreg_gp;
773 if(addr->mem == NULL)
774 addr->mem = new_NoMem();
776 am->new_op1 = new_op1;
777 am->new_op2 = new_op2;
778 am->commutative = commutative;
781 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
783 ir_graph *irg = current_ir_graph;
787 if(am->mem_proj == NULL)
790 /* we have to create a mode_T so the old MemProj can attach to us */
791 mode = get_irn_mode(node);
792 load = get_Proj_pred(am->mem_proj);
794 mark_irn_visited(load);
795 be_set_transformed_node(load, node);
798 set_irn_mode(node, mode_T);
799 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
806 * Construct a standard binary operation, set AM and immediate if required.
808 * @param op1 The first operand
809 * @param op2 The second operand
810 * @param func The node constructor function
811 * @return The constructed ia32 node.
813 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
814 construct_binop_func *func, match_flags_t flags)
816 ir_node *block = get_nodes_block(node);
817 ir_node *new_block = be_transform_node(block);
818 ir_graph *irg = current_ir_graph;
819 dbg_info *dbgi = get_irn_dbg_info(node);
821 ia32_address_mode_t am;
822 ia32_address_t *addr = &am.addr;
824 match_arguments(&am, block, op1, op2, flags);
826 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
827 am.new_op1, am.new_op2);
828 set_am_attributes(new_node, &am);
829 /* we can't use source address mode anymore when using immediates */
830 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
831 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
832 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
834 new_node = fix_mem_proj(new_node, &am);
841 n_ia32_l_binop_right,
842 n_ia32_l_binop_eflags
844 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
845 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
846 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
847 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
848 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
849 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
852 * Construct a binary operation which also consumes the eflags.
854 * @param node The node to transform
855 * @param func The node constructor function
856 * @param flags The match flags
857 * @return The constructor ia32 node
859 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
862 ir_node *src_block = get_nodes_block(node);
863 ir_node *block = be_transform_node(src_block);
864 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
865 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
866 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
867 ir_node *new_eflags = be_transform_node(eflags);
868 ir_graph *irg = current_ir_graph;
869 dbg_info *dbgi = get_irn_dbg_info(node);
871 ia32_address_mode_t am;
872 ia32_address_t *addr = &am.addr;
874 match_arguments(&am, src_block, op1, op2, flags);
876 new_node = func(dbgi, irg, block, addr->base, addr->index,
877 addr->mem, am.new_op1, am.new_op2, new_eflags);
878 set_am_attributes(new_node, &am);
879 /* we can't use source address mode anymore when using immediates */
880 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
881 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
882 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
884 new_node = fix_mem_proj(new_node, &am);
889 static ir_node *get_fpcw(void)
892 if(initial_fpcw != NULL)
895 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
896 &ia32_fp_cw_regs[REG_FPCW]);
897 initial_fpcw = be_transform_node(fpcw);
903 * Construct a standard binary operation, set AM and immediate if required.
905 * @param op1 The first operand
906 * @param op2 The second operand
907 * @param func The node constructor function
908 * @return The constructed ia32 node.
910 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
911 construct_binop_float_func *func,
914 ir_graph *irg = current_ir_graph;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *block = get_nodes_block(node);
917 ir_node *new_block = be_transform_node(block);
919 ia32_address_mode_t am;
920 ia32_address_t *addr = &am.addr;
922 match_arguments(&am, block, op1, op2, flags);
924 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
925 am.new_op1, am.new_op2, get_fpcw());
926 set_am_attributes(new_node, &am);
928 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
930 new_node = fix_mem_proj(new_node, &am);
936 * Construct a shift/rotate binary operation, sets AM and immediate if required.
938 * @param op1 The first operand
939 * @param op2 The second operand
940 * @param func The node constructor function
941 * @return The constructed ia32 node.
943 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
944 construct_shift_func *func,
947 dbg_info *dbgi = get_irn_dbg_info(node);
948 ir_graph *irg = current_ir_graph;
949 ir_node *block = get_nodes_block(node);
950 ir_node *new_block = be_transform_node(block);
951 ir_mode *mode = get_irn_mode(node);
956 assert(! mode_is_float(mode));
957 assert(flags & match_immediate);
958 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
960 if(flags & match_mode_neutral) {
961 op1 = ia32_skip_downconv(op1);
963 new_op1 = be_transform_node(op1);
965 /* the shift amount can be any mode that is bigger than 5 bits, since all
966 * other bits are ignored anyway */
967 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
968 op2 = get_Conv_op(op2);
969 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
971 new_op2 = create_immediate_or_transform(op2, 0);
973 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
974 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
976 /* lowered shift instruction may have a dependency operand, handle it here */
977 if (get_irn_arity(node) == 3) {
978 /* we have a dependency */
979 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
980 add_irn_dep(new_node, new_dep);
988 * Construct a standard unary operation, set AM and immediate if required.
990 * @param op The operand
991 * @param func The node constructor function
992 * @return The constructed ia32 node.
994 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
997 ir_graph *irg = current_ir_graph;
998 dbg_info *dbgi = get_irn_dbg_info(node);
999 ir_node *block = get_nodes_block(node);
1000 ir_node *new_block = be_transform_node(block);
1004 assert(flags == 0 || flags == match_mode_neutral);
1005 if(flags & match_mode_neutral) {
1006 op = ia32_skip_downconv(op);
1009 new_op = be_transform_node(op);
1010 new_node = func(dbgi, irg, new_block, new_op);
1012 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1017 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1018 ia32_address_t *addr)
1020 ir_graph *irg = current_ir_graph;
1021 ir_node *base = addr->base;
1022 ir_node *index = addr->index;
1026 base = ia32_new_NoReg_gp(env_cg);
1028 base = be_transform_node(base);
1032 index = ia32_new_NoReg_gp(env_cg);
1034 index = be_transform_node(index);
1037 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1038 set_address(res, addr);
1043 static int am_has_immediates(const ia32_address_t *addr)
1045 return addr->offset != 0 || addr->symconst_ent != NULL
1046 || addr->frame_entity || addr->use_frame;
1050 * Creates an ia32 Add.
1052 * @return the created ia32 Add node
1054 static ir_node *gen_Add(ir_node *node) {
1055 ir_graph *irg = current_ir_graph;
1056 dbg_info *dbgi = get_irn_dbg_info(node);
1057 ir_node *block = get_nodes_block(node);
1058 ir_node *new_block = be_transform_node(block);
1059 ir_node *op1 = get_Add_left(node);
1060 ir_node *op2 = get_Add_right(node);
1061 ir_mode *mode = get_irn_mode(node);
1063 ir_node *add_immediate_op;
1064 ia32_address_t addr;
1065 ia32_address_mode_t am;
1067 if (mode_is_float(mode)) {
1068 if (USE_SSE2(env_cg))
1069 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1070 match_commutative | match_am);
1072 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1073 match_commutative | match_am);
1076 ia32_mark_non_am(node);
1078 op2 = ia32_skip_downconv(op2);
1079 op1 = ia32_skip_downconv(op1);
1083 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1084 * 1. Add with immediate -> Lea
1085 * 2. Add with possible source address mode -> Add
1086 * 3. Otherwise -> Lea
1088 memset(&addr, 0, sizeof(addr));
1089 ia32_create_address_mode(&addr, node, /*force=*/1);
1090 add_immediate_op = NULL;
1092 if(addr.base == NULL && addr.index == NULL) {
1093 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1094 addr.symconst_sign, addr.offset);
1095 add_irn_dep(new_node, get_irg_frame(irg));
1096 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1099 /* add with immediate? */
1100 if(addr.index == NULL) {
1101 add_immediate_op = addr.base;
1102 } else if(addr.base == NULL && addr.scale == 0) {
1103 add_immediate_op = addr.index;
1106 if(add_immediate_op != NULL) {
1107 if(!am_has_immediates(&addr)) {
1108 #ifdef DEBUG_libfirm
1109 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1112 return be_transform_node(add_immediate_op);
1115 new_node = create_lea_from_address(dbgi, new_block, &addr);
1116 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1120 /* test if we can use source address mode */
1121 match_arguments(&am, block, op1, op2, match_commutative
1122 | match_mode_neutral | match_am | match_immediate | match_try_am);
1124 /* construct an Add with source address mode */
1125 if (am.op_type == ia32_AddrModeS) {
1126 ia32_address_t *am_addr = &am.addr;
1127 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1128 am_addr->index, am_addr->mem, am.new_op1,
1130 set_am_attributes(new_node, &am);
1131 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1133 new_node = fix_mem_proj(new_node, &am);
1138 /* otherwise construct a lea */
1139 new_node = create_lea_from_address(dbgi, new_block, &addr);
1140 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1145 * Creates an ia32 Mul.
1147 * @return the created ia32 Mul node
1149 static ir_node *gen_Mul(ir_node *node) {
1150 ir_node *op1 = get_Mul_left(node);
1151 ir_node *op2 = get_Mul_right(node);
1152 ir_mode *mode = get_irn_mode(node);
1154 if (mode_is_float(mode)) {
1155 if (USE_SSE2(env_cg))
1156 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1157 match_commutative | match_am);
1159 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1160 match_commutative | match_am);
1164 for the lower 32bit of the result it doesn't matter whether we use
1165 signed or unsigned multiplication so we use IMul as it has fewer
1168 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1169 match_commutative | match_am | match_mode_neutral |
1170 match_immediate | match_am_and_immediates);
1174 * Creates an ia32 Mulh.
1175 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1176 * this result while Mul returns the lower 32 bit.
1178 * @return the created ia32 Mulh node
1180 static ir_node *gen_Mulh(ir_node *node)
1182 ir_node *block = get_nodes_block(node);
1183 ir_node *new_block = be_transform_node(block);
1184 ir_graph *irg = current_ir_graph;
1185 dbg_info *dbgi = get_irn_dbg_info(node);
1186 ir_mode *mode = get_irn_mode(node);
1187 ir_node *op1 = get_Mulh_left(node);
1188 ir_node *op2 = get_Mulh_right(node);
1191 match_flags_t flags;
1192 ia32_address_mode_t am;
1193 ia32_address_t *addr = &am.addr;
1195 flags = match_commutative | match_am;
1197 assert(!mode_is_float(mode) && "Mulh with float not supported");
1198 assert(get_mode_size_bits(mode) == 32);
1200 match_arguments(&am, block, op1, op2, flags);
1202 if (mode_is_signed(mode)) {
1203 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1204 addr->index, addr->mem, am.new_op1,
1207 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1208 addr->index, addr->mem, am.new_op1,
1212 set_am_attributes(new_node, &am);
1213 /* we can't use source address mode anymore when using immediates */
1214 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1215 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1216 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1218 assert(get_irn_mode(new_node) == mode_T);
1220 fix_mem_proj(new_node, &am);
1222 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1223 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1224 mode_Iu, pn_ia32_IMul1OP_EDX);
1232 * Creates an ia32 And.
1234 * @return The created ia32 And node
1236 static ir_node *gen_And(ir_node *node) {
1237 ir_node *op1 = get_And_left(node);
1238 ir_node *op2 = get_And_right(node);
1239 assert(! mode_is_float(get_irn_mode(node)));
1241 /* is it a zero extension? */
1242 if (is_Const(op2)) {
1243 tarval *tv = get_Const_tarval(op2);
1244 long v = get_tarval_long(tv);
1246 if (v == 0xFF || v == 0xFFFF) {
1247 dbg_info *dbgi = get_irn_dbg_info(node);
1248 ir_node *block = get_nodes_block(node);
1255 assert(v == 0xFFFF);
1258 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1264 return gen_binop(node, op1, op2, new_rd_ia32_And,
1265 match_commutative | match_mode_neutral | match_am
1272 * Creates an ia32 Or.
1274 * @return The created ia32 Or node
1276 static ir_node *gen_Or(ir_node *node) {
1277 ir_node *op1 = get_Or_left(node);
1278 ir_node *op2 = get_Or_right(node);
1280 assert (! mode_is_float(get_irn_mode(node)));
1281 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1282 | match_mode_neutral | match_am | match_immediate);
1288 * Creates an ia32 Eor.
1290 * @return The created ia32 Eor node
1292 static ir_node *gen_Eor(ir_node *node) {
1293 ir_node *op1 = get_Eor_left(node);
1294 ir_node *op2 = get_Eor_right(node);
1296 assert(! mode_is_float(get_irn_mode(node)));
1297 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1298 | match_mode_neutral | match_am | match_immediate);
1303 * Creates an ia32 Sub.
1305 * @return The created ia32 Sub node
1307 static ir_node *gen_Sub(ir_node *node) {
1308 ir_node *op1 = get_Sub_left(node);
1309 ir_node *op2 = get_Sub_right(node);
1310 ir_mode *mode = get_irn_mode(node);
1312 if (mode_is_float(mode)) {
1313 if (USE_SSE2(env_cg))
1314 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1316 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1321 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1325 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1326 | match_am | match_immediate);
1330 * Generates an ia32 DivMod with additional infrastructure for the
1331 * register allocator if needed.
1333 static ir_node *create_Div(ir_node *node)
1335 ir_graph *irg = current_ir_graph;
1336 dbg_info *dbgi = get_irn_dbg_info(node);
1337 ir_node *block = get_nodes_block(node);
1338 ir_node *new_block = be_transform_node(block);
1345 ir_node *sign_extension;
1347 ia32_address_mode_t am;
1348 ia32_address_t *addr = &am.addr;
1350 /* the upper bits have random contents for smaller modes */
1352 switch (get_irn_opcode(node)) {
1354 op1 = get_Div_left(node);
1355 op2 = get_Div_right(node);
1356 mem = get_Div_mem(node);
1357 mode = get_Div_resmode(node);
1358 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1361 op1 = get_Mod_left(node);
1362 op2 = get_Mod_right(node);
1363 mem = get_Mod_mem(node);
1364 mode = get_Mod_resmode(node);
1365 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1368 op1 = get_DivMod_left(node);
1369 op2 = get_DivMod_right(node);
1370 mem = get_DivMod_mem(node);
1371 mode = get_DivMod_resmode(node);
1372 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1375 panic("invalid divmod node %+F", node);
1378 match_arguments(&am, block, op1, op2, match_am);
1380 if(!is_NoMem(mem)) {
1381 new_mem = be_transform_node(mem);
1382 if(!is_NoMem(addr->mem)) {
1386 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1389 new_mem = addr->mem;
1392 if (mode_is_signed(mode)) {
1393 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1394 add_irn_dep(produceval, get_irg_frame(irg));
1395 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1398 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1399 addr->index, new_mem, am.new_op1,
1400 sign_extension, am.new_op2);
1402 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1403 add_irn_dep(sign_extension, get_irg_frame(irg));
1405 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1406 addr->index, new_mem, am.new_op1,
1407 sign_extension, am.new_op2);
1410 set_ia32_exc_label(new_node, has_exc);
1411 set_irn_pinned(new_node, get_irn_pinned(node));
1413 set_am_attributes(new_node, &am);
1414 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1416 new_node = fix_mem_proj(new_node, &am);
1422 static ir_node *gen_Mod(ir_node *node) {
1423 return create_Div(node);
1426 static ir_node *gen_Div(ir_node *node) {
1427 return create_Div(node);
1430 static ir_node *gen_DivMod(ir_node *node) {
1431 return create_Div(node);
1437 * Creates an ia32 floating Div.
1439 * @return The created ia32 xDiv node
1441 static ir_node *gen_Quot(ir_node *node)
1443 ir_node *op1 = get_Quot_left(node);
1444 ir_node *op2 = get_Quot_right(node);
1446 if (USE_SSE2(env_cg)) {
1447 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1449 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1455 * Creates an ia32 Shl.
1457 * @return The created ia32 Shl node
1459 static ir_node *gen_Shl(ir_node *node) {
1460 ir_node *left = get_Shl_left(node);
1461 ir_node *right = get_Shl_right(node);
1463 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1464 match_mode_neutral | match_immediate);
1468 * Creates an ia32 Shr.
1470 * @return The created ia32 Shr node
1472 static ir_node *gen_Shr(ir_node *node) {
1473 ir_node *left = get_Shr_left(node);
1474 ir_node *right = get_Shr_right(node);
1476 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1482 * Creates an ia32 Sar.
1484 * @return The created ia32 Shrs node
1486 static ir_node *gen_Shrs(ir_node *node) {
1487 ir_node *left = get_Shrs_left(node);
1488 ir_node *right = get_Shrs_right(node);
1489 ir_mode *mode = get_irn_mode(node);
1491 if(is_Const(right) && mode == mode_Is) {
1492 tarval *tv = get_Const_tarval(right);
1493 long val = get_tarval_long(tv);
1495 /* this is a sign extension */
1496 ir_graph *irg = current_ir_graph;
1497 dbg_info *dbgi = get_irn_dbg_info(node);
1498 ir_node *block = be_transform_node(get_nodes_block(node));
1500 ir_node *new_op = be_transform_node(op);
1501 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1502 add_irn_dep(pval, get_irg_frame(irg));
1504 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1508 /* 8 or 16 bit sign extension? */
1509 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1510 ir_node *shl_left = get_Shl_left(left);
1511 ir_node *shl_right = get_Shl_right(left);
1512 if(is_Const(shl_right)) {
1513 tarval *tv1 = get_Const_tarval(right);
1514 tarval *tv2 = get_Const_tarval(shl_right);
1515 if(tv1 == tv2 && tarval_is_long(tv1)) {
1516 long val = get_tarval_long(tv1);
1517 if(val == 16 || val == 24) {
1518 dbg_info *dbgi = get_irn_dbg_info(node);
1519 ir_node *block = get_nodes_block(node);
1529 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1538 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1544 * Creates an ia32 RotL.
1546 * @param op1 The first operator
1547 * @param op2 The second operator
1548 * @return The created ia32 RotL node
1550 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1551 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1557 * Creates an ia32 RotR.
1558 * NOTE: There is no RotR with immediate because this would always be a RotL
1559 * "imm-mode_size_bits" which can be pre-calculated.
1561 * @param op1 The first operator
1562 * @param op2 The second operator
1563 * @return The created ia32 RotR node
1565 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1566 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1572 * Creates an ia32 RotR or RotL (depending on the found pattern).
1574 * @return The created ia32 RotL or RotR node
1576 static ir_node *gen_Rot(ir_node *node) {
1577 ir_node *rotate = NULL;
1578 ir_node *op1 = get_Rot_left(node);
1579 ir_node *op2 = get_Rot_right(node);
1581 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1582 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1583 that means we can create a RotR instead of an Add and a RotL */
1585 if (get_irn_op(op2) == op_Add) {
1587 ir_node *left = get_Add_left(add);
1588 ir_node *right = get_Add_right(add);
1589 if (is_Const(right)) {
1590 tarval *tv = get_Const_tarval(right);
1591 ir_mode *mode = get_irn_mode(node);
1592 long bits = get_mode_size_bits(mode);
1594 if (get_irn_op(left) == op_Minus &&
1595 tarval_is_long(tv) &&
1596 get_tarval_long(tv) == bits &&
1599 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1600 rotate = gen_RotR(node, op1, get_Minus_op(left));
1605 if (rotate == NULL) {
1606 rotate = gen_RotL(node, op1, op2);
1615 * Transforms a Minus node.
1617 * @return The created ia32 Minus node
1619 static ir_node *gen_Minus(ir_node *node)
1621 ir_node *op = get_Minus_op(node);
1622 ir_node *block = be_transform_node(get_nodes_block(node));
1623 ir_graph *irg = current_ir_graph;
1624 dbg_info *dbgi = get_irn_dbg_info(node);
1625 ir_mode *mode = get_irn_mode(node);
1630 if (mode_is_float(mode)) {
1631 ir_node *new_op = be_transform_node(op);
1632 if (USE_SSE2(env_cg)) {
1633 /* TODO: non-optimal... if we have many xXors, then we should
1634 * rather create a load for the const and use that instead of
1635 * several AM nodes... */
1636 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1637 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1638 ir_node *nomem = new_rd_NoMem(irg);
1640 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1641 nomem, new_op, noreg_xmm);
1643 size = get_mode_size_bits(mode);
1644 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1646 set_ia32_am_sc(new_node, ent);
1647 set_ia32_op_type(new_node, ia32_AddrModeS);
1648 set_ia32_ls_mode(new_node, mode);
1650 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1653 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1656 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1662 * Transforms a Not node.
1664 * @return The created ia32 Not node
1666 static ir_node *gen_Not(ir_node *node) {
1667 ir_node *op = get_Not_op(node);
1669 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1670 assert (! mode_is_float(get_irn_mode(node)));
1672 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1678 * Transforms an Abs node.
1680 * @return The created ia32 Abs node
1682 static ir_node *gen_Abs(ir_node *node)
1684 ir_node *block = be_transform_node(get_nodes_block(node));
1685 ir_node *op = get_Abs_op(node);
1686 ir_node *new_op = be_transform_node(op);
1687 ir_graph *irg = current_ir_graph;
1688 dbg_info *dbgi = get_irn_dbg_info(node);
1689 ir_mode *mode = get_irn_mode(node);
1690 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1691 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1692 ir_node *nomem = new_NoMem();
1697 if (mode_is_float(mode)) {
1698 if (USE_SSE2(env_cg)) {
1699 new_node = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp,
1700 nomem, new_op, noreg_fp);
1702 size = get_mode_size_bits(mode);
1703 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1705 set_ia32_am_sc(new_node, ent);
1707 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1709 set_ia32_op_type(new_node, ia32_AddrModeS);
1710 set_ia32_ls_mode(new_node, mode);
1712 new_node = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1713 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1717 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1718 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1721 assert(get_mode_size_bits(mode) == 32);
1723 add_irn_dep(pval, get_irg_frame(irg));
1724 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1726 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1727 new_op, sign_extension);
1728 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1730 new_node = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1731 xor, sign_extension);
1732 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1738 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1740 ir_graph *irg = current_ir_graph;
1748 /* we have a Cmp as input */
1750 ir_node *pred = get_Proj_pred(node);
1752 flags = be_transform_node(pred);
1753 *pnc_out = get_Proj_proj(node);
1758 /* a mode_b value, we have to compare it against 0 */
1759 dbgi = get_irn_dbg_info(node);
1760 new_block = be_transform_node(get_nodes_block(node));
1761 new_op = be_transform_node(node);
1762 noreg = ia32_new_NoReg_gp(env_cg);
1763 nomem = new_NoMem();
1764 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1765 new_op, new_op, 0, 0);
1766 *pnc_out = pn_Cmp_Lg;
1771 * Transforms a Load.
1773 * @return the created ia32 Load node
1775 static ir_node *gen_Load(ir_node *node) {
1776 ir_node *old_block = get_nodes_block(node);
1777 ir_node *block = be_transform_node(old_block);
1778 ir_node *ptr = get_Load_ptr(node);
1779 ir_node *mem = get_Load_mem(node);
1780 ir_node *new_mem = be_transform_node(mem);
1783 ir_graph *irg = current_ir_graph;
1784 dbg_info *dbgi = get_irn_dbg_info(node);
1785 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1786 ir_mode *mode = get_Load_mode(node);
1789 ia32_address_t addr;
1791 /* construct load address */
1792 memset(&addr, 0, sizeof(addr));
1793 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1800 base = be_transform_node(base);
1806 index = be_transform_node(index);
1809 if (mode_is_float(mode)) {
1810 if (USE_SSE2(env_cg)) {
1811 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1813 res_mode = mode_xmm;
1815 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1817 res_mode = mode_vfp;
1820 assert(mode != mode_b);
1822 /* create a conv node with address mode for smaller modes */
1823 if(get_mode_size_bits(mode) < 32) {
1824 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1825 new_mem, noreg, mode);
1827 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1832 set_irn_pinned(new_node, get_irn_pinned(node));
1833 set_ia32_op_type(new_node, ia32_AddrModeS);
1834 set_ia32_ls_mode(new_node, mode);
1835 set_address(new_node, &addr);
1837 /* make sure we are scheduled behind the initial IncSP/Barrier
1838 * to avoid spills being placed before it
1840 if (block == get_irg_start_block(irg)) {
1841 add_irn_dep(new_node, get_irg_frame(irg));
1844 set_ia32_exc_label(new_node,
1845 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1846 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1851 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1852 ir_node *ptr, ir_node *other)
1859 /* we only use address mode if we're the only user of the load */
1860 if(get_irn_n_edges(node) > 1)
1863 load = get_Proj_pred(node);
1866 if(get_nodes_block(load) != block)
1869 /* Store should be attached to the load */
1870 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1872 /* store should have the same pointer as the load */
1873 if(get_Load_ptr(load) != ptr)
1876 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1877 if(other != NULL && get_nodes_block(other) == block
1878 && heights_reachable_in_block(heights, other, load))
1884 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1885 ir_node *mem, ir_node *ptr, ir_mode *mode,
1886 construct_binop_dest_func *func,
1887 construct_binop_dest_func *func8bit,
1888 match_flags_t flags)
1890 ir_node *src_block = get_nodes_block(node);
1892 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1893 ir_graph *irg = current_ir_graph;
1898 ia32_address_mode_t am;
1899 ia32_address_t *addr = &am.addr;
1900 memset(&am, 0, sizeof(am));
1902 assert(flags & match_dest_am);
1903 assert(flags & match_immediate); /* there is no destam node without... */
1904 commutative = (flags & match_commutative) != 0;
1906 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1907 build_address(&am, op1);
1908 new_op = create_immediate_or_transform(op2, 0);
1909 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1910 build_address(&am, op2);
1911 new_op = create_immediate_or_transform(op1, 0);
1916 if(addr->base == NULL)
1917 addr->base = noreg_gp;
1918 if(addr->index == NULL)
1919 addr->index = noreg_gp;
1920 if(addr->mem == NULL)
1921 addr->mem = new_NoMem();
1923 dbgi = get_irn_dbg_info(node);
1924 block = be_transform_node(src_block);
1925 if(get_mode_size_bits(mode) == 8) {
1926 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1929 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1932 set_address(new_node, addr);
1933 set_ia32_op_type(new_node, ia32_AddrModeD);
1934 set_ia32_ls_mode(new_node, mode);
1935 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1940 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1941 ir_node *ptr, ir_mode *mode,
1942 construct_unop_dest_func *func)
1944 ir_graph *irg = current_ir_graph;
1945 ir_node *src_block = get_nodes_block(node);
1949 ia32_address_mode_t am;
1950 ia32_address_t *addr = &am.addr;
1951 memset(&am, 0, sizeof(am));
1953 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1956 build_address(&am, op);
1958 dbgi = get_irn_dbg_info(node);
1959 block = be_transform_node(src_block);
1960 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1961 set_address(new_node, addr);
1962 set_ia32_op_type(new_node, ia32_AddrModeD);
1963 set_ia32_ls_mode(new_node, mode);
1964 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1969 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1970 ir_mode *mode = get_irn_mode(node);
1971 ir_node *psi_true = get_Psi_val(node, 0);
1972 ir_node *psi_default = get_Psi_default(node);
1983 ia32_address_t addr;
1985 if(get_mode_size_bits(mode) != 8)
1988 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1990 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1996 build_address_ptr(&addr, ptr, mem);
1998 irg = current_ir_graph;
1999 dbgi = get_irn_dbg_info(node);
2000 block = get_nodes_block(node);
2001 new_block = be_transform_node(block);
2002 cond = get_Psi_cond(node, 0);
2003 flags = get_flags_node(cond, &pnc);
2004 new_mem = be_transform_node(mem);
2005 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2006 addr.index, addr.mem, flags, pnc, negated);
2007 set_address(new_node, &addr);
2008 set_ia32_op_type(new_node, ia32_AddrModeD);
2009 set_ia32_ls_mode(new_node, mode);
2010 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2015 static ir_node *try_create_dest_am(ir_node *node) {
2016 ir_node *val = get_Store_value(node);
2017 ir_node *mem = get_Store_mem(node);
2018 ir_node *ptr = get_Store_ptr(node);
2019 ir_mode *mode = get_irn_mode(val);
2020 int bits = get_mode_size_bits(mode);
2025 /* handle only GP modes for now... */
2026 if(!mode_needs_gp_reg(mode))
2030 /* store must be the only user of the val node */
2031 if(get_irn_n_edges(val) > 1)
2033 /* skip pointless convs */
2035 ir_node *conv_op = get_Conv_op(val);
2036 ir_mode *pred_mode = get_irn_mode(conv_op);
2037 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2045 /* value must be in the same block */
2046 if(get_nodes_block(node) != get_nodes_block(val))
2049 switch(get_irn_opcode(val)) {
2051 op1 = get_Add_left(val);
2052 op2 = get_Add_right(val);
2053 if(is_Const_1(op2)) {
2054 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2055 new_rd_ia32_IncMem);
2057 } else if(is_Const_Minus_1(op2)) {
2058 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2059 new_rd_ia32_DecMem);
2062 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2063 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2064 match_dest_am | match_commutative |
2068 op1 = get_Sub_left(val);
2069 op2 = get_Sub_right(val);
2071 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2074 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2075 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2076 match_dest_am | match_immediate |
2080 op1 = get_And_left(val);
2081 op2 = get_And_right(val);
2082 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2083 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2084 match_dest_am | match_commutative |
2088 op1 = get_Or_left(val);
2089 op2 = get_Or_right(val);
2090 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2091 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2092 match_dest_am | match_commutative |
2096 op1 = get_Eor_left(val);
2097 op2 = get_Eor_right(val);
2098 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2099 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2100 match_dest_am | match_commutative |
2104 op1 = get_Shl_left(val);
2105 op2 = get_Shl_right(val);
2106 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2107 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2108 match_dest_am | match_immediate);
2111 op1 = get_Shr_left(val);
2112 op2 = get_Shr_right(val);
2113 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2114 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2115 match_dest_am | match_immediate);
2118 op1 = get_Shrs_left(val);
2119 op2 = get_Shrs_right(val);
2120 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2121 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2122 match_dest_am | match_immediate);
2125 op1 = get_Rot_left(val);
2126 op2 = get_Rot_right(val);
2127 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2128 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2129 match_dest_am | match_immediate);
2131 /* TODO: match ROR patterns... */
2133 new_node = try_create_SetMem(val, ptr, mem);
2136 op1 = get_Minus_op(val);
2137 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2140 /* should be lowered already */
2141 assert(mode != mode_b);
2142 op1 = get_Not_op(val);
2143 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2149 if(new_node != NULL) {
2150 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2151 get_irn_pinned(node) == op_pin_state_pinned) {
2152 set_irn_pinned(new_node, op_pin_state_pinned);
2159 static int is_float_to_int32_conv(const ir_node *node)
2161 ir_mode *mode = get_irn_mode(node);
2165 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2170 conv_op = get_Conv_op(node);
2171 conv_mode = get_irn_mode(conv_op);
2173 if(!mode_is_float(conv_mode))
2180 * Transforms a Store.
2182 * @return the created ia32 Store node
2184 static ir_node *gen_Store(ir_node *node)
2186 ir_node *block = get_nodes_block(node);
2187 ir_node *new_block = be_transform_node(block);
2188 ir_node *ptr = get_Store_ptr(node);
2189 ir_node *val = get_Store_value(node);
2190 ir_node *mem = get_Store_mem(node);
2191 ir_graph *irg = current_ir_graph;
2192 dbg_info *dbgi = get_irn_dbg_info(node);
2193 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2194 ir_mode *mode = get_irn_mode(val);
2197 ia32_address_t addr;
2199 /* check for destination address mode */
2200 new_node = try_create_dest_am(node);
2201 if(new_node != NULL)
2204 /* construct store address */
2205 memset(&addr, 0, sizeof(addr));
2206 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2208 if(addr.base == NULL) {
2211 addr.base = be_transform_node(addr.base);
2214 if(addr.index == NULL) {
2217 addr.index = be_transform_node(addr.index);
2219 addr.mem = be_transform_node(mem);
2221 if (mode_is_float(mode)) {
2222 /* convs (and strict-convs) before stores are unnecessary if the mode
2224 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2225 val = get_Conv_op(val);
2227 new_val = be_transform_node(val);
2228 if (USE_SSE2(env_cg)) {
2229 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2230 addr.index, addr.mem, new_val);
2232 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2233 addr.index, addr.mem, new_val, mode);
2235 } else if(is_float_to_int32_conv(val)) {
2236 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2237 val = get_Conv_op(val);
2239 /* convs (and strict-convs) before stores are unnecessary if the mode
2241 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2242 val = get_Conv_op(val);
2244 new_val = be_transform_node(val);
2246 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2247 addr.index, addr.mem, new_val, trunc_mode);
2249 new_val = create_immediate_or_transform(val, 0);
2250 assert(mode != mode_b);
2252 if (get_mode_size_bits(mode) == 8) {
2253 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2254 addr.index, addr.mem, new_val);
2256 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2257 addr.index, addr.mem, new_val);
2261 set_irn_pinned(new_node, get_irn_pinned(node));
2262 set_ia32_op_type(new_node, ia32_AddrModeD);
2263 set_ia32_ls_mode(new_node, mode);
2265 set_ia32_exc_label(new_node,
2266 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2267 set_address(new_node, &addr);
2268 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2273 static ir_node *create_Switch(ir_node *node)
2275 ir_graph *irg = current_ir_graph;
2276 dbg_info *dbgi = get_irn_dbg_info(node);
2277 ir_node *block = be_transform_node(get_nodes_block(node));
2278 ir_node *sel = get_Cond_selector(node);
2279 ir_node *new_sel = be_transform_node(sel);
2280 int switch_min = INT_MAX;
2282 const ir_edge_t *edge;
2284 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2286 /* determine the smallest switch case value */
2287 foreach_out_edge(node, edge) {
2288 ir_node *proj = get_edge_src_irn(edge);
2289 int pn = get_Proj_proj(proj);
2294 if (switch_min != 0) {
2295 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2297 /* if smallest switch case is not 0 we need an additional sub */
2298 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2299 add_ia32_am_offs_int(new_sel, -switch_min);
2300 set_ia32_op_type(new_sel, ia32_AddrModeS);
2302 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2305 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2306 get_Cond_defaultProj(node));
2307 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2312 static ir_node *gen_Cond(ir_node *node) {
2313 ir_node *block = get_nodes_block(node);
2314 ir_node *new_block = be_transform_node(block);
2315 ir_graph *irg = current_ir_graph;
2316 dbg_info *dbgi = get_irn_dbg_info(node);
2317 ir_node *sel = get_Cond_selector(node);
2318 ir_mode *sel_mode = get_irn_mode(sel);
2319 ir_node *flags = NULL;
2323 if (sel_mode != mode_b) {
2324 return create_Switch(node);
2327 /* we get flags from a cmp */
2328 flags = get_flags_node(sel, &pnc);
2330 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2331 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2339 * Transforms a CopyB node.
2341 * @return The transformed node.
2343 static ir_node *gen_CopyB(ir_node *node) {
2344 ir_node *block = be_transform_node(get_nodes_block(node));
2345 ir_node *src = get_CopyB_src(node);
2346 ir_node *new_src = be_transform_node(src);
2347 ir_node *dst = get_CopyB_dst(node);
2348 ir_node *new_dst = be_transform_node(dst);
2349 ir_node *mem = get_CopyB_mem(node);
2350 ir_node *new_mem = be_transform_node(mem);
2351 ir_node *res = NULL;
2352 ir_graph *irg = current_ir_graph;
2353 dbg_info *dbgi = get_irn_dbg_info(node);
2354 int size = get_type_size_bytes(get_CopyB_type(node));
2357 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2358 /* then we need the size explicitly in ECX. */
2359 if (size >= 32 * 4) {
2360 rem = size & 0x3; /* size % 4 */
2363 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2364 add_irn_dep(res, get_irg_frame(irg));
2366 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2369 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2372 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2375 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2380 static ir_node *gen_be_Copy(ir_node *node)
2382 ir_node *new_node = be_duplicate_node(node);
2383 ir_mode *mode = get_irn_mode(new_node);
2385 if (mode_needs_gp_reg(mode)) {
2386 set_irn_mode(new_node, mode_Iu);
2392 static ir_node *create_Fucom(ir_node *node)
2394 ir_graph *irg = current_ir_graph;
2395 dbg_info *dbgi = get_irn_dbg_info(node);
2396 ir_node *block = get_nodes_block(node);
2397 ir_node *new_block = be_transform_node(block);
2398 ir_node *left = get_Cmp_left(node);
2399 ir_node *new_left = be_transform_node(left);
2400 ir_node *right = get_Cmp_right(node);
2404 if(transform_config.use_fucomi) {
2405 new_right = be_transform_node(right);
2406 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2408 set_ia32_commutative(new_node);
2409 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2411 if(transform_config.use_ftst && is_Const_null(right)) {
2412 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2415 new_right = be_transform_node(right);
2416 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2420 set_ia32_commutative(new_node);
2422 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2424 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2425 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2431 static ir_node *create_Ucomi(ir_node *node)
2433 ir_graph *irg = current_ir_graph;
2434 dbg_info *dbgi = get_irn_dbg_info(node);
2435 ir_node *src_block = get_nodes_block(node);
2436 ir_node *new_block = be_transform_node(src_block);
2437 ir_node *left = get_Cmp_left(node);
2438 ir_node *right = get_Cmp_right(node);
2440 ia32_address_mode_t am;
2441 ia32_address_t *addr = &am.addr;
2443 match_arguments(&am, src_block, left, right, match_commutative | match_am);
2445 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2446 addr->mem, am.new_op1, am.new_op2,
2448 set_am_attributes(new_node, &am);
2450 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2452 new_node = fix_mem_proj(new_node, &am);
2458 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2459 * to fold an and into a test node
2461 static int can_fold_test_and(ir_node *node)
2463 const ir_edge_t *edge;
2465 /** we can only have eq and lg projs */
2466 foreach_out_edge(node, edge) {
2467 ir_node *proj = get_edge_src_irn(edge);
2468 pn_Cmp pnc = get_Proj_proj(proj);
2469 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2476 static ir_node *gen_Cmp(ir_node *node)
2478 ir_graph *irg = current_ir_graph;
2479 dbg_info *dbgi = get_irn_dbg_info(node);
2480 ir_node *block = get_nodes_block(node);
2481 ir_node *new_block = be_transform_node(block);
2482 ir_node *left = get_Cmp_left(node);
2483 ir_node *right = get_Cmp_right(node);
2484 ir_mode *cmp_mode = get_irn_mode(left);
2486 ia32_address_mode_t am;
2487 ia32_address_t *addr = &am.addr;
2490 if(mode_is_float(cmp_mode)) {
2491 if (USE_SSE2(env_cg)) {
2492 return create_Ucomi(node);
2494 return create_Fucom(node);
2498 assert(mode_needs_gp_reg(cmp_mode));
2500 /* we prefer the Test instruction where possible except cases where
2501 * we can use SourceAM */
2502 cmp_unsigned = !mode_is_signed(cmp_mode);
2503 if (is_Const_0(right)) {
2505 get_irn_n_edges(left) == 1 &&
2506 can_fold_test_and(node)) {
2507 /* Test(and_left, and_right) */
2508 ir_node *and_left = get_And_left(left);
2509 ir_node *and_right = get_And_right(left);
2510 ir_mode *mode = get_irn_mode(and_left);
2512 match_arguments(&am, block, and_left, and_right, match_commutative |
2513 match_am | match_8bit_am | match_16bit_am |
2514 match_am_and_immediates | match_immediate |
2515 match_8bit | match_16bit);
2516 if (get_mode_size_bits(mode) == 8) {
2517 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2518 addr->index, addr->mem, am.new_op1,
2519 am.new_op2, am.ins_permuted,
2522 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2523 addr->index, addr->mem, am.new_op1,
2524 am.new_op2, am.ins_permuted, cmp_unsigned);
2527 match_arguments(&am, block, NULL, left, match_am | match_8bit_am |
2528 match_16bit_am | match_8bit | match_16bit);
2529 if (am.op_type == ia32_AddrModeS) {
2531 ir_node *imm_zero = try_create_Immediate(right, 0);
2532 if (get_mode_size_bits(cmp_mode) == 8) {
2533 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2534 addr->index, addr->mem, am.new_op2,
2535 imm_zero, am.ins_permuted,
2538 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2539 addr->index, addr->mem, am.new_op2,
2540 imm_zero, am.ins_permuted, cmp_unsigned);
2543 /* Test(left, left) */
2544 if (get_mode_size_bits(cmp_mode) == 8) {
2545 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2546 addr->index, addr->mem, am.new_op2,
2547 am.new_op2, am.ins_permuted,
2550 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2551 addr->index, addr->mem, am.new_op2,
2552 am.new_op2, am.ins_permuted,
2558 /* Cmp(left, right) */
2559 match_arguments(&am, block, left, right, match_commutative | match_am |
2560 match_8bit_am | match_16bit_am | match_am_and_immediates |
2561 match_immediate | match_8bit | match_16bit);
2562 if (get_mode_size_bits(cmp_mode) == 8) {
2563 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2564 addr->index, addr->mem, am.new_op1,
2565 am.new_op2, am.ins_permuted,
2568 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2569 addr->index, addr->mem, am.new_op1,
2570 am.new_op2, am.ins_permuted, cmp_unsigned);
2573 set_am_attributes(new_node, &am);
2574 assert(cmp_mode != NULL);
2575 set_ia32_ls_mode(new_node, cmp_mode);
2577 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2579 new_node = fix_mem_proj(new_node, &am);
2584 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2586 ir_graph *irg = current_ir_graph;
2587 dbg_info *dbgi = get_irn_dbg_info(node);
2588 ir_node *block = get_nodes_block(node);
2589 ir_node *new_block = be_transform_node(block);
2590 ir_node *val_true = get_Psi_val(node, 0);
2591 ir_node *val_false = get_Psi_default(node);
2593 match_flags_t match_flags;
2594 ia32_address_mode_t am;
2595 ia32_address_t *addr;
2597 assert(transform_config.use_cmov);
2598 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2602 match_flags = match_commutative | match_am | match_16bit_am |
2605 match_arguments(&am, block, val_false, val_true, match_flags);
2607 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2608 addr->mem, am.new_op1, am.new_op2, new_flags,
2609 am.ins_permuted, pnc);
2610 set_am_attributes(new_node, &am);
2612 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2614 new_node = fix_mem_proj(new_node, &am);
2621 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2622 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2625 ir_graph *irg = current_ir_graph;
2626 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2627 ir_node *nomem = new_NoMem();
2628 ir_mode *mode = get_irn_mode(orig_node);
2631 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2632 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2634 /* we might need to conv the result up */
2635 if(get_mode_size_bits(mode) > 8) {
2636 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2637 nomem, new_node, mode_Bu);
2638 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2645 * Transforms a Psi node into CMov.
2647 * @return The transformed node.
2649 static ir_node *gen_Psi(ir_node *node)
2651 dbg_info *dbgi = get_irn_dbg_info(node);
2652 ir_node *block = get_nodes_block(node);
2653 ir_node *new_block = be_transform_node(block);
2654 ir_node *psi_true = get_Psi_val(node, 0);
2655 ir_node *psi_default = get_Psi_default(node);
2656 ir_node *cond = get_Psi_cond(node, 0);
2657 ir_node *flags = NULL;
2661 assert(get_Psi_n_conds(node) == 1);
2662 assert(get_irn_mode(cond) == mode_b);
2663 assert(mode_needs_gp_reg(get_irn_mode(node)));
2665 flags = get_flags_node(cond, &pnc);
2667 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2668 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2669 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2670 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2672 new_node = create_CMov(node, flags, pnc);
2679 * Create a conversion from x87 state register to general purpose.
2681 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2682 ir_node *block = be_transform_node(get_nodes_block(node));
2683 ir_node *op = get_Conv_op(node);
2684 ir_node *new_op = be_transform_node(op);
2685 ia32_code_gen_t *cg = env_cg;
2686 ir_graph *irg = current_ir_graph;
2687 dbg_info *dbgi = get_irn_dbg_info(node);
2688 ir_node *noreg = ia32_new_NoReg_gp(cg);
2689 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2690 ir_mode *mode = get_irn_mode(node);
2691 ir_node *fist, *load;
2694 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2695 new_NoMem(), new_op, trunc_mode);
2697 set_irn_pinned(fist, op_pin_state_floats);
2698 set_ia32_use_frame(fist);
2699 set_ia32_op_type(fist, ia32_AddrModeD);
2701 assert(get_mode_size_bits(mode) <= 32);
2702 /* exception we can only store signed 32 bit integers, so for unsigned
2703 we store a 64bit (signed) integer and load the lower bits */
2704 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2705 set_ia32_ls_mode(fist, mode_Ls);
2707 set_ia32_ls_mode(fist, mode_Is);
2709 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2712 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2714 set_irn_pinned(load, op_pin_state_floats);
2715 set_ia32_use_frame(load);
2716 set_ia32_op_type(load, ia32_AddrModeS);
2717 set_ia32_ls_mode(load, mode_Is);
2718 if(get_ia32_ls_mode(fist) == mode_Ls) {
2719 ia32_attr_t *attr = get_ia32_attr(load);
2720 attr->data.need_64bit_stackent = 1;
2722 ia32_attr_t *attr = get_ia32_attr(load);
2723 attr->data.need_32bit_stackent = 1;
2725 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2727 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2731 * Creates a x87 strict Conv by placing a Sore and a Load
2733 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2735 ir_node *block = get_nodes_block(node);
2736 ir_graph *irg = current_ir_graph;
2737 dbg_info *dbgi = get_irn_dbg_info(node);
2738 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2739 ir_node *nomem = new_NoMem();
2740 ir_node *frame = get_irg_frame(irg);
2741 ir_node *store, *load;
2744 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2746 set_ia32_use_frame(store);
2747 set_ia32_op_type(store, ia32_AddrModeD);
2748 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2750 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2752 set_ia32_use_frame(load);
2753 set_ia32_op_type(load, ia32_AddrModeS);
2754 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2756 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2760 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2762 ir_graph *irg = current_ir_graph;
2763 ir_node *start_block = get_irg_start_block(irg);
2764 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2765 symconst, symconst_sign, val);
2766 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2772 * Create a conversion from general purpose to x87 register
2774 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2775 ir_node *src_block = get_nodes_block(node);
2776 ir_node *block = be_transform_node(src_block);
2777 ir_graph *irg = current_ir_graph;
2778 dbg_info *dbgi = get_irn_dbg_info(node);
2779 ir_node *op = get_Conv_op(node);
2780 ir_node *new_op = NULL;
2784 ir_mode *store_mode;
2790 /* fild can use source AM if the operand is a signed 32bit integer */
2791 if (src_mode == mode_Is) {
2792 ia32_address_mode_t am;
2794 match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
2795 if (am.op_type == ia32_AddrModeS) {
2796 ia32_address_t *addr = &am.addr;
2798 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2799 addr->index, addr->mem);
2800 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2803 set_am_attributes(fild, &am);
2804 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2806 fix_mem_proj(fild, &am);
2811 if(new_op == NULL) {
2812 new_op = be_transform_node(op);
2815 noreg = ia32_new_NoReg_gp(env_cg);
2816 nomem = new_NoMem();
2817 mode = get_irn_mode(op);
2819 /* first convert to 32 bit signed if necessary */
2820 src_bits = get_mode_size_bits(src_mode);
2821 if (src_bits == 8) {
2822 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2824 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2826 } else if (src_bits < 32) {
2827 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2829 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2833 assert(get_mode_size_bits(mode) == 32);
2836 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2839 set_ia32_use_frame(store);
2840 set_ia32_op_type(store, ia32_AddrModeD);
2841 set_ia32_ls_mode(store, mode_Iu);
2843 /* exception for 32bit unsigned, do a 64bit spill+load */
2844 if(!mode_is_signed(mode)) {
2847 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2849 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2850 get_irg_frame(irg), noreg, nomem,
2853 set_ia32_use_frame(zero_store);
2854 set_ia32_op_type(zero_store, ia32_AddrModeD);
2855 add_ia32_am_offs_int(zero_store, 4);
2856 set_ia32_ls_mode(zero_store, mode_Iu);
2861 store = new_rd_Sync(dbgi, irg, block, 2, in);
2862 store_mode = mode_Ls;
2864 store_mode = mode_Is;
2868 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2870 set_ia32_use_frame(fild);
2871 set_ia32_op_type(fild, ia32_AddrModeS);
2872 set_ia32_ls_mode(fild, store_mode);
2874 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2880 * Create a conversion from one integer mode into another one
2882 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2883 dbg_info *dbgi, ir_node *block, ir_node *op,
2886 ir_graph *irg = current_ir_graph;
2887 int src_bits = get_mode_size_bits(src_mode);
2888 int tgt_bits = get_mode_size_bits(tgt_mode);
2889 ir_node *new_block = be_transform_node(block);
2891 ir_mode *smaller_mode;
2893 ia32_address_mode_t am;
2894 ia32_address_t *addr = &am.addr;
2896 if (src_bits < tgt_bits) {
2897 smaller_mode = src_mode;
2898 smaller_bits = src_bits;
2900 smaller_mode = tgt_mode;
2901 smaller_bits = tgt_bits;
2904 #ifdef DEBUG_libfirm
2906 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2911 match_arguments(&am, block, NULL, op,
2912 match_8bit | match_16bit | match_8bit_am | match_16bit_am);
2913 if (smaller_bits == 8) {
2914 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2915 addr->index, addr->mem, am.new_op2,
2918 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2919 addr->index, addr->mem, am.new_op2,
2922 set_am_attributes(new_node, &am);
2923 /* match_arguments assume that out-mode = in-mode, this isn't true here
2925 set_ia32_ls_mode(new_node, smaller_mode);
2926 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2927 new_node = fix_mem_proj(new_node, &am);
2932 * Transforms a Conv node.
2934 * @return The created ia32 Conv node
2936 static ir_node *gen_Conv(ir_node *node) {
2937 ir_node *block = get_nodes_block(node);
2938 ir_node *new_block = be_transform_node(block);
2939 ir_node *op = get_Conv_op(node);
2940 ir_node *new_op = NULL;
2941 ir_graph *irg = current_ir_graph;
2942 dbg_info *dbgi = get_irn_dbg_info(node);
2943 ir_mode *src_mode = get_irn_mode(op);
2944 ir_mode *tgt_mode = get_irn_mode(node);
2945 int src_bits = get_mode_size_bits(src_mode);
2946 int tgt_bits = get_mode_size_bits(tgt_mode);
2947 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2948 ir_node *nomem = new_rd_NoMem(irg);
2949 ir_node *res = NULL;
2951 if (src_mode == mode_b) {
2952 assert(mode_is_int(tgt_mode));
2953 /* nothing to do, we already model bools as 0/1 ints */
2954 return be_transform_node(op);
2957 if (src_mode == tgt_mode) {
2958 if (get_Conv_strict(node)) {
2959 if (USE_SSE2(env_cg)) {
2960 /* when we are in SSE mode, we can kill all strict no-op conversion */
2961 return be_transform_node(op);
2964 /* this should be optimized already, but who knows... */
2965 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2966 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2967 return be_transform_node(op);
2971 if (mode_is_float(src_mode)) {
2972 new_op = be_transform_node(op);
2973 /* we convert from float ... */
2974 if (mode_is_float(tgt_mode)) {
2975 if(src_mode == mode_E && tgt_mode == mode_D
2976 && !get_Conv_strict(node)) {
2977 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2982 if (USE_SSE2(env_cg)) {
2983 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2984 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2986 set_ia32_ls_mode(res, tgt_mode);
2988 if(get_Conv_strict(node)) {
2989 res = gen_x87_strict_conv(tgt_mode, new_op);
2990 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2993 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2998 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2999 if (USE_SSE2(env_cg)) {
3000 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3002 set_ia32_ls_mode(res, src_mode);
3004 return gen_x87_fp_to_gp(node);
3008 /* we convert from int ... */
3009 if (mode_is_float(tgt_mode)) {
3011 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3012 if (USE_SSE2(env_cg)) {
3013 new_op = be_transform_node(op);
3014 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3016 set_ia32_ls_mode(res, tgt_mode);
3018 res = gen_x87_gp_to_fp(node, src_mode);
3019 if(get_Conv_strict(node)) {
3020 res = gen_x87_strict_conv(tgt_mode, res);
3021 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3022 ia32_get_old_node_name(env_cg, node));
3026 } else if(tgt_mode == mode_b) {
3027 /* mode_b lowering already took care that we only have 0/1 values */
3028 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3029 src_mode, tgt_mode));
3030 return be_transform_node(op);
3033 if (src_bits == tgt_bits) {
3034 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3035 src_mode, tgt_mode));
3036 return be_transform_node(op);
3039 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3047 static int check_immediate_constraint(long val, char immediate_constraint_type)
3049 switch (immediate_constraint_type) {
3053 return val >= 0 && val <= 32;
3055 return val >= 0 && val <= 63;
3057 return val >= -128 && val <= 127;
3059 return val == 0xff || val == 0xffff;
3061 return val >= 0 && val <= 3;
3063 return val >= 0 && val <= 255;
3065 return val >= 0 && val <= 127;
3069 panic("Invalid immediate constraint found");
3073 static ir_node *try_create_Immediate(ir_node *node,
3074 char immediate_constraint_type)
3077 tarval *offset = NULL;
3078 int offset_sign = 0;
3080 ir_entity *symconst_ent = NULL;
3081 int symconst_sign = 0;
3083 ir_node *cnst = NULL;
3084 ir_node *symconst = NULL;
3087 mode = get_irn_mode(node);
3088 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3092 if(is_Minus(node)) {
3094 node = get_Minus_op(node);
3097 if(is_Const(node)) {
3100 offset_sign = minus;
3101 } else if(is_SymConst(node)) {
3104 symconst_sign = minus;
3105 } else if(is_Add(node)) {
3106 ir_node *left = get_Add_left(node);
3107 ir_node *right = get_Add_right(node);
3108 if(is_Const(left) && is_SymConst(right)) {
3111 symconst_sign = minus;
3112 offset_sign = minus;
3113 } else if(is_SymConst(left) && is_Const(right)) {
3116 symconst_sign = minus;
3117 offset_sign = minus;
3119 } else if(is_Sub(node)) {
3120 ir_node *left = get_Sub_left(node);
3121 ir_node *right = get_Sub_right(node);
3122 if(is_Const(left) && is_SymConst(right)) {
3125 symconst_sign = !minus;
3126 offset_sign = minus;
3127 } else if(is_SymConst(left) && is_Const(right)) {
3130 symconst_sign = minus;
3131 offset_sign = !minus;
3138 offset = get_Const_tarval(cnst);
3139 if(tarval_is_long(offset)) {
3140 val = get_tarval_long(offset);
3142 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3147 if(!check_immediate_constraint(val, immediate_constraint_type))
3150 if(symconst != NULL) {
3151 if(immediate_constraint_type != 0) {
3152 /* we need full 32bits for symconsts */
3156 /* unfortunately the assembler/linker doesn't support -symconst */
3160 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3162 symconst_ent = get_SymConst_entity(symconst);
3164 if(cnst == NULL && symconst == NULL)
3167 if(offset_sign && offset != NULL) {
3168 offset = tarval_neg(offset);
3171 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3176 static ir_node *create_immediate_or_transform(ir_node *node,
3177 char immediate_constraint_type)
3179 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3180 if (new_node == NULL) {
3181 new_node = be_transform_node(node);
3186 static const arch_register_req_t no_register_req = {
3187 arch_register_req_type_none,
3188 NULL, /* regclass */
3189 NULL, /* limit bitset */
3190 { -1, -1 }, /* same pos */
3191 -1 /* different pos */
3195 * An assembler constraint.
3197 typedef struct constraint_t constraint_t;
3198 struct constraint_t {
3201 const arch_register_req_t **out_reqs;
3203 const arch_register_req_t *req;
3204 unsigned immediate_possible;
3205 char immediate_type;
3208 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3210 int immediate_possible = 0;
3211 char immediate_type = 0;
3212 unsigned limited = 0;
3213 const arch_register_class_t *cls = NULL;
3214 ir_graph *irg = current_ir_graph;
3215 struct obstack *obst = get_irg_obstack(irg);
3216 arch_register_req_t *req;
3217 unsigned *limited_ptr = NULL;
3221 /* TODO: replace all the asserts with nice error messages */
3224 /* a memory constraint: no need to do anything in backend about it
3225 * (the dependencies are already respected by the memory edge of
3227 constraint->req = &no_register_req;
3239 assert(cls == NULL ||
3240 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3241 cls = &ia32_reg_classes[CLASS_ia32_gp];
3242 limited |= 1 << REG_EAX;
3245 assert(cls == NULL ||
3246 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3247 cls = &ia32_reg_classes[CLASS_ia32_gp];
3248 limited |= 1 << REG_EBX;
3251 assert(cls == NULL ||
3252 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3253 cls = &ia32_reg_classes[CLASS_ia32_gp];
3254 limited |= 1 << REG_ECX;
3257 assert(cls == NULL ||
3258 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3259 cls = &ia32_reg_classes[CLASS_ia32_gp];
3260 limited |= 1 << REG_EDX;
3263 assert(cls == NULL ||
3264 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3265 cls = &ia32_reg_classes[CLASS_ia32_gp];
3266 limited |= 1 << REG_EDI;
3269 assert(cls == NULL ||
3270 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3271 cls = &ia32_reg_classes[CLASS_ia32_gp];
3272 limited |= 1 << REG_ESI;
3275 case 'q': /* q means lower part of the regs only, this makes no
3276 * difference to Q for us (we only assigne whole registers) */
3277 assert(cls == NULL ||
3278 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3279 cls = &ia32_reg_classes[CLASS_ia32_gp];
3280 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3284 assert(cls == NULL ||
3285 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3286 cls = &ia32_reg_classes[CLASS_ia32_gp];
3287 limited |= 1 << REG_EAX | 1 << REG_EDX;
3290 assert(cls == NULL ||
3291 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3292 cls = &ia32_reg_classes[CLASS_ia32_gp];
3293 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3294 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3301 assert(cls == NULL);
3302 cls = &ia32_reg_classes[CLASS_ia32_gp];
3308 /* TODO: mark values so the x87 simulator knows about t and u */
3309 assert(cls == NULL);
3310 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3315 assert(cls == NULL);
3316 /* TODO: check that sse2 is supported */
3317 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3327 assert(!immediate_possible);
3328 immediate_possible = 1;
3329 immediate_type = *c;
3333 assert(!immediate_possible);
3334 immediate_possible = 1;
3338 assert(!immediate_possible && cls == NULL);
3339 immediate_possible = 1;
3340 cls = &ia32_reg_classes[CLASS_ia32_gp];
3353 assert(constraint->is_in && "can only specify same constraint "
3356 sscanf(c, "%d%n", &same_as, &p);
3364 /* memory constraint no need to do anything in backend about it
3365 * (the dependencies are already respected by the memory edge of
3367 constraint->req = &no_register_req;
3370 case 'E': /* no float consts yet */
3371 case 'F': /* no float consts yet */
3372 case 's': /* makes no sense on x86 */
3373 case 'X': /* we can't support that in firm */
3376 case '<': /* no autodecrement on x86 */
3377 case '>': /* no autoincrement on x86 */
3378 case 'C': /* sse constant not supported yet */
3379 case 'G': /* 80387 constant not supported yet */
3380 case 'y': /* we don't support mmx registers yet */
3381 case 'Z': /* not available in 32 bit mode */
3382 case 'e': /* not available in 32 bit mode */
3383 panic("unsupported asm constraint '%c' found in (%+F)",
3384 *c, current_ir_graph);
3387 panic("unknown asm constraint '%c' found in (%+F)", *c,
3395 const arch_register_req_t *other_constr;
3397 assert(cls == NULL && "same as and register constraint not supported");
3398 assert(!immediate_possible && "same as and immediate constraint not "
3400 assert(same_as < constraint->n_outs && "wrong constraint number in "
3401 "same_as constraint");
3403 other_constr = constraint->out_reqs[same_as];
3405 req = obstack_alloc(obst, sizeof(req[0]));
3406 req->cls = other_constr->cls;
3407 req->type = arch_register_req_type_should_be_same;
3408 req->limited = NULL;
3409 req->other_same[0] = pos;
3410 req->other_same[1] = -1;
3411 req->other_different = -1;
3413 /* switch constraints. This is because in firm we have same_as
3414 * constraints on the output constraints while in the gcc asm syntax
3415 * they are specified on the input constraints */
3416 constraint->req = other_constr;
3417 constraint->out_reqs[same_as] = req;
3418 constraint->immediate_possible = 0;
3422 if(immediate_possible && cls == NULL) {
3423 cls = &ia32_reg_classes[CLASS_ia32_gp];
3425 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3426 assert(cls != NULL);
3428 if(immediate_possible) {
3429 assert(constraint->is_in
3430 && "immediate make no sense for output constraints");
3432 /* todo: check types (no float input on 'r' constrained in and such... */
3435 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3436 limited_ptr = (unsigned*) (req+1);
3438 req = obstack_alloc(obst, sizeof(req[0]));
3440 memset(req, 0, sizeof(req[0]));
3443 req->type = arch_register_req_type_limited;
3444 *limited_ptr = limited;
3445 req->limited = limited_ptr;
3447 req->type = arch_register_req_type_normal;
3451 constraint->req = req;
3452 constraint->immediate_possible = immediate_possible;
3453 constraint->immediate_type = immediate_type;
3456 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3463 panic("Clobbers not supported yet");
3466 static int is_memory_op(const ir_asm_constraint *constraint)
3468 ident *id = constraint->constraint;
3469 const char *str = get_id_str(id);
3472 for(c = str; *c != '\0'; ++c) {
3481 * generates code for a ASM node
3483 static ir_node *gen_ASM(ir_node *node)
3486 ir_graph *irg = current_ir_graph;
3487 ir_node *block = get_nodes_block(node);
3488 ir_node *new_block = be_transform_node(block);
3489 dbg_info *dbgi = get_irn_dbg_info(node);
3493 int n_out_constraints;
3495 const arch_register_req_t **out_reg_reqs;
3496 const arch_register_req_t **in_reg_reqs;
3497 ia32_asm_reg_t *register_map;
3498 unsigned reg_map_size = 0;
3499 struct obstack *obst;
3500 const ir_asm_constraint *in_constraints;
3501 const ir_asm_constraint *out_constraints;
3503 constraint_t parsed_constraint;
3505 arity = get_irn_arity(node);
3506 in = alloca(arity * sizeof(in[0]));
3507 memset(in, 0, arity * sizeof(in[0]));
3509 n_out_constraints = get_ASM_n_output_constraints(node);
3510 n_clobbers = get_ASM_n_clobbers(node);
3511 out_arity = n_out_constraints + n_clobbers;
3513 in_constraints = get_ASM_input_constraints(node);
3514 out_constraints = get_ASM_output_constraints(node);
3515 clobbers = get_ASM_clobbers(node);
3517 /* construct output constraints */
3518 obst = get_irg_obstack(irg);
3519 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3520 parsed_constraint.out_reqs = out_reg_reqs;
3521 parsed_constraint.n_outs = n_out_constraints;
3522 parsed_constraint.is_in = 0;
3524 for(i = 0; i < out_arity; ++i) {
3527 if(i < n_out_constraints) {
3528 const ir_asm_constraint *constraint = &out_constraints[i];
3529 c = get_id_str(constraint->constraint);
3530 parse_asm_constraint(i, &parsed_constraint, c);
3532 if(constraint->pos > reg_map_size)
3533 reg_map_size = constraint->pos;
3535 ident *glob_id = clobbers [i - n_out_constraints];
3536 c = get_id_str(glob_id);
3537 parse_clobber(node, i, &parsed_constraint, c);
3540 out_reg_reqs[i] = parsed_constraint.req;
3543 /* construct input constraints */
3544 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3545 parsed_constraint.is_in = 1;
3546 for(i = 0; i < arity; ++i) {
3547 const ir_asm_constraint *constraint = &in_constraints[i];
3548 ident *constr_id = constraint->constraint;
3549 const char *c = get_id_str(constr_id);
3551 parse_asm_constraint(i, &parsed_constraint, c);
3552 in_reg_reqs[i] = parsed_constraint.req;
3554 if(constraint->pos > reg_map_size)
3555 reg_map_size = constraint->pos;
3557 if(parsed_constraint.immediate_possible) {
3558 ir_node *pred = get_irn_n(node, i);
3559 char imm_type = parsed_constraint.immediate_type;
3560 ir_node *immediate = try_create_Immediate(pred, imm_type);
3562 if(immediate != NULL) {
3569 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3570 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3572 for(i = 0; i < n_out_constraints; ++i) {
3573 const ir_asm_constraint *constraint = &out_constraints[i];
3574 unsigned pos = constraint->pos;
3576 assert(pos < reg_map_size);
3577 register_map[pos].use_input = 0;
3578 register_map[pos].valid = 1;
3579 register_map[pos].memory = is_memory_op(constraint);
3580 register_map[pos].inout_pos = i;
3581 register_map[pos].mode = constraint->mode;
3584 /* transform inputs */
3585 for(i = 0; i < arity; ++i) {
3586 const ir_asm_constraint *constraint = &in_constraints[i];
3587 unsigned pos = constraint->pos;
3588 ir_node *pred = get_irn_n(node, i);
3589 ir_node *transformed;
3591 assert(pos < reg_map_size);
3592 register_map[pos].use_input = 1;
3593 register_map[pos].valid = 1;
3594 register_map[pos].memory = is_memory_op(constraint);
3595 register_map[pos].inout_pos = i;
3596 register_map[pos].mode = constraint->mode;
3601 transformed = be_transform_node(pred);
3602 in[i] = transformed;
3605 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3606 get_ASM_text(node), register_map);
3608 set_ia32_out_req_all(new_node, out_reg_reqs);
3609 set_ia32_in_req_all(new_node, in_reg_reqs);
3611 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3616 /********************************************
3619 * | |__ ___ _ __ ___ __| | ___ ___
3620 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3621 * | |_) | __/ | | | (_) | (_| | __/\__ \
3622 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3624 ********************************************/
3627 * Transforms a FrameAddr into an ia32 Add.
3629 static ir_node *gen_be_FrameAddr(ir_node *node) {
3630 ir_node *block = be_transform_node(get_nodes_block(node));
3631 ir_node *op = be_get_FrameAddr_frame(node);
3632 ir_node *new_op = be_transform_node(op);
3633 ir_graph *irg = current_ir_graph;
3634 dbg_info *dbgi = get_irn_dbg_info(node);
3635 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3638 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3639 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3640 set_ia32_use_frame(new_node);
3642 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3648 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3650 static ir_node *gen_be_Return(ir_node *node) {
3651 ir_graph *irg = current_ir_graph;
3652 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3653 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3654 ir_entity *ent = get_irg_entity(irg);
3655 ir_type *tp = get_entity_type(ent);
3660 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3661 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3664 int pn_ret_val, pn_ret_mem, arity, i;
3666 assert(ret_val != NULL);
3667 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3668 return be_duplicate_node(node);
3671 res_type = get_method_res_type(tp, 0);
3673 if (! is_Primitive_type(res_type)) {
3674 return be_duplicate_node(node);
3677 mode = get_type_mode(res_type);
3678 if (! mode_is_float(mode)) {
3679 return be_duplicate_node(node);
3682 assert(get_method_n_ress(tp) == 1);
3684 pn_ret_val = get_Proj_proj(ret_val);
3685 pn_ret_mem = get_Proj_proj(ret_mem);
3687 /* get the Barrier */
3688 barrier = get_Proj_pred(ret_val);
3690 /* get result input of the Barrier */
3691 ret_val = get_irn_n(barrier, pn_ret_val);
3692 new_ret_val = be_transform_node(ret_val);
3694 /* get memory input of the Barrier */
3695 ret_mem = get_irn_n(barrier, pn_ret_mem);
3696 new_ret_mem = be_transform_node(ret_mem);
3698 frame = get_irg_frame(irg);
3700 dbgi = get_irn_dbg_info(barrier);
3701 block = be_transform_node(get_nodes_block(barrier));
3703 noreg = ia32_new_NoReg_gp(env_cg);
3705 /* store xmm0 onto stack */
3706 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3707 new_ret_mem, new_ret_val);
3708 set_ia32_ls_mode(sse_store, mode);
3709 set_ia32_op_type(sse_store, ia32_AddrModeD);
3710 set_ia32_use_frame(sse_store);
3712 /* load into x87 register */
3713 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3714 set_ia32_op_type(fld, ia32_AddrModeS);
3715 set_ia32_use_frame(fld);
3717 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3718 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3720 /* create a new barrier */
3721 arity = get_irn_arity(barrier);
3722 in = alloca(arity * sizeof(in[0]));
3723 for (i = 0; i < arity; ++i) {
3726 if (i == pn_ret_val) {
3728 } else if (i == pn_ret_mem) {
3731 ir_node *in = get_irn_n(barrier, i);
3732 new_in = be_transform_node(in);
3737 new_barrier = new_ir_node(dbgi, irg, block,
3738 get_irn_op(barrier), get_irn_mode(barrier),
3740 copy_node_attr(barrier, new_barrier);
3741 be_duplicate_deps(barrier, new_barrier);
3742 be_set_transformed_node(barrier, new_barrier);
3743 mark_irn_visited(barrier);
3745 /* transform normally */
3746 return be_duplicate_node(node);
3750 * Transform a be_AddSP into an ia32_SubSP.
3752 static ir_node *gen_be_AddSP(ir_node *node)
3754 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3755 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3757 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3761 * Transform a be_SubSP into an ia32_AddSP
3763 static ir_node *gen_be_SubSP(ir_node *node)
3765 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3766 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3768 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3772 * This function just sets the register for the Unknown node
3773 * as this is not done during register allocation because Unknown
3774 * is an "ignore" node.
3776 static ir_node *gen_Unknown(ir_node *node) {
3777 ir_mode *mode = get_irn_mode(node);
3779 if (mode_is_float(mode)) {
3780 if (USE_SSE2(env_cg)) {
3781 return ia32_new_Unknown_xmm(env_cg);
3783 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3784 ir_graph *irg = current_ir_graph;
3785 dbg_info *dbgi = get_irn_dbg_info(node);
3786 ir_node *block = get_irg_start_block(irg);
3787 return new_rd_ia32_vfldz(dbgi, irg, block);
3789 } else if (mode_needs_gp_reg(mode)) {
3790 return ia32_new_Unknown_gp(env_cg);
3792 panic("unsupported Unknown-Mode");
3798 * Change some phi modes
3800 static ir_node *gen_Phi(ir_node *node) {
3801 ir_node *block = be_transform_node(get_nodes_block(node));
3802 ir_graph *irg = current_ir_graph;
3803 dbg_info *dbgi = get_irn_dbg_info(node);
3804 ir_mode *mode = get_irn_mode(node);
3807 if(mode_needs_gp_reg(mode)) {
3808 /* we shouldn't have any 64bit stuff around anymore */
3809 assert(get_mode_size_bits(mode) <= 32);
3810 /* all integer operations are on 32bit registers now */
3812 } else if(mode_is_float(mode)) {
3813 if (USE_SSE2(env_cg)) {
3820 /* phi nodes allow loops, so we use the old arguments for now
3821 * and fix this later */
3822 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3823 get_irn_in(node) + 1);
3824 copy_node_attr(node, phi);
3825 be_duplicate_deps(node, phi);
3827 be_set_transformed_node(node, phi);
3828 be_enqueue_preds(node);
3836 static ir_node *gen_IJmp(ir_node *node)
3838 ir_node *block = get_nodes_block(node);
3839 ir_node *new_block = be_transform_node(block);
3840 ir_graph *irg = current_ir_graph;
3841 dbg_info *dbgi = get_irn_dbg_info(node);
3842 ir_node *op = get_IJmp_target(node);
3844 ia32_address_mode_t am;
3845 ia32_address_t *addr = &am.addr;
3847 assert(get_irn_mode(op) == mode_P);
3849 match_arguments(&am, block, NULL, op,
3850 match_am | match_8bit_am | match_16bit_am |
3851 match_immediate | match_8bit | match_16bit);
3853 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3854 addr->mem, am.new_op2);
3855 set_am_attributes(new_node, &am);
3856 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3858 new_node = fix_mem_proj(new_node, &am);
3864 /**********************************************************************
3867 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3868 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3869 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3870 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3872 **********************************************************************/
3874 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3876 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3879 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3880 ir_node *val, ir_node *mem);
3883 * Transforms a lowered Load into a "real" one.
3885 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3887 ir_node *block = be_transform_node(get_nodes_block(node));
3888 ir_node *ptr = get_irn_n(node, 0);
3889 ir_node *new_ptr = be_transform_node(ptr);
3890 ir_node *mem = get_irn_n(node, 1);
3891 ir_node *new_mem = be_transform_node(mem);
3892 ir_graph *irg = current_ir_graph;
3893 dbg_info *dbgi = get_irn_dbg_info(node);
3894 ir_mode *mode = get_ia32_ls_mode(node);
3895 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3898 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3900 set_ia32_op_type(new_op, ia32_AddrModeS);
3901 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3902 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3903 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3904 if (is_ia32_am_sc_sign(node))
3905 set_ia32_am_sc_sign(new_op);
3906 set_ia32_ls_mode(new_op, mode);
3907 if (is_ia32_use_frame(node)) {
3908 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3909 set_ia32_use_frame(new_op);
3912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3918 * Transforms a lowered Store into a "real" one.
3920 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3922 ir_node *block = be_transform_node(get_nodes_block(node));
3923 ir_node *ptr = get_irn_n(node, 0);
3924 ir_node *new_ptr = be_transform_node(ptr);
3925 ir_node *val = get_irn_n(node, 1);
3926 ir_node *new_val = be_transform_node(val);
3927 ir_node *mem = get_irn_n(node, 2);
3928 ir_node *new_mem = be_transform_node(mem);
3929 ir_graph *irg = current_ir_graph;
3930 dbg_info *dbgi = get_irn_dbg_info(node);
3931 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3932 ir_mode *mode = get_ia32_ls_mode(node);
3936 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3938 am_offs = get_ia32_am_offs_int(node);
3939 add_ia32_am_offs_int(new_op, am_offs);
3941 set_ia32_op_type(new_op, ia32_AddrModeD);
3942 set_ia32_ls_mode(new_op, mode);
3943 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3944 set_ia32_use_frame(new_op);
3946 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3951 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3953 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
3954 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
3956 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3957 match_immediate | match_mode_neutral);
3960 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3962 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
3963 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
3964 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3968 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3970 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
3971 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
3972 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3976 static ir_node *gen_ia32_l_Add(ir_node *node) {
3977 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3978 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3979 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3980 match_commutative | match_am | match_immediate |
3981 match_mode_neutral);
3983 if(is_Proj(lowered)) {
3984 lowered = get_Proj_pred(lowered);
3986 assert(is_ia32_Add(lowered));
3987 set_irn_mode(lowered, mode_T);
3993 static ir_node *gen_ia32_l_Adc(ir_node *node)
3995 return gen_binop_flags(node, new_rd_ia32_Adc,
3996 match_commutative | match_am | match_immediate |
3997 match_mode_neutral);
4001 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4003 * @param node The node to transform
4004 * @return the created ia32 vfild node
4006 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4007 return gen_lowered_Load(node, new_rd_ia32_vfild);
4011 * Transforms an ia32_l_Load into a "real" ia32_Load node
4013 * @param node The node to transform
4014 * @return the created ia32 Load node
4016 static ir_node *gen_ia32_l_Load(ir_node *node) {
4017 return gen_lowered_Load(node, new_rd_ia32_Load);
4021 * Transforms an ia32_l_Store into a "real" ia32_Store node
4023 * @param node The node to transform
4024 * @return the created ia32 Store node
4026 static ir_node *gen_ia32_l_Store(ir_node *node) {
4027 return gen_lowered_Store(node, new_rd_ia32_Store);
4031 * Transforms a l_vfist into a "real" vfist node.
4033 * @param node The node to transform
4034 * @return the created ia32 vfist node
4036 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4037 ir_node *block = be_transform_node(get_nodes_block(node));
4038 ir_node *ptr = get_irn_n(node, 0);
4039 ir_node *new_ptr = be_transform_node(ptr);
4040 ir_node *val = get_irn_n(node, 1);
4041 ir_node *new_val = be_transform_node(val);
4042 ir_node *mem = get_irn_n(node, 2);
4043 ir_node *new_mem = be_transform_node(mem);
4044 ir_graph *irg = current_ir_graph;
4045 dbg_info *dbgi = get_irn_dbg_info(node);
4046 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4047 ir_mode *mode = get_ia32_ls_mode(node);
4048 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4052 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4053 new_val, trunc_mode);
4055 am_offs = get_ia32_am_offs_int(node);
4056 add_ia32_am_offs_int(new_op, am_offs);
4058 set_ia32_op_type(new_op, ia32_AddrModeD);
4059 set_ia32_ls_mode(new_op, mode);
4060 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4061 set_ia32_use_frame(new_op);
4063 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4069 * Transforms a l_MulS into a "real" MulS node.
4071 * @return the created ia32 Mul node
4073 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4074 ir_node *left = get_binop_left(node);
4075 ir_node *right = get_binop_right(node);
4077 return gen_binop(node, left, right, new_rd_ia32_Mul,
4078 match_commutative | match_am | match_mode_neutral);
4082 * Transforms a l_IMulS into a "real" IMul1OPS node.
4084 * @return the created ia32 IMul1OP node
4086 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4087 ir_node *left = get_binop_left(node);
4088 ir_node *right = get_binop_right(node);
4090 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4091 match_commutative | match_am | match_mode_neutral);
4094 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4095 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4096 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4097 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4098 match_am | match_immediate | match_mode_neutral);
4100 if(is_Proj(lowered)) {
4101 lowered = get_Proj_pred(lowered);
4103 assert(is_ia32_Sub(lowered));
4104 set_irn_mode(lowered, mode_T);
4110 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4111 return gen_binop_flags(node, new_rd_ia32_Sbb,
4112 match_am | match_immediate | match_mode_neutral);
4116 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4117 * op1 - target to be shifted
4118 * op2 - contains bits to be shifted into target
4120 * Only op3 can be an immediate.
4122 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4123 ir_node *low, ir_node *count)
4125 ir_node *block = get_nodes_block(node);
4126 ir_node *new_block = be_transform_node(block);
4127 ir_graph *irg = current_ir_graph;
4128 dbg_info *dbgi = get_irn_dbg_info(node);
4129 ir_node *new_high = be_transform_node(high);
4130 ir_node *new_low = be_transform_node(low);
4134 /* the shift amount can be any mode that is bigger than 5 bits, since all
4135 * other bits are ignored anyway */
4136 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4137 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4138 count = get_Conv_op(count);
4140 new_count = create_immediate_or_transform(count, 0);
4142 if (is_ia32_l_ShlD(node)) {
4143 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4146 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4149 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4154 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4156 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
4157 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
4158 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4159 return gen_lowered_64bit_shifts(node, high, low, count);
4162 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4164 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
4165 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
4166 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4167 return gen_lowered_64bit_shifts(node, high, low, count);
4171 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4173 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4174 ir_node *block = be_transform_node(get_nodes_block(node));
4175 ir_node *val = get_irn_n(node, 1);
4176 ir_node *new_val = be_transform_node(val);
4177 ia32_code_gen_t *cg = env_cg;
4178 ir_node *res = NULL;
4179 ir_graph *irg = current_ir_graph;
4181 ir_node *noreg, *new_ptr, *new_mem;
4188 mem = get_irn_n(node, 2);
4189 new_mem = be_transform_node(mem);
4190 ptr = get_irn_n(node, 0);
4191 new_ptr = be_transform_node(ptr);
4192 noreg = ia32_new_NoReg_gp(cg);
4193 dbgi = get_irn_dbg_info(node);
4195 /* Store x87 -> MEM */
4196 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4197 get_ia32_ls_mode(node));
4198 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4199 set_ia32_use_frame(res);
4200 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4201 set_ia32_op_type(res, ia32_AddrModeD);
4203 /* Load MEM -> SSE */
4204 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4205 get_ia32_ls_mode(node));
4206 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4207 set_ia32_use_frame(res);
4208 set_ia32_op_type(res, ia32_AddrModeS);
4209 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4215 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4217 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4218 ir_node *block = be_transform_node(get_nodes_block(node));
4219 ir_node *val = get_irn_n(node, 1);
4220 ir_node *new_val = be_transform_node(val);
4221 ia32_code_gen_t *cg = env_cg;
4222 ir_graph *irg = current_ir_graph;
4223 ir_node *res = NULL;
4224 ir_entity *fent = get_ia32_frame_ent(node);
4225 ir_mode *lsmode = get_ia32_ls_mode(node);
4227 ir_node *noreg, *new_ptr, *new_mem;
4231 if (! USE_SSE2(cg)) {
4232 /* SSE unit is not used -> skip this node. */
4236 ptr = get_irn_n(node, 0);
4237 new_ptr = be_transform_node(ptr);
4238 mem = get_irn_n(node, 2);
4239 new_mem = be_transform_node(mem);
4240 noreg = ia32_new_NoReg_gp(cg);
4241 dbgi = get_irn_dbg_info(node);
4243 /* Store SSE -> MEM */
4244 if (is_ia32_xLoad(skip_Proj(new_val))) {
4245 ir_node *ld = skip_Proj(new_val);
4247 /* we can vfld the value directly into the fpu */
4248 fent = get_ia32_frame_ent(ld);
4249 ptr = get_irn_n(ld, 0);
4250 offs = get_ia32_am_offs_int(ld);
4252 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4254 set_ia32_frame_ent(res, fent);
4255 set_ia32_use_frame(res);
4256 set_ia32_ls_mode(res, lsmode);
4257 set_ia32_op_type(res, ia32_AddrModeD);
4261 /* Load MEM -> x87 */
4262 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4263 set_ia32_frame_ent(res, fent);
4264 set_ia32_use_frame(res);
4265 add_ia32_am_offs_int(res, offs);
4266 set_ia32_op_type(res, ia32_AddrModeS);
4267 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4272 /*********************************************************
4275 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4276 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4277 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4278 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4280 *********************************************************/
4283 * the BAD transformer.
4285 static ir_node *bad_transform(ir_node *node) {
4286 panic("No transform function for %+F available.\n", node);
4291 * Transform the Projs of an AddSP.
4293 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4294 ir_node *block = be_transform_node(get_nodes_block(node));
4295 ir_node *pred = get_Proj_pred(node);
4296 ir_node *new_pred = be_transform_node(pred);
4297 ir_graph *irg = current_ir_graph;
4298 dbg_info *dbgi = get_irn_dbg_info(node);
4299 long proj = get_Proj_proj(node);
4301 if (proj == pn_be_AddSP_sp) {
4302 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4303 pn_ia32_SubSP_stack);
4304 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4306 } else if(proj == pn_be_AddSP_res) {
4307 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4308 pn_ia32_SubSP_addr);
4309 } else if (proj == pn_be_AddSP_M) {
4310 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4314 return new_rd_Unknown(irg, get_irn_mode(node));
4318 * Transform the Projs of a SubSP.
4320 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4321 ir_node *block = be_transform_node(get_nodes_block(node));
4322 ir_node *pred = get_Proj_pred(node);
4323 ir_node *new_pred = be_transform_node(pred);
4324 ir_graph *irg = current_ir_graph;
4325 dbg_info *dbgi = get_irn_dbg_info(node);
4326 long proj = get_Proj_proj(node);
4328 if (proj == pn_be_SubSP_sp) {
4329 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4330 pn_ia32_AddSP_stack);
4331 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4333 } else if (proj == pn_be_SubSP_M) {
4334 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4338 return new_rd_Unknown(irg, get_irn_mode(node));
4342 * Transform and renumber the Projs from a Load.
4344 static ir_node *gen_Proj_Load(ir_node *node) {
4346 ir_node *block = be_transform_node(get_nodes_block(node));
4347 ir_node *pred = get_Proj_pred(node);
4348 ir_graph *irg = current_ir_graph;
4349 dbg_info *dbgi = get_irn_dbg_info(node);
4350 long proj = get_Proj_proj(node);
4353 /* loads might be part of source address mode matches, so we don't
4354 transform the ProjMs yet (with the exception of loads whose result is
4357 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4360 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4362 /* this is needed, because sometimes we have loops that are only
4363 reachable through the ProjM */
4364 be_enqueue_preds(node);
4365 /* do it in 2 steps, to silence firm verifier */
4366 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4367 set_Proj_proj(res, pn_ia32_Load_M);
4371 /* renumber the proj */
4372 new_pred = be_transform_node(pred);
4373 if (is_ia32_Load(new_pred)) {
4374 if (proj == pn_Load_res) {
4375 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4377 } else if (proj == pn_Load_M) {
4378 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4381 } else if(is_ia32_Conv_I2I(new_pred)
4382 || is_ia32_Conv_I2I8Bit(new_pred)) {
4383 set_irn_mode(new_pred, mode_T);
4384 if (proj == pn_Load_res) {
4385 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4386 } else if (proj == pn_Load_M) {
4387 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4389 } else if (is_ia32_xLoad(new_pred)) {
4390 if (proj == pn_Load_res) {
4391 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4393 } else if (proj == pn_Load_M) {
4394 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4397 } else if (is_ia32_vfld(new_pred)) {
4398 if (proj == pn_Load_res) {
4399 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4401 } else if (proj == pn_Load_M) {
4402 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4406 /* can happen for ProJMs when source address mode happened for the
4409 /* however it should not be the result proj, as that would mean the
4410 load had multiple users and should not have been used for
4412 if(proj != pn_Load_M) {
4413 panic("internal error: transformed node not a Load");
4415 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4419 return new_rd_Unknown(irg, get_irn_mode(node));
4423 * Transform and renumber the Projs from a DivMod like instruction.
4425 static ir_node *gen_Proj_DivMod(ir_node *node) {
4426 ir_node *block = be_transform_node(get_nodes_block(node));
4427 ir_node *pred = get_Proj_pred(node);
4428 ir_node *new_pred = be_transform_node(pred);
4429 ir_graph *irg = current_ir_graph;
4430 dbg_info *dbgi = get_irn_dbg_info(node);
4431 ir_mode *mode = get_irn_mode(node);
4432 long proj = get_Proj_proj(node);
4434 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4436 switch (get_irn_opcode(pred)) {
4440 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4442 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4450 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4452 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4460 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4461 case pn_DivMod_res_div:
4462 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4463 case pn_DivMod_res_mod:
4464 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4474 return new_rd_Unknown(irg, mode);
4478 * Transform and renumber the Projs from a CopyB.
4480 static ir_node *gen_Proj_CopyB(ir_node *node) {
4481 ir_node *block = be_transform_node(get_nodes_block(node));
4482 ir_node *pred = get_Proj_pred(node);
4483 ir_node *new_pred = be_transform_node(pred);
4484 ir_graph *irg = current_ir_graph;
4485 dbg_info *dbgi = get_irn_dbg_info(node);
4486 ir_mode *mode = get_irn_mode(node);
4487 long proj = get_Proj_proj(node);
4490 case pn_CopyB_M_regular:
4491 if (is_ia32_CopyB_i(new_pred)) {
4492 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4493 } else if (is_ia32_CopyB(new_pred)) {
4494 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4502 return new_rd_Unknown(irg, mode);
4506 * Transform and renumber the Projs from a Quot.
4508 static ir_node *gen_Proj_Quot(ir_node *node) {
4509 ir_node *block = be_transform_node(get_nodes_block(node));
4510 ir_node *pred = get_Proj_pred(node);
4511 ir_node *new_pred = be_transform_node(pred);
4512 ir_graph *irg = current_ir_graph;
4513 dbg_info *dbgi = get_irn_dbg_info(node);
4514 ir_mode *mode = get_irn_mode(node);
4515 long proj = get_Proj_proj(node);
4519 if (is_ia32_xDiv(new_pred)) {
4520 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4521 } else if (is_ia32_vfdiv(new_pred)) {
4522 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4526 if (is_ia32_xDiv(new_pred)) {
4527 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4528 } else if (is_ia32_vfdiv(new_pred)) {
4529 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4537 return new_rd_Unknown(irg, mode);
4541 * Transform the Thread Local Storage Proj.
4543 static ir_node *gen_Proj_tls(ir_node *node) {
4544 ir_node *block = be_transform_node(get_nodes_block(node));
4545 ir_graph *irg = current_ir_graph;
4546 dbg_info *dbgi = NULL;
4547 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4552 static ir_node *gen_be_Call(ir_node *node) {
4553 ir_node *res = be_duplicate_node(node);
4554 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4559 static ir_node *gen_be_IncSP(ir_node *node) {
4560 ir_node *res = be_duplicate_node(node);
4561 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4567 * Transform the Projs from a be_Call.
4569 static ir_node *gen_Proj_be_Call(ir_node *node) {
4570 ir_node *block = be_transform_node(get_nodes_block(node));
4571 ir_node *call = get_Proj_pred(node);
4572 ir_node *new_call = be_transform_node(call);
4573 ir_graph *irg = current_ir_graph;
4574 dbg_info *dbgi = get_irn_dbg_info(node);
4575 ir_type *method_type = be_Call_get_type(call);
4576 int n_res = get_method_n_ress(method_type);
4577 long proj = get_Proj_proj(node);
4578 ir_mode *mode = get_irn_mode(node);
4580 const arch_register_class_t *cls;
4582 /* The following is kinda tricky: If we're using SSE, then we have to
4583 * move the result value of the call in floating point registers to an
4584 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4585 * after the call, we have to make sure to correctly make the
4586 * MemProj and the result Proj use these 2 nodes
4588 if (proj == pn_be_Call_M_regular) {
4589 // get new node for result, are we doing the sse load/store hack?
4590 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4591 ir_node *call_res_new;
4592 ir_node *call_res_pred = NULL;
4594 if (call_res != NULL) {
4595 call_res_new = be_transform_node(call_res);
4596 call_res_pred = get_Proj_pred(call_res_new);
4599 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4600 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4601 pn_be_Call_M_regular);
4603 assert(is_ia32_xLoad(call_res_pred));
4604 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4608 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4609 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4610 && USE_SSE2(env_cg)) {
4612 ir_node *frame = get_irg_frame(irg);
4613 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4615 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4618 /* in case there is no memory output: create one to serialize the copy
4620 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4621 pn_be_Call_M_regular);
4622 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4623 pn_be_Call_first_res);
4625 /* store st(0) onto stack */
4626 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4628 set_ia32_op_type(fstp, ia32_AddrModeD);
4629 set_ia32_use_frame(fstp);
4631 /* load into SSE register */
4632 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4634 set_ia32_op_type(sse_load, ia32_AddrModeS);
4635 set_ia32_use_frame(sse_load);
4637 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4643 /* transform call modes */
4644 if (mode_is_data(mode)) {
4645 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4649 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4653 * Transform the Projs from a Cmp.
4655 static ir_node *gen_Proj_Cmp(ir_node *node)
4658 panic("not all mode_b nodes are lowered");
4661 /* normally Cmps are processed when looking at Cond nodes, but this case
4662 * can happen in complicated Psi conditions */
4663 dbg_info *dbgi = get_irn_dbg_info(node);
4664 ir_node *block = get_nodes_block(node);
4665 ir_node *new_block = be_transform_node(block);
4666 ir_node *cmp = get_Proj_pred(node);
4667 ir_node *new_cmp = be_transform_node(cmp);
4668 long pnc = get_Proj_proj(node);
4671 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4678 * Transform and potentially renumber Proj nodes.
4680 static ir_node *gen_Proj(ir_node *node) {
4681 ir_graph *irg = current_ir_graph;
4682 dbg_info *dbgi = get_irn_dbg_info(node);
4683 ir_node *pred = get_Proj_pred(node);
4684 long proj = get_Proj_proj(node);
4686 if (is_Store(pred)) {
4687 if (proj == pn_Store_M) {
4688 return be_transform_node(pred);
4691 return new_r_Bad(irg);
4693 } else if (is_Load(pred)) {
4694 return gen_Proj_Load(node);
4695 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4696 return gen_Proj_DivMod(node);
4697 } else if (is_CopyB(pred)) {
4698 return gen_Proj_CopyB(node);
4699 } else if (is_Quot(pred)) {
4700 return gen_Proj_Quot(node);
4701 } else if (be_is_SubSP(pred)) {
4702 return gen_Proj_be_SubSP(node);
4703 } else if (be_is_AddSP(pred)) {
4704 return gen_Proj_be_AddSP(node);
4705 } else if (be_is_Call(pred)) {
4706 return gen_Proj_be_Call(node);
4707 } else if (is_Cmp(pred)) {
4708 return gen_Proj_Cmp(node);
4709 } else if (get_irn_op(pred) == op_Start) {
4710 if (proj == pn_Start_X_initial_exec) {
4711 ir_node *block = get_nodes_block(pred);
4714 /* we exchange the ProjX with a jump */
4715 block = be_transform_node(block);
4716 jump = new_rd_Jmp(dbgi, irg, block);
4719 if (node == be_get_old_anchor(anchor_tls)) {
4720 return gen_Proj_tls(node);
4723 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4727 ir_node *new_pred = be_transform_node(pred);
4728 ir_node *block = be_transform_node(get_nodes_block(node));
4729 ir_mode *mode = get_irn_mode(node);
4730 if (mode_needs_gp_reg(mode)) {
4731 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4732 get_Proj_proj(node));
4733 #ifdef DEBUG_libfirm
4734 new_proj->node_nr = node->node_nr;
4740 return be_duplicate_node(node);
4744 * Enters all transform functions into the generic pointer
4746 static void register_transformers(void)
4750 /* first clear the generic function pointer for all ops */
4751 clear_irp_opcodes_generic_func();
4753 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4754 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4792 /* transform ops from intrinsic lowering */
4808 GEN(ia32_l_X87toSSE);
4809 GEN(ia32_l_SSEtoX87);
4815 /* we should never see these nodes */
4830 /* handle generic backend nodes */
4839 op_Mulh = get_op_Mulh();
4848 * Pre-transform all unknown and noreg nodes.
4850 static void ia32_pretransform_node(void *arch_cg) {
4851 ia32_code_gen_t *cg = arch_cg;
4853 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4854 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4855 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4856 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4857 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4858 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4863 * Walker, checks if all ia32 nodes producing more than one result have
4864 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4866 static void add_missing_keep_walker(ir_node *node, void *data)
4869 unsigned found_projs = 0;
4870 const ir_edge_t *edge;
4871 ir_mode *mode = get_irn_mode(node);
4876 if(!is_ia32_irn(node))
4879 n_outs = get_ia32_n_res(node);
4882 if(is_ia32_SwitchJmp(node))
4885 assert(n_outs < (int) sizeof(unsigned) * 8);
4886 foreach_out_edge(node, edge) {
4887 ir_node *proj = get_edge_src_irn(edge);
4888 int pn = get_Proj_proj(proj);
4890 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4891 found_projs |= 1 << pn;
4895 /* are keeps missing? */
4897 for(i = 0; i < n_outs; ++i) {
4900 const arch_register_req_t *req;
4901 const arch_register_class_t *class;
4903 if(found_projs & (1 << i)) {
4907 req = get_ia32_out_req(node, i);
4912 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4916 block = get_nodes_block(node);
4917 in[0] = new_r_Proj(current_ir_graph, block, node,
4918 arch_register_class_mode(class), i);
4919 if(last_keep != NULL) {
4920 be_Keep_add_node(last_keep, class, in[0]);
4922 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4923 if(sched_is_scheduled(node)) {
4924 sched_add_after(node, last_keep);
4931 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4934 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4936 ir_graph *irg = be_get_birg_irg(cg->birg);
4937 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4940 /* do the transformation */
4941 void ia32_transform_graph(ia32_code_gen_t *cg) {
4943 ir_graph *irg = cg->irg;
4944 int opt_arch = cg->isa->opt_arch;
4945 int arch = cg->isa->arch;
4947 /* TODO: look at cpu and fill transform config in with that... */
4948 transform_config.use_incdec = 1;
4949 transform_config.use_sse2 = 0;
4950 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4951 transform_config.use_ftst = 0;
4952 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4953 transform_config.use_fucomi = 1;
4954 transform_config.use_cmov = IS_P6_ARCH(arch);
4956 register_transformers();
4958 initial_fpcw = NULL;
4960 heights = heights_new(irg);
4961 ia32_calculate_non_address_mode_nodes(cg->birg);
4963 /* the transform phase is not safe for CSE (yet) because several nodes get
4964 * attributes set after their creation */
4965 cse_last = get_opt_cse();
4968 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4970 set_opt_cse(cse_last);
4972 ia32_free_non_address_mode_nodes();
4973 heights_free(heights);
4977 void ia32_init_transform(void)
4979 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");