2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *op1, ir_node *op2);
109 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
113 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
116 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 ir_node *op1, ir_node *op2, ir_node *fpcw);
120 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *op);
123 /****************************************************************************************************
125 * | | | | / _| | | (_)
126 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
127 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
128 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
129 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
131 ****************************************************************************************************/
133 static ir_node *try_create_Immediate(ir_node *node,
134 char immediate_constraint_type);
136 static ir_node *create_immediate_or_transform(ir_node *node,
137 char immediate_constraint_type);
139 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
140 dbg_info *dbgi, ir_node *block,
141 ir_node *op, ir_node *orig_node);
144 * Return true if a mode can be stored in the GP register set
146 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
147 if(mode == mode_fpcw)
149 if(get_mode_size_bits(mode) > 32)
151 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
155 * creates a unique ident by adding a number to a tag
157 * @param tag the tag string, must contain a %d if a number
160 static ident *unique_id(const char *tag)
162 static unsigned id = 0;
165 snprintf(str, sizeof(str), tag, ++id);
166 return new_id_from_str(str);
170 * Get a primitive type for a mode.
172 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
174 pmap_entry *e = pmap_find(types, mode);
179 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
180 res = new_type_primitive(new_id_from_str(buf), mode);
181 set_type_alignment_bytes(res, 16);
182 pmap_insert(types, mode, res);
190 * Get an atomic entity that is initialized with a tarval
192 static ir_entity *create_float_const_entity(ir_node *cnst)
194 ia32_isa_t *isa = env_cg->isa;
195 tarval *tv = get_Const_tarval(cnst);
196 pmap_entry *e = pmap_find(isa->tv_ent, tv);
201 ir_mode *mode = get_irn_mode(cnst);
202 ir_type *tp = get_Const_type(cnst);
203 if (tp == firm_unknown_type)
204 tp = get_prim_type(isa->types, mode);
206 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
208 set_entity_ld_ident(res, get_entity_ident(res));
209 set_entity_visibility(res, visibility_local);
210 set_entity_variability(res, variability_constant);
211 set_entity_allocation(res, allocation_static);
213 /* we create a new entity here: It's initialization must resist on the
215 rem = current_ir_graph;
216 current_ir_graph = get_const_code_irg();
217 set_atomic_ent_value(res, new_Const_type(tv, tp));
218 current_ir_graph = rem;
220 pmap_insert(isa->tv_ent, tv, res);
228 static int is_Const_0(ir_node *node) {
229 return is_Const(node) && is_Const_null(node);
232 static int is_Const_1(ir_node *node) {
233 return is_Const(node) && is_Const_one(node);
236 static int is_Const_Minus_1(ir_node *node) {
237 return is_Const(node) && is_Const_all_one(node);
241 * returns true if constant can be created with a simple float command
243 static int is_simple_x87_Const(ir_node *node)
245 tarval *tv = get_Const_tarval(node);
247 if(tarval_is_null(tv) || tarval_is_one(tv))
250 /* TODO: match all the other float constants */
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
271 if (USE_SSE2(env_cg)) {
272 if (is_Const_null(node)) {
273 load = new_rd_ia32_xZero(dbgi, irg, block);
274 set_ia32_ls_mode(load, mode);
277 floatent = create_float_const_entity(node);
279 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
287 if (is_Const_null(node)) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (is_Const_one(node)) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = create_float_const_entity(node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_sc(load, floatent);
299 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
300 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
302 set_ia32_ls_mode(load, mode);
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
307 /* Const Nodes before the initial IncSP are a bad idea, because
308 * they could be spilled and we have no SP ready at that point yet.
309 * So add a dependency to the initial frame pointer calculation to
310 * avoid that situation.
312 if (get_irg_start_block(irg) == block) {
313 add_irn_dep(load, get_irg_frame(irg));
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 tarval *tv = get_Const_tarval(node);
323 tv = tarval_convert_to(tv, mode_Iu);
325 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
327 panic("couldn't convert constant tarval (%+F)", node);
329 val = get_tarval_long(tv);
331 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
332 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
344 * Transforms a SymConst.
346 static ir_node *gen_SymConst(ir_node *node) {
347 ir_graph *irg = current_ir_graph;
348 ir_node *old_block = get_nodes_block(node);
349 ir_node *block = be_transform_node(old_block);
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
355 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
356 ir_node *nomem = new_NoMem();
358 if (USE_SSE2(env_cg))
359 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
361 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 set_ia32_am_sc(cnst, get_SymConst_entity(node));
363 set_ia32_use_frame(cnst);
367 if(get_SymConst_kind(node) != symconst_addr_ent) {
368 panic("backend only support symconst_addr_ent (at %+F)", node);
370 entity = get_SymConst_entity(node);
371 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
374 /* Const Nodes before the initial IncSP are a bad idea, because
375 * they could be spilled and we have no SP ready at that point yet
377 if (get_irg_start_block(irg) == block) {
378 add_irn_dep(cnst, get_irg_frame(irg));
381 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
386 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
387 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
388 static const struct {
390 const char *ent_name;
391 const char *cnst_str;
394 } names [ia32_known_const_max] = {
395 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
396 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
397 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
398 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
399 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
401 static ir_entity *ent_cache[ia32_known_const_max];
403 const char *tp_name, *ent_name, *cnst_str;
411 ent_name = names[kct].ent_name;
412 if (! ent_cache[kct]) {
413 tp_name = names[kct].tp_name;
414 cnst_str = names[kct].cnst_str;
416 switch (names[kct].mode) {
417 case 0: mode = mode_Iu; break;
418 case 1: mode = mode_Lu; break;
419 default: mode = mode_F; break;
421 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
422 tp = new_type_primitive(new_id_from_str(tp_name), mode);
423 /* set the specified alignment */
424 set_type_alignment_bytes(tp, names[kct].align);
426 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
428 set_entity_ld_ident(ent, get_entity_ident(ent));
429 set_entity_visibility(ent, visibility_local);
430 set_entity_variability(ent, variability_constant);
431 set_entity_allocation(ent, allocation_static);
433 /* we create a new entity here: It's initialization must resist on the
435 rem = current_ir_graph;
436 current_ir_graph = get_const_code_irg();
437 cnst = new_Const(mode, tv);
438 current_ir_graph = rem;
440 set_atomic_ent_value(ent, cnst);
442 /* cache the entry */
443 ent_cache[kct] = ent;
446 return ent_cache[kct];
451 * Prints the old node name on cg obst and returns a pointer to it.
453 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
454 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
456 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
457 obstack_1grow(isa->name_obst, 0);
458 return obstack_finish(isa->name_obst);
462 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
464 ir_mode *mode = get_irn_mode(node);
468 /* float constants are always available */
469 if(is_Const(node) && mode_is_float(mode)
470 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
476 load = get_Proj_pred(node);
477 pn = get_Proj_proj(node);
478 if(!is_Load(load) || pn != pn_Load_res)
480 if(get_nodes_block(load) != block)
482 /* we only use address mode if we're the only user of the load */
483 if(get_irn_n_edges(node) > 1)
486 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
489 /* don't do AM if other node inputs depend on the load (via mem-proj) */
490 if(other != NULL && get_nodes_block(other) == block
491 && heights_reachable_in_block(heights, other, load))
497 typedef struct ia32_address_mode_t ia32_address_mode_t;
498 struct ia32_address_mode_t {
502 ia32_op_type_t op_type;
509 static void build_address(ia32_address_mode_t *am, ir_node *node)
511 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
512 ia32_address_t *addr = &am->addr;
521 ir_entity *entity = create_float_const_entity(node);
522 addr->base = noreg_gp;
523 addr->index = noreg_gp;
524 addr->mem = new_NoMem();
525 addr->symconst_ent = entity;
527 am->ls_mode = get_irn_mode(node);
531 load = get_Proj_pred(node);
532 ptr = get_Load_ptr(load);
533 mem = get_Load_mem(load);
534 new_mem = be_transform_node(mem);
535 am->ls_mode = get_Load_mode(load);
536 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
538 /* construct load address */
539 ia32_create_address_mode(addr, ptr, 0);
546 base = be_transform_node(base);
552 index = be_transform_node(index);
560 static void set_address(ir_node *node, ia32_address_t *addr)
562 set_ia32_am_scale(node, addr->scale);
563 set_ia32_am_sc(node, addr->symconst_ent);
564 set_ia32_am_offs_int(node, addr->offset);
565 if(addr->symconst_sign)
566 set_ia32_am_sc_sign(node);
568 set_ia32_use_frame(node);
569 set_ia32_frame_ent(node, addr->frame_entity);
572 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
574 set_address(node, &am->addr);
576 set_ia32_op_type(node, am->op_type);
577 set_ia32_ls_mode(node, am->ls_mode);
579 set_ia32_commutative(node);
583 match_commutative = 1 << 0,
584 match_am_and_immediates = 1 << 1,
585 match_no_am = 1 << 2,
586 match_8_bit_am = 1 << 3,
587 match_16_bit_am = 1 << 4,
588 match_no_immediate = 1 << 5
591 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
592 ir_node *op1, ir_node *op2, match_flags_t flags)
594 ia32_address_t *addr = &am->addr;
595 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
598 ir_mode *mode = get_irn_mode(op2);
601 int use_am_and_immediates;
603 int mode_bits = get_mode_size_bits(mode);
605 memset(am, 0, sizeof(am[0]));
607 commutative = (flags & match_commutative) != 0;
608 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
609 use_am = ! (flags & match_no_am);
610 use_immediate = !(flags & match_no_immediate);
613 assert(!commutative || op1 != NULL);
615 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
617 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
621 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
622 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
623 build_address(am, op2);
624 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
625 if(mode_is_float(mode)) {
626 new_op2 = ia32_new_NoReg_vfp(env_cg);
630 am->op_type = ia32_AddrModeS;
631 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
632 use_am && use_source_address_mode(block, op1, op2)) {
634 build_address(am, op1);
636 if(mode_is_float(mode)) {
637 noreg = ia32_new_NoReg_vfp(env_cg);
642 if(new_op2 != NULL) {
645 new_op1 = be_transform_node(op2);
649 am->op_type = ia32_AddrModeS;
651 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
653 new_op2 = be_transform_node(op2);
654 am->op_type = ia32_Normal;
655 am->ls_mode = get_irn_mode(op2);
657 if(addr->base == NULL)
658 addr->base = noreg_gp;
659 if(addr->index == NULL)
660 addr->index = noreg_gp;
661 if(addr->mem == NULL)
662 addr->mem = new_NoMem();
664 am->new_op1 = new_op1;
665 am->new_op2 = new_op2;
666 am->commutative = commutative;
669 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
671 ir_graph *irg = current_ir_graph;
675 if(am->mem_proj == NULL)
678 /* we have to create a mode_T so the old MemProj can attach to us */
679 mode = get_irn_mode(node);
680 load = get_Proj_pred(am->mem_proj);
682 mark_irn_visited(load);
683 be_set_transformed_node(load, node);
686 set_irn_mode(node, mode_T);
687 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
694 * Construct a standard binary operation, set AM and immediate if required.
696 * @param op1 The first operand
697 * @param op2 The second operand
698 * @param func The node constructor function
699 * @return The constructed ia32 node.
701 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
702 construct_binop_func *func, int commutative)
704 ir_node *block = get_nodes_block(node);
705 ir_node *new_block = be_transform_node(block);
706 ir_graph *irg = current_ir_graph;
707 dbg_info *dbgi = get_irn_dbg_info(node);
709 ia32_address_mode_t am;
710 ia32_address_t *addr = &am.addr;
711 match_flags_t flags = 0;
714 flags |= match_commutative;
716 match_arguments(&am, block, op1, op2, flags);
718 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
719 am.new_op1, am.new_op2);
720 set_am_attributes(new_node, &am);
721 /* we can't use source address mode anymore when using immediates */
722 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
723 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
724 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
726 new_node = fix_mem_proj(new_node, &am);
732 * Construct a standard binary operation, set AM and immediate if required.
734 * @param op1 The first operand
735 * @param op2 The second operand
736 * @param func The node constructor function
737 * @return The constructed ia32 node.
739 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
740 construct_binop_func *func,
743 ir_node *block = get_nodes_block(node);
744 ir_node *new_block = be_transform_node(block);
745 dbg_info *dbgi = get_irn_dbg_info(node);
746 ir_graph *irg = current_ir_graph;
748 ia32_address_mode_t am;
749 ia32_address_t *addr = &am.addr;
750 match_flags_t flags = 0;
753 flags |= match_commutative;
755 match_arguments(&am, block, op1, op2, flags);
757 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
758 am.new_op1, am.new_op2);
759 set_am_attributes(new_node, &am);
761 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
763 new_node = fix_mem_proj(new_node, &am);
768 static ir_node *get_fpcw(void)
771 if(initial_fpcw != NULL)
774 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
775 &ia32_fp_cw_regs[REG_FPCW]);
776 initial_fpcw = be_transform_node(fpcw);
782 * Construct a standard binary operation, set AM and immediate if required.
784 * @param op1 The first operand
785 * @param op2 The second operand
786 * @param func The node constructor function
787 * @return The constructed ia32 node.
789 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
790 construct_binop_float_func *func,
793 ir_graph *irg = current_ir_graph;
794 dbg_info *dbgi = get_irn_dbg_info(node);
795 ir_node *block = get_nodes_block(node);
796 ir_node *new_block = be_transform_node(block);
798 ia32_address_mode_t am;
799 ia32_address_t *addr = &am.addr;
800 match_flags_t flags = 0;
803 flags |= match_commutative;
805 match_arguments(&am, block, op1, op2, flags);
807 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
808 am.new_op1, am.new_op2, get_fpcw());
809 set_am_attributes(new_node, &am);
811 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
813 new_node = fix_mem_proj(new_node, &am);
819 * Construct a shift/rotate binary operation, sets AM and immediate if required.
821 * @param op1 The first operand
822 * @param op2 The second operand
823 * @param func The node constructor function
824 * @return The constructed ia32 node.
826 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
827 construct_shift_func *func)
829 dbg_info *dbgi = get_irn_dbg_info(node);
830 ir_graph *irg = current_ir_graph;
831 ir_node *block = get_nodes_block(node);
832 ir_node *new_block = be_transform_node(block);
833 ir_node *new_op1 = be_transform_node(op1);
834 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
837 assert(! mode_is_float(get_irn_mode(node))
838 && "Shift/Rotate with float not supported");
840 res = func(dbgi, irg, new_block, new_op1, new_op2);
841 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
843 /* lowered shift instruction may have a dependency operand, handle it here */
844 if (get_irn_arity(node) == 3) {
845 /* we have a dependency */
846 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
847 add_irn_dep(res, new_dep);
855 * Construct a standard unary operation, set AM and immediate if required.
857 * @param op The operand
858 * @param func The node constructor function
859 * @return The constructed ia32 node.
861 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
863 ir_node *block = be_transform_node(get_nodes_block(node));
864 ir_node *new_op = be_transform_node(op);
865 ir_node *new_node = NULL;
866 ir_graph *irg = current_ir_graph;
867 dbg_info *dbgi = get_irn_dbg_info(node);
869 new_node = func(dbgi, irg, block, new_op);
871 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
876 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
877 ia32_address_t *addr)
879 ir_graph *irg = current_ir_graph;
880 ir_node *base = addr->base;
881 ir_node *index = addr->index;
885 base = ia32_new_NoReg_gp(env_cg);
887 base = be_transform_node(base);
891 index = ia32_new_NoReg_gp(env_cg);
893 index = be_transform_node(index);
896 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
897 set_address(res, addr);
902 static int am_has_immediates(const ia32_address_t *addr)
904 return addr->offset != 0 || addr->symconst_ent != NULL
905 || addr->frame_entity || addr->use_frame;
909 * Creates an ia32 Add.
911 * @return the created ia32 Add node
913 static ir_node *gen_Add(ir_node *node) {
914 ir_graph *irg = current_ir_graph;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *block = get_nodes_block(node);
917 ir_node *new_block = be_transform_node(block);
918 ir_node *op1 = get_Add_left(node);
919 ir_node *op2 = get_Add_right(node);
920 ir_mode *mode = get_irn_mode(node);
921 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
924 ir_node *add_immediate_op;
926 ia32_address_mode_t am;
928 if (mode_is_float(mode)) {
929 if (USE_SSE2(env_cg))
930 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, 1);
932 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, 1);
937 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
938 * 1. Add with immediate -> Lea
939 * 2. Add with possible source address mode -> Add
940 * 3. Otherwise -> Lea
942 memset(&addr, 0, sizeof(addr));
943 ia32_create_address_mode(&addr, node, 1);
944 add_immediate_op = NULL;
946 if(addr.base == NULL && addr.index == NULL) {
947 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
948 addr.symconst_sign, addr.offset);
949 add_irn_dep(new_node, get_irg_frame(irg));
950 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
953 /* add with immediate? */
954 if(addr.index == NULL) {
955 add_immediate_op = addr.base;
956 } else if(addr.base == NULL && addr.scale == 0) {
957 add_immediate_op = addr.index;
960 if(add_immediate_op != NULL) {
961 if(!am_has_immediates(&addr)) {
963 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
966 return be_transform_node(add_immediate_op);
969 new_node = create_lea_from_address(dbgi, new_block, &addr);
970 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
974 /* test if we can use source address mode */
975 memset(&am, 0, sizeof(am));
977 if(use_source_address_mode(block, op2, op1)) {
978 build_address(&am, op2);
979 new_op1 = be_transform_node(op1);
980 } else if(use_source_address_mode(block, op1, op2)) {
981 build_address(&am, op1);
982 new_op1 = be_transform_node(op2);
984 /* construct an Add with source address mode */
985 if(new_op1 != NULL) {
986 ia32_address_t *am_addr = &am.addr;
987 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
988 am_addr->index, am_addr->mem, new_op1, noreg);
989 set_address(new_node, am_addr);
990 set_ia32_op_type(new_node, ia32_AddrModeS);
991 set_ia32_ls_mode(new_node, am.ls_mode);
992 set_ia32_commutative(new_node);
993 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
995 new_node = fix_mem_proj(new_node, &am);
1000 /* otherwise construct a lea */
1001 new_node = create_lea_from_address(dbgi, new_block, &addr);
1002 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1007 * Creates an ia32 Mul.
1009 * @return the created ia32 Mul node
1011 static ir_node *gen_Mul(ir_node *node) {
1012 ir_node *op1 = get_Mul_left(node);
1013 ir_node *op2 = get_Mul_right(node);
1014 ir_mode *mode = get_irn_mode(node);
1016 if (mode_is_float(mode)) {
1017 if (USE_SSE2(env_cg))
1018 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, 1);
1020 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, 1);
1024 for the lower 32bit of the result it doesn't matter whether we use
1025 signed or unsigned multiplication so we use IMul as it has fewer
1028 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
1032 * Creates an ia32 Mulh.
1033 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1034 * this result while Mul returns the lower 32 bit.
1036 * @return the created ia32 Mulh node
1038 static ir_node *gen_Mulh(ir_node *node) {
1039 ir_node *block = be_transform_node(get_nodes_block(node));
1040 ir_node *op1 = get_irn_n(node, 0);
1041 ir_node *new_op1 = be_transform_node(op1);
1042 ir_node *op2 = get_irn_n(node, 1);
1043 ir_node *new_op2 = be_transform_node(op2);
1044 ir_graph *irg = current_ir_graph;
1045 dbg_info *dbgi = get_irn_dbg_info(node);
1046 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1047 ir_mode *mode = get_irn_mode(node);
1048 ir_node *proj_EDX, *res;
1050 assert(!mode_is_float(mode) && "Mulh with float not supported");
1051 if (mode_is_signed(mode)) {
1052 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
1055 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1059 set_ia32_commutative(res);
1061 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1069 * Creates an ia32 And.
1071 * @return The created ia32 And node
1073 static ir_node *gen_And(ir_node *node) {
1074 ir_node *op1 = get_And_left(node);
1075 ir_node *op2 = get_And_right(node);
1076 assert(! mode_is_float(get_irn_mode(node)));
1078 /* is it a zero extension? */
1079 if (is_Const(op2)) {
1080 tarval *tv = get_Const_tarval(op2);
1081 long v = get_tarval_long(tv);
1083 if (v == 0xFF || v == 0xFFFF) {
1084 dbg_info *dbgi = get_irn_dbg_info(node);
1085 ir_node *block = get_nodes_block(node);
1092 assert(v == 0xFFFF);
1095 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1101 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1107 * Creates an ia32 Or.
1109 * @return The created ia32 Or node
1111 static ir_node *gen_Or(ir_node *node) {
1112 ir_node *op1 = get_Or_left(node);
1113 ir_node *op2 = get_Or_right(node);
1115 assert (! mode_is_float(get_irn_mode(node)));
1116 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1122 * Creates an ia32 Eor.
1124 * @return The created ia32 Eor node
1126 static ir_node *gen_Eor(ir_node *node) {
1127 ir_node *op1 = get_Eor_left(node);
1128 ir_node *op2 = get_Eor_right(node);
1130 assert(! mode_is_float(get_irn_mode(node)));
1131 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1136 * Creates an ia32 Sub.
1138 * @return The created ia32 Sub node
1140 static ir_node *gen_Sub(ir_node *node) {
1141 ir_node *op1 = get_Sub_left(node);
1142 ir_node *op2 = get_Sub_right(node);
1143 ir_mode *mode = get_irn_mode(node);
1145 if (mode_is_float(mode)) {
1146 if (USE_SSE2(env_cg))
1147 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1149 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1153 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1157 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1163 * Generates an ia32 DivMod with additional infrastructure for the
1164 * register allocator if needed.
1166 * @param dividend -no comment- :)
1167 * @param divisor -no comment- :)
1168 * @param dm_flav flavour_Div/Mod/DivMod
1169 * @return The created ia32 DivMod node
1171 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1172 ir_node *divisor, ia32_op_flavour_t dm_flav)
1174 ir_node *block = be_transform_node(get_nodes_block(node));
1175 ir_node *new_dividend = be_transform_node(dividend);
1176 ir_node *new_divisor = be_transform_node(divisor);
1177 ir_graph *irg = current_ir_graph;
1178 dbg_info *dbgi = get_irn_dbg_info(node);
1179 ir_mode *mode = get_irn_mode(node);
1180 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1181 ir_node *res, *proj_div, *proj_mod;
1182 ir_node *sign_extension;
1183 ir_node *mem, *new_mem;
1186 proj_div = proj_mod = NULL;
1190 mem = get_Div_mem(node);
1191 mode = get_Div_resmode(node);
1192 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1193 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1196 mem = get_Mod_mem(node);
1197 mode = get_Mod_resmode(node);
1198 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1199 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1201 case flavour_DivMod:
1202 mem = get_DivMod_mem(node);
1203 mode = get_DivMod_resmode(node);
1204 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1205 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1206 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1209 panic("invalid divmod flavour!");
1211 new_mem = be_transform_node(mem);
1213 if (mode_is_signed(mode)) {
1214 /* in signed mode, we need to sign extend the dividend */
1215 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1216 add_irn_dep(produceval, get_irg_frame(irg));
1217 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1220 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1221 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1222 add_irn_dep(sign_extension, get_irg_frame(irg));
1225 if (mode_is_signed(mode)) {
1226 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1227 new_dividend, sign_extension, new_divisor, dm_flav);
1229 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1230 sign_extension, new_divisor, dm_flav);
1233 set_ia32_exc_label(res, has_exc);
1234 set_irn_pinned(res, get_irn_pinned(node));
1236 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1243 * Wrapper for generate_DivMod. Sets flavour_Mod.
1246 static ir_node *gen_Mod(ir_node *node) {
1247 return generate_DivMod(node, get_Mod_left(node),
1248 get_Mod_right(node), flavour_Mod);
1252 * Wrapper for generate_DivMod. Sets flavour_Div.
1255 static ir_node *gen_Div(ir_node *node) {
1256 return generate_DivMod(node, get_Div_left(node),
1257 get_Div_right(node), flavour_Div);
1261 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1263 static ir_node *gen_DivMod(ir_node *node) {
1264 return generate_DivMod(node, get_DivMod_left(node),
1265 get_DivMod_right(node), flavour_DivMod);
1271 * Creates an ia32 floating Div.
1273 * @return The created ia32 xDiv node
1275 static ir_node *gen_Quot(ir_node *node)
1277 ir_node *op1 = get_Quot_left(node);
1278 ir_node *op2 = get_Quot_right(node);
1280 if (USE_SSE2(env_cg)) {
1281 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1283 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1289 * Creates an ia32 Shl.
1291 * @return The created ia32 Shl node
1293 static ir_node *gen_Shl(ir_node *node) {
1294 ir_node *right = get_Shl_right(node);
1296 /* test whether we can build a lea */
1297 if(is_Const(right)) {
1298 tarval *tv = get_Const_tarval(right);
1299 if(tarval_is_long(tv)) {
1300 long val = get_tarval_long(tv);
1301 if(val >= 0 && val <= 3) {
1302 ir_graph *irg = current_ir_graph;
1303 dbg_info *dbgi = get_irn_dbg_info(node);
1304 ir_node *block = be_transform_node(get_nodes_block(node));
1305 ir_node *base = ia32_new_NoReg_gp(env_cg);
1306 ir_node *index = be_transform_node(get_Shl_left(node));
1307 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1308 set_ia32_am_scale(res, val);
1309 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1315 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1322 * Creates an ia32 Shr.
1324 * @return The created ia32 Shr node
1326 static ir_node *gen_Shr(ir_node *node) {
1327 return gen_shift_binop(node, get_Shr_left(node),
1328 get_Shr_right(node), new_rd_ia32_Shr);
1334 * Creates an ia32 Sar.
1336 * @return The created ia32 Shrs node
1338 static ir_node *gen_Shrs(ir_node *node) {
1339 ir_node *left = get_Shrs_left(node);
1340 ir_node *right = get_Shrs_right(node);
1341 ir_mode *mode = get_irn_mode(node);
1342 if(is_Const(right) && mode == mode_Is) {
1343 tarval *tv = get_Const_tarval(right);
1344 long val = get_tarval_long(tv);
1346 /* this is a sign extension */
1347 ir_graph *irg = current_ir_graph;
1348 dbg_info *dbgi = get_irn_dbg_info(node);
1349 ir_node *block = be_transform_node(get_nodes_block(node));
1351 ir_node *new_op = be_transform_node(op);
1352 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1353 add_irn_dep(pval, get_irg_frame(irg));
1355 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1359 /* 8 or 16 bit sign extension? */
1360 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1361 ir_node *shl_left = get_Shl_left(left);
1362 ir_node *shl_right = get_Shl_right(left);
1363 if(is_Const(shl_right)) {
1364 tarval *tv1 = get_Const_tarval(right);
1365 tarval *tv2 = get_Const_tarval(shl_right);
1366 if(tv1 == tv2 && tarval_is_long(tv1)) {
1367 long val = get_tarval_long(tv1);
1368 if(val == 16 || val == 24) {
1369 dbg_info *dbgi = get_irn_dbg_info(node);
1370 ir_node *block = get_nodes_block(node);
1380 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1389 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1395 * Creates an ia32 RotL.
1397 * @param op1 The first operator
1398 * @param op2 The second operator
1399 * @return The created ia32 RotL node
1401 static ir_node *gen_RotL(ir_node *node,
1402 ir_node *op1, ir_node *op2) {
1403 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1409 * Creates an ia32 RotR.
1410 * NOTE: There is no RotR with immediate because this would always be a RotL
1411 * "imm-mode_size_bits" which can be pre-calculated.
1413 * @param op1 The first operator
1414 * @param op2 The second operator
1415 * @return The created ia32 RotR node
1417 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1419 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1425 * Creates an ia32 RotR or RotL (depending on the found pattern).
1427 * @return The created ia32 RotL or RotR node
1429 static ir_node *gen_Rot(ir_node *node) {
1430 ir_node *rotate = NULL;
1431 ir_node *op1 = get_Rot_left(node);
1432 ir_node *op2 = get_Rot_right(node);
1434 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1435 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1436 that means we can create a RotR instead of an Add and a RotL */
1438 if (get_irn_op(op2) == op_Add) {
1440 ir_node *left = get_Add_left(add);
1441 ir_node *right = get_Add_right(add);
1442 if (is_Const(right)) {
1443 tarval *tv = get_Const_tarval(right);
1444 ir_mode *mode = get_irn_mode(node);
1445 long bits = get_mode_size_bits(mode);
1447 if (get_irn_op(left) == op_Minus &&
1448 tarval_is_long(tv) &&
1449 get_tarval_long(tv) == bits)
1451 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1452 rotate = gen_RotR(node, op1, get_Minus_op(left));
1457 if (rotate == NULL) {
1458 rotate = gen_RotL(node, op1, op2);
1467 * Transforms a Minus node.
1469 * @return The created ia32 Minus node
1471 static ir_node *gen_Minus(ir_node *node)
1473 ir_node *op = get_Minus_op(node);
1474 ir_node *block = be_transform_node(get_nodes_block(node));
1475 ir_graph *irg = current_ir_graph;
1476 dbg_info *dbgi = get_irn_dbg_info(node);
1477 ir_mode *mode = get_irn_mode(node);
1482 if (mode_is_float(mode)) {
1483 ir_node *new_op = be_transform_node(op);
1484 if (USE_SSE2(env_cg)) {
1485 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1486 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1487 ir_node *nomem = new_rd_NoMem(irg);
1489 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1492 size = get_mode_size_bits(mode);
1493 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1495 set_ia32_am_sc(res, ent);
1496 set_ia32_op_type(res, ia32_AddrModeS);
1497 set_ia32_ls_mode(res, mode);
1499 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1502 res = gen_unop(node, op, new_rd_ia32_Neg);
1505 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1511 * Transforms a Not node.
1513 * @return The created ia32 Not node
1515 static ir_node *gen_Not(ir_node *node) {
1516 ir_node *op = get_Not_op(node);
1517 ir_mode *mode = get_irn_mode(node);
1519 assert(mode != mode_b); /* should be lowered already */
1521 assert (! mode_is_float(get_irn_mode(node)));
1522 return gen_unop(node, op, new_rd_ia32_Not);
1528 * Transforms an Abs node.
1530 * @return The created ia32 Abs node
1532 static ir_node *gen_Abs(ir_node *node)
1534 ir_node *block = be_transform_node(get_nodes_block(node));
1535 ir_node *op = get_Abs_op(node);
1536 ir_node *new_op = be_transform_node(op);
1537 ir_graph *irg = current_ir_graph;
1538 dbg_info *dbgi = get_irn_dbg_info(node);
1539 ir_mode *mode = get_irn_mode(node);
1540 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1541 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1542 ir_node *nomem = new_NoMem();
1547 if (mode_is_float(mode)) {
1548 if (USE_SSE2(env_cg)) {
1549 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1551 size = get_mode_size_bits(mode);
1552 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1554 set_ia32_am_sc(res, ent);
1556 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1558 set_ia32_op_type(res, ia32_AddrModeS);
1559 set_ia32_ls_mode(res, mode);
1561 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1562 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1566 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1567 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1570 add_irn_dep(pval, get_irg_frame(irg));
1571 SET_IA32_ORIG_NODE(sign_extension,
1572 ia32_get_old_node_name(env_cg, node));
1574 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1576 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1578 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1580 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1587 * Transforms a Load.
1589 * @return the created ia32 Load node
1591 static ir_node *gen_Load(ir_node *node) {
1592 ir_node *old_block = get_nodes_block(node);
1593 ir_node *block = be_transform_node(old_block);
1594 ir_node *ptr = get_Load_ptr(node);
1595 ir_node *mem = get_Load_mem(node);
1596 ir_node *new_mem = be_transform_node(mem);
1599 ir_graph *irg = current_ir_graph;
1600 dbg_info *dbgi = get_irn_dbg_info(node);
1601 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1602 ir_mode *mode = get_Load_mode(node);
1605 ia32_address_t addr;
1607 /* construct load address */
1608 memset(&addr, 0, sizeof(addr));
1609 ia32_create_address_mode(&addr, ptr, 0);
1616 base = be_transform_node(base);
1622 index = be_transform_node(index);
1625 if (mode_is_float(mode)) {
1626 if (USE_SSE2(env_cg)) {
1627 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1629 res_mode = mode_xmm;
1631 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1633 res_mode = mode_vfp;
1639 /* create a conv node with address mode for smaller modes */
1640 if(get_mode_size_bits(mode) < 32) {
1641 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1642 new_mem, noreg, mode);
1644 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1649 set_irn_pinned(new_op, get_irn_pinned(node));
1650 set_ia32_op_type(new_op, ia32_AddrModeS);
1651 set_ia32_ls_mode(new_op, mode);
1652 set_address(new_op, &addr);
1654 /* make sure we are scheduled behind the initial IncSP/Barrier
1655 * to avoid spills being placed before it
1657 if (block == get_irg_start_block(irg)) {
1658 add_irn_dep(new_op, get_irg_frame(irg));
1661 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1662 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1667 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1668 ir_node *ptr, ir_mode *mode, ir_node *other)
1675 /* we only use address mode if we're the only user of the load */
1676 if(get_irn_n_edges(node) > 1)
1679 load = get_Proj_pred(node);
1682 if(get_nodes_block(load) != block)
1685 /* Store should be attached to the load */
1686 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1688 /* store should have the same pointer as the load */
1689 if(get_Load_ptr(load) != ptr)
1692 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1693 if(other != NULL && get_nodes_block(other) == block
1694 && heights_reachable_in_block(heights, other, load))
1697 assert(get_Load_mode(load) == mode);
1702 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1703 ir_node *mem, ir_node *ptr, ir_mode *mode,
1704 construct_binop_dest_func *func,
1705 construct_binop_dest_func *func8bit,
1708 ir_node *src_block = get_nodes_block(node);
1710 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1711 ir_graph *irg = current_ir_graph;
1715 ia32_address_mode_t am;
1716 ia32_address_t *addr = &am.addr;
1717 memset(&am, 0, sizeof(am));
1719 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1720 build_address(&am, op1);
1721 new_op = create_immediate_or_transform(op2, 0);
1722 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1723 build_address(&am, op2);
1724 new_op = create_immediate_or_transform(op1, 0);
1729 if(addr->base == NULL)
1730 addr->base = noreg_gp;
1731 if(addr->index == NULL)
1732 addr->index = noreg_gp;
1733 if(addr->mem == NULL)
1734 addr->mem = new_NoMem();
1736 dbgi = get_irn_dbg_info(node);
1737 block = be_transform_node(src_block);
1738 if(get_mode_size_bits(mode) == 8) {
1739 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1742 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1745 set_address(new_node, addr);
1746 set_ia32_op_type(new_node, ia32_AddrModeD);
1747 set_ia32_ls_mode(new_node, mode);
1748 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1753 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1754 ir_node *ptr, ir_mode *mode,
1755 construct_unop_dest_func *func)
1757 ir_node *src_block = get_nodes_block(node);
1759 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1760 ir_graph *irg = current_ir_graph;
1763 ia32_address_mode_t am;
1764 ia32_address_t *addr = &am.addr;
1765 memset(&am, 0, sizeof(am));
1767 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1770 build_address(&am, op);
1772 if(addr->base == NULL)
1773 addr->base = noreg_gp;
1774 if(addr->index == NULL)
1775 addr->index = noreg_gp;
1776 if(addr->mem == NULL)
1777 addr->mem = new_NoMem();
1779 dbgi = get_irn_dbg_info(node);
1780 block = be_transform_node(src_block);
1781 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1782 set_address(new_node, addr);
1783 set_ia32_op_type(new_node, ia32_AddrModeD);
1784 set_ia32_ls_mode(new_node, mode);
1785 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1790 static ir_node *try_create_dest_am(ir_node *node) {
1791 ir_node *val = get_Store_value(node);
1792 ir_node *mem = get_Store_mem(node);
1793 ir_node *ptr = get_Store_ptr(node);
1794 ir_mode *mode = get_irn_mode(val);
1799 /* handle only GP modes for now... */
1800 if(!mode_needs_gp_reg(mode))
1803 /* store must be the only user of the val node */
1804 if(get_irn_n_edges(val) > 1)
1807 switch(get_irn_opcode(val)) {
1809 op1 = get_Add_left(val);
1810 op2 = get_Add_right(val);
1811 if(is_Const_1(op2)) {
1812 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1813 new_rd_ia32_IncMem);
1815 } else if(is_Const_Minus_1(op2)) {
1816 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1817 new_rd_ia32_DecMem);
1820 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1821 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1824 op1 = get_Sub_left(val);
1825 op2 = get_Sub_right(val);
1827 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1830 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1831 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1834 op1 = get_And_left(val);
1835 op2 = get_And_right(val);
1836 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1837 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1840 op1 = get_Or_left(val);
1841 op2 = get_Or_right(val);
1842 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1843 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1846 op1 = get_Eor_left(val);
1847 op2 = get_Eor_right(val);
1848 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1849 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1852 op1 = get_Shl_left(val);
1853 op2 = get_Shl_right(val);
1854 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1855 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1858 op1 = get_Shr_left(val);
1859 op2 = get_Shr_right(val);
1860 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1861 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1864 op1 = get_Shrs_left(val);
1865 op2 = get_Shrs_right(val);
1866 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1867 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1870 op1 = get_Rot_left(val);
1871 op2 = get_Rot_right(val);
1872 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1873 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1875 /* TODO: match ROR patterns... */
1877 op1 = get_Minus_op(val);
1878 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1881 /* should be lowered already */
1882 assert(mode != mode_b);
1883 op1 = get_Not_op(val);
1884 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1894 * Transforms a Store.
1896 * @return the created ia32 Store node
1898 static ir_node *gen_Store(ir_node *node) {
1899 ir_node *block = be_transform_node(get_nodes_block(node));
1900 ir_node *ptr = get_Store_ptr(node);
1903 ir_node *val = get_Store_value(node);
1905 ir_node *mem = get_Store_mem(node);
1906 ir_node *new_mem = be_transform_node(mem);
1907 ir_graph *irg = current_ir_graph;
1908 dbg_info *dbgi = get_irn_dbg_info(node);
1909 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1910 ir_mode *mode = get_irn_mode(val);
1912 ia32_address_t addr;
1914 /* check for destination address mode */
1915 new_op = try_create_dest_am(node);
1919 /* construct store address */
1920 memset(&addr, 0, sizeof(addr));
1921 ia32_create_address_mode(&addr, ptr, 0);
1928 base = be_transform_node(base);
1934 index = be_transform_node(index);
1937 if (mode_is_float(mode)) {
1938 new_val = be_transform_node(val);
1939 if (USE_SSE2(env_cg)) {
1940 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1943 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1947 new_val = create_immediate_or_transform(val, 0);
1951 if (get_mode_size_bits(mode) == 8) {
1952 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1955 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1960 set_irn_pinned(new_op, get_irn_pinned(node));
1961 set_ia32_op_type(new_op, ia32_AddrModeD);
1962 set_ia32_ls_mode(new_op, mode);
1964 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1965 set_address(new_op, &addr);
1966 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1971 static ir_node *create_Switch(ir_node *node)
1973 ir_graph *irg = current_ir_graph;
1974 dbg_info *dbgi = get_irn_dbg_info(node);
1975 ir_node *block = be_transform_node(get_nodes_block(node));
1976 ir_node *sel = get_Cond_selector(node);
1977 ir_node *new_sel = be_transform_node(sel);
1979 int switch_min = INT_MAX;
1980 const ir_edge_t *edge;
1982 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1984 /* determine the smallest switch case value */
1985 foreach_out_edge(node, edge) {
1986 ir_node *proj = get_edge_src_irn(edge);
1987 int pn = get_Proj_proj(proj);
1992 if (switch_min != 0) {
1993 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1995 /* if smallest switch case is not 0 we need an additional sub */
1996 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1997 add_ia32_am_offs_int(new_sel, -switch_min);
1998 set_ia32_op_type(new_sel, ia32_AddrModeS);
2000 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2003 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2004 set_ia32_pncode(res, get_Cond_defaultProj(node));
2006 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2011 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2013 ir_graph *irg = current_ir_graph;
2021 /* we have a Cmp as input */
2023 ir_node *pred = get_Proj_pred(node);
2025 flags = be_transform_node(pred);
2026 *pnc_out = get_Proj_proj(node);
2031 /* a mode_b value, we have to compare it against 0 */
2032 dbgi = get_irn_dbg_info(node);
2033 new_block = be_transform_node(get_nodes_block(node));
2034 new_op = be_transform_node(node);
2035 noreg = ia32_new_NoReg_gp(env_cg);
2036 nomem = new_NoMem();
2037 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2038 new_op, new_op, 0, 0);
2039 *pnc_out = pn_Cmp_Lg;
2043 static ir_node *gen_Cond(ir_node *node) {
2044 ir_node *block = get_nodes_block(node);
2045 ir_node *new_block = be_transform_node(block);
2046 ir_graph *irg = current_ir_graph;
2047 dbg_info *dbgi = get_irn_dbg_info(node);
2048 ir_node *sel = get_Cond_selector(node);
2049 ir_mode *sel_mode = get_irn_mode(sel);
2051 ir_node *flags = NULL;
2054 if (sel_mode != mode_b) {
2055 return create_Switch(node);
2058 /* we get flags from a cmp */
2059 flags = get_flags_node(sel, &pnc);
2061 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2062 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2070 * Transforms a CopyB node.
2072 * @return The transformed node.
2074 static ir_node *gen_CopyB(ir_node *node) {
2075 ir_node *block = be_transform_node(get_nodes_block(node));
2076 ir_node *src = get_CopyB_src(node);
2077 ir_node *new_src = be_transform_node(src);
2078 ir_node *dst = get_CopyB_dst(node);
2079 ir_node *new_dst = be_transform_node(dst);
2080 ir_node *mem = get_CopyB_mem(node);
2081 ir_node *new_mem = be_transform_node(mem);
2082 ir_node *res = NULL;
2083 ir_graph *irg = current_ir_graph;
2084 dbg_info *dbgi = get_irn_dbg_info(node);
2085 int size = get_type_size_bytes(get_CopyB_type(node));
2088 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2089 /* then we need the size explicitly in ECX. */
2090 if (size >= 32 * 4) {
2091 rem = size & 0x3; /* size % 4 */
2094 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2096 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2098 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2100 add_irn_dep(res, get_irg_frame(irg));
2102 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2103 /* we misuse the pncode field for the copyb size */
2104 set_ia32_pncode(res, rem);
2106 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2107 set_ia32_pncode(res, size);
2110 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2115 static ir_node *gen_be_Copy(ir_node *node)
2117 ir_node *result = be_duplicate_node(node);
2118 ir_mode *mode = get_irn_mode(result);
2120 if (mode_needs_gp_reg(mode)) {
2121 set_irn_mode(result, mode_Iu);
2128 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2129 * to fold an and into a test node
2131 static int can_fold_test_and(ir_node *node)
2133 const ir_edge_t *edge;
2135 /** we can only have eq and lg projs */
2136 foreach_out_edge(node, edge) {
2137 ir_node *proj = get_edge_src_irn(edge);
2138 pn_Cmp pnc = get_Proj_proj(proj);
2139 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2146 static ir_node *try_create_Test(ir_node *node)
2148 ir_graph *irg = current_ir_graph;
2149 dbg_info *dbgi = get_irn_dbg_info(node);
2150 ir_node *block = get_nodes_block(node);
2151 ir_node *new_block = be_transform_node(block);
2152 ir_node *cmp_left = get_Cmp_left(node);
2153 ir_node *cmp_right = get_Cmp_right(node);
2158 ia32_address_mode_t am;
2159 ia32_address_t *addr = &am.addr;
2162 /* can we use a test instruction? */
2163 if(!is_Const_0(cmp_right))
2166 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2167 can_fold_test_and(node)) {
2168 ir_node *and_left = get_And_left(cmp_left);
2169 ir_node *and_right = get_And_right(cmp_left);
2171 mode = get_irn_mode(and_left);
2175 mode = get_irn_mode(cmp_left);
2180 assert(get_mode_size_bits(mode) <= 32);
2182 match_arguments(&am, block, left, right, match_commutative |
2183 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2185 cmp_unsigned = !mode_is_signed(mode);
2186 if(get_mode_size_bits(mode) == 8) {
2187 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2188 addr->index, addr->mem, am.new_op1,
2189 am.new_op2, am.flipped, cmp_unsigned);
2191 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2192 addr->mem, am.new_op1, am.new_op2, am.flipped,
2195 set_am_attributes(res, &am);
2196 assert(mode != NULL);
2197 set_ia32_ls_mode(res, mode);
2199 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2201 res = fix_mem_proj(res, &am);
2205 static ir_node *create_Fucom(ir_node *node)
2207 ir_graph *irg = current_ir_graph;
2208 dbg_info *dbgi = get_irn_dbg_info(node);
2209 ir_node *block = get_nodes_block(node);
2210 ir_node *new_block = be_transform_node(block);
2211 ir_node *left = get_Cmp_left(node);
2212 ir_node *new_left = be_transform_node(left);
2213 ir_node *right = get_Cmp_right(node);
2217 if(transform_config.use_fucomi) {
2218 new_right = be_transform_node(right);
2219 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2220 set_ia32_commutative(res);
2221 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2223 if(transform_config.use_ftst && is_Const_null(right)) {
2224 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2226 new_right = be_transform_node(right);
2227 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2231 set_ia32_commutative(res);
2233 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2235 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2236 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2242 static ir_node *create_Ucomi(ir_node *node)
2244 ir_graph *irg = current_ir_graph;
2245 dbg_info *dbgi = get_irn_dbg_info(node);
2246 ir_node *src_block = get_nodes_block(node);
2247 ir_node *new_block = be_transform_node(src_block);
2248 ir_node *left = get_Cmp_left(node);
2249 ir_node *right = get_Cmp_right(node);
2251 ia32_address_mode_t am;
2252 ia32_address_t *addr = &am.addr;
2254 match_arguments(&am, src_block, left, right, match_commutative);
2256 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2257 addr->mem, am.new_op1, am.new_op2, am.flipped);
2258 set_am_attributes(new_node, &am);
2260 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2262 new_node = fix_mem_proj(new_node, &am);
2267 static ir_node *gen_Cmp(ir_node *node)
2269 ir_graph *irg = current_ir_graph;
2270 dbg_info *dbgi = get_irn_dbg_info(node);
2271 ir_node *block = get_nodes_block(node);
2272 ir_node *new_block = be_transform_node(block);
2273 ir_node *left = get_Cmp_left(node);
2274 ir_node *right = get_Cmp_right(node);
2275 ir_mode *cmp_mode = get_irn_mode(left);
2277 ia32_address_mode_t am;
2278 ia32_address_t *addr = &am.addr;
2281 if(mode_is_float(cmp_mode)) {
2282 if (USE_SSE2(env_cg)) {
2283 return create_Ucomi(node);
2285 return create_Fucom(node);
2289 assert(mode_needs_gp_reg(cmp_mode));
2291 /* we prefer the Test instruction where possible except cases where
2292 * we can use SourceAM */
2293 if(!use_source_address_mode(block, left, right) &&
2294 !use_source_address_mode(block, right, left)) {
2295 res = try_create_Test(node);
2300 match_arguments(&am, block, left, right,
2301 match_commutative | match_8_bit_am | match_16_bit_am |
2302 match_am_and_immediates);
2304 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2305 if(get_mode_size_bits(cmp_mode) == 8) {
2306 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2307 addr->mem, am.new_op1, am.new_op2,
2308 am.flipped, cmp_unsigned);
2310 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2311 addr->mem, am.new_op1, am.new_op2, am.flipped,
2314 set_am_attributes(res, &am);
2315 assert(cmp_mode != NULL);
2316 set_ia32_ls_mode(res, cmp_mode);
2318 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2320 res = fix_mem_proj(res, &am);
2325 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2327 ir_graph *irg = current_ir_graph;
2328 dbg_info *dbgi = get_irn_dbg_info(node);
2329 ir_node *block = get_nodes_block(node);
2330 ir_node *new_block = be_transform_node(block);
2331 ir_node *val_true = get_Psi_val(node, 0);
2332 ir_node *val_false = get_Psi_default(node);
2334 match_flags_t match_flags;
2336 assert(transform_config.use_cmov);
2338 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2340 ia32_address_mode_t am;
2341 ia32_address_t *addr = &am.addr;
2343 match_flags = match_commutative | match_no_immediate | match_16_bit_am;
2345 match_arguments(&am, block, val_false, val_true, match_flags);
2347 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2348 addr->mem, am.new_op1, am.new_op2, new_flags,
2350 set_am_attributes(new_node, &am);
2352 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2354 new_node = fix_mem_proj(new_node, &am);
2361 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2362 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2364 ir_graph *irg = current_ir_graph;
2365 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2366 ir_node *nomem = new_NoMem();
2369 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2370 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2371 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2372 nomem, res, mode_Bu);
2373 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2379 * Transforms a Psi node into CMov.
2381 * @return The transformed node.
2383 static ir_node *gen_Psi(ir_node *node)
2385 dbg_info *dbgi = get_irn_dbg_info(node);
2386 ir_node *block = get_nodes_block(node);
2387 ir_node *new_block = be_transform_node(block);
2388 ir_node *psi_true = get_Psi_val(node, 0);
2389 ir_node *psi_default = get_Psi_default(node);
2390 ir_node *cond = get_Psi_cond(node, 0);
2391 ir_node *flags = NULL;
2396 assert(get_Psi_n_conds(node) == 1);
2397 assert(get_irn_mode(cond) == mode_b);
2398 assert(mode_needs_gp_reg(get_irn_mode(node)));
2400 flags = get_flags_node(cond, &pnc);
2402 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2403 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2404 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2405 pnc = get_negated_pnc(pnc, cmp_mode);
2406 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2408 res = create_CMov(node, flags, pnc);
2415 * Create a conversion from x87 state register to general purpose.
2417 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2418 ir_node *block = be_transform_node(get_nodes_block(node));
2419 ir_node *op = get_Conv_op(node);
2420 ir_node *new_op = be_transform_node(op);
2421 ia32_code_gen_t *cg = env_cg;
2422 ir_graph *irg = current_ir_graph;
2423 dbg_info *dbgi = get_irn_dbg_info(node);
2424 ir_node *noreg = ia32_new_NoReg_gp(cg);
2425 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2426 ir_mode *mode = get_irn_mode(node);
2427 ir_node *fist, *load;
2430 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2431 new_NoMem(), new_op, trunc_mode);
2433 set_irn_pinned(fist, op_pin_state_floats);
2434 set_ia32_use_frame(fist);
2435 set_ia32_op_type(fist, ia32_AddrModeD);
2437 assert(get_mode_size_bits(mode) <= 32);
2438 /* exception we can only store signed 32 bit integers, so for unsigned
2439 we store a 64bit (signed) integer and load the lower bits */
2440 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2441 set_ia32_ls_mode(fist, mode_Ls);
2443 set_ia32_ls_mode(fist, mode_Is);
2445 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2448 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2450 set_irn_pinned(load, op_pin_state_floats);
2451 set_ia32_use_frame(load);
2452 set_ia32_op_type(load, ia32_AddrModeS);
2453 set_ia32_ls_mode(load, mode_Is);
2454 if(get_ia32_ls_mode(fist) == mode_Ls) {
2455 ia32_attr_t *attr = get_ia32_attr(load);
2456 attr->data.need_64bit_stackent = 1;
2458 ia32_attr_t *attr = get_ia32_attr(load);
2459 attr->data.need_32bit_stackent = 1;
2461 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2463 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2467 * Creates a x87 strict Conv by placing a Sore and a Load
2469 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2471 ir_node *block = get_nodes_block(node);
2472 ir_graph *irg = current_ir_graph;
2473 dbg_info *dbgi = get_irn_dbg_info(node);
2474 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2475 ir_node *nomem = new_NoMem();
2476 ir_node *frame = get_irg_frame(irg);
2477 ir_node *store, *load;
2480 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2482 set_ia32_use_frame(store);
2483 set_ia32_op_type(store, ia32_AddrModeD);
2484 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2486 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2488 set_ia32_use_frame(load);
2489 set_ia32_op_type(load, ia32_AddrModeS);
2490 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2492 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2496 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2498 ir_graph *irg = current_ir_graph;
2499 ir_node *start_block = get_irg_start_block(irg);
2500 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2501 symconst, symconst_sign, val);
2502 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2508 * Create a conversion from general purpose to x87 register
2510 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2511 ir_node *src_block = get_nodes_block(node);
2512 ir_node *block = be_transform_node(src_block);
2513 ir_graph *irg = current_ir_graph;
2514 dbg_info *dbgi = get_irn_dbg_info(node);
2515 ir_node *op = get_Conv_op(node);
2520 ir_mode *store_mode;
2526 /* fild can use source AM if the operand is a signed 32bit integer */
2527 if (src_mode == mode_Is) {
2528 ia32_address_mode_t am;
2530 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2531 if (am.op_type == ia32_AddrModeS) {
2532 ia32_address_t *addr = &am.addr;
2534 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2535 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2537 set_am_attributes(fild, &am);
2538 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2540 fix_mem_proj(fild, &am);
2544 new_op = am.new_op2;
2546 new_op = be_transform_node(op);
2549 noreg = ia32_new_NoReg_gp(env_cg);
2550 nomem = new_NoMem();
2551 mode = get_irn_mode(op);
2553 /* first convert to 32 bit signed if necessary */
2554 src_bits = get_mode_size_bits(src_mode);
2555 if (src_bits == 8) {
2556 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2558 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2560 } else if (src_bits < 32) {
2561 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2563 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2567 assert(get_mode_size_bits(mode) == 32);
2570 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2573 set_ia32_use_frame(store);
2574 set_ia32_op_type(store, ia32_AddrModeD);
2575 set_ia32_ls_mode(store, mode_Iu);
2577 /* exception for 32bit unsigned, do a 64bit spill+load */
2578 if(!mode_is_signed(mode)) {
2581 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2583 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2584 get_irg_frame(irg), noreg, nomem,
2587 set_ia32_use_frame(zero_store);
2588 set_ia32_op_type(zero_store, ia32_AddrModeD);
2589 add_ia32_am_offs_int(zero_store, 4);
2590 set_ia32_ls_mode(zero_store, mode_Iu);
2595 store = new_rd_Sync(dbgi, irg, block, 2, in);
2596 store_mode = mode_Ls;
2598 store_mode = mode_Is;
2602 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2604 set_ia32_use_frame(fild);
2605 set_ia32_op_type(fild, ia32_AddrModeS);
2606 set_ia32_ls_mode(fild, store_mode);
2608 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2614 * Crete a conversion from one integer mode into another one
2616 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2617 dbg_info *dbgi, ir_node *block, ir_node *op,
2620 ir_graph *irg = current_ir_graph;
2621 int src_bits = get_mode_size_bits(src_mode);
2622 int tgt_bits = get_mode_size_bits(tgt_mode);
2623 ir_node *new_block = be_transform_node(block);
2624 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2627 ir_mode *smaller_mode;
2629 ia32_address_mode_t am;
2630 ia32_address_t *addr = &am.addr;
2632 if (src_bits < tgt_bits) {
2633 smaller_mode = src_mode;
2634 smaller_bits = src_bits;
2636 smaller_mode = tgt_mode;
2637 smaller_bits = tgt_bits;
2640 memset(&am, 0, sizeof(am));
2641 if(use_source_address_mode(block, op, NULL)) {
2642 build_address(&am, op);
2644 am.op_type = ia32_AddrModeS;
2646 new_op = be_transform_node(op);
2647 am.op_type = ia32_Normal;
2649 if(addr->base == NULL)
2651 if(addr->index == NULL)
2652 addr->index = noreg;
2653 if(addr->mem == NULL)
2654 addr->mem = new_NoMem();
2656 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2657 if (smaller_bits == 8) {
2658 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2659 addr->index, addr->mem, new_op,
2662 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2663 addr->index, addr->mem, new_op,
2667 set_am_attributes(res, &am);
2668 set_ia32_ls_mode(res, smaller_mode);
2669 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2670 res = fix_mem_proj(res, &am);
2676 * Transforms a Conv node.
2678 * @return The created ia32 Conv node
2680 static ir_node *gen_Conv(ir_node *node) {
2681 ir_node *block = get_nodes_block(node);
2682 ir_node *new_block = be_transform_node(block);
2683 ir_node *op = get_Conv_op(node);
2684 ir_node *new_op = NULL;
2685 ir_graph *irg = current_ir_graph;
2686 dbg_info *dbgi = get_irn_dbg_info(node);
2687 ir_mode *src_mode = get_irn_mode(op);
2688 ir_mode *tgt_mode = get_irn_mode(node);
2689 int src_bits = get_mode_size_bits(src_mode);
2690 int tgt_bits = get_mode_size_bits(tgt_mode);
2691 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2692 ir_node *nomem = new_rd_NoMem(irg);
2693 ir_node *res = NULL;
2695 if (src_mode == mode_b) {
2696 assert(mode_is_int(tgt_mode));
2697 /* nothing to do, we already model bools as 0/1 ints */
2698 return be_transform_node(op);
2701 if (src_mode == tgt_mode) {
2702 if (get_Conv_strict(node)) {
2703 if (USE_SSE2(env_cg)) {
2704 /* when we are in SSE mode, we can kill all strict no-op conversion */
2705 return be_transform_node(op);
2708 /* this should be optimized already, but who knows... */
2709 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2710 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2711 return be_transform_node(op);
2715 if (mode_is_float(src_mode)) {
2716 new_op = be_transform_node(op);
2717 /* we convert from float ... */
2718 if (mode_is_float(tgt_mode)) {
2719 if(src_mode == mode_E && tgt_mode == mode_D
2720 && !get_Conv_strict(node)) {
2721 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2726 if (USE_SSE2(env_cg)) {
2727 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2728 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2730 set_ia32_ls_mode(res, tgt_mode);
2732 if(get_Conv_strict(node)) {
2733 res = gen_x87_strict_conv(tgt_mode, new_op);
2734 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2737 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2742 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2743 if (USE_SSE2(env_cg)) {
2744 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2746 set_ia32_ls_mode(res, src_mode);
2748 return gen_x87_fp_to_gp(node);
2752 /* we convert from int ... */
2753 if (mode_is_float(tgt_mode)) {
2755 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2756 if (USE_SSE2(env_cg)) {
2757 new_op = be_transform_node(op);
2758 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2760 set_ia32_ls_mode(res, tgt_mode);
2762 res = gen_x87_gp_to_fp(node, src_mode);
2763 if(get_Conv_strict(node)) {
2764 res = gen_x87_strict_conv(tgt_mode, res);
2765 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2766 ia32_get_old_node_name(env_cg, node));
2770 } else if(tgt_mode == mode_b) {
2771 /* mode_b lowering already took care that we only have 0/1 values */
2772 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2773 src_mode, tgt_mode));
2774 return be_transform_node(op);
2777 if (src_bits == tgt_bits) {
2778 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2779 src_mode, tgt_mode));
2780 return be_transform_node(op);
2783 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2791 static int check_immediate_constraint(long val, char immediate_constraint_type)
2793 switch (immediate_constraint_type) {
2797 return val >= 0 && val <= 32;
2799 return val >= 0 && val <= 63;
2801 return val >= -128 && val <= 127;
2803 return val == 0xff || val == 0xffff;
2805 return val >= 0 && val <= 3;
2807 return val >= 0 && val <= 255;
2809 return val >= 0 && val <= 127;
2813 panic("Invalid immediate constraint found");
2817 static ir_node *try_create_Immediate(ir_node *node,
2818 char immediate_constraint_type)
2821 tarval *offset = NULL;
2822 int offset_sign = 0;
2824 ir_entity *symconst_ent = NULL;
2825 int symconst_sign = 0;
2827 ir_node *cnst = NULL;
2828 ir_node *symconst = NULL;
2831 mode = get_irn_mode(node);
2832 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2836 if(is_Minus(node)) {
2838 node = get_Minus_op(node);
2841 if(is_Const(node)) {
2844 offset_sign = minus;
2845 } else if(is_SymConst(node)) {
2848 symconst_sign = minus;
2849 } else if(is_Add(node)) {
2850 ir_node *left = get_Add_left(node);
2851 ir_node *right = get_Add_right(node);
2852 if(is_Const(left) && is_SymConst(right)) {
2855 symconst_sign = minus;
2856 offset_sign = minus;
2857 } else if(is_SymConst(left) && is_Const(right)) {
2860 symconst_sign = minus;
2861 offset_sign = minus;
2863 } else if(is_Sub(node)) {
2864 ir_node *left = get_Sub_left(node);
2865 ir_node *right = get_Sub_right(node);
2866 if(is_Const(left) && is_SymConst(right)) {
2869 symconst_sign = !minus;
2870 offset_sign = minus;
2871 } else if(is_SymConst(left) && is_Const(right)) {
2874 symconst_sign = minus;
2875 offset_sign = !minus;
2882 offset = get_Const_tarval(cnst);
2883 if(tarval_is_long(offset)) {
2884 val = get_tarval_long(offset);
2886 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2891 if(!check_immediate_constraint(val, immediate_constraint_type))
2894 if(symconst != NULL) {
2895 if(immediate_constraint_type != 0) {
2896 /* we need full 32bits for symconsts */
2900 /* unfortunately the assembler/linker doesn't support -symconst */
2904 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2906 symconst_ent = get_SymConst_entity(symconst);
2908 if(cnst == NULL && symconst == NULL)
2911 if(offset_sign && offset != NULL) {
2912 offset = tarval_neg(offset);
2915 res = create_Immediate(symconst_ent, symconst_sign, val);
2920 static ir_node *create_immediate_or_transform(ir_node *node,
2921 char immediate_constraint_type)
2923 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2924 if (new_node == NULL) {
2925 new_node = be_transform_node(node);
2930 typedef struct constraint_t constraint_t;
2931 struct constraint_t {
2934 const arch_register_req_t **out_reqs;
2936 const arch_register_req_t *req;
2937 unsigned immediate_possible;
2938 char immediate_type;
2941 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2943 int immediate_possible = 0;
2944 char immediate_type = 0;
2945 unsigned limited = 0;
2946 const arch_register_class_t *cls = NULL;
2947 ir_graph *irg = current_ir_graph;
2948 struct obstack *obst = get_irg_obstack(irg);
2949 arch_register_req_t *req;
2950 unsigned *limited_ptr;
2954 /* TODO: replace all the asserts with nice error messages */
2956 printf("Constraint: %s\n", c);
2966 assert(cls == NULL ||
2967 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2968 cls = &ia32_reg_classes[CLASS_ia32_gp];
2969 limited |= 1 << REG_EAX;
2972 assert(cls == NULL ||
2973 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2974 cls = &ia32_reg_classes[CLASS_ia32_gp];
2975 limited |= 1 << REG_EBX;
2978 assert(cls == NULL ||
2979 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2980 cls = &ia32_reg_classes[CLASS_ia32_gp];
2981 limited |= 1 << REG_ECX;
2984 assert(cls == NULL ||
2985 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2986 cls = &ia32_reg_classes[CLASS_ia32_gp];
2987 limited |= 1 << REG_EDX;
2990 assert(cls == NULL ||
2991 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2992 cls = &ia32_reg_classes[CLASS_ia32_gp];
2993 limited |= 1 << REG_EDI;
2996 assert(cls == NULL ||
2997 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2998 cls = &ia32_reg_classes[CLASS_ia32_gp];
2999 limited |= 1 << REG_ESI;
3002 case 'q': /* q means lower part of the regs only, this makes no
3003 * difference to Q for us (we only assigne whole registers) */
3004 assert(cls == NULL ||
3005 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3006 cls = &ia32_reg_classes[CLASS_ia32_gp];
3007 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3011 assert(cls == NULL ||
3012 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3013 cls = &ia32_reg_classes[CLASS_ia32_gp];
3014 limited |= 1 << REG_EAX | 1 << REG_EDX;
3017 assert(cls == NULL ||
3018 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3019 cls = &ia32_reg_classes[CLASS_ia32_gp];
3020 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3021 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3028 assert(cls == NULL);
3029 cls = &ia32_reg_classes[CLASS_ia32_gp];
3035 /* TODO: mark values so the x87 simulator knows about t and u */
3036 assert(cls == NULL);
3037 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3042 assert(cls == NULL);
3043 /* TODO: check that sse2 is supported */
3044 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3054 assert(!immediate_possible);
3055 immediate_possible = 1;
3056 immediate_type = *c;
3060 assert(!immediate_possible);
3061 immediate_possible = 1;
3065 assert(!immediate_possible && cls == NULL);
3066 immediate_possible = 1;
3067 cls = &ia32_reg_classes[CLASS_ia32_gp];
3080 assert(constraint->is_in && "can only specify same constraint "
3083 sscanf(c, "%d%n", &same_as, &p);
3090 case 'E': /* no float consts yet */
3091 case 'F': /* no float consts yet */
3092 case 's': /* makes no sense on x86 */
3093 case 'X': /* we can't support that in firm */
3097 case '<': /* no autodecrement on x86 */
3098 case '>': /* no autoincrement on x86 */
3099 case 'C': /* sse constant not supported yet */
3100 case 'G': /* 80387 constant not supported yet */
3101 case 'y': /* we don't support mmx registers yet */
3102 case 'Z': /* not available in 32 bit mode */
3103 case 'e': /* not available in 32 bit mode */
3104 panic("unsupported asm constraint '%c' found in (%+F)",
3105 *c, current_ir_graph);
3108 panic("unknown asm constraint '%c' found in (%+F)", *c,
3116 const arch_register_req_t *other_constr;
3118 assert(cls == NULL && "same as and register constraint not supported");
3119 assert(!immediate_possible && "same as and immediate constraint not "
3121 assert(same_as < constraint->n_outs && "wrong constraint number in "
3122 "same_as constraint");
3124 other_constr = constraint->out_reqs[same_as];
3126 req = obstack_alloc(obst, sizeof(req[0]));
3127 req->cls = other_constr->cls;
3128 req->type = arch_register_req_type_should_be_same;
3129 req->limited = NULL;
3130 req->other_same[0] = pos;
3131 req->other_same[1] = -1;
3132 req->other_different = -1;
3134 /* switch constraints. This is because in firm we have same_as
3135 * constraints on the output constraints while in the gcc asm syntax
3136 * they are specified on the input constraints */
3137 constraint->req = other_constr;
3138 constraint->out_reqs[same_as] = req;
3139 constraint->immediate_possible = 0;
3143 if(immediate_possible && cls == NULL) {
3144 cls = &ia32_reg_classes[CLASS_ia32_gp];
3146 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3147 assert(cls != NULL);
3149 if(immediate_possible) {
3150 assert(constraint->is_in
3151 && "imeediates make no sense for output constraints");
3153 /* todo: check types (no float input on 'r' constrained in and such... */
3156 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3157 limited_ptr = (unsigned*) (req+1);
3159 req = obstack_alloc(obst, sizeof(req[0]));
3161 memset(req, 0, sizeof(req[0]));
3164 req->type = arch_register_req_type_limited;
3165 *limited_ptr = limited;
3166 req->limited = limited_ptr;
3168 req->type = arch_register_req_type_normal;
3172 constraint->req = req;
3173 constraint->immediate_possible = immediate_possible;
3174 constraint->immediate_type = immediate_type;
3177 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3184 panic("Clobbers not supported yet");
3188 * generates code for a ASM node
3190 static ir_node *gen_ASM(ir_node *node)
3193 ir_graph *irg = current_ir_graph;
3194 ir_node *block = be_transform_node(get_nodes_block(node));
3195 dbg_info *dbgi = get_irn_dbg_info(node);
3202 ia32_asm_attr_t *attr;
3203 const arch_register_req_t **out_reqs;
3204 const arch_register_req_t **in_reqs;
3205 struct obstack *obst;
3206 constraint_t parsed_constraint;
3208 /* transform inputs */
3209 arity = get_irn_arity(node);
3210 in = alloca(arity * sizeof(in[0]));
3211 memset(in, 0, arity * sizeof(in[0]));
3213 n_outs = get_ASM_n_output_constraints(node);
3214 n_clobbers = get_ASM_n_clobbers(node);
3215 out_arity = n_outs + n_clobbers;
3217 /* construct register constraints */
3218 obst = get_irg_obstack(irg);
3219 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3220 parsed_constraint.out_reqs = out_reqs;
3221 parsed_constraint.n_outs = n_outs;
3222 parsed_constraint.is_in = 0;
3223 for(i = 0; i < out_arity; ++i) {
3227 const ir_asm_constraint *constraint;
3228 constraint = & get_ASM_output_constraints(node) [i];
3229 c = get_id_str(constraint->constraint);
3230 parse_asm_constraint(i, &parsed_constraint, c);
3232 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3233 c = get_id_str(glob_id);
3234 parse_clobber(node, i, &parsed_constraint, c);
3236 out_reqs[i] = parsed_constraint.req;
3239 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3240 parsed_constraint.is_in = 1;
3241 for(i = 0; i < arity; ++i) {
3242 const ir_asm_constraint *constraint;
3246 constraint = & get_ASM_input_constraints(node) [i];
3247 constr_id = constraint->constraint;
3248 c = get_id_str(constr_id);
3249 parse_asm_constraint(i, &parsed_constraint, c);
3250 in_reqs[i] = parsed_constraint.req;
3252 if(parsed_constraint.immediate_possible) {
3253 ir_node *pred = get_irn_n(node, i);
3254 char imm_type = parsed_constraint.immediate_type;
3255 ir_node *immediate = try_create_Immediate(pred, imm_type);
3257 if(immediate != NULL) {
3263 /* transform inputs */
3264 for(i = 0; i < arity; ++i) {
3266 ir_node *transformed;
3271 pred = get_irn_n(node, i);
3272 transformed = be_transform_node(pred);
3273 in[i] = transformed;
3276 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3278 generic_attr = get_irn_generic_attr(res);
3279 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3280 attr->asm_text = get_ASM_text(node);
3281 set_ia32_out_req_all(res, out_reqs);
3282 set_ia32_in_req_all(res, in_reqs);
3284 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3289 /********************************************
3292 * | |__ ___ _ __ ___ __| | ___ ___
3293 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3294 * | |_) | __/ | | | (_) | (_| | __/\__ \
3295 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3297 ********************************************/
3300 * Transforms a FrameAddr into an ia32 Add.
3302 static ir_node *gen_be_FrameAddr(ir_node *node) {
3303 ir_node *block = be_transform_node(get_nodes_block(node));
3304 ir_node *op = be_get_FrameAddr_frame(node);
3305 ir_node *new_op = be_transform_node(op);
3306 ir_graph *irg = current_ir_graph;
3307 dbg_info *dbgi = get_irn_dbg_info(node);
3308 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3311 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3312 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3313 set_ia32_use_frame(res);
3315 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3321 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3323 static ir_node *gen_be_Return(ir_node *node) {
3324 ir_graph *irg = current_ir_graph;
3325 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3326 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3327 ir_entity *ent = get_irg_entity(irg);
3328 ir_type *tp = get_entity_type(ent);
3333 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3334 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3337 int pn_ret_val, pn_ret_mem, arity, i;
3339 assert(ret_val != NULL);
3340 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3341 return be_duplicate_node(node);
3344 res_type = get_method_res_type(tp, 0);
3346 if (! is_Primitive_type(res_type)) {
3347 return be_duplicate_node(node);
3350 mode = get_type_mode(res_type);
3351 if (! mode_is_float(mode)) {
3352 return be_duplicate_node(node);
3355 assert(get_method_n_ress(tp) == 1);
3357 pn_ret_val = get_Proj_proj(ret_val);
3358 pn_ret_mem = get_Proj_proj(ret_mem);
3360 /* get the Barrier */
3361 barrier = get_Proj_pred(ret_val);
3363 /* get result input of the Barrier */
3364 ret_val = get_irn_n(barrier, pn_ret_val);
3365 new_ret_val = be_transform_node(ret_val);
3367 /* get memory input of the Barrier */
3368 ret_mem = get_irn_n(barrier, pn_ret_mem);
3369 new_ret_mem = be_transform_node(ret_mem);
3371 frame = get_irg_frame(irg);
3373 dbgi = get_irn_dbg_info(barrier);
3374 block = be_transform_node(get_nodes_block(barrier));
3376 noreg = ia32_new_NoReg_gp(env_cg);
3378 /* store xmm0 onto stack */
3379 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3380 new_ret_mem, new_ret_val);
3381 set_ia32_ls_mode(sse_store, mode);
3382 set_ia32_op_type(sse_store, ia32_AddrModeD);
3383 set_ia32_use_frame(sse_store);
3385 /* load into x87 register */
3386 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3387 set_ia32_op_type(fld, ia32_AddrModeS);
3388 set_ia32_use_frame(fld);
3390 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3391 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3393 /* create a new barrier */
3394 arity = get_irn_arity(barrier);
3395 in = alloca(arity * sizeof(in[0]));
3396 for (i = 0; i < arity; ++i) {
3399 if (i == pn_ret_val) {
3401 } else if (i == pn_ret_mem) {
3404 ir_node *in = get_irn_n(barrier, i);
3405 new_in = be_transform_node(in);
3410 new_barrier = new_ir_node(dbgi, irg, block,
3411 get_irn_op(barrier), get_irn_mode(barrier),
3413 copy_node_attr(barrier, new_barrier);
3414 be_duplicate_deps(barrier, new_barrier);
3415 be_set_transformed_node(barrier, new_barrier);
3416 mark_irn_visited(barrier);
3418 /* transform normally */
3419 return be_duplicate_node(node);
3423 * Transform a be_AddSP into an ia32_SubSP.
3425 static ir_node *gen_be_AddSP(ir_node *node)
3427 ir_node *src_block = get_nodes_block(node);
3428 ir_node *new_block = be_transform_node(src_block);
3429 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3430 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3431 ir_graph *irg = current_ir_graph;
3432 dbg_info *dbgi = get_irn_dbg_info(node);
3434 ia32_address_mode_t am;
3435 ia32_address_t *addr = &am.addr;
3436 match_flags_t flags = 0;
3438 match_arguments(&am, src_block, sp, sz, flags);
3440 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3441 addr->mem, am.new_op1, am.new_op2);
3442 set_am_attributes(new_node, &am);
3443 /* we can't use source address mode anymore when using immediates */
3444 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3445 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3446 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3448 new_node = fix_mem_proj(new_node, &am);
3454 * Transform a be_SubSP into an ia32_AddSP
3456 static ir_node *gen_be_SubSP(ir_node *node)
3458 ir_node *src_block = get_nodes_block(node);
3459 ir_node *new_block = be_transform_node(src_block);
3460 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3461 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3462 ir_graph *irg = current_ir_graph;
3463 dbg_info *dbgi = get_irn_dbg_info(node);
3465 ia32_address_mode_t am;
3466 ia32_address_t *addr = &am.addr;
3467 match_flags_t flags = 0;
3469 match_arguments(&am, src_block, sp, sz, flags);
3471 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3472 addr->mem, am.new_op1, am.new_op2);
3473 set_am_attributes(new_node, &am);
3474 /* we can't use source address mode anymore when using immediates */
3475 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3476 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3477 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3479 new_node = fix_mem_proj(new_node, &am);
3485 * This function just sets the register for the Unknown node
3486 * as this is not done during register allocation because Unknown
3487 * is an "ignore" node.
3489 static ir_node *gen_Unknown(ir_node *node) {
3490 ir_mode *mode = get_irn_mode(node);
3492 if (mode_is_float(mode)) {
3493 if (USE_SSE2(env_cg)) {
3494 return ia32_new_Unknown_xmm(env_cg);
3496 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3497 ir_graph *irg = current_ir_graph;
3498 dbg_info *dbgi = get_irn_dbg_info(node);
3499 ir_node *block = get_irg_start_block(irg);
3500 return new_rd_ia32_vfldz(dbgi, irg, block);
3502 } else if (mode_needs_gp_reg(mode)) {
3503 return ia32_new_Unknown_gp(env_cg);
3505 assert(0 && "unsupported Unknown-Mode");
3512 * Change some phi modes
3514 static ir_node *gen_Phi(ir_node *node) {
3515 ir_node *block = be_transform_node(get_nodes_block(node));
3516 ir_graph *irg = current_ir_graph;
3517 dbg_info *dbgi = get_irn_dbg_info(node);
3518 ir_mode *mode = get_irn_mode(node);
3521 if(mode_needs_gp_reg(mode)) {
3522 /* we shouldn't have any 64bit stuff around anymore */
3523 assert(get_mode_size_bits(mode) <= 32);
3524 /* all integer operations are on 32bit registers now */
3526 } else if(mode_is_float(mode)) {
3527 if (USE_SSE2(env_cg)) {
3534 /* phi nodes allow loops, so we use the old arguments for now
3535 * and fix this later */
3536 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3537 get_irn_in(node) + 1);
3538 copy_node_attr(node, phi);
3539 be_duplicate_deps(node, phi);
3541 be_set_transformed_node(node, phi);
3542 be_enqueue_preds(node);
3550 static ir_node *gen_IJmp(ir_node *node) {
3551 /* TODO: support AM */
3552 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3556 /**********************************************************************
3559 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3560 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3561 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3562 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3564 **********************************************************************/
3566 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3568 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3571 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3572 ir_node *val, ir_node *mem);
3575 * Transforms a lowered Load into a "real" one.
3577 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3579 ir_node *block = be_transform_node(get_nodes_block(node));
3580 ir_node *ptr = get_irn_n(node, 0);
3581 ir_node *new_ptr = be_transform_node(ptr);
3582 ir_node *mem = get_irn_n(node, 1);
3583 ir_node *new_mem = be_transform_node(mem);
3584 ir_graph *irg = current_ir_graph;
3585 dbg_info *dbgi = get_irn_dbg_info(node);
3586 ir_mode *mode = get_ia32_ls_mode(node);
3587 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3590 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3592 set_ia32_op_type(new_op, ia32_AddrModeS);
3593 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3594 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3595 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3596 if (is_ia32_am_sc_sign(node))
3597 set_ia32_am_sc_sign(new_op);
3598 set_ia32_ls_mode(new_op, mode);
3599 if (is_ia32_use_frame(node)) {
3600 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3601 set_ia32_use_frame(new_op);
3604 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3610 * Transforms a lowered Store into a "real" one.
3612 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3614 ir_node *block = be_transform_node(get_nodes_block(node));
3615 ir_node *ptr = get_irn_n(node, 0);
3616 ir_node *new_ptr = be_transform_node(ptr);
3617 ir_node *val = get_irn_n(node, 1);
3618 ir_node *new_val = be_transform_node(val);
3619 ir_node *mem = get_irn_n(node, 2);
3620 ir_node *new_mem = be_transform_node(mem);
3621 ir_graph *irg = current_ir_graph;
3622 dbg_info *dbgi = get_irn_dbg_info(node);
3623 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3624 ir_mode *mode = get_ia32_ls_mode(node);
3628 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3630 am_offs = get_ia32_am_offs_int(node);
3631 add_ia32_am_offs_int(new_op, am_offs);
3633 set_ia32_op_type(new_op, ia32_AddrModeD);
3634 set_ia32_ls_mode(new_op, mode);
3635 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3636 set_ia32_use_frame(new_op);
3638 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3645 * Transforms an ia32_l_XXX into a "real" XXX node
3647 * @param node The node to transform
3648 * @return the created ia32 XXX node
3650 #define GEN_LOWERED_OP(op) \
3651 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3652 return gen_binop(node, get_binop_left(node), \
3653 get_binop_right(node), new_rd_ia32_##op,0); \
3656 #define GEN_LOWERED_x87_OP(op) \
3657 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3659 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3660 get_binop_right(node), new_rd_ia32_##op, 0); \
3664 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3665 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3666 return gen_shift_binop(node, get_irn_n(node, 0), \
3667 get_irn_n(node, 1), new_rd_ia32_##op); \
3670 GEN_LOWERED_x87_OP(vfprem)
3671 GEN_LOWERED_x87_OP(vfmul)
3672 GEN_LOWERED_x87_OP(vfsub)
3673 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3674 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3675 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3676 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3678 static ir_node *gen_ia32_l_Add(ir_node *node) {
3679 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3680 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3681 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3683 if(is_Proj(lowered)) {
3684 lowered = get_Proj_pred(lowered);
3686 assert(is_ia32_Add(lowered));
3687 set_irn_mode(lowered, mode_T);
3693 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3694 ir_node *src_block = get_nodes_block(node);
3695 ir_node *block = be_transform_node(src_block);
3696 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3697 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3698 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3699 ir_node *new_flags = be_transform_node(flags);
3700 ir_graph *irg = current_ir_graph;
3701 dbg_info *dbgi = get_irn_dbg_info(node);
3703 ia32_address_mode_t am;
3704 ia32_address_t *addr = &am.addr;
3706 match_arguments(&am, src_block, op1, op2, match_commutative);
3708 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3709 addr->mem, am.new_op1, am.new_op2, new_flags);
3710 set_am_attributes(new_node, &am);
3711 /* we can't use source address mode anymore when using immediates */
3712 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3713 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3714 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3716 new_node = fix_mem_proj(new_node, &am);
3722 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3724 * @param node The node to transform
3725 * @return the created ia32 Neg node
3727 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3728 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3732 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3734 * @param node The node to transform
3735 * @return the created ia32 vfild node
3737 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3738 return gen_lowered_Load(node, new_rd_ia32_vfild);
3742 * Transforms an ia32_l_Load into a "real" ia32_Load node
3744 * @param node The node to transform
3745 * @return the created ia32 Load node
3747 static ir_node *gen_ia32_l_Load(ir_node *node) {
3748 return gen_lowered_Load(node, new_rd_ia32_Load);
3752 * Transforms an ia32_l_Store into a "real" ia32_Store node
3754 * @param node The node to transform
3755 * @return the created ia32 Store node
3757 static ir_node *gen_ia32_l_Store(ir_node *node) {
3758 return gen_lowered_Store(node, new_rd_ia32_Store);
3762 * Transforms a l_vfist into a "real" vfist node.
3764 * @param node The node to transform
3765 * @return the created ia32 vfist node
3767 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3768 ir_node *block = be_transform_node(get_nodes_block(node));
3769 ir_node *ptr = get_irn_n(node, 0);
3770 ir_node *new_ptr = be_transform_node(ptr);
3771 ir_node *val = get_irn_n(node, 1);
3772 ir_node *new_val = be_transform_node(val);
3773 ir_node *mem = get_irn_n(node, 2);
3774 ir_node *new_mem = be_transform_node(mem);
3775 ir_graph *irg = current_ir_graph;
3776 dbg_info *dbgi = get_irn_dbg_info(node);
3777 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3778 ir_mode *mode = get_ia32_ls_mode(node);
3779 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3783 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3784 new_val, trunc_mode);
3786 am_offs = get_ia32_am_offs_int(node);
3787 add_ia32_am_offs_int(new_op, am_offs);
3789 set_ia32_op_type(new_op, ia32_AddrModeD);
3790 set_ia32_ls_mode(new_op, mode);
3791 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3792 set_ia32_use_frame(new_op);
3794 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3800 * Transforms a l_vfdiv into a "real" vfdiv node.
3802 * @param env The transformation environment
3803 * @return the created ia32 vfdiv node
3805 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3806 ir_node *block = be_transform_node(get_nodes_block(node));
3807 ir_node *left = get_binop_left(node);
3808 ir_node *new_left = be_transform_node(left);
3809 ir_node *right = get_binop_right(node);
3810 ir_node *new_right = be_transform_node(right);
3811 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3812 ir_graph *irg = current_ir_graph;
3813 dbg_info *dbgi = get_irn_dbg_info(node);
3814 ir_node *fpcw = get_fpcw();
3817 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3818 new_left, new_right, fpcw);
3819 clear_ia32_commutative(vfdiv);
3821 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3827 * Transforms a l_MulS into a "real" MulS node.
3829 * @param env The transformation environment
3830 * @return the created ia32 Mul node
3832 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3833 ir_node *block = be_transform_node(get_nodes_block(node));
3834 ir_node *left = get_binop_left(node);
3835 ir_node *new_left = be_transform_node(left);
3836 ir_node *right = get_binop_right(node);
3837 ir_node *new_right = be_transform_node(right);
3838 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3839 ir_graph *irg = current_ir_graph;
3840 dbg_info *dbgi = get_irn_dbg_info(node);
3842 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3843 /* and then skip the result Proj, because all needed Projs are already there. */
3844 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3845 new_left, new_right);
3846 clear_ia32_commutative(muls);
3848 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3854 * Transforms a l_IMulS into a "real" IMul1OPS node.
3856 * @param env The transformation environment
3857 * @return the created ia32 IMul1OP node
3859 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3860 ir_node *block = be_transform_node(get_nodes_block(node));
3861 ir_node *left = get_binop_left(node);
3862 ir_node *new_left = be_transform_node(left);
3863 ir_node *right = get_binop_right(node);
3864 ir_node *new_right = be_transform_node(right);
3865 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3866 ir_graph *irg = current_ir_graph;
3867 dbg_info *dbgi = get_irn_dbg_info(node);
3869 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3870 /* and then skip the result Proj, because all needed Projs are already there. */
3871 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3872 new_NoMem(), new_left, new_right);
3873 clear_ia32_commutative(muls);
3875 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3880 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3881 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3882 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3883 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3885 if(is_Proj(lowered)) {
3886 lowered = get_Proj_pred(lowered);
3888 assert(is_ia32_Sub(lowered));
3889 set_irn_mode(lowered, mode_T);
3895 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3896 ir_node *src_block = get_nodes_block(node);
3897 ir_node *block = be_transform_node(src_block);
3898 ir_node *op1 = get_irn_n(node, n_ia32_l_Sbb_left);
3899 ir_node *op2 = get_irn_n(node, n_ia32_l_Sbb_right);
3900 ir_node *flags = get_irn_n(node, n_ia32_l_Sbb_eflags);
3901 ir_node *new_flags = be_transform_node(flags);
3902 ir_graph *irg = current_ir_graph;
3903 dbg_info *dbgi = get_irn_dbg_info(node);
3905 ia32_address_mode_t am;
3906 ia32_address_t *addr = &am.addr;
3908 match_arguments(&am, src_block, op1, op2, match_commutative);
3910 new_node = new_rd_ia32_Sbb(dbgi, irg, block, addr->base, addr->index,
3911 addr->mem, am.new_op1, am.new_op2, new_flags);
3912 set_am_attributes(new_node, &am);
3913 /* we can't use source address mode anymore when using immediates */
3914 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3915 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3916 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3918 new_node = fix_mem_proj(new_node, &am);
3924 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3925 * op1 - target to be shifted
3926 * op2 - contains bits to be shifted into target
3928 * Only op3 can be an immediate.
3930 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3931 ir_node *op2, ir_node *count)
3933 ir_node *block = be_transform_node(get_nodes_block(node));
3934 ir_node *new_op = NULL;
3935 ir_graph *irg = current_ir_graph;
3936 dbg_info *dbgi = get_irn_dbg_info(node);
3937 ir_node *new_op1 = be_transform_node(op1);
3938 ir_node *new_op2 = be_transform_node(op2);
3939 ir_node *new_count = create_immediate_or_transform(count, 'I');
3941 /* TODO proper AM support */
3943 if (is_ia32_l_ShlD(node))
3944 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3946 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3948 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3953 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3954 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3955 get_irn_n(node, 1), get_irn_n(node, 2));
3958 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3959 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3960 get_irn_n(node, 1), get_irn_n(node, 2));
3964 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3966 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3967 ir_node *block = be_transform_node(get_nodes_block(node));
3968 ir_node *val = get_irn_n(node, 1);
3969 ir_node *new_val = be_transform_node(val);
3970 ia32_code_gen_t *cg = env_cg;
3971 ir_node *res = NULL;
3972 ir_graph *irg = current_ir_graph;
3974 ir_node *noreg, *new_ptr, *new_mem;
3981 mem = get_irn_n(node, 2);
3982 new_mem = be_transform_node(mem);
3983 ptr = get_irn_n(node, 0);
3984 new_ptr = be_transform_node(ptr);
3985 noreg = ia32_new_NoReg_gp(cg);
3986 dbgi = get_irn_dbg_info(node);
3988 /* Store x87 -> MEM */
3989 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3990 get_ia32_ls_mode(node));
3991 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3992 set_ia32_use_frame(res);
3993 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3994 set_ia32_op_type(res, ia32_AddrModeD);
3996 /* Load MEM -> SSE */
3997 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3998 get_ia32_ls_mode(node));
3999 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4000 set_ia32_use_frame(res);
4001 set_ia32_op_type(res, ia32_AddrModeS);
4002 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4008 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4010 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4011 ir_node *block = be_transform_node(get_nodes_block(node));
4012 ir_node *val = get_irn_n(node, 1);
4013 ir_node *new_val = be_transform_node(val);
4014 ia32_code_gen_t *cg = env_cg;
4015 ir_graph *irg = current_ir_graph;
4016 ir_node *res = NULL;
4017 ir_entity *fent = get_ia32_frame_ent(node);
4018 ir_mode *lsmode = get_ia32_ls_mode(node);
4020 ir_node *noreg, *new_ptr, *new_mem;
4024 if (! USE_SSE2(cg)) {
4025 /* SSE unit is not used -> skip this node. */
4029 ptr = get_irn_n(node, 0);
4030 new_ptr = be_transform_node(ptr);
4031 mem = get_irn_n(node, 2);
4032 new_mem = be_transform_node(mem);
4033 noreg = ia32_new_NoReg_gp(cg);
4034 dbgi = get_irn_dbg_info(node);
4036 /* Store SSE -> MEM */
4037 if (is_ia32_xLoad(skip_Proj(new_val))) {
4038 ir_node *ld = skip_Proj(new_val);
4040 /* we can vfld the value directly into the fpu */
4041 fent = get_ia32_frame_ent(ld);
4042 ptr = get_irn_n(ld, 0);
4043 offs = get_ia32_am_offs_int(ld);
4045 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4047 set_ia32_frame_ent(res, fent);
4048 set_ia32_use_frame(res);
4049 set_ia32_ls_mode(res, lsmode);
4050 set_ia32_op_type(res, ia32_AddrModeD);
4054 /* Load MEM -> x87 */
4055 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4056 set_ia32_frame_ent(res, fent);
4057 set_ia32_use_frame(res);
4058 add_ia32_am_offs_int(res, offs);
4059 set_ia32_op_type(res, ia32_AddrModeS);
4060 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4065 /*********************************************************
4068 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4069 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4070 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4071 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4073 *********************************************************/
4076 * the BAD transformer.
4078 static ir_node *bad_transform(ir_node *node) {
4079 panic("No transform function for %+F available.\n", node);
4084 * Transform the Projs of an AddSP.
4086 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4087 ir_node *block = be_transform_node(get_nodes_block(node));
4088 ir_node *pred = get_Proj_pred(node);
4089 ir_node *new_pred = be_transform_node(pred);
4090 ir_graph *irg = current_ir_graph;
4091 dbg_info *dbgi = get_irn_dbg_info(node);
4092 long proj = get_Proj_proj(node);
4094 if (proj == pn_be_AddSP_sp) {
4095 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4096 pn_ia32_SubSP_stack);
4097 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4099 } else if(proj == pn_be_AddSP_res) {
4100 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4101 pn_ia32_SubSP_addr);
4102 } else if (proj == pn_be_AddSP_M) {
4103 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4107 return new_rd_Unknown(irg, get_irn_mode(node));
4111 * Transform the Projs of a SubSP.
4113 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4114 ir_node *block = be_transform_node(get_nodes_block(node));
4115 ir_node *pred = get_Proj_pred(node);
4116 ir_node *new_pred = be_transform_node(pred);
4117 ir_graph *irg = current_ir_graph;
4118 dbg_info *dbgi = get_irn_dbg_info(node);
4119 long proj = get_Proj_proj(node);
4121 if (proj == pn_be_SubSP_sp) {
4122 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4123 pn_ia32_AddSP_stack);
4124 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4126 } else if (proj == pn_be_SubSP_M) {
4127 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4131 return new_rd_Unknown(irg, get_irn_mode(node));
4135 * Transform and renumber the Projs from a Load.
4137 static ir_node *gen_Proj_Load(ir_node *node) {
4139 ir_node *block = be_transform_node(get_nodes_block(node));
4140 ir_node *pred = get_Proj_pred(node);
4141 ir_graph *irg = current_ir_graph;
4142 dbg_info *dbgi = get_irn_dbg_info(node);
4143 long proj = get_Proj_proj(node);
4146 /* loads might be part of source address mode matches, so we don't
4147 transform the ProjMs yet (with the exception of loads whose result is
4150 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4153 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4155 /* this is needed, because sometimes we have loops that are only
4156 reachable through the ProjM */
4157 be_enqueue_preds(node);
4158 /* do it in 2 steps, to silence firm verifier */
4159 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4160 set_Proj_proj(res, pn_ia32_Load_M);
4164 /* renumber the proj */
4165 new_pred = be_transform_node(pred);
4166 if (is_ia32_Load(new_pred)) {
4167 if (proj == pn_Load_res) {
4168 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4170 } else if (proj == pn_Load_M) {
4171 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4174 } else if(is_ia32_Conv_I2I(new_pred)) {
4175 set_irn_mode(new_pred, mode_T);
4176 if (proj == pn_Load_res) {
4177 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4178 } else if (proj == pn_Load_M) {
4179 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4181 } else if (is_ia32_xLoad(new_pred)) {
4182 if (proj == pn_Load_res) {
4183 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4185 } else if (proj == pn_Load_M) {
4186 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4189 } else if (is_ia32_vfld(new_pred)) {
4190 if (proj == pn_Load_res) {
4191 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4193 } else if (proj == pn_Load_M) {
4194 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4198 /* can happen for ProJMs when source address mode happened for the
4201 /* however it should not be the result proj, as that would mean the
4202 load had multiple users and should not have been used for
4204 if(proj != pn_Load_M) {
4205 panic("internal error: transformed node not a Load");
4207 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4211 return new_rd_Unknown(irg, get_irn_mode(node));
4215 * Transform and renumber the Projs from a DivMod like instruction.
4217 static ir_node *gen_Proj_DivMod(ir_node *node) {
4218 ir_node *block = be_transform_node(get_nodes_block(node));
4219 ir_node *pred = get_Proj_pred(node);
4220 ir_node *new_pred = be_transform_node(pred);
4221 ir_graph *irg = current_ir_graph;
4222 dbg_info *dbgi = get_irn_dbg_info(node);
4223 ir_mode *mode = get_irn_mode(node);
4224 long proj = get_Proj_proj(node);
4226 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4228 switch (get_irn_opcode(pred)) {
4232 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4234 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4242 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4244 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4252 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4253 case pn_DivMod_res_div:
4254 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4255 case pn_DivMod_res_mod:
4256 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4266 return new_rd_Unknown(irg, mode);
4270 * Transform and renumber the Projs from a CopyB.
4272 static ir_node *gen_Proj_CopyB(ir_node *node) {
4273 ir_node *block = be_transform_node(get_nodes_block(node));
4274 ir_node *pred = get_Proj_pred(node);
4275 ir_node *new_pred = be_transform_node(pred);
4276 ir_graph *irg = current_ir_graph;
4277 dbg_info *dbgi = get_irn_dbg_info(node);
4278 ir_mode *mode = get_irn_mode(node);
4279 long proj = get_Proj_proj(node);
4282 case pn_CopyB_M_regular:
4283 if (is_ia32_CopyB_i(new_pred)) {
4284 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4285 } else if (is_ia32_CopyB(new_pred)) {
4286 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4294 return new_rd_Unknown(irg, mode);
4298 * Transform and renumber the Projs from a vfdiv.
4300 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4301 ir_node *block = be_transform_node(get_nodes_block(node));
4302 ir_node *pred = get_Proj_pred(node);
4303 ir_node *new_pred = be_transform_node(pred);
4304 ir_graph *irg = current_ir_graph;
4305 dbg_info *dbgi = get_irn_dbg_info(node);
4306 ir_mode *mode = get_irn_mode(node);
4307 long proj = get_Proj_proj(node);
4310 case pn_ia32_l_vfdiv_M:
4311 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4312 case pn_ia32_l_vfdiv_res:
4313 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4318 return new_rd_Unknown(irg, mode);
4322 * Transform and renumber the Projs from a Quot.
4324 static ir_node *gen_Proj_Quot(ir_node *node) {
4325 ir_node *block = be_transform_node(get_nodes_block(node));
4326 ir_node *pred = get_Proj_pred(node);
4327 ir_node *new_pred = be_transform_node(pred);
4328 ir_graph *irg = current_ir_graph;
4329 dbg_info *dbgi = get_irn_dbg_info(node);
4330 ir_mode *mode = get_irn_mode(node);
4331 long proj = get_Proj_proj(node);
4335 if (is_ia32_xDiv(new_pred)) {
4336 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4337 } else if (is_ia32_vfdiv(new_pred)) {
4338 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4342 if (is_ia32_xDiv(new_pred)) {
4343 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4344 } else if (is_ia32_vfdiv(new_pred)) {
4345 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4353 return new_rd_Unknown(irg, mode);
4357 * Transform the Thread Local Storage Proj.
4359 static ir_node *gen_Proj_tls(ir_node *node) {
4360 ir_node *block = be_transform_node(get_nodes_block(node));
4361 ir_graph *irg = current_ir_graph;
4362 dbg_info *dbgi = NULL;
4363 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4368 static ir_node *gen_be_Call(ir_node *node) {
4369 ir_node *res = be_duplicate_node(node);
4370 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4375 static ir_node *gen_be_IncSP(ir_node *node) {
4376 ir_node *res = be_duplicate_node(node);
4377 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4383 * Transform the Projs from a be_Call.
4385 static ir_node *gen_Proj_be_Call(ir_node *node) {
4386 ir_node *block = be_transform_node(get_nodes_block(node));
4387 ir_node *call = get_Proj_pred(node);
4388 ir_node *new_call = be_transform_node(call);
4389 ir_graph *irg = current_ir_graph;
4390 dbg_info *dbgi = get_irn_dbg_info(node);
4391 ir_type *method_type = be_Call_get_type(call);
4392 int n_res = get_method_n_ress(method_type);
4393 long proj = get_Proj_proj(node);
4394 ir_mode *mode = get_irn_mode(node);
4396 const arch_register_class_t *cls;
4398 /* The following is kinda tricky: If we're using SSE, then we have to
4399 * move the result value of the call in floating point registers to an
4400 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4401 * after the call, we have to make sure to correctly make the
4402 * MemProj and the result Proj use these 2 nodes
4404 if (proj == pn_be_Call_M_regular) {
4405 // get new node for result, are we doing the sse load/store hack?
4406 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4407 ir_node *call_res_new;
4408 ir_node *call_res_pred = NULL;
4410 if (call_res != NULL) {
4411 call_res_new = be_transform_node(call_res);
4412 call_res_pred = get_Proj_pred(call_res_new);
4415 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4416 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4417 pn_be_Call_M_regular);
4419 assert(is_ia32_xLoad(call_res_pred));
4420 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4424 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4425 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4426 && USE_SSE2(env_cg)) {
4428 ir_node *frame = get_irg_frame(irg);
4429 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4431 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4434 /* in case there is no memory output: create one to serialize the copy
4436 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4437 pn_be_Call_M_regular);
4438 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4439 pn_be_Call_first_res);
4441 /* store st(0) onto stack */
4442 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4444 set_ia32_op_type(fstp, ia32_AddrModeD);
4445 set_ia32_use_frame(fstp);
4447 /* load into SSE register */
4448 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4450 set_ia32_op_type(sse_load, ia32_AddrModeS);
4451 set_ia32_use_frame(sse_load);
4453 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4459 /* transform call modes */
4460 if (mode_is_data(mode)) {
4461 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4465 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4469 * Transform the Projs from a Cmp.
4471 static ir_node *gen_Proj_Cmp(ir_node *node)
4473 /* normally Cmps are processed when looking at Cond nodes, but this case
4474 * can happen in complicated Psi conditions */
4475 dbg_info *dbgi = get_irn_dbg_info(node);
4476 ir_node *block = get_nodes_block(node);
4477 ir_node *new_block = be_transform_node(block);
4478 ir_node *cmp = get_Proj_pred(node);
4479 ir_node *new_cmp = be_transform_node(cmp);
4480 long pnc = get_Proj_proj(node);
4483 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4489 * Transform and potentially renumber Proj nodes.
4491 static ir_node *gen_Proj(ir_node *node) {
4492 ir_graph *irg = current_ir_graph;
4493 dbg_info *dbgi = get_irn_dbg_info(node);
4494 ir_node *pred = get_Proj_pred(node);
4495 long proj = get_Proj_proj(node);
4497 if (is_Store(pred)) {
4498 if (proj == pn_Store_M) {
4499 return be_transform_node(pred);
4502 return new_r_Bad(irg);
4504 } else if (is_Load(pred)) {
4505 return gen_Proj_Load(node);
4506 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4507 return gen_Proj_DivMod(node);
4508 } else if (is_CopyB(pred)) {
4509 return gen_Proj_CopyB(node);
4510 } else if (is_Quot(pred)) {
4511 return gen_Proj_Quot(node);
4512 } else if (is_ia32_l_vfdiv(pred)) {
4513 return gen_Proj_l_vfdiv(node);
4514 } else if (be_is_SubSP(pred)) {
4515 return gen_Proj_be_SubSP(node);
4516 } else if (be_is_AddSP(pred)) {
4517 return gen_Proj_be_AddSP(node);
4518 } else if (be_is_Call(pred)) {
4519 return gen_Proj_be_Call(node);
4520 } else if (is_Cmp(pred)) {
4521 return gen_Proj_Cmp(node);
4522 } else if (get_irn_op(pred) == op_Start) {
4523 if (proj == pn_Start_X_initial_exec) {
4524 ir_node *block = get_nodes_block(pred);
4527 /* we exchange the ProjX with a jump */
4528 block = be_transform_node(block);
4529 jump = new_rd_Jmp(dbgi, irg, block);
4532 if (node == be_get_old_anchor(anchor_tls)) {
4533 return gen_Proj_tls(node);
4536 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4540 ir_node *new_pred = be_transform_node(pred);
4541 ir_node *block = be_transform_node(get_nodes_block(node));
4542 ir_mode *mode = get_irn_mode(node);
4543 if (mode_needs_gp_reg(mode)) {
4544 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4545 get_Proj_proj(node));
4546 #ifdef DEBUG_libfirm
4547 new_proj->node_nr = node->node_nr;
4553 return be_duplicate_node(node);
4557 * Enters all transform functions into the generic pointer
4559 static void register_transformers(void)
4563 /* first clear the generic function pointer for all ops */
4564 clear_irp_opcodes_generic_func();
4566 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4567 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4605 /* transform ops from intrinsic lowering */
4627 GEN(ia32_l_X87toSSE);
4628 GEN(ia32_l_SSEtoX87);
4634 /* we should never see these nodes */
4649 /* handle generic backend nodes */
4658 op_Mulh = get_op_Mulh();
4667 * Pre-transform all unknown and noreg nodes.
4669 static void ia32_pretransform_node(void *arch_cg) {
4670 ia32_code_gen_t *cg = arch_cg;
4672 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4673 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4674 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4675 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4676 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4677 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4682 * Walker, checks if all ia32 nodes producing more than one result have
4683 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4685 static void add_missing_keep_walker(ir_node *node, void *data)
4688 unsigned found_projs = 0;
4689 const ir_edge_t *edge;
4690 ir_mode *mode = get_irn_mode(node);
4695 if(!is_ia32_irn(node))
4698 n_outs = get_ia32_n_res(node);
4701 if(is_ia32_SwitchJmp(node))
4704 assert(n_outs < (int) sizeof(unsigned) * 8);
4705 foreach_out_edge(node, edge) {
4706 ir_node *proj = get_edge_src_irn(edge);
4707 int pn = get_Proj_proj(proj);
4709 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4710 found_projs |= 1 << pn;
4714 /* are keeps missing? */
4716 for(i = 0; i < n_outs; ++i) {
4719 const arch_register_req_t *req;
4720 const arch_register_class_t *class;
4722 if(found_projs & (1 << i)) {
4726 req = get_ia32_out_req(node, i);
4731 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4735 block = get_nodes_block(node);
4736 in[0] = new_r_Proj(current_ir_graph, block, node,
4737 arch_register_class_mode(class), i);
4738 if(last_keep != NULL) {
4739 be_Keep_add_node(last_keep, class, in[0]);
4741 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4742 if(sched_is_scheduled(node)) {
4743 sched_add_after(node, last_keep);
4750 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4753 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4755 ir_graph *irg = be_get_birg_irg(cg->birg);
4756 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4759 /* do the transformation */
4760 void ia32_transform_graph(ia32_code_gen_t *cg) {
4761 ir_graph *irg = cg->irg;
4763 /* TODO: look at cpu and fill transform config in with that... */
4764 transform_config.use_incdec = 1;
4765 transform_config.use_sse2 = 0;
4766 transform_config.use_ffreep = 0;
4767 transform_config.use_ftst = 0;
4768 transform_config.use_femms = 0;
4769 transform_config.use_fucomi = 1;
4770 transform_config.use_cmov = 1;
4772 register_transformers();
4774 initial_fpcw = NULL;
4776 heights = heights_new(irg);
4777 calculate_non_address_mode_nodes(irg);
4779 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4781 free_non_address_mode_nodes();
4782 heights_free(heights);
4786 void ia32_init_transform(void)
4788 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");