2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative : 1;
516 unsigned ins_permuted : 1;
519 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
523 /* construct load address */
524 memset(addr, 0, sizeof(addr[0]));
525 ia32_create_address_mode(addr, ptr, /*force=*/0);
527 if(addr->base == NULL) {
528 addr->base = noreg_gp;
530 addr->base = be_transform_node(addr->base);
533 if(addr->index == NULL) {
534 addr->index = noreg_gp;
536 addr->index = be_transform_node(addr->index);
538 addr->mem = be_transform_node(mem);
541 static void build_address(ia32_address_mode_t *am, ir_node *node)
543 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
544 ia32_address_t *addr = &am->addr;
553 ir_entity *entity = create_float_const_entity(node);
554 addr->base = noreg_gp;
555 addr->index = noreg_gp;
556 addr->mem = new_NoMem();
557 addr->symconst_ent = entity;
559 am->ls_mode = get_irn_mode(node);
560 am->pinned = op_pin_state_floats;
564 load = get_Proj_pred(node);
565 ptr = get_Load_ptr(load);
566 mem = get_Load_mem(load);
567 new_mem = be_transform_node(mem);
568 am->pinned = get_irn_pinned(load);
569 am->ls_mode = get_Load_mode(load);
570 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
572 /* construct load address */
573 ia32_create_address_mode(addr, ptr, /*force=*/0);
580 base = be_transform_node(base);
586 index = be_transform_node(index);
594 static void set_address(ir_node *node, const ia32_address_t *addr)
596 set_ia32_am_scale(node, addr->scale);
597 set_ia32_am_sc(node, addr->symconst_ent);
598 set_ia32_am_offs_int(node, addr->offset);
599 if(addr->symconst_sign)
600 set_ia32_am_sc_sign(node);
602 set_ia32_use_frame(node);
603 set_ia32_frame_ent(node, addr->frame_entity);
606 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
608 set_address(node, &am->addr);
610 set_ia32_op_type(node, am->op_type);
611 set_ia32_ls_mode(node, am->ls_mode);
612 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
613 set_irn_pinned(node, am->pinned);
616 set_ia32_commutative(node);
620 * Check, if a given node is a Down-Conv, ie. a integer Conv
621 * from a mode with a mode with more bits to a mode with lesser bits.
622 * Moreover, we return only true if the node has not more than 1 user.
624 * @param node the node
625 * @return non-zero if node is a Down-Conv
627 static int is_downconv(const ir_node *node)
635 /* we only want to skip the conv when we're the only user
636 * (not optimal but for now...)
638 if(get_irn_n_edges(node) > 1)
641 src_mode = get_irn_mode(get_Conv_op(node));
642 dest_mode = get_irn_mode(node);
643 return mode_needs_gp_reg(src_mode)
644 && mode_needs_gp_reg(dest_mode)
645 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
648 /* Skip all Down-Conv's on a given node and return the resulting node. */
649 ir_node *ia32_skip_downconv(ir_node *node) {
650 while (is_downconv(node))
651 node = get_Conv_op(node);
657 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
659 ir_mode *mode = get_irn_mode(node);
664 if(mode_is_signed(mode)) {
669 block = get_nodes_block(node);
670 dbgi = get_irn_dbg_info(node);
672 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
676 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
677 ir_node *op1, ir_node *op2, match_flags_t flags)
679 ia32_address_t *addr = &am->addr;
680 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
683 ir_mode *mode = get_irn_mode(op2);
685 unsigned commutative;
686 int use_am_and_immediates;
688 int mode_bits = get_mode_size_bits(mode);
690 memset(am, 0, sizeof(am[0]));
692 commutative = (flags & match_commutative) != 0;
693 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
694 use_am = (flags & match_am) != 0;
695 use_immediate = (flags & match_immediate) != 0;
696 assert(!use_am_and_immediates || use_immediate);
699 assert(!commutative || op1 != NULL);
702 if (! (flags & match_8bit_am))
704 assert((flags & match_mode_neutral) || (flags & match_8bit));
705 } else if(mode_bits == 16) {
706 if(! (flags & match_16bit_am))
708 assert((flags & match_mode_neutral) || (flags & match_16bit));
711 /* we can simply skip downconvs for mode neutral nodes: the upper bits
712 * can be random for these operations */
713 if(flags & match_mode_neutral) {
714 op2 = ia32_skip_downconv(op2);
716 op1 = ia32_skip_downconv(op1);
720 if(! (flags & match_try_am) && use_immediate)
721 new_op2 = try_create_Immediate(op2, 0);
725 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
726 build_address(am, op2);
727 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
728 if(mode_is_float(mode)) {
729 new_op2 = ia32_new_NoReg_vfp(env_cg);
733 am->op_type = ia32_AddrModeS;
734 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
735 use_am && ia32_use_source_address_mode(block, op1, op2)) {
737 build_address(am, op1);
739 if(mode_is_float(mode)) {
740 noreg = ia32_new_NoReg_vfp(env_cg);
745 if(new_op2 != NULL) {
748 new_op1 = be_transform_node(op2);
750 am->ins_permuted = 1;
752 am->op_type = ia32_AddrModeS;
754 if(flags & match_try_am) {
757 am->op_type = ia32_Normal;
761 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
763 new_op2 = be_transform_node(op2);
764 am->op_type = ia32_Normal;
765 am->ls_mode = get_irn_mode(op2);
766 if(flags & match_mode_neutral)
767 am->ls_mode = mode_Iu;
769 if(addr->base == NULL)
770 addr->base = noreg_gp;
771 if(addr->index == NULL)
772 addr->index = noreg_gp;
773 if(addr->mem == NULL)
774 addr->mem = new_NoMem();
776 am->new_op1 = new_op1;
777 am->new_op2 = new_op2;
778 am->commutative = commutative;
781 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
783 ir_graph *irg = current_ir_graph;
787 if(am->mem_proj == NULL)
790 /* we have to create a mode_T so the old MemProj can attach to us */
791 mode = get_irn_mode(node);
792 load = get_Proj_pred(am->mem_proj);
794 mark_irn_visited(load);
795 be_set_transformed_node(load, node);
798 set_irn_mode(node, mode_T);
799 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
806 * Construct a standard binary operation, set AM and immediate if required.
808 * @param op1 The first operand
809 * @param op2 The second operand
810 * @param func The node constructor function
811 * @return The constructed ia32 node.
813 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
814 construct_binop_func *func, match_flags_t flags)
816 ir_node *block = get_nodes_block(node);
817 ir_node *new_block = be_transform_node(block);
818 ir_graph *irg = current_ir_graph;
819 dbg_info *dbgi = get_irn_dbg_info(node);
821 ia32_address_mode_t am;
822 ia32_address_t *addr = &am.addr;
824 match_arguments(&am, block, op1, op2, flags);
826 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
827 am.new_op1, am.new_op2);
828 set_am_attributes(new_node, &am);
829 /* we can't use source address mode anymore when using immediates */
830 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
831 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
832 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
834 new_node = fix_mem_proj(new_node, &am);
841 n_ia32_l_binop_right,
842 n_ia32_l_binop_eflags
844 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
845 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
846 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
847 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
848 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
849 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
852 * Construct a binary operation which also consumes the eflags.
854 * @param node The node to transform
855 * @param func The node constructor function
856 * @param flags The match flags
857 * @return The constructor ia32 node
859 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
862 ir_node *src_block = get_nodes_block(node);
863 ir_node *block = be_transform_node(src_block);
864 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
865 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
866 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
867 ir_node *new_eflags = be_transform_node(eflags);
868 ir_graph *irg = current_ir_graph;
869 dbg_info *dbgi = get_irn_dbg_info(node);
871 ia32_address_mode_t am;
872 ia32_address_t *addr = &am.addr;
874 match_arguments(&am, src_block, op1, op2, flags);
876 new_node = func(dbgi, irg, block, addr->base, addr->index,
877 addr->mem, am.new_op1, am.new_op2, new_eflags);
878 set_am_attributes(new_node, &am);
879 /* we can't use source address mode anymore when using immediates */
880 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
881 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
882 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
884 new_node = fix_mem_proj(new_node, &am);
889 static ir_node *get_fpcw(void)
892 if(initial_fpcw != NULL)
895 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
896 &ia32_fp_cw_regs[REG_FPCW]);
897 initial_fpcw = be_transform_node(fpcw);
903 * Construct a standard binary operation, set AM and immediate if required.
905 * @param op1 The first operand
906 * @param op2 The second operand
907 * @param func The node constructor function
908 * @return The constructed ia32 node.
910 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
911 construct_binop_float_func *func,
914 ir_graph *irg = current_ir_graph;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *block = get_nodes_block(node);
917 ir_node *new_block = be_transform_node(block);
918 ir_mode *mode = get_irn_mode(node);
920 ia32_address_mode_t am;
921 ia32_address_t *addr = &am.addr;
923 /* cannot use addresmode with long double on x87 */
924 if (get_mode_size_bits(mode) > 64) flags &= ~match_am;
926 match_arguments(&am, block, op1, op2, flags);
928 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
929 am.new_op1, am.new_op2, get_fpcw());
930 set_am_attributes(new_node, &am);
932 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
934 new_node = fix_mem_proj(new_node, &am);
940 * Construct a shift/rotate binary operation, sets AM and immediate if required.
942 * @param op1 The first operand
943 * @param op2 The second operand
944 * @param func The node constructor function
945 * @return The constructed ia32 node.
947 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
948 construct_shift_func *func,
951 dbg_info *dbgi = get_irn_dbg_info(node);
952 ir_graph *irg = current_ir_graph;
953 ir_node *block = get_nodes_block(node);
954 ir_node *new_block = be_transform_node(block);
955 ir_mode *mode = get_irn_mode(node);
960 assert(! mode_is_float(mode));
961 assert(flags & match_immediate);
962 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
964 if(flags & match_mode_neutral) {
965 op1 = ia32_skip_downconv(op1);
967 new_op1 = be_transform_node(op1);
969 /* the shift amount can be any mode that is bigger than 5 bits, since all
970 * other bits are ignored anyway */
971 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
972 op2 = get_Conv_op(op2);
973 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
975 new_op2 = create_immediate_or_transform(op2, 0);
977 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
978 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
980 /* lowered shift instruction may have a dependency operand, handle it here */
981 if (get_irn_arity(node) == 3) {
982 /* we have a dependency */
983 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
984 add_irn_dep(new_node, new_dep);
992 * Construct a standard unary operation, set AM and immediate if required.
994 * @param op The operand
995 * @param func The node constructor function
996 * @return The constructed ia32 node.
998 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1001 ir_graph *irg = current_ir_graph;
1002 dbg_info *dbgi = get_irn_dbg_info(node);
1003 ir_node *block = get_nodes_block(node);
1004 ir_node *new_block = be_transform_node(block);
1008 assert(flags == 0 || flags == match_mode_neutral);
1009 if(flags & match_mode_neutral) {
1010 op = ia32_skip_downconv(op);
1013 new_op = be_transform_node(op);
1014 new_node = func(dbgi, irg, new_block, new_op);
1016 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1021 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1022 ia32_address_t *addr)
1024 ir_graph *irg = current_ir_graph;
1025 ir_node *base = addr->base;
1026 ir_node *index = addr->index;
1030 base = ia32_new_NoReg_gp(env_cg);
1032 base = be_transform_node(base);
1036 index = ia32_new_NoReg_gp(env_cg);
1038 index = be_transform_node(index);
1041 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1042 set_address(res, addr);
1047 static int am_has_immediates(const ia32_address_t *addr)
1049 return addr->offset != 0 || addr->symconst_ent != NULL
1050 || addr->frame_entity || addr->use_frame;
1054 * Creates an ia32 Add.
1056 * @return the created ia32 Add node
1058 static ir_node *gen_Add(ir_node *node) {
1059 ir_graph *irg = current_ir_graph;
1060 dbg_info *dbgi = get_irn_dbg_info(node);
1061 ir_node *block = get_nodes_block(node);
1062 ir_node *new_block = be_transform_node(block);
1063 ir_node *op1 = get_Add_left(node);
1064 ir_node *op2 = get_Add_right(node);
1065 ir_mode *mode = get_irn_mode(node);
1067 ir_node *add_immediate_op;
1068 ia32_address_t addr;
1069 ia32_address_mode_t am;
1071 if (mode_is_float(mode)) {
1072 if (USE_SSE2(env_cg))
1073 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1074 match_commutative | match_am);
1076 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1077 match_commutative | match_am);
1080 ia32_mark_non_am(node);
1082 op2 = ia32_skip_downconv(op2);
1083 op1 = ia32_skip_downconv(op1);
1087 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1088 * 1. Add with immediate -> Lea
1089 * 2. Add with possible source address mode -> Add
1090 * 3. Otherwise -> Lea
1092 memset(&addr, 0, sizeof(addr));
1093 ia32_create_address_mode(&addr, node, /*force=*/1);
1094 add_immediate_op = NULL;
1096 if(addr.base == NULL && addr.index == NULL) {
1097 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1098 addr.symconst_sign, addr.offset);
1099 add_irn_dep(new_node, get_irg_frame(irg));
1100 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1103 /* add with immediate? */
1104 if(addr.index == NULL) {
1105 add_immediate_op = addr.base;
1106 } else if(addr.base == NULL && addr.scale == 0) {
1107 add_immediate_op = addr.index;
1110 if(add_immediate_op != NULL) {
1111 if(!am_has_immediates(&addr)) {
1112 #ifdef DEBUG_libfirm
1113 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1116 return be_transform_node(add_immediate_op);
1119 new_node = create_lea_from_address(dbgi, new_block, &addr);
1120 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1124 /* test if we can use source address mode */
1125 match_arguments(&am, block, op1, op2, match_commutative
1126 | match_mode_neutral | match_am | match_immediate | match_try_am);
1128 /* construct an Add with source address mode */
1129 if (am.op_type == ia32_AddrModeS) {
1130 ia32_address_t *am_addr = &am.addr;
1131 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1132 am_addr->index, am_addr->mem, am.new_op1,
1134 set_am_attributes(new_node, &am);
1135 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1137 new_node = fix_mem_proj(new_node, &am);
1142 /* otherwise construct a lea */
1143 new_node = create_lea_from_address(dbgi, new_block, &addr);
1144 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1149 * Creates an ia32 Mul.
1151 * @return the created ia32 Mul node
1153 static ir_node *gen_Mul(ir_node *node) {
1154 ir_node *op1 = get_Mul_left(node);
1155 ir_node *op2 = get_Mul_right(node);
1156 ir_mode *mode = get_irn_mode(node);
1158 if (mode_is_float(mode)) {
1159 if (USE_SSE2(env_cg))
1160 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1161 match_commutative | match_am);
1163 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1164 match_commutative | match_am);
1168 for the lower 32bit of the result it doesn't matter whether we use
1169 signed or unsigned multiplication so we use IMul as it has fewer
1172 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1173 match_commutative | match_am | match_mode_neutral |
1174 match_immediate | match_am_and_immediates);
1178 * Creates an ia32 Mulh.
1179 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1180 * this result while Mul returns the lower 32 bit.
1182 * @return the created ia32 Mulh node
1184 static ir_node *gen_Mulh(ir_node *node)
1186 ir_node *block = get_nodes_block(node);
1187 ir_node *new_block = be_transform_node(block);
1188 ir_graph *irg = current_ir_graph;
1189 dbg_info *dbgi = get_irn_dbg_info(node);
1190 ir_mode *mode = get_irn_mode(node);
1191 ir_node *op1 = get_Mulh_left(node);
1192 ir_node *op2 = get_Mulh_right(node);
1195 match_flags_t flags;
1196 ia32_address_mode_t am;
1197 ia32_address_t *addr = &am.addr;
1199 flags = match_commutative | match_am;
1201 assert(!mode_is_float(mode) && "Mulh with float not supported");
1202 assert(get_mode_size_bits(mode) == 32);
1204 match_arguments(&am, block, op1, op2, flags);
1206 if (mode_is_signed(mode)) {
1207 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1208 addr->index, addr->mem, am.new_op1,
1211 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1212 addr->index, addr->mem, am.new_op1,
1216 set_am_attributes(new_node, &am);
1217 /* we can't use source address mode anymore when using immediates */
1218 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1219 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1220 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1222 assert(get_irn_mode(new_node) == mode_T);
1224 fix_mem_proj(new_node, &am);
1226 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1227 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1228 mode_Iu, pn_ia32_IMul1OP_EDX);
1236 * Creates an ia32 And.
1238 * @return The created ia32 And node
1240 static ir_node *gen_And(ir_node *node) {
1241 ir_node *op1 = get_And_left(node);
1242 ir_node *op2 = get_And_right(node);
1243 assert(! mode_is_float(get_irn_mode(node)));
1245 /* is it a zero extension? */
1246 if (is_Const(op2)) {
1247 tarval *tv = get_Const_tarval(op2);
1248 long v = get_tarval_long(tv);
1250 if (v == 0xFF || v == 0xFFFF) {
1251 dbg_info *dbgi = get_irn_dbg_info(node);
1252 ir_node *block = get_nodes_block(node);
1259 assert(v == 0xFFFF);
1262 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1268 return gen_binop(node, op1, op2, new_rd_ia32_And,
1269 match_commutative | match_mode_neutral | match_am
1276 * Creates an ia32 Or.
1278 * @return The created ia32 Or node
1280 static ir_node *gen_Or(ir_node *node) {
1281 ir_node *op1 = get_Or_left(node);
1282 ir_node *op2 = get_Or_right(node);
1284 assert (! mode_is_float(get_irn_mode(node)));
1285 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1286 | match_mode_neutral | match_am | match_immediate);
1292 * Creates an ia32 Eor.
1294 * @return The created ia32 Eor node
1296 static ir_node *gen_Eor(ir_node *node) {
1297 ir_node *op1 = get_Eor_left(node);
1298 ir_node *op2 = get_Eor_right(node);
1300 assert(! mode_is_float(get_irn_mode(node)));
1301 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1302 | match_mode_neutral | match_am | match_immediate);
1307 * Creates an ia32 Sub.
1309 * @return The created ia32 Sub node
1311 static ir_node *gen_Sub(ir_node *node) {
1312 ir_node *op1 = get_Sub_left(node);
1313 ir_node *op2 = get_Sub_right(node);
1314 ir_mode *mode = get_irn_mode(node);
1316 if (mode_is_float(mode)) {
1317 if (USE_SSE2(env_cg))
1318 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1320 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1325 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1329 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1330 | match_am | match_immediate);
1334 * Generates an ia32 DivMod with additional infrastructure for the
1335 * register allocator if needed.
1337 static ir_node *create_Div(ir_node *node)
1339 ir_graph *irg = current_ir_graph;
1340 dbg_info *dbgi = get_irn_dbg_info(node);
1341 ir_node *block = get_nodes_block(node);
1342 ir_node *new_block = be_transform_node(block);
1349 ir_node *sign_extension;
1351 ia32_address_mode_t am;
1352 ia32_address_t *addr = &am.addr;
1354 /* the upper bits have random contents for smaller modes */
1356 switch (get_irn_opcode(node)) {
1358 op1 = get_Div_left(node);
1359 op2 = get_Div_right(node);
1360 mem = get_Div_mem(node);
1361 mode = get_Div_resmode(node);
1362 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1365 op1 = get_Mod_left(node);
1366 op2 = get_Mod_right(node);
1367 mem = get_Mod_mem(node);
1368 mode = get_Mod_resmode(node);
1369 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1372 op1 = get_DivMod_left(node);
1373 op2 = get_DivMod_right(node);
1374 mem = get_DivMod_mem(node);
1375 mode = get_DivMod_resmode(node);
1376 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1379 panic("invalid divmod node %+F", node);
1382 match_arguments(&am, block, op1, op2, match_am);
1384 if(!is_NoMem(mem)) {
1385 new_mem = be_transform_node(mem);
1386 if(!is_NoMem(addr->mem)) {
1390 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1393 new_mem = addr->mem;
1396 if (mode_is_signed(mode)) {
1397 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1398 add_irn_dep(produceval, get_irg_frame(irg));
1399 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1402 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1403 addr->index, new_mem, am.new_op1,
1404 sign_extension, am.new_op2);
1406 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1407 add_irn_dep(sign_extension, get_irg_frame(irg));
1409 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1410 addr->index, new_mem, am.new_op1,
1411 sign_extension, am.new_op2);
1414 set_ia32_exc_label(new_node, has_exc);
1415 set_irn_pinned(new_node, get_irn_pinned(node));
1417 set_am_attributes(new_node, &am);
1418 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1420 new_node = fix_mem_proj(new_node, &am);
1426 static ir_node *gen_Mod(ir_node *node) {
1427 return create_Div(node);
1430 static ir_node *gen_Div(ir_node *node) {
1431 return create_Div(node);
1434 static ir_node *gen_DivMod(ir_node *node) {
1435 return create_Div(node);
1441 * Creates an ia32 floating Div.
1443 * @return The created ia32 xDiv node
1445 static ir_node *gen_Quot(ir_node *node)
1447 ir_node *op1 = get_Quot_left(node);
1448 ir_node *op2 = get_Quot_right(node);
1450 if (USE_SSE2(env_cg)) {
1451 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1453 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1459 * Creates an ia32 Shl.
1461 * @return The created ia32 Shl node
1463 static ir_node *gen_Shl(ir_node *node) {
1464 ir_node *left = get_Shl_left(node);
1465 ir_node *right = get_Shl_right(node);
1467 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1468 match_mode_neutral | match_immediate);
1472 * Creates an ia32 Shr.
1474 * @return The created ia32 Shr node
1476 static ir_node *gen_Shr(ir_node *node) {
1477 ir_node *left = get_Shr_left(node);
1478 ir_node *right = get_Shr_right(node);
1480 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1486 * Creates an ia32 Sar.
1488 * @return The created ia32 Shrs node
1490 static ir_node *gen_Shrs(ir_node *node) {
1491 ir_node *left = get_Shrs_left(node);
1492 ir_node *right = get_Shrs_right(node);
1493 ir_mode *mode = get_irn_mode(node);
1495 if(is_Const(right) && mode == mode_Is) {
1496 tarval *tv = get_Const_tarval(right);
1497 long val = get_tarval_long(tv);
1499 /* this is a sign extension */
1500 ir_graph *irg = current_ir_graph;
1501 dbg_info *dbgi = get_irn_dbg_info(node);
1502 ir_node *block = be_transform_node(get_nodes_block(node));
1504 ir_node *new_op = be_transform_node(op);
1505 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1506 add_irn_dep(pval, get_irg_frame(irg));
1508 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1512 /* 8 or 16 bit sign extension? */
1513 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1514 ir_node *shl_left = get_Shl_left(left);
1515 ir_node *shl_right = get_Shl_right(left);
1516 if(is_Const(shl_right)) {
1517 tarval *tv1 = get_Const_tarval(right);
1518 tarval *tv2 = get_Const_tarval(shl_right);
1519 if(tv1 == tv2 && tarval_is_long(tv1)) {
1520 long val = get_tarval_long(tv1);
1521 if(val == 16 || val == 24) {
1522 dbg_info *dbgi = get_irn_dbg_info(node);
1523 ir_node *block = get_nodes_block(node);
1533 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1542 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1548 * Creates an ia32 RotL.
1550 * @param op1 The first operator
1551 * @param op2 The second operator
1552 * @return The created ia32 RotL node
1554 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1555 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1561 * Creates an ia32 RotR.
1562 * NOTE: There is no RotR with immediate because this would always be a RotL
1563 * "imm-mode_size_bits" which can be pre-calculated.
1565 * @param op1 The first operator
1566 * @param op2 The second operator
1567 * @return The created ia32 RotR node
1569 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1570 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1576 * Creates an ia32 RotR or RotL (depending on the found pattern).
1578 * @return The created ia32 RotL or RotR node
1580 static ir_node *gen_Rot(ir_node *node) {
1581 ir_node *rotate = NULL;
1582 ir_node *op1 = get_Rot_left(node);
1583 ir_node *op2 = get_Rot_right(node);
1585 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1586 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1587 that means we can create a RotR instead of an Add and a RotL */
1589 if (get_irn_op(op2) == op_Add) {
1591 ir_node *left = get_Add_left(add);
1592 ir_node *right = get_Add_right(add);
1593 if (is_Const(right)) {
1594 tarval *tv = get_Const_tarval(right);
1595 ir_mode *mode = get_irn_mode(node);
1596 long bits = get_mode_size_bits(mode);
1598 if (get_irn_op(left) == op_Minus &&
1599 tarval_is_long(tv) &&
1600 get_tarval_long(tv) == bits &&
1603 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1604 rotate = gen_RotR(node, op1, get_Minus_op(left));
1609 if (rotate == NULL) {
1610 rotate = gen_RotL(node, op1, op2);
1619 * Transforms a Minus node.
1621 * @return The created ia32 Minus node
1623 static ir_node *gen_Minus(ir_node *node)
1625 ir_node *op = get_Minus_op(node);
1626 ir_node *block = be_transform_node(get_nodes_block(node));
1627 ir_graph *irg = current_ir_graph;
1628 dbg_info *dbgi = get_irn_dbg_info(node);
1629 ir_mode *mode = get_irn_mode(node);
1634 if (mode_is_float(mode)) {
1635 ir_node *new_op = be_transform_node(op);
1636 if (USE_SSE2(env_cg)) {
1637 /* TODO: non-optimal... if we have many xXors, then we should
1638 * rather create a load for the const and use that instead of
1639 * several AM nodes... */
1640 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1641 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1642 ir_node *nomem = new_rd_NoMem(irg);
1644 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1645 nomem, new_op, noreg_xmm);
1647 size = get_mode_size_bits(mode);
1648 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1650 set_ia32_am_sc(new_node, ent);
1651 set_ia32_op_type(new_node, ia32_AddrModeS);
1652 set_ia32_ls_mode(new_node, mode);
1654 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1657 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1660 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1666 * Transforms a Not node.
1668 * @return The created ia32 Not node
1670 static ir_node *gen_Not(ir_node *node) {
1671 ir_node *op = get_Not_op(node);
1673 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1674 assert (! mode_is_float(get_irn_mode(node)));
1676 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1682 * Transforms an Abs node.
1684 * @return The created ia32 Abs node
1686 static ir_node *gen_Abs(ir_node *node)
1688 ir_node *block = be_transform_node(get_nodes_block(node));
1689 ir_node *op = get_Abs_op(node);
1690 ir_node *new_op = be_transform_node(op);
1691 ir_graph *irg = current_ir_graph;
1692 dbg_info *dbgi = get_irn_dbg_info(node);
1693 ir_mode *mode = get_irn_mode(node);
1694 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1695 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1696 ir_node *nomem = new_NoMem();
1701 if (mode_is_float(mode)) {
1702 if (USE_SSE2(env_cg)) {
1703 new_node = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp,
1704 nomem, new_op, noreg_fp);
1706 size = get_mode_size_bits(mode);
1707 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1709 set_ia32_am_sc(new_node, ent);
1711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1713 set_ia32_op_type(new_node, ia32_AddrModeS);
1714 set_ia32_ls_mode(new_node, mode);
1716 new_node = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1717 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1721 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1722 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1725 assert(get_mode_size_bits(mode) == 32);
1727 add_irn_dep(pval, get_irg_frame(irg));
1728 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1730 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1731 new_op, sign_extension);
1732 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1734 new_node = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1735 xor, sign_extension);
1736 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1742 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1744 ir_graph *irg = current_ir_graph;
1752 /* we have a Cmp as input */
1754 ir_node *pred = get_Proj_pred(node);
1756 flags = be_transform_node(pred);
1757 *pnc_out = get_Proj_proj(node);
1762 /* a mode_b value, we have to compare it against 0 */
1763 dbgi = get_irn_dbg_info(node);
1764 new_block = be_transform_node(get_nodes_block(node));
1765 new_op = be_transform_node(node);
1766 noreg = ia32_new_NoReg_gp(env_cg);
1767 nomem = new_NoMem();
1768 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1769 new_op, new_op, 0, 0);
1770 *pnc_out = pn_Cmp_Lg;
1775 * Transforms a Load.
1777 * @return the created ia32 Load node
1779 static ir_node *gen_Load(ir_node *node) {
1780 ir_node *old_block = get_nodes_block(node);
1781 ir_node *block = be_transform_node(old_block);
1782 ir_node *ptr = get_Load_ptr(node);
1783 ir_node *mem = get_Load_mem(node);
1784 ir_node *new_mem = be_transform_node(mem);
1787 ir_graph *irg = current_ir_graph;
1788 dbg_info *dbgi = get_irn_dbg_info(node);
1789 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1790 ir_mode *mode = get_Load_mode(node);
1793 ia32_address_t addr;
1795 /* construct load address */
1796 memset(&addr, 0, sizeof(addr));
1797 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1804 base = be_transform_node(base);
1810 index = be_transform_node(index);
1813 if (mode_is_float(mode)) {
1814 if (USE_SSE2(env_cg)) {
1815 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1817 res_mode = mode_xmm;
1819 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1821 res_mode = mode_vfp;
1824 assert(mode != mode_b);
1826 /* create a conv node with address mode for smaller modes */
1827 if(get_mode_size_bits(mode) < 32) {
1828 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1829 new_mem, noreg, mode);
1831 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1836 set_irn_pinned(new_node, get_irn_pinned(node));
1837 set_ia32_op_type(new_node, ia32_AddrModeS);
1838 set_ia32_ls_mode(new_node, mode);
1839 set_address(new_node, &addr);
1841 /* make sure we are scheduled behind the initial IncSP/Barrier
1842 * to avoid spills being placed before it
1844 if (block == get_irg_start_block(irg)) {
1845 add_irn_dep(new_node, get_irg_frame(irg));
1848 set_ia32_exc_label(new_node,
1849 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1850 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1855 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1856 ir_node *ptr, ir_node *other)
1863 /* we only use address mode if we're the only user of the load */
1864 if(get_irn_n_edges(node) > 1)
1867 load = get_Proj_pred(node);
1870 if(get_nodes_block(load) != block)
1873 /* Store should be attached to the load */
1874 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1876 /* store should have the same pointer as the load */
1877 if(get_Load_ptr(load) != ptr)
1880 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1881 if(other != NULL && get_nodes_block(other) == block
1882 && heights_reachable_in_block(heights, other, load))
1888 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1889 ir_node *mem, ir_node *ptr, ir_mode *mode,
1890 construct_binop_dest_func *func,
1891 construct_binop_dest_func *func8bit,
1892 match_flags_t flags)
1894 ir_node *src_block = get_nodes_block(node);
1896 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1897 ir_graph *irg = current_ir_graph;
1902 ia32_address_mode_t am;
1903 ia32_address_t *addr = &am.addr;
1904 memset(&am, 0, sizeof(am));
1906 assert(flags & match_dest_am);
1907 assert(flags & match_immediate); /* there is no destam node without... */
1908 commutative = (flags & match_commutative) != 0;
1910 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1911 build_address(&am, op1);
1912 new_op = create_immediate_or_transform(op2, 0);
1913 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1914 build_address(&am, op2);
1915 new_op = create_immediate_or_transform(op1, 0);
1920 if(addr->base == NULL)
1921 addr->base = noreg_gp;
1922 if(addr->index == NULL)
1923 addr->index = noreg_gp;
1924 if(addr->mem == NULL)
1925 addr->mem = new_NoMem();
1927 dbgi = get_irn_dbg_info(node);
1928 block = be_transform_node(src_block);
1929 if(get_mode_size_bits(mode) == 8) {
1930 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1933 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1936 set_address(new_node, addr);
1937 set_ia32_op_type(new_node, ia32_AddrModeD);
1938 set_ia32_ls_mode(new_node, mode);
1939 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1944 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1945 ir_node *ptr, ir_mode *mode,
1946 construct_unop_dest_func *func)
1948 ir_graph *irg = current_ir_graph;
1949 ir_node *src_block = get_nodes_block(node);
1953 ia32_address_mode_t am;
1954 ia32_address_t *addr = &am.addr;
1955 memset(&am, 0, sizeof(am));
1957 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1960 build_address(&am, op);
1962 dbgi = get_irn_dbg_info(node);
1963 block = be_transform_node(src_block);
1964 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1965 set_address(new_node, addr);
1966 set_ia32_op_type(new_node, ia32_AddrModeD);
1967 set_ia32_ls_mode(new_node, mode);
1968 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1973 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1974 ir_mode *mode = get_irn_mode(node);
1975 ir_node *psi_true = get_Psi_val(node, 0);
1976 ir_node *psi_default = get_Psi_default(node);
1987 ia32_address_t addr;
1989 if(get_mode_size_bits(mode) != 8)
1992 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1994 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2000 build_address_ptr(&addr, ptr, mem);
2002 irg = current_ir_graph;
2003 dbgi = get_irn_dbg_info(node);
2004 block = get_nodes_block(node);
2005 new_block = be_transform_node(block);
2006 cond = get_Psi_cond(node, 0);
2007 flags = get_flags_node(cond, &pnc);
2008 new_mem = be_transform_node(mem);
2009 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2010 addr.index, addr.mem, flags, pnc, negated);
2011 set_address(new_node, &addr);
2012 set_ia32_op_type(new_node, ia32_AddrModeD);
2013 set_ia32_ls_mode(new_node, mode);
2014 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2019 static ir_node *try_create_dest_am(ir_node *node) {
2020 ir_node *val = get_Store_value(node);
2021 ir_node *mem = get_Store_mem(node);
2022 ir_node *ptr = get_Store_ptr(node);
2023 ir_mode *mode = get_irn_mode(val);
2024 int bits = get_mode_size_bits(mode);
2029 /* handle only GP modes for now... */
2030 if(!mode_needs_gp_reg(mode))
2034 /* store must be the only user of the val node */
2035 if(get_irn_n_edges(val) > 1)
2037 /* skip pointless convs */
2039 ir_node *conv_op = get_Conv_op(val);
2040 ir_mode *pred_mode = get_irn_mode(conv_op);
2041 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2049 /* value must be in the same block */
2050 if(get_nodes_block(node) != get_nodes_block(val))
2053 switch(get_irn_opcode(val)) {
2055 op1 = get_Add_left(val);
2056 op2 = get_Add_right(val);
2057 if(is_Const_1(op2)) {
2058 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2059 new_rd_ia32_IncMem);
2061 } else if(is_Const_Minus_1(op2)) {
2062 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2063 new_rd_ia32_DecMem);
2066 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2067 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2068 match_dest_am | match_commutative |
2072 op1 = get_Sub_left(val);
2073 op2 = get_Sub_right(val);
2075 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2078 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2079 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2080 match_dest_am | match_immediate |
2084 op1 = get_And_left(val);
2085 op2 = get_And_right(val);
2086 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2087 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2088 match_dest_am | match_commutative |
2092 op1 = get_Or_left(val);
2093 op2 = get_Or_right(val);
2094 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2095 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2096 match_dest_am | match_commutative |
2100 op1 = get_Eor_left(val);
2101 op2 = get_Eor_right(val);
2102 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2103 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2104 match_dest_am | match_commutative |
2108 op1 = get_Shl_left(val);
2109 op2 = get_Shl_right(val);
2110 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2111 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2112 match_dest_am | match_immediate);
2115 op1 = get_Shr_left(val);
2116 op2 = get_Shr_right(val);
2117 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2118 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2119 match_dest_am | match_immediate);
2122 op1 = get_Shrs_left(val);
2123 op2 = get_Shrs_right(val);
2124 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2125 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2126 match_dest_am | match_immediate);
2129 op1 = get_Rot_left(val);
2130 op2 = get_Rot_right(val);
2131 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2132 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2133 match_dest_am | match_immediate);
2135 /* TODO: match ROR patterns... */
2137 new_node = try_create_SetMem(val, ptr, mem);
2140 op1 = get_Minus_op(val);
2141 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2144 /* should be lowered already */
2145 assert(mode != mode_b);
2146 op1 = get_Not_op(val);
2147 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2153 if(new_node != NULL) {
2154 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2155 get_irn_pinned(node) == op_pin_state_pinned) {
2156 set_irn_pinned(new_node, op_pin_state_pinned);
2163 static int is_float_to_int32_conv(const ir_node *node)
2165 ir_mode *mode = get_irn_mode(node);
2169 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2174 conv_op = get_Conv_op(node);
2175 conv_mode = get_irn_mode(conv_op);
2177 if(!mode_is_float(conv_mode))
2184 * Transforms a Store.
2186 * @return the created ia32 Store node
2188 static ir_node *gen_Store(ir_node *node)
2190 ir_node *block = get_nodes_block(node);
2191 ir_node *new_block = be_transform_node(block);
2192 ir_node *ptr = get_Store_ptr(node);
2193 ir_node *val = get_Store_value(node);
2194 ir_node *mem = get_Store_mem(node);
2195 ir_graph *irg = current_ir_graph;
2196 dbg_info *dbgi = get_irn_dbg_info(node);
2197 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2198 ir_mode *mode = get_irn_mode(val);
2201 ia32_address_t addr;
2203 /* check for destination address mode */
2204 new_node = try_create_dest_am(node);
2205 if(new_node != NULL)
2208 /* construct store address */
2209 memset(&addr, 0, sizeof(addr));
2210 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2212 if(addr.base == NULL) {
2215 addr.base = be_transform_node(addr.base);
2218 if(addr.index == NULL) {
2221 addr.index = be_transform_node(addr.index);
2223 addr.mem = be_transform_node(mem);
2225 if (mode_is_float(mode)) {
2226 /* convs (and strict-convs) before stores are unnecessary if the mode
2228 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2229 val = get_Conv_op(val);
2231 new_val = be_transform_node(val);
2232 if (USE_SSE2(env_cg)) {
2233 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2234 addr.index, addr.mem, new_val);
2236 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2237 addr.index, addr.mem, new_val, mode);
2239 } else if(is_float_to_int32_conv(val)) {
2240 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2241 val = get_Conv_op(val);
2243 /* convs (and strict-convs) before stores are unnecessary if the mode
2245 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2246 val = get_Conv_op(val);
2248 new_val = be_transform_node(val);
2250 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2251 addr.index, addr.mem, new_val, trunc_mode);
2253 new_val = create_immediate_or_transform(val, 0);
2254 assert(mode != mode_b);
2256 if (get_mode_size_bits(mode) == 8) {
2257 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2258 addr.index, addr.mem, new_val);
2260 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2261 addr.index, addr.mem, new_val);
2265 set_irn_pinned(new_node, get_irn_pinned(node));
2266 set_ia32_op_type(new_node, ia32_AddrModeD);
2267 set_ia32_ls_mode(new_node, mode);
2269 set_ia32_exc_label(new_node,
2270 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2271 set_address(new_node, &addr);
2272 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2277 static ir_node *create_Switch(ir_node *node)
2279 ir_graph *irg = current_ir_graph;
2280 dbg_info *dbgi = get_irn_dbg_info(node);
2281 ir_node *block = be_transform_node(get_nodes_block(node));
2282 ir_node *sel = get_Cond_selector(node);
2283 ir_node *new_sel = be_transform_node(sel);
2284 int switch_min = INT_MAX;
2286 const ir_edge_t *edge;
2288 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2290 /* determine the smallest switch case value */
2291 foreach_out_edge(node, edge) {
2292 ir_node *proj = get_edge_src_irn(edge);
2293 int pn = get_Proj_proj(proj);
2298 if (switch_min != 0) {
2299 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2301 /* if smallest switch case is not 0 we need an additional sub */
2302 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2303 add_ia32_am_offs_int(new_sel, -switch_min);
2304 set_ia32_op_type(new_sel, ia32_AddrModeS);
2306 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2309 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2310 get_Cond_defaultProj(node));
2311 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2316 static ir_node *gen_Cond(ir_node *node) {
2317 ir_node *block = get_nodes_block(node);
2318 ir_node *new_block = be_transform_node(block);
2319 ir_graph *irg = current_ir_graph;
2320 dbg_info *dbgi = get_irn_dbg_info(node);
2321 ir_node *sel = get_Cond_selector(node);
2322 ir_mode *sel_mode = get_irn_mode(sel);
2323 ir_node *flags = NULL;
2327 if (sel_mode != mode_b) {
2328 return create_Switch(node);
2331 /* we get flags from a cmp */
2332 flags = get_flags_node(sel, &pnc);
2334 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2335 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2343 * Transforms a CopyB node.
2345 * @return The transformed node.
2347 static ir_node *gen_CopyB(ir_node *node) {
2348 ir_node *block = be_transform_node(get_nodes_block(node));
2349 ir_node *src = get_CopyB_src(node);
2350 ir_node *new_src = be_transform_node(src);
2351 ir_node *dst = get_CopyB_dst(node);
2352 ir_node *new_dst = be_transform_node(dst);
2353 ir_node *mem = get_CopyB_mem(node);
2354 ir_node *new_mem = be_transform_node(mem);
2355 ir_node *res = NULL;
2356 ir_graph *irg = current_ir_graph;
2357 dbg_info *dbgi = get_irn_dbg_info(node);
2358 int size = get_type_size_bytes(get_CopyB_type(node));
2361 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2362 /* then we need the size explicitly in ECX. */
2363 if (size >= 32 * 4) {
2364 rem = size & 0x3; /* size % 4 */
2367 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2368 add_irn_dep(res, get_irg_frame(irg));
2370 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2373 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2376 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2379 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2384 static ir_node *gen_be_Copy(ir_node *node)
2386 ir_node *new_node = be_duplicate_node(node);
2387 ir_mode *mode = get_irn_mode(new_node);
2389 if (mode_needs_gp_reg(mode)) {
2390 set_irn_mode(new_node, mode_Iu);
2396 static ir_node *create_Fucom(ir_node *node)
2398 ir_graph *irg = current_ir_graph;
2399 dbg_info *dbgi = get_irn_dbg_info(node);
2400 ir_node *block = get_nodes_block(node);
2401 ir_node *new_block = be_transform_node(block);
2402 ir_node *left = get_Cmp_left(node);
2403 ir_node *new_left = be_transform_node(left);
2404 ir_node *right = get_Cmp_right(node);
2408 if(transform_config.use_fucomi) {
2409 new_right = be_transform_node(right);
2410 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2412 set_ia32_commutative(new_node);
2413 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2415 if(transform_config.use_ftst && is_Const_null(right)) {
2416 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2419 new_right = be_transform_node(right);
2420 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2424 set_ia32_commutative(new_node);
2426 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2428 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2429 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2435 static ir_node *create_Ucomi(ir_node *node)
2437 ir_graph *irg = current_ir_graph;
2438 dbg_info *dbgi = get_irn_dbg_info(node);
2439 ir_node *src_block = get_nodes_block(node);
2440 ir_node *new_block = be_transform_node(src_block);
2441 ir_node *left = get_Cmp_left(node);
2442 ir_node *right = get_Cmp_right(node);
2444 ia32_address_mode_t am;
2445 ia32_address_t *addr = &am.addr;
2447 match_arguments(&am, src_block, left, right, match_commutative | match_am);
2449 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2450 addr->mem, am.new_op1, am.new_op2,
2452 set_am_attributes(new_node, &am);
2454 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2456 new_node = fix_mem_proj(new_node, &am);
2462 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2463 * to fold an and into a test node
2465 static int can_fold_test_and(ir_node *node)
2467 const ir_edge_t *edge;
2469 /** we can only have eq and lg projs */
2470 foreach_out_edge(node, edge) {
2471 ir_node *proj = get_edge_src_irn(edge);
2472 pn_Cmp pnc = get_Proj_proj(proj);
2473 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2480 static ir_node *gen_Cmp(ir_node *node)
2482 ir_graph *irg = current_ir_graph;
2483 dbg_info *dbgi = get_irn_dbg_info(node);
2484 ir_node *block = get_nodes_block(node);
2485 ir_node *new_block = be_transform_node(block);
2486 ir_node *left = get_Cmp_left(node);
2487 ir_node *right = get_Cmp_right(node);
2488 ir_mode *cmp_mode = get_irn_mode(left);
2490 ia32_address_mode_t am;
2491 ia32_address_t *addr = &am.addr;
2494 if(mode_is_float(cmp_mode)) {
2495 if (USE_SSE2(env_cg)) {
2496 return create_Ucomi(node);
2498 return create_Fucom(node);
2502 assert(mode_needs_gp_reg(cmp_mode));
2504 /* we prefer the Test instruction where possible except cases where
2505 * we can use SourceAM */
2506 cmp_unsigned = !mode_is_signed(cmp_mode);
2507 if (is_Const_0(right)) {
2509 get_irn_n_edges(left) == 1 &&
2510 can_fold_test_and(node)) {
2511 /* Test(and_left, and_right) */
2512 ir_node *and_left = get_And_left(left);
2513 ir_node *and_right = get_And_right(left);
2514 ir_mode *mode = get_irn_mode(and_left);
2516 match_arguments(&am, block, and_left, and_right, match_commutative |
2517 match_am | match_8bit_am | match_16bit_am |
2518 match_am_and_immediates | match_immediate |
2519 match_8bit | match_16bit);
2520 if (get_mode_size_bits(mode) == 8) {
2521 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2522 addr->index, addr->mem, am.new_op1,
2523 am.new_op2, am.ins_permuted,
2526 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2527 addr->index, addr->mem, am.new_op1,
2528 am.new_op2, am.ins_permuted, cmp_unsigned);
2531 match_arguments(&am, block, NULL, left, match_am | match_8bit_am |
2532 match_16bit_am | match_8bit | match_16bit);
2533 if (am.op_type == ia32_AddrModeS) {
2535 ir_node *imm_zero = try_create_Immediate(right, 0);
2536 if (get_mode_size_bits(cmp_mode) == 8) {
2537 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2538 addr->index, addr->mem, am.new_op2,
2539 imm_zero, am.ins_permuted,
2542 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2543 addr->index, addr->mem, am.new_op2,
2544 imm_zero, am.ins_permuted, cmp_unsigned);
2547 /* Test(left, left) */
2548 if (get_mode_size_bits(cmp_mode) == 8) {
2549 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2550 addr->index, addr->mem, am.new_op2,
2551 am.new_op2, am.ins_permuted,
2554 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2555 addr->index, addr->mem, am.new_op2,
2556 am.new_op2, am.ins_permuted,
2562 /* Cmp(left, right) */
2563 match_arguments(&am, block, left, right, match_commutative | match_am |
2564 match_8bit_am | match_16bit_am | match_am_and_immediates |
2565 match_immediate | match_8bit | match_16bit);
2566 if (get_mode_size_bits(cmp_mode) == 8) {
2567 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2568 addr->index, addr->mem, am.new_op1,
2569 am.new_op2, am.ins_permuted,
2572 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2573 addr->index, addr->mem, am.new_op1,
2574 am.new_op2, am.ins_permuted, cmp_unsigned);
2577 set_am_attributes(new_node, &am);
2578 assert(cmp_mode != NULL);
2579 set_ia32_ls_mode(new_node, cmp_mode);
2581 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2583 new_node = fix_mem_proj(new_node, &am);
2588 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2590 ir_graph *irg = current_ir_graph;
2591 dbg_info *dbgi = get_irn_dbg_info(node);
2592 ir_node *block = get_nodes_block(node);
2593 ir_node *new_block = be_transform_node(block);
2594 ir_node *val_true = get_Psi_val(node, 0);
2595 ir_node *val_false = get_Psi_default(node);
2597 match_flags_t match_flags;
2598 ia32_address_mode_t am;
2599 ia32_address_t *addr;
2601 assert(transform_config.use_cmov);
2602 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2606 match_flags = match_commutative | match_am | match_16bit_am |
2609 match_arguments(&am, block, val_false, val_true, match_flags);
2611 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2612 addr->mem, am.new_op1, am.new_op2, new_flags,
2613 am.ins_permuted, pnc);
2614 set_am_attributes(new_node, &am);
2616 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2618 new_node = fix_mem_proj(new_node, &am);
2625 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2626 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2629 ir_graph *irg = current_ir_graph;
2630 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2631 ir_node *nomem = new_NoMem();
2632 ir_mode *mode = get_irn_mode(orig_node);
2635 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2636 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2638 /* we might need to conv the result up */
2639 if(get_mode_size_bits(mode) > 8) {
2640 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2641 nomem, new_node, mode_Bu);
2642 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2649 * Transforms a Psi node into CMov.
2651 * @return The transformed node.
2653 static ir_node *gen_Psi(ir_node *node)
2655 dbg_info *dbgi = get_irn_dbg_info(node);
2656 ir_node *block = get_nodes_block(node);
2657 ir_node *new_block = be_transform_node(block);
2658 ir_node *psi_true = get_Psi_val(node, 0);
2659 ir_node *psi_default = get_Psi_default(node);
2660 ir_node *cond = get_Psi_cond(node, 0);
2661 ir_node *flags = NULL;
2665 assert(get_Psi_n_conds(node) == 1);
2666 assert(get_irn_mode(cond) == mode_b);
2667 assert(mode_needs_gp_reg(get_irn_mode(node)));
2669 flags = get_flags_node(cond, &pnc);
2671 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2672 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2673 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2674 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2676 new_node = create_CMov(node, flags, pnc);
2683 * Create a conversion from x87 state register to general purpose.
2685 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2686 ir_node *block = be_transform_node(get_nodes_block(node));
2687 ir_node *op = get_Conv_op(node);
2688 ir_node *new_op = be_transform_node(op);
2689 ia32_code_gen_t *cg = env_cg;
2690 ir_graph *irg = current_ir_graph;
2691 dbg_info *dbgi = get_irn_dbg_info(node);
2692 ir_node *noreg = ia32_new_NoReg_gp(cg);
2693 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2694 ir_mode *mode = get_irn_mode(node);
2695 ir_node *fist, *load;
2698 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2699 new_NoMem(), new_op, trunc_mode);
2701 set_irn_pinned(fist, op_pin_state_floats);
2702 set_ia32_use_frame(fist);
2703 set_ia32_op_type(fist, ia32_AddrModeD);
2705 assert(get_mode_size_bits(mode) <= 32);
2706 /* exception we can only store signed 32 bit integers, so for unsigned
2707 we store a 64bit (signed) integer and load the lower bits */
2708 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2709 set_ia32_ls_mode(fist, mode_Ls);
2711 set_ia32_ls_mode(fist, mode_Is);
2713 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2716 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2718 set_irn_pinned(load, op_pin_state_floats);
2719 set_ia32_use_frame(load);
2720 set_ia32_op_type(load, ia32_AddrModeS);
2721 set_ia32_ls_mode(load, mode_Is);
2722 if(get_ia32_ls_mode(fist) == mode_Ls) {
2723 ia32_attr_t *attr = get_ia32_attr(load);
2724 attr->data.need_64bit_stackent = 1;
2726 ia32_attr_t *attr = get_ia32_attr(load);
2727 attr->data.need_32bit_stackent = 1;
2729 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2731 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2735 * Creates a x87 strict Conv by placing a Sore and a Load
2737 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2739 ir_node *block = get_nodes_block(node);
2740 ir_graph *irg = current_ir_graph;
2741 dbg_info *dbgi = get_irn_dbg_info(node);
2742 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2743 ir_node *nomem = new_NoMem();
2744 ir_node *frame = get_irg_frame(irg);
2745 ir_node *store, *load;
2748 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2750 set_ia32_use_frame(store);
2751 set_ia32_op_type(store, ia32_AddrModeD);
2752 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2754 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2756 set_ia32_use_frame(load);
2757 set_ia32_op_type(load, ia32_AddrModeS);
2758 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2760 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2764 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2766 ir_graph *irg = current_ir_graph;
2767 ir_node *start_block = get_irg_start_block(irg);
2768 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2769 symconst, symconst_sign, val);
2770 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2776 * Create a conversion from general purpose to x87 register
2778 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2779 ir_node *src_block = get_nodes_block(node);
2780 ir_node *block = be_transform_node(src_block);
2781 ir_graph *irg = current_ir_graph;
2782 dbg_info *dbgi = get_irn_dbg_info(node);
2783 ir_node *op = get_Conv_op(node);
2784 ir_node *new_op = NULL;
2788 ir_mode *store_mode;
2794 /* fild can use source AM if the operand is a signed 32bit integer */
2795 if (src_mode == mode_Is) {
2796 ia32_address_mode_t am;
2798 match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
2799 if (am.op_type == ia32_AddrModeS) {
2800 ia32_address_t *addr = &am.addr;
2802 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2803 addr->index, addr->mem);
2804 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2807 set_am_attributes(fild, &am);
2808 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2810 fix_mem_proj(fild, &am);
2815 if(new_op == NULL) {
2816 new_op = be_transform_node(op);
2819 noreg = ia32_new_NoReg_gp(env_cg);
2820 nomem = new_NoMem();
2821 mode = get_irn_mode(op);
2823 /* first convert to 32 bit signed if necessary */
2824 src_bits = get_mode_size_bits(src_mode);
2825 if (src_bits == 8) {
2826 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2828 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2830 } else if (src_bits < 32) {
2831 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2833 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2837 assert(get_mode_size_bits(mode) == 32);
2840 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2843 set_ia32_use_frame(store);
2844 set_ia32_op_type(store, ia32_AddrModeD);
2845 set_ia32_ls_mode(store, mode_Iu);
2847 /* exception for 32bit unsigned, do a 64bit spill+load */
2848 if(!mode_is_signed(mode)) {
2851 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2853 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2854 get_irg_frame(irg), noreg, nomem,
2857 set_ia32_use_frame(zero_store);
2858 set_ia32_op_type(zero_store, ia32_AddrModeD);
2859 add_ia32_am_offs_int(zero_store, 4);
2860 set_ia32_ls_mode(zero_store, mode_Iu);
2865 store = new_rd_Sync(dbgi, irg, block, 2, in);
2866 store_mode = mode_Ls;
2868 store_mode = mode_Is;
2872 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2874 set_ia32_use_frame(fild);
2875 set_ia32_op_type(fild, ia32_AddrModeS);
2876 set_ia32_ls_mode(fild, store_mode);
2878 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2884 * Create a conversion from one integer mode into another one
2886 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2887 dbg_info *dbgi, ir_node *block, ir_node *op,
2890 ir_graph *irg = current_ir_graph;
2891 int src_bits = get_mode_size_bits(src_mode);
2892 int tgt_bits = get_mode_size_bits(tgt_mode);
2893 ir_node *new_block = be_transform_node(block);
2895 ir_mode *smaller_mode;
2897 ia32_address_mode_t am;
2898 ia32_address_t *addr = &am.addr;
2900 if (src_bits < tgt_bits) {
2901 smaller_mode = src_mode;
2902 smaller_bits = src_bits;
2904 smaller_mode = tgt_mode;
2905 smaller_bits = tgt_bits;
2908 #ifdef DEBUG_libfirm
2910 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2915 match_arguments(&am, block, NULL, op,
2916 match_8bit | match_16bit | match_8bit_am | match_16bit_am);
2917 if (smaller_bits == 8) {
2918 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2919 addr->index, addr->mem, am.new_op2,
2922 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2923 addr->index, addr->mem, am.new_op2,
2926 set_am_attributes(new_node, &am);
2927 /* match_arguments assume that out-mode = in-mode, this isn't true here
2929 set_ia32_ls_mode(new_node, smaller_mode);
2930 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2931 new_node = fix_mem_proj(new_node, &am);
2936 * Transforms a Conv node.
2938 * @return The created ia32 Conv node
2940 static ir_node *gen_Conv(ir_node *node) {
2941 ir_node *block = get_nodes_block(node);
2942 ir_node *new_block = be_transform_node(block);
2943 ir_node *op = get_Conv_op(node);
2944 ir_node *new_op = NULL;
2945 ir_graph *irg = current_ir_graph;
2946 dbg_info *dbgi = get_irn_dbg_info(node);
2947 ir_mode *src_mode = get_irn_mode(op);
2948 ir_mode *tgt_mode = get_irn_mode(node);
2949 int src_bits = get_mode_size_bits(src_mode);
2950 int tgt_bits = get_mode_size_bits(tgt_mode);
2951 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2952 ir_node *nomem = new_rd_NoMem(irg);
2953 ir_node *res = NULL;
2955 if (src_mode == mode_b) {
2956 assert(mode_is_int(tgt_mode));
2957 /* nothing to do, we already model bools as 0/1 ints */
2958 return be_transform_node(op);
2961 if (src_mode == tgt_mode) {
2962 if (get_Conv_strict(node)) {
2963 if (USE_SSE2(env_cg)) {
2964 /* when we are in SSE mode, we can kill all strict no-op conversion */
2965 return be_transform_node(op);
2968 /* this should be optimized already, but who knows... */
2969 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2970 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2971 return be_transform_node(op);
2975 if (mode_is_float(src_mode)) {
2976 new_op = be_transform_node(op);
2977 /* we convert from float ... */
2978 if (mode_is_float(tgt_mode)) {
2979 if(src_mode == mode_E && tgt_mode == mode_D
2980 && !get_Conv_strict(node)) {
2981 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2986 if (USE_SSE2(env_cg)) {
2987 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2988 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2990 set_ia32_ls_mode(res, tgt_mode);
2992 if(get_Conv_strict(node)) {
2993 res = gen_x87_strict_conv(tgt_mode, new_op);
2994 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2997 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3002 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3003 if (USE_SSE2(env_cg)) {
3004 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3006 set_ia32_ls_mode(res, src_mode);
3008 return gen_x87_fp_to_gp(node);
3012 /* we convert from int ... */
3013 if (mode_is_float(tgt_mode)) {
3015 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3016 if (USE_SSE2(env_cg)) {
3017 new_op = be_transform_node(op);
3018 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3020 set_ia32_ls_mode(res, tgt_mode);
3022 res = gen_x87_gp_to_fp(node, src_mode);
3023 if(get_Conv_strict(node)) {
3024 res = gen_x87_strict_conv(tgt_mode, res);
3025 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3026 ia32_get_old_node_name(env_cg, node));
3030 } else if(tgt_mode == mode_b) {
3031 /* mode_b lowering already took care that we only have 0/1 values */
3032 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3033 src_mode, tgt_mode));
3034 return be_transform_node(op);
3037 if (src_bits == tgt_bits) {
3038 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3039 src_mode, tgt_mode));
3040 return be_transform_node(op);
3043 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3051 static int check_immediate_constraint(long val, char immediate_constraint_type)
3053 switch (immediate_constraint_type) {
3057 return val >= 0 && val <= 32;
3059 return val >= 0 && val <= 63;
3061 return val >= -128 && val <= 127;
3063 return val == 0xff || val == 0xffff;
3065 return val >= 0 && val <= 3;
3067 return val >= 0 && val <= 255;
3069 return val >= 0 && val <= 127;
3073 panic("Invalid immediate constraint found");
3077 static ir_node *try_create_Immediate(ir_node *node,
3078 char immediate_constraint_type)
3081 tarval *offset = NULL;
3082 int offset_sign = 0;
3084 ir_entity *symconst_ent = NULL;
3085 int symconst_sign = 0;
3087 ir_node *cnst = NULL;
3088 ir_node *symconst = NULL;
3091 mode = get_irn_mode(node);
3092 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3096 if(is_Minus(node)) {
3098 node = get_Minus_op(node);
3101 if(is_Const(node)) {
3104 offset_sign = minus;
3105 } else if(is_SymConst(node)) {
3108 symconst_sign = minus;
3109 } else if(is_Add(node)) {
3110 ir_node *left = get_Add_left(node);
3111 ir_node *right = get_Add_right(node);
3112 if(is_Const(left) && is_SymConst(right)) {
3115 symconst_sign = minus;
3116 offset_sign = minus;
3117 } else if(is_SymConst(left) && is_Const(right)) {
3120 symconst_sign = minus;
3121 offset_sign = minus;
3123 } else if(is_Sub(node)) {
3124 ir_node *left = get_Sub_left(node);
3125 ir_node *right = get_Sub_right(node);
3126 if(is_Const(left) && is_SymConst(right)) {
3129 symconst_sign = !minus;
3130 offset_sign = minus;
3131 } else if(is_SymConst(left) && is_Const(right)) {
3134 symconst_sign = minus;
3135 offset_sign = !minus;
3142 offset = get_Const_tarval(cnst);
3143 if(tarval_is_long(offset)) {
3144 val = get_tarval_long(offset);
3146 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3151 if(!check_immediate_constraint(val, immediate_constraint_type))
3154 if(symconst != NULL) {
3155 if(immediate_constraint_type != 0) {
3156 /* we need full 32bits for symconsts */
3160 /* unfortunately the assembler/linker doesn't support -symconst */
3164 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3166 symconst_ent = get_SymConst_entity(symconst);
3168 if(cnst == NULL && symconst == NULL)
3171 if(offset_sign && offset != NULL) {
3172 offset = tarval_neg(offset);
3175 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3180 static ir_node *create_immediate_or_transform(ir_node *node,
3181 char immediate_constraint_type)
3183 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3184 if (new_node == NULL) {
3185 new_node = be_transform_node(node);
3190 static const arch_register_req_t no_register_req = {
3191 arch_register_req_type_none,
3192 NULL, /* regclass */
3193 NULL, /* limit bitset */
3195 0 /* different pos */
3199 * An assembler constraint.
3201 typedef struct constraint_t constraint_t;
3202 struct constraint_t {
3205 const arch_register_req_t **out_reqs;
3207 const arch_register_req_t *req;
3208 unsigned immediate_possible;
3209 char immediate_type;
3212 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3214 int immediate_possible = 0;
3215 char immediate_type = 0;
3216 unsigned limited = 0;
3217 const arch_register_class_t *cls = NULL;
3218 ir_graph *irg = current_ir_graph;
3219 struct obstack *obst = get_irg_obstack(irg);
3220 arch_register_req_t *req;
3221 unsigned *limited_ptr = NULL;
3225 /* TODO: replace all the asserts with nice error messages */
3228 /* a memory constraint: no need to do anything in backend about it
3229 * (the dependencies are already respected by the memory edge of
3231 constraint->req = &no_register_req;
3243 assert(cls == NULL ||
3244 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3245 cls = &ia32_reg_classes[CLASS_ia32_gp];
3246 limited |= 1 << REG_EAX;
3249 assert(cls == NULL ||
3250 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3251 cls = &ia32_reg_classes[CLASS_ia32_gp];
3252 limited |= 1 << REG_EBX;
3255 assert(cls == NULL ||
3256 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3257 cls = &ia32_reg_classes[CLASS_ia32_gp];
3258 limited |= 1 << REG_ECX;
3261 assert(cls == NULL ||
3262 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3263 cls = &ia32_reg_classes[CLASS_ia32_gp];
3264 limited |= 1 << REG_EDX;
3267 assert(cls == NULL ||
3268 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3269 cls = &ia32_reg_classes[CLASS_ia32_gp];
3270 limited |= 1 << REG_EDI;
3273 assert(cls == NULL ||
3274 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3275 cls = &ia32_reg_classes[CLASS_ia32_gp];
3276 limited |= 1 << REG_ESI;
3279 case 'q': /* q means lower part of the regs only, this makes no
3280 * difference to Q for us (we only assigne whole registers) */
3281 assert(cls == NULL ||
3282 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3283 cls = &ia32_reg_classes[CLASS_ia32_gp];
3284 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3288 assert(cls == NULL ||
3289 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3290 cls = &ia32_reg_classes[CLASS_ia32_gp];
3291 limited |= 1 << REG_EAX | 1 << REG_EDX;
3294 assert(cls == NULL ||
3295 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3296 cls = &ia32_reg_classes[CLASS_ia32_gp];
3297 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3298 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3305 assert(cls == NULL);
3306 cls = &ia32_reg_classes[CLASS_ia32_gp];
3312 /* TODO: mark values so the x87 simulator knows about t and u */
3313 assert(cls == NULL);
3314 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3319 assert(cls == NULL);
3320 /* TODO: check that sse2 is supported */
3321 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3331 assert(!immediate_possible);
3332 immediate_possible = 1;
3333 immediate_type = *c;
3337 assert(!immediate_possible);
3338 immediate_possible = 1;
3342 assert(!immediate_possible && cls == NULL);
3343 immediate_possible = 1;
3344 cls = &ia32_reg_classes[CLASS_ia32_gp];
3357 assert(constraint->is_in && "can only specify same constraint "
3360 sscanf(c, "%d%n", &same_as, &p);
3368 /* memory constraint no need to do anything in backend about it
3369 * (the dependencies are already respected by the memory edge of
3371 constraint->req = &no_register_req;
3374 case 'E': /* no float consts yet */
3375 case 'F': /* no float consts yet */
3376 case 's': /* makes no sense on x86 */
3377 case 'X': /* we can't support that in firm */
3380 case '<': /* no autodecrement on x86 */
3381 case '>': /* no autoincrement on x86 */
3382 case 'C': /* sse constant not supported yet */
3383 case 'G': /* 80387 constant not supported yet */
3384 case 'y': /* we don't support mmx registers yet */
3385 case 'Z': /* not available in 32 bit mode */
3386 case 'e': /* not available in 32 bit mode */
3387 panic("unsupported asm constraint '%c' found in (%+F)",
3388 *c, current_ir_graph);
3391 panic("unknown asm constraint '%c' found in (%+F)", *c,
3399 const arch_register_req_t *other_constr;
3401 assert(cls == NULL && "same as and register constraint not supported");
3402 assert(!immediate_possible && "same as and immediate constraint not "
3404 assert(same_as < constraint->n_outs && "wrong constraint number in "
3405 "same_as constraint");
3407 other_constr = constraint->out_reqs[same_as];
3409 req = obstack_alloc(obst, sizeof(req[0]));
3410 req->cls = other_constr->cls;
3411 req->type = arch_register_req_type_should_be_same;
3412 req->limited = NULL;
3413 req->other_same = 1U << pos;
3414 req->other_different = 0;
3416 /* switch constraints. This is because in firm we have same_as
3417 * constraints on the output constraints while in the gcc asm syntax
3418 * they are specified on the input constraints */
3419 constraint->req = other_constr;
3420 constraint->out_reqs[same_as] = req;
3421 constraint->immediate_possible = 0;
3425 if(immediate_possible && cls == NULL) {
3426 cls = &ia32_reg_classes[CLASS_ia32_gp];
3428 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3429 assert(cls != NULL);
3431 if(immediate_possible) {
3432 assert(constraint->is_in
3433 && "immediate make no sense for output constraints");
3435 /* todo: check types (no float input on 'r' constrained in and such... */
3438 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3439 limited_ptr = (unsigned*) (req+1);
3441 req = obstack_alloc(obst, sizeof(req[0]));
3443 memset(req, 0, sizeof(req[0]));
3446 req->type = arch_register_req_type_limited;
3447 *limited_ptr = limited;
3448 req->limited = limited_ptr;
3450 req->type = arch_register_req_type_normal;
3454 constraint->req = req;
3455 constraint->immediate_possible = immediate_possible;
3456 constraint->immediate_type = immediate_type;
3459 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3466 panic("Clobbers not supported yet");
3469 static int is_memory_op(const ir_asm_constraint *constraint)
3471 ident *id = constraint->constraint;
3472 const char *str = get_id_str(id);
3475 for(c = str; *c != '\0'; ++c) {
3484 * generates code for a ASM node
3486 static ir_node *gen_ASM(ir_node *node)
3489 ir_graph *irg = current_ir_graph;
3490 ir_node *block = get_nodes_block(node);
3491 ir_node *new_block = be_transform_node(block);
3492 dbg_info *dbgi = get_irn_dbg_info(node);
3496 int n_out_constraints;
3498 const arch_register_req_t **out_reg_reqs;
3499 const arch_register_req_t **in_reg_reqs;
3500 ia32_asm_reg_t *register_map;
3501 unsigned reg_map_size = 0;
3502 struct obstack *obst;
3503 const ir_asm_constraint *in_constraints;
3504 const ir_asm_constraint *out_constraints;
3506 constraint_t parsed_constraint;
3508 arity = get_irn_arity(node);
3509 in = alloca(arity * sizeof(in[0]));
3510 memset(in, 0, arity * sizeof(in[0]));
3512 n_out_constraints = get_ASM_n_output_constraints(node);
3513 n_clobbers = get_ASM_n_clobbers(node);
3514 out_arity = n_out_constraints + n_clobbers;
3516 in_constraints = get_ASM_input_constraints(node);
3517 out_constraints = get_ASM_output_constraints(node);
3518 clobbers = get_ASM_clobbers(node);
3520 /* construct output constraints */
3521 obst = get_irg_obstack(irg);
3522 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3523 parsed_constraint.out_reqs = out_reg_reqs;
3524 parsed_constraint.n_outs = n_out_constraints;
3525 parsed_constraint.is_in = 0;
3527 for(i = 0; i < out_arity; ++i) {
3530 if(i < n_out_constraints) {
3531 const ir_asm_constraint *constraint = &out_constraints[i];
3532 c = get_id_str(constraint->constraint);
3533 parse_asm_constraint(i, &parsed_constraint, c);
3535 if(constraint->pos > reg_map_size)
3536 reg_map_size = constraint->pos;
3538 ident *glob_id = clobbers [i - n_out_constraints];
3539 c = get_id_str(glob_id);
3540 parse_clobber(node, i, &parsed_constraint, c);
3543 out_reg_reqs[i] = parsed_constraint.req;
3546 /* construct input constraints */
3547 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3548 parsed_constraint.is_in = 1;
3549 for(i = 0; i < arity; ++i) {
3550 const ir_asm_constraint *constraint = &in_constraints[i];
3551 ident *constr_id = constraint->constraint;
3552 const char *c = get_id_str(constr_id);
3554 parse_asm_constraint(i, &parsed_constraint, c);
3555 in_reg_reqs[i] = parsed_constraint.req;
3557 if(constraint->pos > reg_map_size)
3558 reg_map_size = constraint->pos;
3560 if(parsed_constraint.immediate_possible) {
3561 ir_node *pred = get_irn_n(node, i);
3562 char imm_type = parsed_constraint.immediate_type;
3563 ir_node *immediate = try_create_Immediate(pred, imm_type);
3565 if(immediate != NULL) {
3572 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3573 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3575 for(i = 0; i < n_out_constraints; ++i) {
3576 const ir_asm_constraint *constraint = &out_constraints[i];
3577 unsigned pos = constraint->pos;
3579 assert(pos < reg_map_size);
3580 register_map[pos].use_input = 0;
3581 register_map[pos].valid = 1;
3582 register_map[pos].memory = is_memory_op(constraint);
3583 register_map[pos].inout_pos = i;
3584 register_map[pos].mode = constraint->mode;
3587 /* transform inputs */
3588 for(i = 0; i < arity; ++i) {
3589 const ir_asm_constraint *constraint = &in_constraints[i];
3590 unsigned pos = constraint->pos;
3591 ir_node *pred = get_irn_n(node, i);
3592 ir_node *transformed;
3594 assert(pos < reg_map_size);
3595 register_map[pos].use_input = 1;
3596 register_map[pos].valid = 1;
3597 register_map[pos].memory = is_memory_op(constraint);
3598 register_map[pos].inout_pos = i;
3599 register_map[pos].mode = constraint->mode;
3604 transformed = be_transform_node(pred);
3605 in[i] = transformed;
3608 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3609 get_ASM_text(node), register_map);
3611 set_ia32_out_req_all(new_node, out_reg_reqs);
3612 set_ia32_in_req_all(new_node, in_reg_reqs);
3614 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3619 /********************************************
3622 * | |__ ___ _ __ ___ __| | ___ ___
3623 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3624 * | |_) | __/ | | | (_) | (_| | __/\__ \
3625 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3627 ********************************************/
3630 * Transforms a FrameAddr into an ia32 Add.
3632 static ir_node *gen_be_FrameAddr(ir_node *node) {
3633 ir_node *block = be_transform_node(get_nodes_block(node));
3634 ir_node *op = be_get_FrameAddr_frame(node);
3635 ir_node *new_op = be_transform_node(op);
3636 ir_graph *irg = current_ir_graph;
3637 dbg_info *dbgi = get_irn_dbg_info(node);
3638 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3641 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3642 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3643 set_ia32_use_frame(new_node);
3645 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3651 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3653 static ir_node *gen_be_Return(ir_node *node) {
3654 ir_graph *irg = current_ir_graph;
3655 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3656 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3657 ir_entity *ent = get_irg_entity(irg);
3658 ir_type *tp = get_entity_type(ent);
3663 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3664 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3667 int pn_ret_val, pn_ret_mem, arity, i;
3669 assert(ret_val != NULL);
3670 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3671 return be_duplicate_node(node);
3674 res_type = get_method_res_type(tp, 0);
3676 if (! is_Primitive_type(res_type)) {
3677 return be_duplicate_node(node);
3680 mode = get_type_mode(res_type);
3681 if (! mode_is_float(mode)) {
3682 return be_duplicate_node(node);
3685 assert(get_method_n_ress(tp) == 1);
3687 pn_ret_val = get_Proj_proj(ret_val);
3688 pn_ret_mem = get_Proj_proj(ret_mem);
3690 /* get the Barrier */
3691 barrier = get_Proj_pred(ret_val);
3693 /* get result input of the Barrier */
3694 ret_val = get_irn_n(barrier, pn_ret_val);
3695 new_ret_val = be_transform_node(ret_val);
3697 /* get memory input of the Barrier */
3698 ret_mem = get_irn_n(barrier, pn_ret_mem);
3699 new_ret_mem = be_transform_node(ret_mem);
3701 frame = get_irg_frame(irg);
3703 dbgi = get_irn_dbg_info(barrier);
3704 block = be_transform_node(get_nodes_block(barrier));
3706 noreg = ia32_new_NoReg_gp(env_cg);
3708 /* store xmm0 onto stack */
3709 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3710 new_ret_mem, new_ret_val);
3711 set_ia32_ls_mode(sse_store, mode);
3712 set_ia32_op_type(sse_store, ia32_AddrModeD);
3713 set_ia32_use_frame(sse_store);
3715 /* load into x87 register */
3716 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3717 set_ia32_op_type(fld, ia32_AddrModeS);
3718 set_ia32_use_frame(fld);
3720 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3721 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3723 /* create a new barrier */
3724 arity = get_irn_arity(barrier);
3725 in = alloca(arity * sizeof(in[0]));
3726 for (i = 0; i < arity; ++i) {
3729 if (i == pn_ret_val) {
3731 } else if (i == pn_ret_mem) {
3734 ir_node *in = get_irn_n(barrier, i);
3735 new_in = be_transform_node(in);
3740 new_barrier = new_ir_node(dbgi, irg, block,
3741 get_irn_op(barrier), get_irn_mode(barrier),
3743 copy_node_attr(barrier, new_barrier);
3744 be_duplicate_deps(barrier, new_barrier);
3745 be_set_transformed_node(barrier, new_barrier);
3746 mark_irn_visited(barrier);
3748 /* transform normally */
3749 return be_duplicate_node(node);
3753 * Transform a be_AddSP into an ia32_SubSP.
3755 static ir_node *gen_be_AddSP(ir_node *node)
3757 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3758 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3760 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3764 * Transform a be_SubSP into an ia32_AddSP
3766 static ir_node *gen_be_SubSP(ir_node *node)
3768 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3769 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3771 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3775 * This function just sets the register for the Unknown node
3776 * as this is not done during register allocation because Unknown
3777 * is an "ignore" node.
3779 static ir_node *gen_Unknown(ir_node *node) {
3780 ir_mode *mode = get_irn_mode(node);
3782 if (mode_is_float(mode)) {
3783 if (USE_SSE2(env_cg)) {
3784 return ia32_new_Unknown_xmm(env_cg);
3786 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3787 ir_graph *irg = current_ir_graph;
3788 dbg_info *dbgi = get_irn_dbg_info(node);
3789 ir_node *block = get_irg_start_block(irg);
3790 return new_rd_ia32_vfldz(dbgi, irg, block);
3792 } else if (mode_needs_gp_reg(mode)) {
3793 return ia32_new_Unknown_gp(env_cg);
3795 panic("unsupported Unknown-Mode");
3801 * Change some phi modes
3803 static ir_node *gen_Phi(ir_node *node) {
3804 ir_node *block = be_transform_node(get_nodes_block(node));
3805 ir_graph *irg = current_ir_graph;
3806 dbg_info *dbgi = get_irn_dbg_info(node);
3807 ir_mode *mode = get_irn_mode(node);
3810 if(mode_needs_gp_reg(mode)) {
3811 /* we shouldn't have any 64bit stuff around anymore */
3812 assert(get_mode_size_bits(mode) <= 32);
3813 /* all integer operations are on 32bit registers now */
3815 } else if(mode_is_float(mode)) {
3816 if (USE_SSE2(env_cg)) {
3823 /* phi nodes allow loops, so we use the old arguments for now
3824 * and fix this later */
3825 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3826 get_irn_in(node) + 1);
3827 copy_node_attr(node, phi);
3828 be_duplicate_deps(node, phi);
3830 be_set_transformed_node(node, phi);
3831 be_enqueue_preds(node);
3839 static ir_node *gen_IJmp(ir_node *node)
3841 ir_node *block = get_nodes_block(node);
3842 ir_node *new_block = be_transform_node(block);
3843 ir_graph *irg = current_ir_graph;
3844 dbg_info *dbgi = get_irn_dbg_info(node);
3845 ir_node *op = get_IJmp_target(node);
3847 ia32_address_mode_t am;
3848 ia32_address_t *addr = &am.addr;
3850 assert(get_irn_mode(op) == mode_P);
3852 match_arguments(&am, block, NULL, op,
3853 match_am | match_8bit_am | match_16bit_am |
3854 match_immediate | match_8bit | match_16bit);
3856 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3857 addr->mem, am.new_op2);
3858 set_am_attributes(new_node, &am);
3859 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3861 new_node = fix_mem_proj(new_node, &am);
3867 /**********************************************************************
3870 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3871 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3872 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3873 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3875 **********************************************************************/
3877 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3879 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3882 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3883 ir_node *val, ir_node *mem);
3886 * Transforms a lowered Load into a "real" one.
3888 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3890 ir_node *block = be_transform_node(get_nodes_block(node));
3891 ir_node *ptr = get_irn_n(node, 0);
3892 ir_node *new_ptr = be_transform_node(ptr);
3893 ir_node *mem = get_irn_n(node, 1);
3894 ir_node *new_mem = be_transform_node(mem);
3895 ir_graph *irg = current_ir_graph;
3896 dbg_info *dbgi = get_irn_dbg_info(node);
3897 ir_mode *mode = get_ia32_ls_mode(node);
3898 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3901 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3903 set_ia32_op_type(new_op, ia32_AddrModeS);
3904 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3905 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3906 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3907 if (is_ia32_am_sc_sign(node))
3908 set_ia32_am_sc_sign(new_op);
3909 set_ia32_ls_mode(new_op, mode);
3910 if (is_ia32_use_frame(node)) {
3911 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3912 set_ia32_use_frame(new_op);
3915 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3921 * Transforms a lowered Store into a "real" one.
3923 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3925 ir_node *block = be_transform_node(get_nodes_block(node));
3926 ir_node *ptr = get_irn_n(node, 0);
3927 ir_node *new_ptr = be_transform_node(ptr);
3928 ir_node *val = get_irn_n(node, 1);
3929 ir_node *new_val = be_transform_node(val);
3930 ir_node *mem = get_irn_n(node, 2);
3931 ir_node *new_mem = be_transform_node(mem);
3932 ir_graph *irg = current_ir_graph;
3933 dbg_info *dbgi = get_irn_dbg_info(node);
3934 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3935 ir_mode *mode = get_ia32_ls_mode(node);
3939 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3941 am_offs = get_ia32_am_offs_int(node);
3942 add_ia32_am_offs_int(new_op, am_offs);
3944 set_ia32_op_type(new_op, ia32_AddrModeD);
3945 set_ia32_ls_mode(new_op, mode);
3946 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3947 set_ia32_use_frame(new_op);
3949 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3954 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3956 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
3957 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
3959 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3960 match_immediate | match_mode_neutral);
3963 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3965 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
3966 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
3967 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3971 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3973 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
3974 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
3975 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3979 static ir_node *gen_ia32_l_Add(ir_node *node) {
3980 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3981 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3982 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3983 match_commutative | match_am | match_immediate |
3984 match_mode_neutral);
3986 if(is_Proj(lowered)) {
3987 lowered = get_Proj_pred(lowered);
3989 assert(is_ia32_Add(lowered));
3990 set_irn_mode(lowered, mode_T);
3996 static ir_node *gen_ia32_l_Adc(ir_node *node)
3998 return gen_binop_flags(node, new_rd_ia32_Adc,
3999 match_commutative | match_am | match_immediate |
4000 match_mode_neutral);
4004 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4006 * @param node The node to transform
4007 * @return the created ia32 vfild node
4009 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4010 return gen_lowered_Load(node, new_rd_ia32_vfild);
4014 * Transforms an ia32_l_Load into a "real" ia32_Load node
4016 * @param node The node to transform
4017 * @return the created ia32 Load node
4019 static ir_node *gen_ia32_l_Load(ir_node *node) {
4020 return gen_lowered_Load(node, new_rd_ia32_Load);
4024 * Transforms an ia32_l_Store into a "real" ia32_Store node
4026 * @param node The node to transform
4027 * @return the created ia32 Store node
4029 static ir_node *gen_ia32_l_Store(ir_node *node) {
4030 return gen_lowered_Store(node, new_rd_ia32_Store);
4034 * Transforms a l_vfist into a "real" vfist node.
4036 * @param node The node to transform
4037 * @return the created ia32 vfist node
4039 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4040 ir_node *block = be_transform_node(get_nodes_block(node));
4041 ir_node *ptr = get_irn_n(node, 0);
4042 ir_node *new_ptr = be_transform_node(ptr);
4043 ir_node *val = get_irn_n(node, 1);
4044 ir_node *new_val = be_transform_node(val);
4045 ir_node *mem = get_irn_n(node, 2);
4046 ir_node *new_mem = be_transform_node(mem);
4047 ir_graph *irg = current_ir_graph;
4048 dbg_info *dbgi = get_irn_dbg_info(node);
4049 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4050 ir_mode *mode = get_ia32_ls_mode(node);
4051 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4055 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4056 new_val, trunc_mode);
4058 am_offs = get_ia32_am_offs_int(node);
4059 add_ia32_am_offs_int(new_op, am_offs);
4061 set_ia32_op_type(new_op, ia32_AddrModeD);
4062 set_ia32_ls_mode(new_op, mode);
4063 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4064 set_ia32_use_frame(new_op);
4066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4072 * Transforms a l_MulS into a "real" MulS node.
4074 * @return the created ia32 Mul node
4076 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4077 ir_node *left = get_binop_left(node);
4078 ir_node *right = get_binop_right(node);
4080 return gen_binop(node, left, right, new_rd_ia32_Mul,
4081 match_commutative | match_am | match_mode_neutral);
4085 * Transforms a l_IMulS into a "real" IMul1OPS node.
4087 * @return the created ia32 IMul1OP node
4089 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4090 ir_node *left = get_binop_left(node);
4091 ir_node *right = get_binop_right(node);
4093 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4094 match_commutative | match_am | match_mode_neutral);
4097 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4098 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4099 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4100 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4101 match_am | match_immediate | match_mode_neutral);
4103 if(is_Proj(lowered)) {
4104 lowered = get_Proj_pred(lowered);
4106 assert(is_ia32_Sub(lowered));
4107 set_irn_mode(lowered, mode_T);
4113 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4114 return gen_binop_flags(node, new_rd_ia32_Sbb,
4115 match_am | match_immediate | match_mode_neutral);
4119 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4120 * op1 - target to be shifted
4121 * op2 - contains bits to be shifted into target
4123 * Only op3 can be an immediate.
4125 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4126 ir_node *low, ir_node *count)
4128 ir_node *block = get_nodes_block(node);
4129 ir_node *new_block = be_transform_node(block);
4130 ir_graph *irg = current_ir_graph;
4131 dbg_info *dbgi = get_irn_dbg_info(node);
4132 ir_node *new_high = be_transform_node(high);
4133 ir_node *new_low = be_transform_node(low);
4137 /* the shift amount can be any mode that is bigger than 5 bits, since all
4138 * other bits are ignored anyway */
4139 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4140 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4141 count = get_Conv_op(count);
4143 new_count = create_immediate_or_transform(count, 0);
4145 if (is_ia32_l_ShlD(node)) {
4146 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4149 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4152 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4157 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4159 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
4160 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
4161 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4162 return gen_lowered_64bit_shifts(node, high, low, count);
4165 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4167 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
4168 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
4169 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4170 return gen_lowered_64bit_shifts(node, high, low, count);
4174 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4176 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4177 ir_node *block = be_transform_node(get_nodes_block(node));
4178 ir_node *val = get_irn_n(node, 1);
4179 ir_node *new_val = be_transform_node(val);
4180 ia32_code_gen_t *cg = env_cg;
4181 ir_node *res = NULL;
4182 ir_graph *irg = current_ir_graph;
4184 ir_node *noreg, *new_ptr, *new_mem;
4191 mem = get_irn_n(node, 2);
4192 new_mem = be_transform_node(mem);
4193 ptr = get_irn_n(node, 0);
4194 new_ptr = be_transform_node(ptr);
4195 noreg = ia32_new_NoReg_gp(cg);
4196 dbgi = get_irn_dbg_info(node);
4198 /* Store x87 -> MEM */
4199 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4200 get_ia32_ls_mode(node));
4201 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4202 set_ia32_use_frame(res);
4203 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4204 set_ia32_op_type(res, ia32_AddrModeD);
4206 /* Load MEM -> SSE */
4207 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4208 get_ia32_ls_mode(node));
4209 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4210 set_ia32_use_frame(res);
4211 set_ia32_op_type(res, ia32_AddrModeS);
4212 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4218 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4220 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4221 ir_node *block = be_transform_node(get_nodes_block(node));
4222 ir_node *val = get_irn_n(node, 1);
4223 ir_node *new_val = be_transform_node(val);
4224 ia32_code_gen_t *cg = env_cg;
4225 ir_graph *irg = current_ir_graph;
4226 ir_node *res = NULL;
4227 ir_entity *fent = get_ia32_frame_ent(node);
4228 ir_mode *lsmode = get_ia32_ls_mode(node);
4230 ir_node *noreg, *new_ptr, *new_mem;
4234 if (! USE_SSE2(cg)) {
4235 /* SSE unit is not used -> skip this node. */
4239 ptr = get_irn_n(node, 0);
4240 new_ptr = be_transform_node(ptr);
4241 mem = get_irn_n(node, 2);
4242 new_mem = be_transform_node(mem);
4243 noreg = ia32_new_NoReg_gp(cg);
4244 dbgi = get_irn_dbg_info(node);
4246 /* Store SSE -> MEM */
4247 if (is_ia32_xLoad(skip_Proj(new_val))) {
4248 ir_node *ld = skip_Proj(new_val);
4250 /* we can vfld the value directly into the fpu */
4251 fent = get_ia32_frame_ent(ld);
4252 ptr = get_irn_n(ld, 0);
4253 offs = get_ia32_am_offs_int(ld);
4255 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4257 set_ia32_frame_ent(res, fent);
4258 set_ia32_use_frame(res);
4259 set_ia32_ls_mode(res, lsmode);
4260 set_ia32_op_type(res, ia32_AddrModeD);
4264 /* Load MEM -> x87 */
4265 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4266 set_ia32_frame_ent(res, fent);
4267 set_ia32_use_frame(res);
4268 add_ia32_am_offs_int(res, offs);
4269 set_ia32_op_type(res, ia32_AddrModeS);
4270 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4275 /*********************************************************
4278 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4279 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4280 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4281 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4283 *********************************************************/
4286 * the BAD transformer.
4288 static ir_node *bad_transform(ir_node *node) {
4289 panic("No transform function for %+F available.\n", node);
4294 * Transform the Projs of an AddSP.
4296 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4297 ir_node *block = be_transform_node(get_nodes_block(node));
4298 ir_node *pred = get_Proj_pred(node);
4299 ir_node *new_pred = be_transform_node(pred);
4300 ir_graph *irg = current_ir_graph;
4301 dbg_info *dbgi = get_irn_dbg_info(node);
4302 long proj = get_Proj_proj(node);
4304 if (proj == pn_be_AddSP_sp) {
4305 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4306 pn_ia32_SubSP_stack);
4307 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4309 } else if(proj == pn_be_AddSP_res) {
4310 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4311 pn_ia32_SubSP_addr);
4312 } else if (proj == pn_be_AddSP_M) {
4313 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4317 return new_rd_Unknown(irg, get_irn_mode(node));
4321 * Transform the Projs of a SubSP.
4323 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4324 ir_node *block = be_transform_node(get_nodes_block(node));
4325 ir_node *pred = get_Proj_pred(node);
4326 ir_node *new_pred = be_transform_node(pred);
4327 ir_graph *irg = current_ir_graph;
4328 dbg_info *dbgi = get_irn_dbg_info(node);
4329 long proj = get_Proj_proj(node);
4331 if (proj == pn_be_SubSP_sp) {
4332 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4333 pn_ia32_AddSP_stack);
4334 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4336 } else if (proj == pn_be_SubSP_M) {
4337 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4341 return new_rd_Unknown(irg, get_irn_mode(node));
4345 * Transform and renumber the Projs from a Load.
4347 static ir_node *gen_Proj_Load(ir_node *node) {
4349 ir_node *block = be_transform_node(get_nodes_block(node));
4350 ir_node *pred = get_Proj_pred(node);
4351 ir_graph *irg = current_ir_graph;
4352 dbg_info *dbgi = get_irn_dbg_info(node);
4353 long proj = get_Proj_proj(node);
4356 /* loads might be part of source address mode matches, so we don't
4357 transform the ProjMs yet (with the exception of loads whose result is
4360 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4363 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4365 /* this is needed, because sometimes we have loops that are only
4366 reachable through the ProjM */
4367 be_enqueue_preds(node);
4368 /* do it in 2 steps, to silence firm verifier */
4369 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4370 set_Proj_proj(res, pn_ia32_Load_M);
4374 /* renumber the proj */
4375 new_pred = be_transform_node(pred);
4376 if (is_ia32_Load(new_pred)) {
4377 if (proj == pn_Load_res) {
4378 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4380 } else if (proj == pn_Load_M) {
4381 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4384 } else if(is_ia32_Conv_I2I(new_pred)
4385 || is_ia32_Conv_I2I8Bit(new_pred)) {
4386 set_irn_mode(new_pred, mode_T);
4387 if (proj == pn_Load_res) {
4388 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4389 } else if (proj == pn_Load_M) {
4390 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4392 } else if (is_ia32_xLoad(new_pred)) {
4393 if (proj == pn_Load_res) {
4394 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4396 } else if (proj == pn_Load_M) {
4397 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4400 } else if (is_ia32_vfld(new_pred)) {
4401 if (proj == pn_Load_res) {
4402 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4404 } else if (proj == pn_Load_M) {
4405 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4409 /* can happen for ProJMs when source address mode happened for the
4412 /* however it should not be the result proj, as that would mean the
4413 load had multiple users and should not have been used for
4415 if(proj != pn_Load_M) {
4416 panic("internal error: transformed node not a Load");
4418 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4422 return new_rd_Unknown(irg, get_irn_mode(node));
4426 * Transform and renumber the Projs from a DivMod like instruction.
4428 static ir_node *gen_Proj_DivMod(ir_node *node) {
4429 ir_node *block = be_transform_node(get_nodes_block(node));
4430 ir_node *pred = get_Proj_pred(node);
4431 ir_node *new_pred = be_transform_node(pred);
4432 ir_graph *irg = current_ir_graph;
4433 dbg_info *dbgi = get_irn_dbg_info(node);
4434 ir_mode *mode = get_irn_mode(node);
4435 long proj = get_Proj_proj(node);
4437 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4439 switch (get_irn_opcode(pred)) {
4443 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4445 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4453 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4455 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4463 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4464 case pn_DivMod_res_div:
4465 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4466 case pn_DivMod_res_mod:
4467 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4477 return new_rd_Unknown(irg, mode);
4481 * Transform and renumber the Projs from a CopyB.
4483 static ir_node *gen_Proj_CopyB(ir_node *node) {
4484 ir_node *block = be_transform_node(get_nodes_block(node));
4485 ir_node *pred = get_Proj_pred(node);
4486 ir_node *new_pred = be_transform_node(pred);
4487 ir_graph *irg = current_ir_graph;
4488 dbg_info *dbgi = get_irn_dbg_info(node);
4489 ir_mode *mode = get_irn_mode(node);
4490 long proj = get_Proj_proj(node);
4493 case pn_CopyB_M_regular:
4494 if (is_ia32_CopyB_i(new_pred)) {
4495 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4496 } else if (is_ia32_CopyB(new_pred)) {
4497 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4505 return new_rd_Unknown(irg, mode);
4509 * Transform and renumber the Projs from a Quot.
4511 static ir_node *gen_Proj_Quot(ir_node *node) {
4512 ir_node *block = be_transform_node(get_nodes_block(node));
4513 ir_node *pred = get_Proj_pred(node);
4514 ir_node *new_pred = be_transform_node(pred);
4515 ir_graph *irg = current_ir_graph;
4516 dbg_info *dbgi = get_irn_dbg_info(node);
4517 ir_mode *mode = get_irn_mode(node);
4518 long proj = get_Proj_proj(node);
4522 if (is_ia32_xDiv(new_pred)) {
4523 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4524 } else if (is_ia32_vfdiv(new_pred)) {
4525 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4529 if (is_ia32_xDiv(new_pred)) {
4530 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4531 } else if (is_ia32_vfdiv(new_pred)) {
4532 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4540 return new_rd_Unknown(irg, mode);
4544 * Transform the Thread Local Storage Proj.
4546 static ir_node *gen_Proj_tls(ir_node *node) {
4547 ir_node *block = be_transform_node(get_nodes_block(node));
4548 ir_graph *irg = current_ir_graph;
4549 dbg_info *dbgi = NULL;
4550 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4555 static ir_node *gen_be_Call(ir_node *node) {
4556 ir_node *res = be_duplicate_node(node);
4557 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4562 static ir_node *gen_be_IncSP(ir_node *node) {
4563 ir_node *res = be_duplicate_node(node);
4564 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4570 * Transform the Projs from a be_Call.
4572 static ir_node *gen_Proj_be_Call(ir_node *node) {
4573 ir_node *block = be_transform_node(get_nodes_block(node));
4574 ir_node *call = get_Proj_pred(node);
4575 ir_node *new_call = be_transform_node(call);
4576 ir_graph *irg = current_ir_graph;
4577 dbg_info *dbgi = get_irn_dbg_info(node);
4578 ir_type *method_type = be_Call_get_type(call);
4579 int n_res = get_method_n_ress(method_type);
4580 long proj = get_Proj_proj(node);
4581 ir_mode *mode = get_irn_mode(node);
4583 const arch_register_class_t *cls;
4585 /* The following is kinda tricky: If we're using SSE, then we have to
4586 * move the result value of the call in floating point registers to an
4587 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4588 * after the call, we have to make sure to correctly make the
4589 * MemProj and the result Proj use these 2 nodes
4591 if (proj == pn_be_Call_M_regular) {
4592 // get new node for result, are we doing the sse load/store hack?
4593 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4594 ir_node *call_res_new;
4595 ir_node *call_res_pred = NULL;
4597 if (call_res != NULL) {
4598 call_res_new = be_transform_node(call_res);
4599 call_res_pred = get_Proj_pred(call_res_new);
4602 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4603 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4604 pn_be_Call_M_regular);
4606 assert(is_ia32_xLoad(call_res_pred));
4607 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4611 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4612 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4613 && USE_SSE2(env_cg)) {
4615 ir_node *frame = get_irg_frame(irg);
4616 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4618 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4621 /* in case there is no memory output: create one to serialize the copy
4623 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4624 pn_be_Call_M_regular);
4625 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4626 pn_be_Call_first_res);
4628 /* store st(0) onto stack */
4629 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4631 set_ia32_op_type(fstp, ia32_AddrModeD);
4632 set_ia32_use_frame(fstp);
4634 /* load into SSE register */
4635 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4637 set_ia32_op_type(sse_load, ia32_AddrModeS);
4638 set_ia32_use_frame(sse_load);
4640 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4646 /* transform call modes */
4647 if (mode_is_data(mode)) {
4648 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4652 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4656 * Transform the Projs from a Cmp.
4658 static ir_node *gen_Proj_Cmp(ir_node *node)
4661 panic("not all mode_b nodes are lowered");
4664 /* normally Cmps are processed when looking at Cond nodes, but this case
4665 * can happen in complicated Psi conditions */
4666 dbg_info *dbgi = get_irn_dbg_info(node);
4667 ir_node *block = get_nodes_block(node);
4668 ir_node *new_block = be_transform_node(block);
4669 ir_node *cmp = get_Proj_pred(node);
4670 ir_node *new_cmp = be_transform_node(cmp);
4671 long pnc = get_Proj_proj(node);
4674 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4681 * Transform and potentially renumber Proj nodes.
4683 static ir_node *gen_Proj(ir_node *node) {
4684 ir_graph *irg = current_ir_graph;
4685 dbg_info *dbgi = get_irn_dbg_info(node);
4686 ir_node *pred = get_Proj_pred(node);
4687 long proj = get_Proj_proj(node);
4689 if (is_Store(pred)) {
4690 if (proj == pn_Store_M) {
4691 return be_transform_node(pred);
4694 return new_r_Bad(irg);
4696 } else if (is_Load(pred)) {
4697 return gen_Proj_Load(node);
4698 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4699 return gen_Proj_DivMod(node);
4700 } else if (is_CopyB(pred)) {
4701 return gen_Proj_CopyB(node);
4702 } else if (is_Quot(pred)) {
4703 return gen_Proj_Quot(node);
4704 } else if (be_is_SubSP(pred)) {
4705 return gen_Proj_be_SubSP(node);
4706 } else if (be_is_AddSP(pred)) {
4707 return gen_Proj_be_AddSP(node);
4708 } else if (be_is_Call(pred)) {
4709 return gen_Proj_be_Call(node);
4710 } else if (is_Cmp(pred)) {
4711 return gen_Proj_Cmp(node);
4712 } else if (get_irn_op(pred) == op_Start) {
4713 if (proj == pn_Start_X_initial_exec) {
4714 ir_node *block = get_nodes_block(pred);
4717 /* we exchange the ProjX with a jump */
4718 block = be_transform_node(block);
4719 jump = new_rd_Jmp(dbgi, irg, block);
4722 if (node == be_get_old_anchor(anchor_tls)) {
4723 return gen_Proj_tls(node);
4726 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4730 ir_node *new_pred = be_transform_node(pred);
4731 ir_node *block = be_transform_node(get_nodes_block(node));
4732 ir_mode *mode = get_irn_mode(node);
4733 if (mode_needs_gp_reg(mode)) {
4734 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4735 get_Proj_proj(node));
4736 #ifdef DEBUG_libfirm
4737 new_proj->node_nr = node->node_nr;
4743 return be_duplicate_node(node);
4747 * Enters all transform functions into the generic pointer
4749 static void register_transformers(void)
4753 /* first clear the generic function pointer for all ops */
4754 clear_irp_opcodes_generic_func();
4756 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4757 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4795 /* transform ops from intrinsic lowering */
4811 GEN(ia32_l_X87toSSE);
4812 GEN(ia32_l_SSEtoX87);
4818 /* we should never see these nodes */
4833 /* handle generic backend nodes */
4842 op_Mulh = get_op_Mulh();
4851 * Pre-transform all unknown and noreg nodes.
4853 static void ia32_pretransform_node(void *arch_cg) {
4854 ia32_code_gen_t *cg = arch_cg;
4856 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4857 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4858 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4859 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4860 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4861 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4866 * Walker, checks if all ia32 nodes producing more than one result have
4867 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4869 static void add_missing_keep_walker(ir_node *node, void *data)
4872 unsigned found_projs = 0;
4873 const ir_edge_t *edge;
4874 ir_mode *mode = get_irn_mode(node);
4879 if(!is_ia32_irn(node))
4882 n_outs = get_ia32_n_res(node);
4885 if(is_ia32_SwitchJmp(node))
4888 assert(n_outs < (int) sizeof(unsigned) * 8);
4889 foreach_out_edge(node, edge) {
4890 ir_node *proj = get_edge_src_irn(edge);
4891 int pn = get_Proj_proj(proj);
4893 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4894 found_projs |= 1 << pn;
4898 /* are keeps missing? */
4900 for(i = 0; i < n_outs; ++i) {
4903 const arch_register_req_t *req;
4904 const arch_register_class_t *class;
4906 if(found_projs & (1 << i)) {
4910 req = get_ia32_out_req(node, i);
4915 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4919 block = get_nodes_block(node);
4920 in[0] = new_r_Proj(current_ir_graph, block, node,
4921 arch_register_class_mode(class), i);
4922 if(last_keep != NULL) {
4923 be_Keep_add_node(last_keep, class, in[0]);
4925 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4926 if(sched_is_scheduled(node)) {
4927 sched_add_after(node, last_keep);
4934 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4937 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4939 ir_graph *irg = be_get_birg_irg(cg->birg);
4940 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4943 /* do the transformation */
4944 void ia32_transform_graph(ia32_code_gen_t *cg) {
4946 ir_graph *irg = cg->irg;
4947 int opt_arch = cg->isa->opt_arch;
4948 int arch = cg->isa->arch;
4950 /* TODO: look at cpu and fill transform config in with that... */
4951 transform_config.use_incdec = 1;
4952 transform_config.use_sse2 = 0;
4953 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4954 transform_config.use_ftst = 0;
4955 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4956 transform_config.use_fucomi = 1;
4957 transform_config.use_cmov = IS_P6_ARCH(arch);
4959 register_transformers();
4961 initial_fpcw = NULL;
4963 heights = heights_new(irg);
4964 ia32_calculate_non_address_mode_nodes(cg->birg);
4966 /* the transform phase is not safe for CSE (yet) because several nodes get
4967 * attributes set after their creation */
4968 cse_last = get_opt_cse();
4971 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4973 set_opt_cse(cse_last);
4975 ia32_free_non_address_mode_nodes();
4976 heights_free(heights);
4980 void ia32_init_transform(void)
4982 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");