2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "bearch_ia32_t.h"
29 #include "ia32_nodes_attr.h"
30 #include "../arch/archop.h" /* we need this for Min and Max nodes */
31 #include "ia32_transform.h"
32 #include "ia32_new_nodes.h"
34 #include "gen_ia32_regalloc_if.h"
36 #define SFP_SIGN "0x80000000"
37 #define DFP_SIGN "0x8000000000000000"
38 #define SFP_ABS "0x7FFFFFFF"
39 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
41 #define TP_SFP_SIGN "ia32_sfp_sign"
42 #define TP_DFP_SIGN "ia32_dfp_sign"
43 #define TP_SFP_ABS "ia32_sfp_abs"
44 #define TP_DFP_ABS "ia32_dfp_abs"
46 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
47 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
48 #define ENT_SFP_ABS "IA32_SFP_ABS"
49 #define ENT_DFP_ABS "IA32_DFP_ABS"
51 extern ir_op *get_op_Mulh(void);
53 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
54 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
56 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
57 ir_node *op, ir_node *mem, ir_mode *mode);
60 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
63 /****************************************************************************************************
65 * | | | | / _| | | (_)
66 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
67 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
68 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
69 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
71 ****************************************************************************************************/
78 /* Compares two (entity, tarval) combinations */
79 static int cmp_tv_ent(const void *a, const void *b, size_t len) {
80 const struct tv_ent *e1 = a;
81 const struct tv_ent *e2 = b;
83 return !(e1->tv == e2->tv);
86 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
87 static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
88 static set *const_set = NULL;
100 const_set = new_set(cmp_tv_ent, 10);
105 tp_name = TP_SFP_SIGN;
106 ent_name = ENT_SFP_SIGN;
110 tp_name = TP_DFP_SIGN;
111 ent_name = ENT_DFP_SIGN;
115 tp_name = TP_SFP_ABS;
116 ent_name = ENT_SFP_ABS;
120 tp_name = TP_DFP_ABS;
121 ent_name = ENT_DFP_ABS;
127 key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
130 entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
133 tp = new_type_primitive(new_id_from_str(tp_name), mode);
134 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
136 set_entity_ld_ident(ent, get_entity_ident(ent));
137 set_entity_visibility(ent, visibility_local);
138 set_entity_variability(ent, variability_constant);
139 set_entity_allocation(ent, allocation_static);
141 /* we create a new entity here: It's initialization must resist on the
143 rem = current_ir_graph;
144 current_ir_graph = get_const_code_irg();
145 cnst = new_Const(mode, key.tv);
146 current_ir_graph = rem;
148 set_atomic_ent_value(ent, cnst);
150 /* set the entry for hashmap */
159 * Prints the old node name on cg obst and returns a pointer to it.
161 const char *get_old_node_name(ia32_transform_env_t *env) {
162 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
164 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
165 obstack_1grow(isa->name_obst, 0);
166 return obstack_finish(isa->name_obst);
170 /* determine if one operator is an Imm */
171 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
173 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
174 else return is_ia32_Cnst(op2) ? op2 : NULL;
177 /* determine if one operator is not an Imm */
178 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
179 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
184 * Construct a standard binary operation, set AM and immediate if required.
186 * @param env The transformation environment
187 * @param op1 The first operand
188 * @param op2 The second operand
189 * @param func The node constructor function
190 * @return The constructed ia32 node.
192 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
193 ir_node *new_op = NULL;
194 ir_mode *mode = env->mode;
195 dbg_info *dbg = env->dbg;
196 ir_graph *irg = env->irg;
197 ir_node *block = env->block;
198 firm_dbg_module_t *mod = env->mod;
199 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
200 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
201 ir_node *nomem = new_NoMem();
202 ir_node *expr_op, *imm_op;
204 /* Check if immediate optimization is on and */
205 /* if it's an operation with immediate. */
206 if (! env->cg->opt.immops) {
210 else if (is_op_commutative(get_irn_op(env->irn))) {
211 imm_op = get_immediate_op(op1, op2);
212 expr_op = get_expr_op(op1, op2);
215 imm_op = get_immediate_op(NULL, op2);
216 expr_op = get_expr_op(op1, op2);
219 assert((expr_op || imm_op) && "invalid operands");
222 /* We have two consts here: not yet supported */
226 if (mode_is_float(mode)) {
227 /* floating point operations */
229 DB((mod, LEVEL_1, "FP with immediate ..."));
230 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
231 set_ia32_Immop_attr(new_op, imm_op);
232 set_ia32_am_support(new_op, ia32_am_None);
235 DB((mod, LEVEL_1, "FP binop ..."));
236 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
237 set_ia32_am_support(new_op, ia32_am_Source);
241 /* integer operations */
243 /* This is expr + const */
244 DB((mod, LEVEL_1, "INT with immediate ..."));
245 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
246 set_ia32_Immop_attr(new_op, imm_op);
249 set_ia32_am_support(new_op, ia32_am_Dest);
252 DB((mod, LEVEL_1, "INT binop ..."));
253 /* This is a normal operation */
254 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
257 set_ia32_am_support(new_op, ia32_am_Full);
262 set_ia32_orig_node(new_op, get_old_node_name(env));
265 if (is_op_commutative(get_irn_op(env->irn))) {
266 set_ia32_commutative(new_op);
269 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
275 * Construct a shift/rotate binary operation, sets AM and immediate if required.
277 * @param env The transformation environment
278 * @param op1 The first operand
279 * @param op2 The second operand
280 * @param func The node constructor function
281 * @return The constructed ia32 node.
283 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
284 ir_node *new_op = NULL;
285 ir_mode *mode = env->mode;
286 dbg_info *dbg = env->dbg;
287 ir_graph *irg = env->irg;
288 ir_node *block = env->block;
289 firm_dbg_module_t *mod = env->mod;
290 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
291 ir_node *nomem = new_NoMem();
292 ir_node *expr_op, *imm_op;
295 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
297 /* Check if immediate optimization is on and */
298 /* if it's an operation with immediate. */
299 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
300 expr_op = get_expr_op(op1, op2);
302 assert((expr_op || imm_op) && "invalid operands");
305 /* We have two consts here: not yet supported */
309 /* Limit imm_op within range imm8 */
311 tv = get_ia32_Immop_tarval(imm_op);
314 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
321 /* integer operations */
323 /* This is shift/rot with const */
324 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
326 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
327 set_ia32_Immop_attr(new_op, imm_op);
330 /* This is a normal shift/rot */
331 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
332 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
336 set_ia32_am_support(new_op, ia32_am_Dest);
339 set_ia32_orig_node(new_op, get_old_node_name(env));
342 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
347 * Construct a standard unary operation, set AM and immediate if required.
349 * @param env The transformation environment
350 * @param op The operand
351 * @param func The node constructor function
352 * @return The constructed ia32 node.
354 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
355 ir_node *new_op = NULL;
356 ir_mode *mode = env->mode;
357 dbg_info *dbg = env->dbg;
358 firm_dbg_module_t *mod = env->mod;
359 ir_graph *irg = env->irg;
360 ir_node *block = env->block;
361 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
362 ir_node *nomem = new_NoMem();
364 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
366 if (mode_is_float(mode)) {
367 DB((mod, LEVEL_1, "FP unop ..."));
368 /* floating point operations don't support implicit store */
369 set_ia32_am_support(new_op, ia32_am_None);
372 DB((mod, LEVEL_1, "INT unop ..."));
373 set_ia32_am_support(new_op, ia32_am_Dest);
377 set_ia32_orig_node(new_op, get_old_node_name(env));
380 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
386 * Creates an ia32 Add with immediate.
388 * @param env The transformation environment
389 * @param expr_op The expression operator
390 * @param const_op The constant
391 * @return the created ia32 Add node
393 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
394 ir_node *new_op = NULL;
395 tarval *tv = get_ia32_Immop_tarval(const_op);
396 firm_dbg_module_t *mod = env->mod;
397 dbg_info *dbg = env->dbg;
398 ir_graph *irg = env->irg;
399 ir_node *block = env->block;
400 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
401 ir_node *nomem = new_NoMem();
403 tarval_classification_t class_tv, class_negtv;
405 /* try to optimize to inc/dec */
406 if (env->cg->opt.incdec && tv) {
407 /* optimize tarvals */
408 class_tv = classify_tarval(tv);
409 class_negtv = classify_tarval(tarval_neg(tv));
411 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
412 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
413 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
416 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
417 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
418 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
424 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
425 set_ia32_Immop_attr(new_op, const_op);
432 * Creates an ia32 Add.
434 * @param dbg firm node dbg
435 * @param block the block the new node should belong to
436 * @param op1 first operator
437 * @param op2 second operator
438 * @param mode node mode
439 * @return the created ia32 Add node
441 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
442 ir_node *new_op = NULL;
443 dbg_info *dbg = env->dbg;
444 ir_mode *mode = env->mode;
445 ir_graph *irg = env->irg;
446 ir_node *block = env->block;
447 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
448 ir_node *nomem = new_NoMem();
449 ir_node *expr_op, *imm_op;
451 /* Check if immediate optimization is on and */
452 /* if it's an operation with immediate. */
453 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
454 expr_op = get_expr_op(op1, op2);
456 assert((expr_op || imm_op) && "invalid operands");
458 if (mode_is_float(mode)) {
459 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
464 /* No expr_op means, that we have two const - one symconst and */
465 /* one tarval or another symconst - because this case is not */
466 /* covered by constant folding */
468 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
469 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
470 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
473 set_ia32_am_support(new_op, ia32_am_Source);
474 set_ia32_op_type(new_op, ia32_AddrModeS);
475 set_ia32_am_flavour(new_op, ia32_am_O);
477 /* Lea doesn't need a Proj */
481 /* This is expr + const */
482 new_op = gen_imm_Add(env, expr_op, imm_op);
485 set_ia32_am_support(new_op, ia32_am_Dest);
488 /* This is a normal add */
489 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
492 set_ia32_am_support(new_op, ia32_am_Full);
497 set_ia32_orig_node(new_op, get_old_node_name(env));
500 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
506 * Creates an ia32 Mul.
508 * @param dbg firm node dbg
509 * @param block the block the new node should belong to
510 * @param op1 first operator
511 * @param op2 second operator
512 * @param mode node mode
513 * @return the created ia32 Mul node
515 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
518 if (mode_is_float(env->mode)) {
519 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
522 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
531 * Creates an ia32 Mulh.
532 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
533 * this result while Mul returns the lower 32 bit.
535 * @param env The transformation environment
536 * @param op1 The first operator
537 * @param op2 The second operator
538 * @return the created ia32 Mulh node
540 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
541 ir_node *proj_EAX, *proj_EDX, *mulh;
544 assert(mode_is_float(env->mode) && "Mulh with float not supported");
545 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
546 mulh = get_Proj_pred(proj_EAX);
547 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
549 /* to be on the save side */
550 set_Proj_proj(proj_EAX, pn_EAX);
552 if (get_ia32_cnst(mulh)) {
553 /* Mulh with const cannot have AM */
554 set_ia32_am_support(mulh, ia32_am_None);
557 /* Mulh cannot have AM for destination */
558 set_ia32_am_support(mulh, ia32_am_Source);
564 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
572 * Creates an ia32 And.
574 * @param env The transformation environment
575 * @param op1 The first operator
576 * @param op2 The second operator
577 * @return The created ia32 And node
579 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
580 if (mode_is_float(env->mode)) {
581 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
584 return gen_binop(env, op1, op2, new_rd_ia32_And);
591 * Creates an ia32 Or.
593 * @param env The transformation environment
594 * @param op1 The first operator
595 * @param op2 The second operator
596 * @return The created ia32 Or node
598 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
599 if (mode_is_float(env->mode)) {
600 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
603 return gen_binop(env, op1, op2, new_rd_ia32_Or);
610 * Creates an ia32 Eor.
612 * @param env The transformation environment
613 * @param op1 The first operator
614 * @param op2 The second operator
615 * @return The created ia32 Eor node
617 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
618 if (mode_is_float(env->mode)) {
619 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
622 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
629 * Creates an ia32 Max.
631 * @param env The transformation environment
632 * @param op1 The first operator
633 * @param op2 The second operator
634 * @return the created ia32 Max node
636 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
639 if (mode_is_float(env->mode)) {
640 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
643 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
644 set_ia32_am_support(new_op, ia32_am_None);
653 * Creates an ia32 Min.
655 * @param env The transformation environment
656 * @param op1 The first operator
657 * @param op2 The second operator
658 * @return the created ia32 Min node
660 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
663 if (mode_is_float(env->mode)) {
664 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
667 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
668 set_ia32_am_support(new_op, ia32_am_None);
670 set_ia32_orig_node(new_op, get_old_node_name(env));
680 * Creates an ia32 Sub with immediate.
682 * @param env The transformation environment
683 * @param op1 The first operator
684 * @param op2 The second operator
685 * @return The created ia32 Sub node
687 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
688 ir_node *new_op = NULL;
689 tarval *tv = get_ia32_Immop_tarval(const_op);
690 firm_dbg_module_t *mod = env->mod;
691 dbg_info *dbg = env->dbg;
692 ir_graph *irg = env->irg;
693 ir_node *block = env->block;
694 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
695 ir_node *nomem = new_NoMem();
697 tarval_classification_t class_tv, class_negtv;
699 /* try to optimize to inc/dec */
700 if (env->cg->opt.incdec && tv) {
701 /* optimize tarvals */
702 class_tv = classify_tarval(tv);
703 class_negtv = classify_tarval(tarval_neg(tv));
705 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
706 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
707 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
710 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
711 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
712 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
718 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
719 set_ia32_Immop_attr(new_op, const_op);
726 * Creates an ia32 Sub.
728 * @param env The transformation environment
729 * @param op1 The first operator
730 * @param op2 The second operator
731 * @return The created ia32 Sub node
733 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
734 ir_node *new_op = NULL;
735 dbg_info *dbg = env->dbg;
736 ir_mode *mode = env->mode;
737 ir_graph *irg = env->irg;
738 ir_node *block = env->block;
739 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
740 ir_node *nomem = new_NoMem();
741 ir_node *expr_op, *imm_op;
743 /* Check if immediate optimization is on and */
744 /* if it's an operation with immediate. */
745 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
746 expr_op = get_expr_op(op1, op2);
748 assert((expr_op || imm_op) && "invalid operands");
750 if (mode_is_float(mode)) {
751 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
756 /* No expr_op means, that we have two const - one symconst and */
757 /* one tarval or another symconst - because this case is not */
758 /* covered by constant folding */
760 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
761 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
762 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
765 set_ia32_am_support(new_op, ia32_am_Source);
766 set_ia32_op_type(new_op, ia32_AddrModeS);
767 set_ia32_am_flavour(new_op, ia32_am_O);
769 /* Lea doesn't need a Proj */
773 /* This is expr - const */
774 new_op = gen_imm_Sub(env, expr_op, imm_op);
777 set_ia32_am_support(new_op, ia32_am_Dest);
780 /* This is a normal sub */
781 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
784 set_ia32_am_support(new_op, ia32_am_Full);
789 set_ia32_orig_node(new_op, get_old_node_name(env));
792 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
798 * Generates an ia32 DivMod with additional infrastructure for the
799 * register allocator if needed.
801 * @param env The transformation environment
802 * @param dividend -no comment- :)
803 * @param divisor -no comment- :)
804 * @param dm_flav flavour_Div/Mod/DivMod
805 * @return The created ia32 DivMod node
807 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
809 ir_node *edx_node, *cltd;
811 dbg_info *dbg = env->dbg;
812 ir_graph *irg = env->irg;
813 ir_node *block = env->block;
814 ir_mode *mode = env->mode;
815 ir_node *irn = env->irn;
820 mem = get_Div_mem(irn);
823 mem = get_Mod_mem(irn);
826 mem = get_DivMod_mem(irn);
832 if (mode_is_signed(mode)) {
833 /* in signed mode, we need to sign extend the dividend */
834 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
835 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
836 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
839 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
840 set_ia32_Const_type(edx_node, ia32_Const);
841 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
844 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode);
846 set_ia32_flavour(res, dm_flav);
847 set_ia32_n_res(res, 2);
849 /* Only one proj is used -> We must add a second proj and */
850 /* connect this one to a Keep node to eat up the second */
851 /* destroyed register. */
852 if (get_irn_n_edges(irn) == 1) {
853 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
854 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
856 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
857 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
860 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
863 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
867 set_ia32_orig_node(res, get_old_node_name(env));
875 * Wrapper for generate_DivMod. Sets flavour_Mod.
877 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
878 return generate_DivMod(env, op1, op2, flavour_Mod);
884 * Wrapper for generate_DivMod. Sets flavour_Div.
886 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
887 return generate_DivMod(env, op1, op2, flavour_Div);
893 * Wrapper for generate_DivMod. Sets flavour_DivMod.
895 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
896 return generate_DivMod(env, op1, op2, flavour_DivMod);
902 * Creates an ia32 floating Div.
904 * @param env The transformation environment
905 * @param op1 The first operator
906 * @param op2 The second operator
907 * @return The created ia32 fDiv node
909 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
910 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
911 ir_node *nomem = new_rd_NoMem(env->irg);
914 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
915 set_ia32_am_support(new_op, ia32_am_Source);
918 set_ia32_orig_node(new_op, get_old_node_name(env));
927 * Creates an ia32 Shl.
929 * @param env The transformation environment
930 * @param op1 The first operator
931 * @param op2 The second operator
932 * @return The created ia32 Shl node
934 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
935 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
941 * Creates an ia32 Shr.
943 * @param env The transformation environment
944 * @param op1 The first operator
945 * @param op2 The second operator
946 * @return The created ia32 Shr node
948 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
949 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
955 * Creates an ia32 Shrs.
957 * @param env The transformation environment
958 * @param op1 The first operator
959 * @param op2 The second operator
960 * @return The created ia32 Shrs node
962 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
963 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
969 * Creates an ia32 RotL.
971 * @param env The transformation environment
972 * @param op1 The first operator
973 * @param op2 The second operator
974 * @return The created ia32 RotL node
976 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
977 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
983 * Creates an ia32 RotR.
984 * NOTE: There is no RotR with immediate because this would always be a RotL
985 * "imm-mode_size_bits" which can be pre-calculated.
987 * @param env The transformation environment
988 * @param op1 The first operator
989 * @param op2 The second operator
990 * @return The created ia32 RotR node
992 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
993 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
999 * Creates an ia32 RotR or RotL (depending on the found pattern).
1001 * @param env The transformation environment
1002 * @param op1 The first operator
1003 * @param op2 The second operator
1004 * @return The created ia32 RotL or RotR node
1006 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1007 ir_node *rotate = NULL;
1009 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1010 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1011 that means we can create a RotR instead of an Add and a RotL */
1014 ir_node *pred = get_Proj_pred(op2);
1016 if (is_ia32_Add(pred)) {
1017 ir_node *pred_pred = get_irn_n(pred, 2);
1018 tarval *tv = get_ia32_Immop_tarval(pred);
1019 long bits = get_mode_size_bits(env->mode);
1021 if (is_Proj(pred_pred)) {
1022 pred_pred = get_Proj_pred(pred_pred);
1025 if (is_ia32_Minus(pred_pred) &&
1026 tarval_is_long(tv) &&
1027 get_tarval_long(tv) == bits)
1029 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1030 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1037 rotate = gen_RotL(env, op1, op2);
1046 * Transforms a Minus node.
1048 * @param env The transformation environment
1049 * @param op The operator
1050 * @return The created ia32 Minus node
1052 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1055 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1056 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1057 ir_node *nomem = new_rd_NoMem(env->irg);
1060 if (mode_is_float(env->mode)) {
1061 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1063 size = get_mode_size_bits(env->mode);
1064 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1066 set_ia32_sc(new_op, name);
1069 set_ia32_orig_node(new_op, get_old_node_name(env));
1072 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1075 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1084 * Transforms a Not node.
1086 * @param env The transformation environment
1087 * @param op The operator
1088 * @return The created ia32 Not node
1090 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1093 if (mode_is_float(env->mode)) {
1097 new_op = gen_unop(env, op, new_rd_ia32_Not);
1106 * Transforms an Abs node.
1108 * @param env The transformation environment
1109 * @param op The operator
1110 * @return The created ia32 Abs node
1112 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1113 ir_node *res, *p_eax, *p_edx;
1114 dbg_info *dbg = env->dbg;
1115 ir_mode *mode = env->mode;
1116 ir_graph *irg = env->irg;
1117 ir_node *block = env->block;
1118 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1119 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1120 ir_node *nomem = new_NoMem();
1124 if (mode_is_float(mode)) {
1125 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1127 size = get_mode_size_bits(mode);
1128 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1130 set_ia32_sc(res, name);
1133 set_ia32_orig_node(res, get_old_node_name(env));
1136 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1139 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1141 set_ia32_orig_node(res, get_old_node_name(env));
1144 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1145 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1147 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1149 set_ia32_orig_node(res, get_old_node_name(env));
1152 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1154 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1156 set_ia32_orig_node(res, get_old_node_name(env));
1159 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1168 * Transforms a Load.
1170 * @param mod the debug module
1171 * @param block the block the new node should belong to
1172 * @param node the ir Load node
1173 * @param mode node mode
1174 * @return the created ia32 Load node
1176 static ir_node *gen_Load(ia32_transform_env_t *env) {
1177 ir_node *node = env->irn;
1178 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1181 if (mode_is_float(env->mode)) {
1182 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1185 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1188 set_ia32_am_support(new_op, ia32_am_Source);
1189 set_ia32_op_type(new_op, ia32_AddrModeS);
1190 set_ia32_am_flavour(new_op, ia32_B);
1191 set_ia32_ls_mode(new_op, get_Load_mode(node));
1194 set_ia32_orig_node(new_op, get_old_node_name(env));
1203 * Transforms a Store.
1205 * @param mod the debug module
1206 * @param block the block the new node should belong to
1207 * @param node the ir Store node
1208 * @param mode node mode
1209 * @return the created ia32 Store node
1211 static ir_node *gen_Store(ia32_transform_env_t *env) {
1212 ir_node *node = env->irn;
1213 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1214 ir_node *val = get_Store_value(node);
1215 ir_node *ptr = get_Store_ptr(node);
1216 ir_node *mem = get_Store_mem(node);
1217 ir_node *sval = val;
1220 /* in case of storing a const -> make it an attribute */
1221 if (is_ia32_Cnst(val)) {
1225 if (mode_is_float(env->mode)) {
1226 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1229 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1232 /* stored const is an attribute (saves a register) */
1233 if (is_ia32_Cnst(val)) {
1234 set_ia32_Immop_attr(new_op, val);
1237 set_ia32_am_support(new_op, ia32_am_Dest);
1238 set_ia32_op_type(new_op, ia32_AddrModeD);
1239 set_ia32_am_flavour(new_op, ia32_B);
1240 set_ia32_ls_mode(new_op, get_irn_mode(val));
1243 set_ia32_orig_node(new_op, get_old_node_name(env));
1252 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1254 * @param env The transformation environment
1255 * @return The transformed node.
1257 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1258 dbg_info *dbg = env->dbg;
1259 ir_graph *irg = env->irg;
1260 ir_node *block = env->block;
1261 ir_node *node = env->irn;
1262 ir_node *sel = get_Cond_selector(node);
1263 ir_mode *sel_mode = get_irn_mode(sel);
1264 ir_node *res = NULL;
1265 ir_node *pred = NULL;
1266 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1267 ir_node *nomem = new_NoMem();
1268 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1270 if (is_Proj(sel) && sel_mode == mode_b) {
1271 pred = get_Proj_pred(sel);
1273 /* get both compare operators */
1274 cmp_a = get_Cmp_left(pred);
1275 cmp_b = get_Cmp_right(pred);
1277 /* check if we can use a CondJmp with immediate */
1278 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1279 expr = get_expr_op(cmp_a, cmp_b);
1282 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1283 set_ia32_Immop_attr(res, cnst);
1286 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1289 set_ia32_pncode(res, get_Proj_proj(sel));
1290 set_ia32_am_support(res, ia32_am_Source);
1293 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1294 set_ia32_pncode(res, get_Cond_defaultProj(node));
1298 set_ia32_orig_node(res, get_old_node_name(env));
1307 * Transforms a CopyB node.
1309 * @param env The transformation environment
1310 * @return The transformed node.
1312 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1313 ir_node *res = NULL;
1314 dbg_info *dbg = env->dbg;
1315 ir_graph *irg = env->irg;
1316 ir_mode *mode = env->mode;
1317 ir_node *block = env->block;
1318 ir_node *node = env->irn;
1319 ir_node *src = get_CopyB_src(node);
1320 ir_node *dst = get_CopyB_dst(node);
1321 ir_node *mem = get_CopyB_mem(node);
1322 int size = get_type_size_bytes(get_CopyB_type(node));
1325 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1326 /* then we need the size explicitly in ECX. */
1327 if (size >= 16 * 4) {
1328 rem = size & 0x3; /* size % 4 */
1331 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1332 set_ia32_op_type(res, ia32_Const);
1333 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1335 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1336 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1339 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1340 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1344 set_ia32_orig_node(res, get_old_node_name(env));
1353 * Transforms a Mux node into CMov.
1355 * @param env The transformation environment
1356 * @return The transformed node.
1358 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1359 ir_node *node = env->irn;
1360 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1361 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1364 set_ia32_orig_node(new_op, get_old_node_name(env));
1372 * Checks of we can omit the Int -> Int Conv
1374 static int ignore_int_conv(ir_mode *src_mode, ir_mode *tgt_mode) {
1376 int src_sign = mode_is_signed(src_mode);
1377 int tgt_sign = mode_is_signed(tgt_mode);
1378 int src_bits = get_mode_size_bits(src_mode);
1379 int tgt_bits = get_mode_size_bits(tgt_mode);
1381 /* mode_P is already converted in mode_Is */
1383 /* ignore mode_P -> mode_Is Convs */
1384 ignore = ((src_mode == mode_P) && (tgt_mode == mode_Is)) ? 1 : 0;
1386 /* ignore mode_Is -> mode_P Convs */
1387 ignore = ((src_mode == mode_Is) && (tgt_mode == mode_P)) ? 1 : 0;
1390 /* ignore Convs small -> big if same signedness */
1391 ignore = (src_sign == tgt_sign) && (src_bits < tgt_bits) ? 1 : ignore;
1393 /* ignore Bool -> Int Conv */
1394 ignore = (src_mode == mode_b) ? 1 : ignore;
1396 /* ignore Int -> Int Convs if same bitsize */
1397 ignore = (src_bits == tgt_bits) ? 1 : ignore;
1403 * Transforms a Conv node.
1405 * @param env The transformation environment
1406 * @param op The operator
1407 * @return The created ia32 Conv node
1409 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1410 dbg_info *dbg = env->dbg;
1411 ir_graph *irg = env->irg;
1412 ir_mode *src_mode = get_irn_mode(op);
1413 ir_mode *tgt_mode = env->mode;
1414 ir_node *block = env->block;
1415 ir_node *new_op = NULL;
1416 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1417 ir_node *nomem = new_rd_NoMem(irg);
1418 firm_dbg_module_t *mod = env->mod;
1420 if (src_mode == tgt_mode) {
1421 /* this can happen when changing mode_P to mode_Is */
1422 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1423 edges_reroute(env->irn, op, irg);
1425 else if (mode_is_float(src_mode)) {
1426 /* we convert from float ... */
1427 if (mode_is_float(tgt_mode)) {
1429 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1430 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1434 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1435 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1439 /* we convert from int ... */
1440 if (mode_is_float(tgt_mode)) {
1442 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1443 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1447 DB((mod, LEVEL_1, "create Conv(int, int) ..."));
1449 /* check if we can omit the Conv */
1450 if (ignore_int_conv(src_mode, tgt_mode)) {
1451 DB((mod, LEVEL_1, "omitted Conv ..."));
1452 edges_reroute(env->irn, op, irg);
1455 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1462 set_ia32_orig_node(new_op, get_old_node_name(env));
1465 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1473 /********************************************
1476 * | |__ ___ _ __ ___ __| | ___ ___
1477 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1478 * | |_) | __/ | | | (_) | (_| | __/\__ \
1479 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1481 ********************************************/
1484 * Transforms a FrameAddr into an ia32 Add.
1486 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1487 ir_node *new_op = NULL;
1488 ir_node *node = env->irn;
1489 ir_node *op = get_irn_n(node, 0);
1490 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1491 ir_node *nomem = new_rd_NoMem(env->irg);
1493 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1494 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1495 set_ia32_am_support(new_op, ia32_am_Full);
1496 set_ia32_use_frame(new_op);
1499 set_ia32_orig_node(new_op, get_old_node_name(env));
1502 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1506 * Transforms a FrameLoad into an ia32 Load.
1508 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1509 ir_node *new_op = NULL;
1510 ir_node *node = env->irn;
1511 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1512 ir_node *mem = get_irn_n(node, 0);
1513 ir_node *ptr = get_irn_n(node, 1);
1514 entity *ent = be_get_frame_entity(node);
1515 ir_mode *mode = get_type_mode(get_entity_type(ent));
1517 if (mode_is_float(mode)) {
1518 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1521 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1524 set_ia32_frame_ent(new_op, ent);
1526 set_ia32_am_support(new_op, ia32_am_Source);
1527 set_ia32_op_type(new_op, ia32_AddrModeS);
1528 set_ia32_am_flavour(new_op, ia32_B);
1529 set_ia32_ls_mode(new_op, mode);
1532 set_ia32_orig_node(new_op, get_old_node_name(env));
1540 * Transforms a FrameStore into an ia32 Store.
1542 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1543 ir_node *new_op = NULL;
1544 ir_node *node = env->irn;
1545 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1546 ir_node *mem = get_irn_n(node, 0);
1547 ir_node *ptr = get_irn_n(node, 1);
1548 ir_node *val = get_irn_n(node, 2);
1549 entity *ent = be_get_frame_entity(node);
1550 ir_mode *mode = get_irn_mode(val);
1552 if (mode_is_float(mode)) {
1553 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1556 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1558 set_ia32_frame_ent(new_op, ent);
1560 set_ia32_am_support(new_op, ia32_am_Dest);
1561 set_ia32_op_type(new_op, ia32_AddrModeD);
1562 set_ia32_am_flavour(new_op, ia32_B);
1563 set_ia32_ls_mode(new_op, mode);
1566 set_ia32_orig_node(new_op, get_old_node_name(env));
1574 /*********************************************************
1577 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1578 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1579 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1580 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1582 *********************************************************/
1585 * Transforms the given firm node (and maybe some other related nodes)
1586 * into one or more assembler nodes.
1588 * @param node the firm node
1589 * @param env the debug module
1591 void ia32_transform_node(ir_node *node, void *env) {
1592 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1593 opcode code = get_irn_opcode(node);
1594 ir_node *asm_node = NULL;
1595 ia32_transform_env_t tenv;
1600 tenv.block = get_nodes_block(node);
1601 tenv.dbg = get_irn_dbg_info(node);
1602 tenv.irg = current_ir_graph;
1604 tenv.mod = cgenv->mod;
1605 tenv.mode = get_irn_mode(node);
1608 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1609 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1610 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1611 #define IGN(a) case iro_##a: break
1612 #define BAD(a) case iro_##a: goto bad
1613 #define OTHER_BIN(a) \
1614 if (get_irn_op(node) == get_op_##a()) { \
1615 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1619 if (be_is_##a(node)) { \
1620 asm_node = gen_##a(&tenv); \
1624 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1671 /* constant transformation happens earlier */
1700 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1704 /* exchange nodes if a new one was generated */
1706 exchange(node, asm_node);
1707 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1710 DB((tenv.mod, LEVEL_1, "ignored\n"));