2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
60 #include "bearch_ia32_t.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_map_regs.h"
65 #include "ia32_dbg_stat.h"
66 #include "ia32_optimize.h"
67 #include "ia32_util.h"
68 #include "ia32_address_mode.h"
69 #include "ia32_architecture.h"
71 #include "gen_ia32_regalloc_if.h"
73 #define SFP_SIGN "0x80000000"
74 #define DFP_SIGN "0x8000000000000000"
75 #define SFP_ABS "0x7FFFFFFF"
76 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define DFP_INTMAX "9223372036854775807"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
83 #define TP_INT_MAX "ia32_int_max"
85 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
86 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
87 #define ENT_SFP_ABS "IA32_SFP_ABS"
88 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define ENT_INT_MAX "IA32_INT_MAX"
91 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
92 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
96 /** hold the current code generator during transformation */
97 static ia32_code_gen_t *env_cg = NULL;
98 static ir_node *initial_fpcw = NULL;
99 static heights_t *heights = NULL;
101 extern ir_op *get_op_Mulh(void);
103 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
104 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
105 ir_node *op1, ir_node *op2);
107 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
108 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
109 ir_node *op1, ir_node *op2, ir_node *flags);
111 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
112 ir_node *block, ir_node *op1, ir_node *op2);
114 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
115 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
119 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
121 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
122 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
123 ir_node *op1, ir_node *op2, ir_node *fpcw);
125 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
126 ir_node *block, ir_node *op);
128 static ir_node *try_create_Immediate(ir_node *node,
129 char immediate_constraint_type);
131 static ir_node *create_immediate_or_transform(ir_node *node,
132 char immediate_constraint_type);
134 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
135 dbg_info *dbgi, ir_node *block,
136 ir_node *op, ir_node *orig_node);
139 * Return true if a mode can be stored in the GP register set
141 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
142 if(mode == mode_fpcw)
144 if(get_mode_size_bits(mode) > 32)
146 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
150 * creates a unique ident by adding a number to a tag
152 * @param tag the tag string, must contain a %d if a number
155 static ident *unique_id(const char *tag)
157 static unsigned id = 0;
160 snprintf(str, sizeof(str), tag, ++id);
161 return new_id_from_str(str);
165 * Get a primitive type for a mode.
167 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
169 pmap_entry *e = pmap_find(types, mode);
174 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
175 res = new_type_primitive(new_id_from_str(buf), mode);
176 set_type_alignment_bytes(res, 16);
177 pmap_insert(types, mode, res);
185 * Creates an immediate.
187 * @param symconst if set, create a SymConst immediate
188 * @param symconst_sign sign for the symconst
189 * @param val integer value for the immediate
191 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
193 ir_graph *irg = current_ir_graph;
194 ir_node *start_block = get_irg_start_block(irg);
195 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
196 symconst, symconst_sign, val);
197 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
203 * Get an atomic entity that is initialized with a tarval forming
206 * @param cnst the node representing the constant
208 static ir_entity *create_float_const_entity(ir_node *cnst)
210 ia32_isa_t *isa = env_cg->isa;
211 tarval *key = get_Const_tarval(cnst);
212 pmap_entry *e = pmap_find(isa->tv_ent, key);
218 ir_mode *mode = get_tarval_mode(tv);
221 if (! ia32_cg_config.use_sse2) {
222 /* try to reduce the mode to produce smaller sized entities */
223 if (mode != mode_F) {
224 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
226 tv = tarval_convert_to(tv, mode);
227 } else if (mode != mode_D) {
228 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
230 tv = tarval_convert_to(tv, mode);
236 if (mode == get_irn_mode(cnst)) {
237 /* mode was not changed */
238 tp = get_Const_type(cnst);
239 if (tp == firm_unknown_type)
240 tp = get_prim_type(isa->types, mode);
242 tp = get_prim_type(isa->types, mode);
244 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
246 set_entity_ld_ident(res, get_entity_ident(res));
247 set_entity_visibility(res, visibility_local);
248 set_entity_variability(res, variability_constant);
249 set_entity_allocation(res, allocation_static);
251 /* we create a new entity here: It's initialization must resist on the
253 rem = current_ir_graph;
254 current_ir_graph = get_const_code_irg();
255 set_atomic_ent_value(res, new_Const_type(tv, tp));
256 current_ir_graph = rem;
258 pmap_insert(isa->tv_ent, key, res);
266 static int is_Const_0(ir_node *node) {
267 return is_Const(node) && is_Const_null(node);
270 static int is_Const_1(ir_node *node) {
271 return is_Const(node) && is_Const_one(node);
274 static int is_Const_Minus_1(ir_node *node) {
275 return is_Const(node) && is_Const_all_one(node);
279 * returns true if constant can be created with a simple float command
281 static int is_simple_x87_Const(ir_node *node)
283 tarval *tv = get_Const_tarval(node);
284 if (tarval_is_null(tv) || tarval_is_one(tv))
287 /* TODO: match all the other float constants */
292 * returns true if constant can be created with a simple float command
294 static int is_simple_sse_Const(ir_node *node)
296 tarval *tv = get_Const_tarval(node);
297 ir_mode *mode = get_tarval_mode(tv);
302 if (tarval_is_null(tv) || tarval_is_one(tv))
305 if (mode == mode_D) {
306 unsigned val = get_tarval_sub_bits(tv, 0) |
307 (get_tarval_sub_bits(tv, 1) << 8) |
308 (get_tarval_sub_bits(tv, 2) << 16) |
309 (get_tarval_sub_bits(tv, 3) << 24);
311 /* lower 32bit are zero, really a 32bit constant */
315 /* TODO: match all the other float constants */
320 * Transforms a Const.
322 static ir_node *gen_Const(ir_node *node) {
323 ir_graph *irg = current_ir_graph;
324 ir_node *old_block = get_nodes_block(node);
325 ir_node *block = be_transform_node(old_block);
326 dbg_info *dbgi = get_irn_dbg_info(node);
327 ir_mode *mode = get_irn_mode(node);
329 assert(is_Const(node));
331 if (mode_is_float(mode)) {
333 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
334 ir_node *nomem = new_NoMem();
338 if (ia32_cg_config.use_sse2) {
339 tarval *tv = get_Const_tarval(node);
340 if (tarval_is_null(tv)) {
341 load = new_rd_ia32_xZero(dbgi, irg, block);
342 set_ia32_ls_mode(load, mode);
344 } else if (tarval_is_one(tv)) {
345 int cnst = mode == mode_F ? 26 : 55;
346 ir_node *imm1 = create_Immediate(NULL, 0, cnst);
347 ir_node *imm2 = create_Immediate(NULL, 0, 2);
348 ir_node *pslld, *psrld;
350 load = new_rd_ia32_xAllOnes(dbgi, irg, block);
351 set_ia32_ls_mode(load, mode);
352 pslld = new_rd_ia32_xPslld(dbgi, irg, block, load, imm1);
353 set_ia32_ls_mode(pslld, mode);
354 psrld = new_rd_ia32_xPsrld(dbgi, irg, block, pslld, imm2);
355 set_ia32_ls_mode(psrld, mode);
357 } else if (mode == mode_F) {
358 /* we can place any 32bit constant by using a movd gp, sse */
359 unsigned val = get_tarval_sub_bits(tv, 0) |
360 (get_tarval_sub_bits(tv, 1) << 8) |
361 (get_tarval_sub_bits(tv, 2) << 16) |
362 (get_tarval_sub_bits(tv, 3) << 24);
363 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
364 load = new_rd_ia32_xMovd(dbgi, irg, block, cnst);
365 set_ia32_ls_mode(load, mode);
368 if (mode == mode_D) {
369 unsigned val = get_tarval_sub_bits(tv, 0) |
370 (get_tarval_sub_bits(tv, 1) << 8) |
371 (get_tarval_sub_bits(tv, 2) << 16) |
372 (get_tarval_sub_bits(tv, 3) << 24);
374 ir_node *imm32 = create_Immediate(NULL, 0, 32);
375 ir_node *cnst, *psllq;
377 /* fine, lower 32bit are zero, produce 32bit value */
378 val = get_tarval_sub_bits(tv, 4) |
379 (get_tarval_sub_bits(tv, 5) << 8) |
380 (get_tarval_sub_bits(tv, 6) << 16) |
381 (get_tarval_sub_bits(tv, 7) << 24);
382 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
383 load = new_rd_ia32_xMovd(dbgi, irg, block, cnst);
384 set_ia32_ls_mode(load, mode);
385 psllq = new_rd_ia32_xPsllq(dbgi, irg, block, load, imm32);
386 set_ia32_ls_mode(psllq, mode);
391 floatent = create_float_const_entity(node);
393 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
395 set_ia32_op_type(load, ia32_AddrModeS);
396 set_ia32_am_sc(load, floatent);
397 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
398 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
401 if (is_Const_null(node)) {
402 load = new_rd_ia32_vfldz(dbgi, irg, block);
404 set_ia32_ls_mode(load, mode);
405 } else if (is_Const_one(node)) {
406 load = new_rd_ia32_vfld1(dbgi, irg, block);
408 set_ia32_ls_mode(load, mode);
410 floatent = create_float_const_entity(node);
412 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
413 set_ia32_op_type(load, ia32_AddrModeS);
414 set_ia32_am_sc(load, floatent);
415 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
416 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
417 /* take the mode from the entity */
418 set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent)));
422 /* Const Nodes before the initial IncSP are a bad idea, because
423 * they could be spilled and we have no SP ready at that point yet.
424 * So add a dependency to the initial frame pointer calculation to
425 * avoid that situation.
427 if (get_irg_start_block(irg) == block) {
428 add_irn_dep(load, get_irg_frame(irg));
431 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
433 } else { /* non-float mode */
435 tarval *tv = get_Const_tarval(node);
438 tv = tarval_convert_to(tv, mode_Iu);
440 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
442 panic("couldn't convert constant tarval (%+F)", node);
444 val = get_tarval_long(tv);
446 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
447 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
450 if (get_irg_start_block(irg) == block) {
451 add_irn_dep(cnst, get_irg_frame(irg));
459 * Transforms a SymConst.
461 static ir_node *gen_SymConst(ir_node *node) {
462 ir_graph *irg = current_ir_graph;
463 ir_node *old_block = get_nodes_block(node);
464 ir_node *block = be_transform_node(old_block);
465 dbg_info *dbgi = get_irn_dbg_info(node);
466 ir_mode *mode = get_irn_mode(node);
469 if (mode_is_float(mode)) {
470 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
471 ir_node *nomem = new_NoMem();
473 if (ia32_cg_config.use_sse2)
474 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
476 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
477 set_ia32_am_sc(cnst, get_SymConst_entity(node));
478 set_ia32_use_frame(cnst);
482 if(get_SymConst_kind(node) != symconst_addr_ent) {
483 panic("backend only support symconst_addr_ent (at %+F)", node);
485 entity = get_SymConst_entity(node);
486 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
489 /* Const Nodes before the initial IncSP are a bad idea, because
490 * they could be spilled and we have no SP ready at that point yet
492 if (get_irg_start_block(irg) == block) {
493 add_irn_dep(cnst, get_irg_frame(irg));
496 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
501 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
502 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
503 static const struct {
505 const char *ent_name;
506 const char *cnst_str;
509 } names [ia32_known_const_max] = {
510 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
511 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
512 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
513 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
514 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
516 static ir_entity *ent_cache[ia32_known_const_max];
518 const char *tp_name, *ent_name, *cnst_str;
526 ent_name = names[kct].ent_name;
527 if (! ent_cache[kct]) {
528 tp_name = names[kct].tp_name;
529 cnst_str = names[kct].cnst_str;
531 switch (names[kct].mode) {
532 case 0: mode = mode_Iu; break;
533 case 1: mode = mode_Lu; break;
534 default: mode = mode_F; break;
536 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
537 tp = new_type_primitive(new_id_from_str(tp_name), mode);
538 /* set the specified alignment */
539 set_type_alignment_bytes(tp, names[kct].align);
541 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
543 set_entity_ld_ident(ent, get_entity_ident(ent));
544 set_entity_visibility(ent, visibility_local);
545 set_entity_variability(ent, variability_constant);
546 set_entity_allocation(ent, allocation_static);
548 /* we create a new entity here: It's initialization must resist on the
550 rem = current_ir_graph;
551 current_ir_graph = get_const_code_irg();
552 cnst = new_Const(mode, tv);
553 current_ir_graph = rem;
555 set_atomic_ent_value(ent, cnst);
557 /* cache the entry */
558 ent_cache[kct] = ent;
561 return ent_cache[kct];
566 * Prints the old node name on cg obst and returns a pointer to it.
568 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
569 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
571 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
572 obstack_1grow(isa->name_obst, 0);
573 return obstack_finish(isa->name_obst);
578 * return true if the node is a Proj(Load) and could be used in source address
579 * mode for another node. Will return only true if the @p other node is not
580 * dependent on the memory of the Load (for binary operations use the other
581 * input here, for unary operations use NULL).
583 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
584 ir_node *other, ir_node *other2)
589 /* float constants are always available */
590 if (is_Const(node)) {
591 ir_mode *mode = get_irn_mode(node);
592 if (mode_is_float(mode)) {
593 if (ia32_cg_config.use_sse2) {
594 if (is_simple_sse_Const(node))
597 if (is_simple_x87_Const(node))
600 if (get_irn_n_edges(node) > 1)
608 load = get_Proj_pred(node);
609 pn = get_Proj_proj(node);
610 if (!is_Load(load) || pn != pn_Load_res)
612 if (get_nodes_block(load) != block)
614 /* we only use address mode if we're the only user of the load */
615 if (get_irn_n_edges(node) > 1)
617 /* in some edge cases with address mode we might reach the load normally
618 * and through some AM sequence, if it is already materialized then we
619 * can't create an AM node from it */
620 if (be_is_transformed(node))
623 /* don't do AM if other node inputs depend on the load (via mem-proj) */
624 if (other != NULL && get_nodes_block(other) == block &&
625 heights_reachable_in_block(heights, other, load))
627 if (other2 != NULL && get_nodes_block(other2) == block &&
628 heights_reachable_in_block(heights, other2, load))
634 typedef struct ia32_address_mode_t ia32_address_mode_t;
635 struct ia32_address_mode_t {
639 ia32_op_type_t op_type;
643 unsigned commutative : 1;
644 unsigned ins_permuted : 1;
647 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
651 /* construct load address */
652 memset(addr, 0, sizeof(addr[0]));
653 ia32_create_address_mode(addr, ptr, /*force=*/0);
655 noreg_gp = ia32_new_NoReg_gp(env_cg);
656 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
657 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
658 addr->mem = be_transform_node(mem);
661 static void build_address(ia32_address_mode_t *am, ir_node *node)
663 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
664 ia32_address_t *addr = &am->addr;
670 if (is_Const(node)) {
671 ir_entity *entity = create_float_const_entity(node);
672 addr->base = noreg_gp;
673 addr->index = noreg_gp;
674 addr->mem = new_NoMem();
675 addr->symconst_ent = entity;
677 am->ls_mode = get_type_mode(get_entity_type(entity));
678 am->pinned = op_pin_state_floats;
682 load = get_Proj_pred(node);
683 ptr = get_Load_ptr(load);
684 mem = get_Load_mem(load);
685 new_mem = be_transform_node(mem);
686 am->pinned = get_irn_pinned(load);
687 am->ls_mode = get_Load_mode(load);
688 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
690 /* construct load address */
691 ia32_create_address_mode(addr, ptr, /*force=*/0);
693 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
694 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
698 static void set_address(ir_node *node, const ia32_address_t *addr)
700 set_ia32_am_scale(node, addr->scale);
701 set_ia32_am_sc(node, addr->symconst_ent);
702 set_ia32_am_offs_int(node, addr->offset);
703 if(addr->symconst_sign)
704 set_ia32_am_sc_sign(node);
706 set_ia32_use_frame(node);
707 set_ia32_frame_ent(node, addr->frame_entity);
711 * Apply attributes of a given address mode to a node.
713 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
715 set_address(node, &am->addr);
717 set_ia32_op_type(node, am->op_type);
718 set_ia32_ls_mode(node, am->ls_mode);
719 if (am->pinned == op_pin_state_pinned) {
720 set_irn_pinned(node, am->pinned);
723 set_ia32_commutative(node);
727 * Check, if a given node is a Down-Conv, ie. a integer Conv
728 * from a mode with a mode with more bits to a mode with lesser bits.
729 * Moreover, we return only true if the node has not more than 1 user.
731 * @param node the node
732 * @return non-zero if node is a Down-Conv
734 static int is_downconv(const ir_node *node)
742 /* we only want to skip the conv when we're the only user
743 * (not optimal but for now...)
745 if(get_irn_n_edges(node) > 1)
748 src_mode = get_irn_mode(get_Conv_op(node));
749 dest_mode = get_irn_mode(node);
750 return mode_needs_gp_reg(src_mode)
751 && mode_needs_gp_reg(dest_mode)
752 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
755 /* Skip all Down-Conv's on a given node and return the resulting node. */
756 ir_node *ia32_skip_downconv(ir_node *node) {
757 while (is_downconv(node))
758 node = get_Conv_op(node);
764 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
766 ir_mode *mode = get_irn_mode(node);
771 if(mode_is_signed(mode)) {
776 block = get_nodes_block(node);
777 dbgi = get_irn_dbg_info(node);
779 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
784 * matches operands of a node into ia32 addressing/operand modes. This covers
785 * usage of source address mode, immediates, operations with non 32-bit modes,
787 * The resulting data is filled into the @p am struct. block is the block
788 * of the node whose arguments are matched. op1, op2 are the first and second
789 * input that are matched (op1 may be NULL). other_op is another unrelated
790 * input that is not matched! but which is needed sometimes to check if AM
791 * for op1/op2 is legal.
792 * @p flags describes the supported modes of the operation in detail.
794 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
795 ir_node *op1, ir_node *op2, ir_node *other_op,
798 ia32_address_t *addr = &am->addr;
799 ir_mode *mode = get_irn_mode(op2);
800 int mode_bits = get_mode_size_bits(mode);
801 ir_node *noreg_gp, *new_op1, *new_op2;
803 unsigned commutative;
804 int use_am_and_immediates;
807 memset(am, 0, sizeof(am[0]));
809 commutative = (flags & match_commutative) != 0;
810 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
811 use_am = (flags & match_am) != 0;
812 use_immediate = (flags & match_immediate) != 0;
813 assert(!use_am_and_immediates || use_immediate);
816 assert(!commutative || op1 != NULL);
817 assert(use_am || !(flags & match_8bit_am));
818 assert(use_am || !(flags & match_16bit_am));
820 if (mode_bits == 8) {
821 if (!(flags & match_8bit_am))
823 /* we don't automatically add upconvs yet */
824 assert((flags & match_mode_neutral) || (flags & match_8bit));
825 } else if (mode_bits == 16) {
826 if (!(flags & match_16bit_am))
828 /* we don't automatically add upconvs yet */
829 assert((flags & match_mode_neutral) || (flags & match_16bit));
832 /* we can simply skip downconvs for mode neutral nodes: the upper bits
833 * can be random for these operations */
834 if (flags & match_mode_neutral) {
835 op2 = ia32_skip_downconv(op2);
837 op1 = ia32_skip_downconv(op1);
841 /* match immediates. firm nodes are normalized: constants are always on the
844 if (!(flags & match_try_am) && use_immediate) {
845 new_op2 = try_create_Immediate(op2, 0);
848 noreg_gp = ia32_new_NoReg_gp(env_cg);
849 if (new_op2 == NULL &&
850 use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
851 build_address(am, op2);
852 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
853 if (mode_is_float(mode)) {
854 new_op2 = ia32_new_NoReg_vfp(env_cg);
858 am->op_type = ia32_AddrModeS;
859 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
861 ia32_use_source_address_mode(block, op1, op2, other_op)) {
863 build_address(am, op1);
865 if (mode_is_float(mode)) {
866 noreg = ia32_new_NoReg_vfp(env_cg);
871 if (new_op2 != NULL) {
874 new_op1 = be_transform_node(op2);
876 am->ins_permuted = 1;
878 am->op_type = ia32_AddrModeS;
880 if (flags & match_try_am) {
883 am->op_type = ia32_Normal;
887 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
889 new_op2 = be_transform_node(op2);
890 am->op_type = ia32_Normal;
891 am->ls_mode = get_irn_mode(op2);
892 if (flags & match_mode_neutral)
893 am->ls_mode = mode_Iu;
895 if (addr->base == NULL)
896 addr->base = noreg_gp;
897 if (addr->index == NULL)
898 addr->index = noreg_gp;
899 if (addr->mem == NULL)
900 addr->mem = new_NoMem();
902 am->new_op1 = new_op1;
903 am->new_op2 = new_op2;
904 am->commutative = commutative;
907 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
912 if (am->mem_proj == NULL)
915 /* we have to create a mode_T so the old MemProj can attach to us */
916 mode = get_irn_mode(node);
917 load = get_Proj_pred(am->mem_proj);
919 mark_irn_visited(load);
920 be_set_transformed_node(load, node);
922 if (mode != mode_T) {
923 set_irn_mode(node, mode_T);
924 return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res);
931 * Construct a standard binary operation, set AM and immediate if required.
933 * @param op1 The first operand
934 * @param op2 The second operand
935 * @param func The node constructor function
936 * @return The constructed ia32 node.
938 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
939 construct_binop_func *func, match_flags_t flags)
942 ir_node *block, *new_block, *new_node;
943 ia32_address_mode_t am;
944 ia32_address_t *addr = &am.addr;
946 block = get_nodes_block(node);
947 match_arguments(&am, block, op1, op2, NULL, flags);
949 dbgi = get_irn_dbg_info(node);
950 new_block = be_transform_node(block);
951 new_node = func(dbgi, current_ir_graph, new_block,
952 addr->base, addr->index, addr->mem,
953 am.new_op1, am.new_op2);
954 set_am_attributes(new_node, &am);
955 /* we can't use source address mode anymore when using immediates */
956 if (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
957 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
958 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
960 new_node = fix_mem_proj(new_node, &am);
967 n_ia32_l_binop_right,
968 n_ia32_l_binop_eflags
970 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
971 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
972 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
973 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
974 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
975 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
978 * Construct a binary operation which also consumes the eflags.
980 * @param node The node to transform
981 * @param func The node constructor function
982 * @param flags The match flags
983 * @return The constructor ia32 node
985 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
988 ir_node *src_block = get_nodes_block(node);
989 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
990 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
992 ir_node *block, *new_node, *eflags, *new_eflags;
993 ia32_address_mode_t am;
994 ia32_address_t *addr = &am.addr;
996 match_arguments(&am, src_block, op1, op2, NULL, flags);
998 dbgi = get_irn_dbg_info(node);
999 block = be_transform_node(src_block);
1000 eflags = get_irn_n(node, n_ia32_l_binop_eflags);
1001 new_eflags = be_transform_node(eflags);
1002 new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index,
1003 addr->mem, am.new_op1, am.new_op2, new_eflags);
1004 set_am_attributes(new_node, &am);
1005 /* we can't use source address mode anymore when using immediates */
1006 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1007 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1008 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1010 new_node = fix_mem_proj(new_node, &am);
1015 static ir_node *get_fpcw(void)
1018 if (initial_fpcw != NULL)
1019 return initial_fpcw;
1021 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1022 &ia32_fp_cw_regs[REG_FPCW]);
1023 initial_fpcw = be_transform_node(fpcw);
1025 return initial_fpcw;
1029 * Construct a standard binary operation, set AM and immediate if required.
1031 * @param op1 The first operand
1032 * @param op2 The second operand
1033 * @param func The node constructor function
1034 * @return The constructed ia32 node.
1036 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1037 construct_binop_float_func *func,
1038 match_flags_t flags)
1040 ir_mode *mode = get_irn_mode(node);
1042 ir_node *block, *new_block, *new_node;
1043 ia32_address_mode_t am;
1044 ia32_address_t *addr = &am.addr;
1046 /* cannot use address mode with long double on x87 */
1047 if (get_mode_size_bits(mode) > 64)
1050 block = get_nodes_block(node);
1051 match_arguments(&am, block, op1, op2, NULL, flags);
1053 dbgi = get_irn_dbg_info(node);
1054 new_block = be_transform_node(block);
1055 new_node = func(dbgi, current_ir_graph, new_block,
1056 addr->base, addr->index, addr->mem,
1057 am.new_op1, am.new_op2, get_fpcw());
1058 set_am_attributes(new_node, &am);
1060 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1062 new_node = fix_mem_proj(new_node, &am);
1068 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1070 * @param op1 The first operand
1071 * @param op2 The second operand
1072 * @param func The node constructor function
1073 * @return The constructed ia32 node.
1075 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1076 construct_shift_func *func,
1077 match_flags_t flags)
1080 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
1082 assert(! mode_is_float(get_irn_mode(node)));
1083 assert(flags & match_immediate);
1084 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
1086 if (flags & match_mode_neutral) {
1087 op1 = ia32_skip_downconv(op1);
1088 } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
1089 panic("right shifting of non-32bit values not supported, yet");
1091 new_op1 = be_transform_node(op1);
1093 /* the shift amount can be any mode that is bigger than 5 bits, since all
1094 * other bits are ignored anyway */
1095 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1096 op2 = get_Conv_op(op2);
1097 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1099 new_op2 = create_immediate_or_transform(op2, 0);
1101 dbgi = get_irn_dbg_info(node);
1102 block = get_nodes_block(node);
1103 new_block = be_transform_node(block);
1104 new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2);
1105 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1107 /* lowered shift instruction may have a dependency operand, handle it here */
1108 if (get_irn_arity(node) == 3) {
1109 /* we have a dependency */
1110 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
1111 add_irn_dep(new_node, new_dep);
1119 * Construct a standard unary operation, set AM and immediate if required.
1121 * @param op The operand
1122 * @param func The node constructor function
1123 * @return The constructed ia32 node.
1125 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1126 match_flags_t flags)
1129 ir_node *block, *new_block, *new_op, *new_node;
1131 assert(flags == 0 || flags == match_mode_neutral);
1132 if (flags & match_mode_neutral) {
1133 op = ia32_skip_downconv(op);
1136 new_op = be_transform_node(op);
1137 dbgi = get_irn_dbg_info(node);
1138 block = get_nodes_block(node);
1139 new_block = be_transform_node(block);
1140 new_node = func(dbgi, current_ir_graph, new_block, new_op);
1142 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1147 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1148 ia32_address_t *addr)
1150 ir_node *base, *index, *res;
1154 base = ia32_new_NoReg_gp(env_cg);
1156 base = be_transform_node(base);
1159 index = addr->index;
1160 if (index == NULL) {
1161 index = ia32_new_NoReg_gp(env_cg);
1163 index = be_transform_node(index);
1166 res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index);
1167 set_address(res, addr);
1173 * Returns non-zero if a given address mode has a symbolic or
1174 * numerical offset != 0.
1176 static int am_has_immediates(const ia32_address_t *addr)
1178 return addr->offset != 0 || addr->symconst_ent != NULL
1179 || addr->frame_entity || addr->use_frame;
1183 * Creates an ia32 Add.
1185 * @return the created ia32 Add node
1187 static ir_node *gen_Add(ir_node *node) {
1188 ir_mode *mode = get_irn_mode(node);
1189 ir_node *op1 = get_Add_left(node);
1190 ir_node *op2 = get_Add_right(node);
1192 ir_node *block, *new_block, *new_node, *add_immediate_op;
1193 ia32_address_t addr;
1194 ia32_address_mode_t am;
1196 if (mode_is_float(mode)) {
1197 if (ia32_cg_config.use_sse2)
1198 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1199 match_commutative | match_am);
1201 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1202 match_commutative | match_am);
1205 ia32_mark_non_am(node);
1207 op2 = ia32_skip_downconv(op2);
1208 op1 = ia32_skip_downconv(op1);
1212 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1213 * 1. Add with immediate -> Lea
1214 * 2. Add with possible source address mode -> Add
1215 * 3. Otherwise -> Lea
1217 memset(&addr, 0, sizeof(addr));
1218 ia32_create_address_mode(&addr, node, /*force=*/1);
1219 add_immediate_op = NULL;
1221 dbgi = get_irn_dbg_info(node);
1222 block = get_nodes_block(node);
1223 new_block = be_transform_node(block);
1226 if(addr.base == NULL && addr.index == NULL) {
1227 ir_graph *irg = current_ir_graph;
1228 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1229 addr.symconst_sign, addr.offset);
1230 add_irn_dep(new_node, get_irg_frame(irg));
1231 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1234 /* add with immediate? */
1235 if(addr.index == NULL) {
1236 add_immediate_op = addr.base;
1237 } else if(addr.base == NULL && addr.scale == 0) {
1238 add_immediate_op = addr.index;
1241 if(add_immediate_op != NULL) {
1242 if(!am_has_immediates(&addr)) {
1243 #ifdef DEBUG_libfirm
1244 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1247 return be_transform_node(add_immediate_op);
1250 new_node = create_lea_from_address(dbgi, new_block, &addr);
1251 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1255 /* test if we can use source address mode */
1256 match_arguments(&am, block, op1, op2, NULL, match_commutative
1257 | match_mode_neutral | match_am | match_immediate | match_try_am);
1259 /* construct an Add with source address mode */
1260 if (am.op_type == ia32_AddrModeS) {
1261 ir_graph *irg = current_ir_graph;
1262 ia32_address_t *am_addr = &am.addr;
1263 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1264 am_addr->index, am_addr->mem, am.new_op1,
1266 set_am_attributes(new_node, &am);
1267 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1269 new_node = fix_mem_proj(new_node, &am);
1274 /* otherwise construct a lea */
1275 new_node = create_lea_from_address(dbgi, new_block, &addr);
1276 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1281 * Creates an ia32 Mul.
1283 * @return the created ia32 Mul node
1285 static ir_node *gen_Mul(ir_node *node) {
1286 ir_node *op1 = get_Mul_left(node);
1287 ir_node *op2 = get_Mul_right(node);
1288 ir_mode *mode = get_irn_mode(node);
1290 if (mode_is_float(mode)) {
1291 if (ia32_cg_config.use_sse2)
1292 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1293 match_commutative | match_am);
1295 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1296 match_commutative | match_am);
1298 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1299 match_commutative | match_am | match_mode_neutral |
1300 match_immediate | match_am_and_immediates);
1304 * Creates an ia32 Mulh.
1305 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1306 * this result while Mul returns the lower 32 bit.
1308 * @return the created ia32 Mulh node
1310 static ir_node *gen_Mulh(ir_node *node)
1312 ir_node *block = get_nodes_block(node);
1313 ir_node *new_block = be_transform_node(block);
1314 ir_graph *irg = current_ir_graph;
1315 dbg_info *dbgi = get_irn_dbg_info(node);
1316 ir_mode *mode = get_irn_mode(node);
1317 ir_node *op1 = get_Mulh_left(node);
1318 ir_node *op2 = get_Mulh_right(node);
1319 ir_node *proj_res_high;
1321 ia32_address_mode_t am;
1322 ia32_address_t *addr = &am.addr;
1324 assert(!mode_is_float(mode) && "Mulh with float not supported");
1325 assert(get_mode_size_bits(mode) == 32);
1327 match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am);
1329 if (mode_is_signed(mode)) {
1330 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1331 addr->index, addr->mem, am.new_op1,
1334 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1335 addr->index, addr->mem, am.new_op1,
1339 set_am_attributes(new_node, &am);
1340 /* we can't use source address mode anymore when using immediates */
1341 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1342 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1343 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1345 assert(get_irn_mode(new_node) == mode_T);
1347 fix_mem_proj(new_node, &am);
1349 assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high);
1350 proj_res_high = new_rd_Proj(dbgi, irg, block, new_node,
1351 mode_Iu, pn_ia32_IMul1OP_res_high);
1353 return proj_res_high;
1359 * Creates an ia32 And.
1361 * @return The created ia32 And node
1363 static ir_node *gen_And(ir_node *node) {
1364 ir_node *op1 = get_And_left(node);
1365 ir_node *op2 = get_And_right(node);
1366 assert(! mode_is_float(get_irn_mode(node)));
1368 /* is it a zero extension? */
1369 if (is_Const(op2)) {
1370 tarval *tv = get_Const_tarval(op2);
1371 long v = get_tarval_long(tv);
1373 if (v == 0xFF || v == 0xFFFF) {
1374 dbg_info *dbgi = get_irn_dbg_info(node);
1375 ir_node *block = get_nodes_block(node);
1382 assert(v == 0xFFFF);
1385 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1390 return gen_binop(node, op1, op2, new_rd_ia32_And,
1391 match_commutative | match_mode_neutral | match_am
1398 * Creates an ia32 Or.
1400 * @return The created ia32 Or node
1402 static ir_node *gen_Or(ir_node *node) {
1403 ir_node *op1 = get_Or_left(node);
1404 ir_node *op2 = get_Or_right(node);
1406 assert (! mode_is_float(get_irn_mode(node)));
1407 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1408 | match_mode_neutral | match_am | match_immediate);
1414 * Creates an ia32 Eor.
1416 * @return The created ia32 Eor node
1418 static ir_node *gen_Eor(ir_node *node) {
1419 ir_node *op1 = get_Eor_left(node);
1420 ir_node *op2 = get_Eor_right(node);
1422 assert(! mode_is_float(get_irn_mode(node)));
1423 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1424 | match_mode_neutral | match_am | match_immediate);
1429 * Creates an ia32 Sub.
1431 * @return The created ia32 Sub node
1433 static ir_node *gen_Sub(ir_node *node) {
1434 ir_node *op1 = get_Sub_left(node);
1435 ir_node *op2 = get_Sub_right(node);
1436 ir_mode *mode = get_irn_mode(node);
1438 if (mode_is_float(mode)) {
1439 if (ia32_cg_config.use_sse2)
1440 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1442 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1446 if (is_Const(op2)) {
1447 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1451 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1452 | match_am | match_immediate);
1456 * Generates an ia32 DivMod with additional infrastructure for the
1457 * register allocator if needed.
1459 static ir_node *create_Div(ir_node *node)
1461 ir_graph *irg = current_ir_graph;
1462 dbg_info *dbgi = get_irn_dbg_info(node);
1463 ir_node *block = get_nodes_block(node);
1464 ir_node *new_block = be_transform_node(block);
1471 ir_node *sign_extension;
1472 ia32_address_mode_t am;
1473 ia32_address_t *addr = &am.addr;
1475 /* the upper bits have random contents for smaller modes */
1476 switch (get_irn_opcode(node)) {
1478 op1 = get_Div_left(node);
1479 op2 = get_Div_right(node);
1480 mem = get_Div_mem(node);
1481 mode = get_Div_resmode(node);
1484 op1 = get_Mod_left(node);
1485 op2 = get_Mod_right(node);
1486 mem = get_Mod_mem(node);
1487 mode = get_Mod_resmode(node);
1490 op1 = get_DivMod_left(node);
1491 op2 = get_DivMod_right(node);
1492 mem = get_DivMod_mem(node);
1493 mode = get_DivMod_resmode(node);
1496 panic("invalid divmod node %+F", node);
1499 match_arguments(&am, block, op1, op2, NULL, match_am);
1501 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1502 is the memory of the consumed address. We can have only the second op as address
1503 in Div nodes, so check only op2. */
1504 if(!is_NoMem(mem) && skip_Proj(mem) != skip_Proj(op2)) {
1505 new_mem = be_transform_node(mem);
1506 if(!is_NoMem(addr->mem)) {
1510 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1513 new_mem = addr->mem;
1516 if (mode_is_signed(mode)) {
1517 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1518 add_irn_dep(produceval, get_irg_frame(irg));
1519 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1522 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1523 addr->index, new_mem, am.new_op2,
1524 am.new_op1, sign_extension);
1526 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1527 add_irn_dep(sign_extension, get_irg_frame(irg));
1529 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1530 addr->index, new_mem, am.new_op2,
1531 am.new_op1, sign_extension);
1534 set_irn_pinned(new_node, get_irn_pinned(node));
1536 set_am_attributes(new_node, &am);
1537 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1539 new_node = fix_mem_proj(new_node, &am);
1545 static ir_node *gen_Mod(ir_node *node) {
1546 return create_Div(node);
1549 static ir_node *gen_Div(ir_node *node) {
1550 return create_Div(node);
1553 static ir_node *gen_DivMod(ir_node *node) {
1554 return create_Div(node);
1560 * Creates an ia32 floating Div.
1562 * @return The created ia32 xDiv node
1564 static ir_node *gen_Quot(ir_node *node)
1566 ir_node *op1 = get_Quot_left(node);
1567 ir_node *op2 = get_Quot_right(node);
1569 if (ia32_cg_config.use_sse2) {
1570 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1572 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1578 * Creates an ia32 Shl.
1580 * @return The created ia32 Shl node
1582 static ir_node *gen_Shl(ir_node *node) {
1583 ir_node *left = get_Shl_left(node);
1584 ir_node *right = get_Shl_right(node);
1586 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1587 match_mode_neutral | match_immediate);
1591 * Creates an ia32 Shr.
1593 * @return The created ia32 Shr node
1595 static ir_node *gen_Shr(ir_node *node) {
1596 ir_node *left = get_Shr_left(node);
1597 ir_node *right = get_Shr_right(node);
1599 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1605 * Creates an ia32 Sar.
1607 * @return The created ia32 Shrs node
1609 static ir_node *gen_Shrs(ir_node *node) {
1610 ir_node *left = get_Shrs_left(node);
1611 ir_node *right = get_Shrs_right(node);
1612 ir_mode *mode = get_irn_mode(node);
1614 if(is_Const(right) && mode == mode_Is) {
1615 tarval *tv = get_Const_tarval(right);
1616 long val = get_tarval_long(tv);
1618 /* this is a sign extension */
1619 ir_graph *irg = current_ir_graph;
1620 dbg_info *dbgi = get_irn_dbg_info(node);
1621 ir_node *block = be_transform_node(get_nodes_block(node));
1623 ir_node *new_op = be_transform_node(op);
1624 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1625 add_irn_dep(pval, get_irg_frame(irg));
1627 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1631 /* 8 or 16 bit sign extension? */
1632 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1633 ir_node *shl_left = get_Shl_left(left);
1634 ir_node *shl_right = get_Shl_right(left);
1635 if(is_Const(shl_right)) {
1636 tarval *tv1 = get_Const_tarval(right);
1637 tarval *tv2 = get_Const_tarval(shl_right);
1638 if(tv1 == tv2 && tarval_is_long(tv1)) {
1639 long val = get_tarval_long(tv1);
1640 if(val == 16 || val == 24) {
1641 dbg_info *dbgi = get_irn_dbg_info(node);
1642 ir_node *block = get_nodes_block(node);
1652 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1661 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1667 * Creates an ia32 RotL.
1669 * @param op1 The first operator
1670 * @param op2 The second operator
1671 * @return The created ia32 RotL node
1673 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1674 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1680 * Creates an ia32 RotR.
1681 * NOTE: There is no RotR with immediate because this would always be a RotL
1682 * "imm-mode_size_bits" which can be pre-calculated.
1684 * @param op1 The first operator
1685 * @param op2 The second operator
1686 * @return The created ia32 RotR node
1688 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1689 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1695 * Creates an ia32 RotR or RotL (depending on the found pattern).
1697 * @return The created ia32 RotL or RotR node
1699 static ir_node *gen_Rot(ir_node *node) {
1700 ir_node *rotate = NULL;
1701 ir_node *op1 = get_Rot_left(node);
1702 ir_node *op2 = get_Rot_right(node);
1704 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1705 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1706 that means we can create a RotR instead of an Add and a RotL */
1708 if (get_irn_op(op2) == op_Add) {
1710 ir_node *left = get_Add_left(add);
1711 ir_node *right = get_Add_right(add);
1712 if (is_Const(right)) {
1713 tarval *tv = get_Const_tarval(right);
1714 ir_mode *mode = get_irn_mode(node);
1715 long bits = get_mode_size_bits(mode);
1717 if (get_irn_op(left) == op_Minus &&
1718 tarval_is_long(tv) &&
1719 get_tarval_long(tv) == bits &&
1722 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1723 rotate = gen_RotR(node, op1, get_Minus_op(left));
1728 if (rotate == NULL) {
1729 rotate = gen_RotL(node, op1, op2);
1738 * Transforms a Minus node.
1740 * @return The created ia32 Minus node
1742 static ir_node *gen_Minus(ir_node *node)
1744 ir_node *op = get_Minus_op(node);
1745 ir_node *block = be_transform_node(get_nodes_block(node));
1746 ir_graph *irg = current_ir_graph;
1747 dbg_info *dbgi = get_irn_dbg_info(node);
1748 ir_mode *mode = get_irn_mode(node);
1753 if (mode_is_float(mode)) {
1754 ir_node *new_op = be_transform_node(op);
1755 if (ia32_cg_config.use_sse2) {
1756 /* TODO: non-optimal... if we have many xXors, then we should
1757 * rather create a load for the const and use that instead of
1758 * several AM nodes... */
1759 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1760 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1761 ir_node *nomem = new_rd_NoMem(irg);
1763 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1764 nomem, new_op, noreg_xmm);
1766 size = get_mode_size_bits(mode);
1767 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1769 set_ia32_am_sc(new_node, ent);
1770 set_ia32_op_type(new_node, ia32_AddrModeS);
1771 set_ia32_ls_mode(new_node, mode);
1773 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1776 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1779 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1785 * Transforms a Not node.
1787 * @return The created ia32 Not node
1789 static ir_node *gen_Not(ir_node *node) {
1790 ir_node *op = get_Not_op(node);
1792 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1793 assert (! mode_is_float(get_irn_mode(node)));
1795 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1801 * Transforms an Abs node.
1803 * @return The created ia32 Abs node
1805 static ir_node *gen_Abs(ir_node *node)
1807 ir_node *block = get_nodes_block(node);
1808 ir_node *new_block = be_transform_node(block);
1809 ir_node *op = get_Abs_op(node);
1810 ir_graph *irg = current_ir_graph;
1811 dbg_info *dbgi = get_irn_dbg_info(node);
1812 ir_mode *mode = get_irn_mode(node);
1813 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1814 ir_node *nomem = new_NoMem();
1820 if (mode_is_float(mode)) {
1821 new_op = be_transform_node(op);
1823 if (ia32_cg_config.use_sse2) {
1824 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1825 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1826 nomem, new_op, noreg_fp);
1828 size = get_mode_size_bits(mode);
1829 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1831 set_ia32_am_sc(new_node, ent);
1833 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1835 set_ia32_op_type(new_node, ia32_AddrModeS);
1836 set_ia32_ls_mode(new_node, mode);
1838 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1839 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1842 ir_node *xor, *pval, *sign_extension;
1844 if (get_mode_size_bits(mode) == 32) {
1845 new_op = be_transform_node(op);
1847 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1850 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1851 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1854 add_irn_dep(pval, get_irg_frame(irg));
1855 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1857 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1858 nomem, new_op, sign_extension);
1859 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1861 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1862 nomem, xor, sign_extension);
1863 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1870 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
1872 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) {
1873 dbg_info *dbgi = get_irn_dbg_info(cmp);
1874 ir_node *block = get_nodes_block(cmp);
1875 ir_node *new_block = be_transform_node(block);
1876 ir_node *op1 = be_transform_node(x);
1877 ir_node *op2 = be_transform_node(n);
1879 return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2);
1883 * Transform a node returning a "flag" result.
1885 * @param node the node to transform
1886 * @param pnc_out the compare mode to use
1888 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1897 /* we have a Cmp as input */
1898 if (is_Proj(node)) {
1899 ir_node *pred = get_Proj_pred(node);
1901 pn_Cmp pnc = get_Proj_proj(node);
1902 if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
1903 ir_node *l = get_Cmp_left(pred);
1904 ir_node *r = get_Cmp_right(pred);
1906 ir_node *la = get_And_left(l);
1907 ir_node *ra = get_And_right(l);
1909 ir_node *c = get_Shl_left(la);
1910 if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
1911 /* (1 << n) & ra) */
1912 ir_node *n = get_Shl_right(la);
1913 flags = gen_bt(pred, ra, n);
1914 /* we must generate a Jc/Jnc jump */
1915 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Ge : pn_Cmp_Lt;
1918 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1923 ir_node *c = get_Shl_left(ra);
1924 if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
1925 /* la & (1 << n)) */
1926 ir_node *n = get_Shl_right(ra);
1927 flags = gen_bt(pred, la, n);
1928 /* we must generate a Jc/Jnc jump */
1929 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Ge : pn_Cmp_Lt;
1932 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1938 flags = be_transform_node(pred);
1944 /* a mode_b value, we have to compare it against 0 */
1945 dbgi = get_irn_dbg_info(node);
1946 new_block = be_transform_node(get_nodes_block(node));
1947 new_op = be_transform_node(node);
1948 noreg = ia32_new_NoReg_gp(env_cg);
1949 nomem = new_NoMem();
1950 flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem,
1951 new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
1952 *pnc_out = pn_Cmp_Lg;
1957 * Transforms a Load.
1959 * @return the created ia32 Load node
1961 static ir_node *gen_Load(ir_node *node) {
1962 ir_node *old_block = get_nodes_block(node);
1963 ir_node *block = be_transform_node(old_block);
1964 ir_node *ptr = get_Load_ptr(node);
1965 ir_node *mem = get_Load_mem(node);
1966 ir_node *new_mem = be_transform_node(mem);
1969 ir_graph *irg = current_ir_graph;
1970 dbg_info *dbgi = get_irn_dbg_info(node);
1971 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1972 ir_mode *mode = get_Load_mode(node);
1975 ia32_address_t addr;
1977 /* construct load address */
1978 memset(&addr, 0, sizeof(addr));
1979 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1986 base = be_transform_node(base);
1992 index = be_transform_node(index);
1995 if (mode_is_float(mode)) {
1996 if (ia32_cg_config.use_sse2) {
1997 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1999 res_mode = mode_xmm;
2001 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
2003 res_mode = mode_vfp;
2006 assert(mode != mode_b);
2008 /* create a conv node with address mode for smaller modes */
2009 if(get_mode_size_bits(mode) < 32) {
2010 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
2011 new_mem, noreg, mode);
2013 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
2018 set_irn_pinned(new_node, get_irn_pinned(node));
2019 set_ia32_op_type(new_node, ia32_AddrModeS);
2020 set_ia32_ls_mode(new_node, mode);
2021 set_address(new_node, &addr);
2023 if(get_irn_pinned(node) == op_pin_state_floats) {
2024 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
2027 /* make sure we are scheduled behind the initial IncSP/Barrier
2028 * to avoid spills being placed before it
2030 if (block == get_irg_start_block(irg)) {
2031 add_irn_dep(new_node, get_irg_frame(irg));
2034 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2039 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2040 ir_node *ptr, ir_node *other)
2047 /* we only use address mode if we're the only user of the load */
2048 if(get_irn_n_edges(node) > 1)
2051 load = get_Proj_pred(node);
2054 if(get_nodes_block(load) != block)
2057 /* Store should be attached to the load */
2058 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
2060 /* store should have the same pointer as the load */
2061 if(get_Load_ptr(load) != ptr)
2064 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2065 if(other != NULL && get_nodes_block(other) == block
2066 && heights_reachable_in_block(heights, other, load))
2072 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2073 ir_node *mem, ir_node *ptr, ir_mode *mode,
2074 construct_binop_dest_func *func,
2075 construct_binop_dest_func *func8bit,
2076 match_flags_t flags)
2078 ir_node *src_block = get_nodes_block(node);
2080 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
2081 ir_graph *irg = current_ir_graph;
2086 ia32_address_mode_t am;
2087 ia32_address_t *addr = &am.addr;
2088 memset(&am, 0, sizeof(am));
2090 assert(flags & match_dest_am);
2091 assert(flags & match_immediate); /* there is no destam node without... */
2092 commutative = (flags & match_commutative) != 0;
2094 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
2095 build_address(&am, op1);
2096 new_op = create_immediate_or_transform(op2, 0);
2097 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2098 build_address(&am, op2);
2099 new_op = create_immediate_or_transform(op1, 0);
2104 if(addr->base == NULL)
2105 addr->base = noreg_gp;
2106 if(addr->index == NULL)
2107 addr->index = noreg_gp;
2108 if(addr->mem == NULL)
2109 addr->mem = new_NoMem();
2111 dbgi = get_irn_dbg_info(node);
2112 block = be_transform_node(src_block);
2113 if(get_mode_size_bits(mode) == 8) {
2114 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
2117 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
2120 set_address(new_node, addr);
2121 set_ia32_op_type(new_node, ia32_AddrModeD);
2122 set_ia32_ls_mode(new_node, mode);
2123 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2128 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2129 ir_node *ptr, ir_mode *mode,
2130 construct_unop_dest_func *func)
2132 ir_graph *irg = current_ir_graph;
2133 ir_node *src_block = get_nodes_block(node);
2137 ia32_address_mode_t am;
2138 ia32_address_t *addr = &am.addr;
2139 memset(&am, 0, sizeof(am));
2141 if(!use_dest_am(src_block, op, mem, ptr, NULL))
2144 build_address(&am, op);
2146 dbgi = get_irn_dbg_info(node);
2147 block = be_transform_node(src_block);
2148 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
2149 set_address(new_node, addr);
2150 set_ia32_op_type(new_node, ia32_AddrModeD);
2151 set_ia32_ls_mode(new_node, mode);
2152 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2157 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
2158 ir_mode *mode = get_irn_mode(node);
2159 ir_node *psi_true = get_Psi_val(node, 0);
2160 ir_node *psi_default = get_Psi_default(node);
2171 ia32_address_t addr;
2173 if(get_mode_size_bits(mode) != 8)
2176 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2178 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2184 build_address_ptr(&addr, ptr, mem);
2186 irg = current_ir_graph;
2187 dbgi = get_irn_dbg_info(node);
2188 block = get_nodes_block(node);
2189 new_block = be_transform_node(block);
2190 cond = get_Psi_cond(node, 0);
2191 flags = get_flags_node(cond, &pnc);
2192 new_mem = be_transform_node(mem);
2193 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2194 addr.index, addr.mem, flags, pnc, negated);
2195 set_address(new_node, &addr);
2196 set_ia32_op_type(new_node, ia32_AddrModeD);
2197 set_ia32_ls_mode(new_node, mode);
2198 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2203 static ir_node *try_create_dest_am(ir_node *node) {
2204 ir_node *val = get_Store_value(node);
2205 ir_node *mem = get_Store_mem(node);
2206 ir_node *ptr = get_Store_ptr(node);
2207 ir_mode *mode = get_irn_mode(val);
2208 unsigned bits = get_mode_size_bits(mode);
2213 /* handle only GP modes for now... */
2214 if(!mode_needs_gp_reg(mode))
2218 /* store must be the only user of the val node */
2219 if(get_irn_n_edges(val) > 1)
2221 /* skip pointless convs */
2223 ir_node *conv_op = get_Conv_op(val);
2224 ir_mode *pred_mode = get_irn_mode(conv_op);
2225 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2233 /* value must be in the same block */
2234 if(get_nodes_block(node) != get_nodes_block(val))
2237 switch(get_irn_opcode(val)) {
2239 op1 = get_Add_left(val);
2240 op2 = get_Add_right(val);
2241 if(is_Const_1(op2)) {
2242 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2243 new_rd_ia32_IncMem);
2245 } else if(is_Const_Minus_1(op2)) {
2246 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2247 new_rd_ia32_DecMem);
2250 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2251 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2252 match_dest_am | match_commutative |
2256 op1 = get_Sub_left(val);
2257 op2 = get_Sub_right(val);
2259 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2262 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2263 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2264 match_dest_am | match_immediate |
2268 op1 = get_And_left(val);
2269 op2 = get_And_right(val);
2270 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2271 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2272 match_dest_am | match_commutative |
2276 op1 = get_Or_left(val);
2277 op2 = get_Or_right(val);
2278 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2279 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2280 match_dest_am | match_commutative |
2284 op1 = get_Eor_left(val);
2285 op2 = get_Eor_right(val);
2286 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2287 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2288 match_dest_am | match_commutative |
2292 op1 = get_Shl_left(val);
2293 op2 = get_Shl_right(val);
2294 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2295 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2296 match_dest_am | match_immediate);
2299 op1 = get_Shr_left(val);
2300 op2 = get_Shr_right(val);
2301 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2302 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2303 match_dest_am | match_immediate);
2306 op1 = get_Shrs_left(val);
2307 op2 = get_Shrs_right(val);
2308 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2309 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2310 match_dest_am | match_immediate);
2313 op1 = get_Rot_left(val);
2314 op2 = get_Rot_right(val);
2315 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2316 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2317 match_dest_am | match_immediate);
2319 /* TODO: match ROR patterns... */
2321 new_node = try_create_SetMem(val, ptr, mem);
2324 op1 = get_Minus_op(val);
2325 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2328 /* should be lowered already */
2329 assert(mode != mode_b);
2330 op1 = get_Not_op(val);
2331 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2337 if(new_node != NULL) {
2338 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2339 get_irn_pinned(node) == op_pin_state_pinned) {
2340 set_irn_pinned(new_node, op_pin_state_pinned);
2347 static int is_float_to_int32_conv(const ir_node *node)
2349 ir_mode *mode = get_irn_mode(node);
2353 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2358 conv_op = get_Conv_op(node);
2359 conv_mode = get_irn_mode(conv_op);
2361 if(!mode_is_float(conv_mode))
2368 * Transform a Store(floatConst).
2370 * @return the created ia32 Store node
2372 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) {
2373 ir_mode *mode = get_irn_mode(cns);
2374 int size = get_mode_size_bits(mode);
2375 tarval *tv = get_Const_tarval(cns);
2376 ir_node *block = get_nodes_block(node);
2377 ir_node *new_block = be_transform_node(block);
2378 ir_node *ptr = get_Store_ptr(node);
2379 ir_node *mem = get_Store_mem(node);
2380 ir_graph *irg = current_ir_graph;
2381 dbg_info *dbgi = get_irn_dbg_info(node);
2382 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2385 ia32_address_t addr;
2387 unsigned val = get_tarval_sub_bits(tv, 0) |
2388 (get_tarval_sub_bits(tv, 1) << 8) |
2389 (get_tarval_sub_bits(tv, 2) << 16) |
2390 (get_tarval_sub_bits(tv, 3) << 24);
2391 ir_node *imm = create_Immediate(NULL, 0, val);
2393 /* construct store address */
2394 memset(&addr, 0, sizeof(addr));
2395 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2397 if (addr.base == NULL) {
2400 addr.base = be_transform_node(addr.base);
2403 if (addr.index == NULL) {
2406 addr.index = be_transform_node(addr.index);
2408 addr.mem = be_transform_node(mem);
2410 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2411 addr.index, addr.mem, imm);
2413 set_irn_pinned(new_node, get_irn_pinned(node));
2414 set_ia32_op_type(new_node, ia32_AddrModeD);
2415 set_ia32_ls_mode(new_node, mode_Iu);
2417 set_address(new_node, &addr);
2419 /** add more stores if needed */
2421 unsigned val = get_tarval_sub_bits(tv, ofs) |
2422 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2423 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2424 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2425 ir_node *imm = create_Immediate(NULL, 0, val);
2428 addr.mem = new_node;
2430 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2431 addr.index, addr.mem, imm);
2433 set_irn_pinned(new_node, get_irn_pinned(node));
2434 set_ia32_op_type(new_node, ia32_AddrModeD);
2435 set_ia32_ls_mode(new_node, mode_Iu);
2437 set_address(new_node, &addr);
2442 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2447 * Transforms a normal Store.
2449 * @return the created ia32 Store node
2451 static ir_node *gen_normal_Store(ir_node *node)
2453 ir_node *val = get_Store_value(node);
2454 ir_mode *mode = get_irn_mode(val);
2455 ir_node *block = get_nodes_block(node);
2456 ir_node *new_block = be_transform_node(block);
2457 ir_node *ptr = get_Store_ptr(node);
2458 ir_node *mem = get_Store_mem(node);
2459 ir_graph *irg = current_ir_graph;
2460 dbg_info *dbgi = get_irn_dbg_info(node);
2461 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2464 ia32_address_t addr;
2466 /* check for destination address mode */
2467 new_node = try_create_dest_am(node);
2468 if (new_node != NULL)
2471 /* construct store address */
2472 memset(&addr, 0, sizeof(addr));
2473 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2475 if (addr.base == NULL) {
2478 addr.base = be_transform_node(addr.base);
2481 if (addr.index == NULL) {
2484 addr.index = be_transform_node(addr.index);
2486 addr.mem = be_transform_node(mem);
2488 if (mode_is_float(mode)) {
2489 /* convs (and strict-convs) before stores are unnecessary if the mode
2491 while (is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2492 val = get_Conv_op(val);
2494 new_val = be_transform_node(val);
2495 if (ia32_cg_config.use_sse2) {
2496 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2497 addr.index, addr.mem, new_val);
2499 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2500 addr.index, addr.mem, new_val, mode);
2502 } else if (is_float_to_int32_conv(val)) {
2503 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2504 val = get_Conv_op(val);
2506 /* convs (and strict-convs) before stores are unnecessary if the mode
2508 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2509 val = get_Conv_op(val);
2511 new_val = be_transform_node(val);
2513 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2514 addr.index, addr.mem, new_val, trunc_mode);
2516 new_val = create_immediate_or_transform(val, 0);
2517 assert(mode != mode_b);
2519 if (get_mode_size_bits(mode) == 8) {
2520 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2521 addr.index, addr.mem, new_val);
2523 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2524 addr.index, addr.mem, new_val);
2528 set_irn_pinned(new_node, get_irn_pinned(node));
2529 set_ia32_op_type(new_node, ia32_AddrModeD);
2530 set_ia32_ls_mode(new_node, mode);
2532 set_address(new_node, &addr);
2533 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2539 * Transforms a Store.
2541 * @return the created ia32 Store node
2543 static ir_node *gen_Store(ir_node *node)
2545 ir_node *val = get_Store_value(node);
2546 ir_mode *mode = get_irn_mode(val);
2548 if (mode_is_float(mode) && is_Const(val)) {
2551 /* we are storing a floating point constant */
2552 if (ia32_cg_config.use_sse2) {
2553 transform = !is_simple_sse_Const(val);
2555 transform = !is_simple_x87_Const(val);
2558 return gen_float_const_Store(node, val);
2560 return gen_normal_Store(node);
2564 * Transforms a Switch.
2566 * @return the created ia32 SwitchJmp node
2568 static ir_node *create_Switch(ir_node *node)
2570 ir_graph *irg = current_ir_graph;
2571 dbg_info *dbgi = get_irn_dbg_info(node);
2572 ir_node *block = be_transform_node(get_nodes_block(node));
2573 ir_node *sel = get_Cond_selector(node);
2574 ir_node *new_sel = be_transform_node(sel);
2575 int switch_min = INT_MAX;
2576 int switch_max = INT_MIN;
2577 long default_pn = get_Cond_defaultProj(node);
2579 const ir_edge_t *edge;
2581 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2583 /* determine the smallest switch case value */
2584 foreach_out_edge(node, edge) {
2585 ir_node *proj = get_edge_src_irn(edge);
2586 long pn = get_Proj_proj(proj);
2587 if(pn == default_pn)
2596 if((unsigned) (switch_max - switch_min) > 256000) {
2597 panic("Size of switch %+F bigger than 256000", node);
2600 if (switch_min != 0) {
2601 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2603 /* if smallest switch case is not 0 we need an additional sub */
2604 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2605 add_ia32_am_offs_int(new_sel, -switch_min);
2606 set_ia32_op_type(new_sel, ia32_AddrModeS);
2608 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2611 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn);
2612 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2618 * Transform a Cond node.
2620 static ir_node *gen_Cond(ir_node *node) {
2621 ir_node *block = get_nodes_block(node);
2622 ir_node *new_block = be_transform_node(block);
2623 ir_graph *irg = current_ir_graph;
2624 dbg_info *dbgi = get_irn_dbg_info(node);
2625 ir_node *sel = get_Cond_selector(node);
2626 ir_mode *sel_mode = get_irn_mode(sel);
2627 ir_node *flags = NULL;
2631 if (sel_mode != mode_b) {
2632 return create_Switch(node);
2635 /* we get flags from a Cmp */
2636 flags = get_flags_node(sel, &pnc);
2638 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2639 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2645 * Transforms a CopyB node.
2647 * @return The transformed node.
2649 static ir_node *gen_CopyB(ir_node *node) {
2650 ir_node *block = be_transform_node(get_nodes_block(node));
2651 ir_node *src = get_CopyB_src(node);
2652 ir_node *new_src = be_transform_node(src);
2653 ir_node *dst = get_CopyB_dst(node);
2654 ir_node *new_dst = be_transform_node(dst);
2655 ir_node *mem = get_CopyB_mem(node);
2656 ir_node *new_mem = be_transform_node(mem);
2657 ir_node *res = NULL;
2658 ir_graph *irg = current_ir_graph;
2659 dbg_info *dbgi = get_irn_dbg_info(node);
2660 int size = get_type_size_bytes(get_CopyB_type(node));
2663 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2664 /* then we need the size explicitly in ECX. */
2665 if (size >= 32 * 4) {
2666 rem = size & 0x3; /* size % 4 */
2669 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2670 add_irn_dep(res, get_irg_frame(irg));
2672 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2675 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2678 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2681 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2686 static ir_node *gen_be_Copy(ir_node *node)
2688 ir_node *new_node = be_duplicate_node(node);
2689 ir_mode *mode = get_irn_mode(new_node);
2691 if (mode_needs_gp_reg(mode)) {
2692 set_irn_mode(new_node, mode_Iu);
2698 static ir_node *create_Fucom(ir_node *node)
2700 ir_graph *irg = current_ir_graph;
2701 dbg_info *dbgi = get_irn_dbg_info(node);
2702 ir_node *block = get_nodes_block(node);
2703 ir_node *new_block = be_transform_node(block);
2704 ir_node *left = get_Cmp_left(node);
2705 ir_node *new_left = be_transform_node(left);
2706 ir_node *right = get_Cmp_right(node);
2710 if(ia32_cg_config.use_fucomi) {
2711 new_right = be_transform_node(right);
2712 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2714 set_ia32_commutative(new_node);
2715 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2717 if(ia32_cg_config.use_ftst && is_Const_0(right)) {
2718 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2721 new_right = be_transform_node(right);
2722 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2726 set_ia32_commutative(new_node);
2728 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2730 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2731 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2737 static ir_node *create_Ucomi(ir_node *node)
2739 ir_graph *irg = current_ir_graph;
2740 dbg_info *dbgi = get_irn_dbg_info(node);
2741 ir_node *src_block = get_nodes_block(node);
2742 ir_node *new_block = be_transform_node(src_block);
2743 ir_node *left = get_Cmp_left(node);
2744 ir_node *right = get_Cmp_right(node);
2746 ia32_address_mode_t am;
2747 ia32_address_t *addr = &am.addr;
2749 match_arguments(&am, src_block, left, right, NULL,
2750 match_commutative | match_am);
2752 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2753 addr->mem, am.new_op1, am.new_op2,
2755 set_am_attributes(new_node, &am);
2757 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2759 new_node = fix_mem_proj(new_node, &am);
2765 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2766 * to fold an and into a test node
2768 static int can_fold_test_and(ir_node *node)
2770 const ir_edge_t *edge;
2772 /** we can only have eq and lg projs */
2773 foreach_out_edge(node, edge) {
2774 ir_node *proj = get_edge_src_irn(edge);
2775 pn_Cmp pnc = get_Proj_proj(proj);
2776 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2784 * Generate code for a Cmp.
2786 static ir_node *gen_Cmp(ir_node *node)
2788 ir_graph *irg = current_ir_graph;
2789 dbg_info *dbgi = get_irn_dbg_info(node);
2790 ir_node *block = get_nodes_block(node);
2791 ir_node *new_block = be_transform_node(block);
2792 ir_node *left = get_Cmp_left(node);
2793 ir_node *right = get_Cmp_right(node);
2794 ir_mode *cmp_mode = get_irn_mode(left);
2796 ia32_address_mode_t am;
2797 ia32_address_t *addr = &am.addr;
2800 if(mode_is_float(cmp_mode)) {
2801 if (ia32_cg_config.use_sse2) {
2802 return create_Ucomi(node);
2804 return create_Fucom(node);
2808 assert(mode_needs_gp_reg(cmp_mode));
2810 /* we prefer the Test instruction where possible except cases where
2811 * we can use SourceAM */
2812 cmp_unsigned = !mode_is_signed(cmp_mode);
2813 if (is_Const_0(right)) {
2815 get_irn_n_edges(left) == 1 &&
2816 can_fold_test_and(node)) {
2817 /* Test(and_left, and_right) */
2818 ir_node *and_left = get_And_left(left);
2819 ir_node *and_right = get_And_right(left);
2820 ir_mode *mode = get_irn_mode(and_left);
2822 match_arguments(&am, block, and_left, and_right, NULL,
2824 match_am | match_8bit_am | match_16bit_am |
2825 match_am_and_immediates | match_immediate |
2826 match_8bit | match_16bit);
2827 if (get_mode_size_bits(mode) == 8) {
2828 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2829 addr->index, addr->mem, am.new_op1,
2830 am.new_op2, am.ins_permuted,
2833 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2834 addr->index, addr->mem, am.new_op1,
2835 am.new_op2, am.ins_permuted, cmp_unsigned);
2838 match_arguments(&am, block, NULL, left, NULL,
2839 match_am | match_8bit_am | match_16bit_am |
2840 match_8bit | match_16bit);
2841 if (am.op_type == ia32_AddrModeS) {
2843 ir_node *imm_zero = try_create_Immediate(right, 0);
2844 if (get_mode_size_bits(cmp_mode) == 8) {
2845 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2846 addr->index, addr->mem, am.new_op2,
2847 imm_zero, am.ins_permuted,
2850 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2851 addr->index, addr->mem, am.new_op2,
2852 imm_zero, am.ins_permuted, cmp_unsigned);
2855 /* Test(left, left) */
2856 if (get_mode_size_bits(cmp_mode) == 8) {
2857 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2858 addr->index, addr->mem, am.new_op2,
2859 am.new_op2, am.ins_permuted,
2862 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2863 addr->index, addr->mem, am.new_op2,
2864 am.new_op2, am.ins_permuted,
2870 /* Cmp(left, right) */
2871 match_arguments(&am, block, left, right, NULL,
2872 match_commutative | match_am | match_8bit_am |
2873 match_16bit_am | match_am_and_immediates |
2874 match_immediate | match_8bit | match_16bit);
2875 if (get_mode_size_bits(cmp_mode) == 8) {
2876 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2877 addr->index, addr->mem, am.new_op1,
2878 am.new_op2, am.ins_permuted,
2881 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2882 addr->index, addr->mem, am.new_op1,
2883 am.new_op2, am.ins_permuted, cmp_unsigned);
2886 set_am_attributes(new_node, &am);
2887 assert(cmp_mode != NULL);
2888 set_ia32_ls_mode(new_node, cmp_mode);
2890 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2892 new_node = fix_mem_proj(new_node, &am);
2897 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2900 ir_graph *irg = current_ir_graph;
2901 dbg_info *dbgi = get_irn_dbg_info(node);
2902 ir_node *block = get_nodes_block(node);
2903 ir_node *new_block = be_transform_node(block);
2904 ir_node *val_true = get_Psi_val(node, 0);
2905 ir_node *val_false = get_Psi_default(node);
2907 match_flags_t match_flags;
2908 ia32_address_mode_t am;
2909 ia32_address_t *addr;
2911 assert(ia32_cg_config.use_cmov);
2912 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2916 match_flags = match_commutative | match_am | match_16bit_am |
2919 match_arguments(&am, block, val_false, val_true, flags, match_flags);
2921 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2922 addr->mem, am.new_op1, am.new_op2, new_flags,
2923 am.ins_permuted, pnc);
2924 set_am_attributes(new_node, &am);
2926 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2928 new_node = fix_mem_proj(new_node, &am);
2935 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2936 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2939 ir_graph *irg = current_ir_graph;
2940 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2941 ir_node *nomem = new_NoMem();
2942 ir_mode *mode = get_irn_mode(orig_node);
2945 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2946 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2948 /* we might need to conv the result up */
2949 if(get_mode_size_bits(mode) > 8) {
2950 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2951 nomem, new_node, mode_Bu);
2952 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2959 * Transforms a Psi node into CMov.
2961 * @return The transformed node.
2963 static ir_node *gen_Psi(ir_node *node)
2965 dbg_info *dbgi = get_irn_dbg_info(node);
2966 ir_node *block = get_nodes_block(node);
2967 ir_node *new_block = be_transform_node(block);
2968 ir_node *psi_true = get_Psi_val(node, 0);
2969 ir_node *psi_default = get_Psi_default(node);
2970 ir_node *cond = get_Psi_cond(node, 0);
2971 ir_node *flags = NULL;
2975 assert(get_Psi_n_conds(node) == 1);
2976 assert(get_irn_mode(cond) == mode_b);
2977 assert(mode_needs_gp_reg(get_irn_mode(node)));
2979 flags = get_flags_node(cond, &pnc);
2981 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2982 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2983 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2984 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2986 new_node = create_CMov(node, cond, flags, pnc);
2993 * Create a conversion from x87 state register to general purpose.
2995 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2996 ir_node *block = be_transform_node(get_nodes_block(node));
2997 ir_node *op = get_Conv_op(node);
2998 ir_node *new_op = be_transform_node(op);
2999 ia32_code_gen_t *cg = env_cg;
3000 ir_graph *irg = current_ir_graph;
3001 dbg_info *dbgi = get_irn_dbg_info(node);
3002 ir_node *noreg = ia32_new_NoReg_gp(cg);
3003 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
3004 ir_mode *mode = get_irn_mode(node);
3005 ir_node *fist, *load;
3008 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
3009 new_NoMem(), new_op, trunc_mode);
3011 set_irn_pinned(fist, op_pin_state_floats);
3012 set_ia32_use_frame(fist);
3013 set_ia32_op_type(fist, ia32_AddrModeD);
3015 assert(get_mode_size_bits(mode) <= 32);
3016 /* exception we can only store signed 32 bit integers, so for unsigned
3017 we store a 64bit (signed) integer and load the lower bits */
3018 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3019 set_ia32_ls_mode(fist, mode_Ls);
3021 set_ia32_ls_mode(fist, mode_Is);
3023 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
3026 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
3028 set_irn_pinned(load, op_pin_state_floats);
3029 set_ia32_use_frame(load);
3030 set_ia32_op_type(load, ia32_AddrModeS);
3031 set_ia32_ls_mode(load, mode_Is);
3032 if(get_ia32_ls_mode(fist) == mode_Ls) {
3033 ia32_attr_t *attr = get_ia32_attr(load);
3034 attr->data.need_64bit_stackent = 1;
3036 ia32_attr_t *attr = get_ia32_attr(load);
3037 attr->data.need_32bit_stackent = 1;
3039 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
3041 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
3045 * Creates a x87 strict Conv by placing a Sore and a Load
3047 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3049 ir_node *block = get_nodes_block(node);
3050 ir_graph *irg = current_ir_graph;
3051 dbg_info *dbgi = get_irn_dbg_info(node);
3052 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3053 ir_node *nomem = new_NoMem();
3054 ir_node *frame = get_irg_frame(irg);
3055 ir_node *store, *load;
3058 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
3060 set_ia32_use_frame(store);
3061 set_ia32_op_type(store, ia32_AddrModeD);
3062 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
3064 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
3066 set_ia32_use_frame(load);
3067 set_ia32_op_type(load, ia32_AddrModeS);
3068 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
3070 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
3075 * Create a conversion from general purpose to x87 register
3077 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
3078 ir_node *src_block = get_nodes_block(node);
3079 ir_node *block = be_transform_node(src_block);
3080 ir_graph *irg = current_ir_graph;
3081 dbg_info *dbgi = get_irn_dbg_info(node);
3082 ir_node *op = get_Conv_op(node);
3083 ir_node *new_op = NULL;
3087 ir_mode *store_mode;
3093 /* fild can use source AM if the operand is a signed 32bit integer */
3094 if (src_mode == mode_Is) {
3095 ia32_address_mode_t am;
3097 match_arguments(&am, src_block, NULL, op, NULL,
3098 match_am | match_try_am);
3099 if (am.op_type == ia32_AddrModeS) {
3100 ia32_address_t *addr = &am.addr;
3102 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
3103 addr->index, addr->mem);
3104 new_node = new_r_Proj(irg, block, fild, mode_vfp,
3107 set_am_attributes(fild, &am);
3108 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
3110 fix_mem_proj(fild, &am);
3115 if(new_op == NULL) {
3116 new_op = be_transform_node(op);
3119 noreg = ia32_new_NoReg_gp(env_cg);
3120 nomem = new_NoMem();
3121 mode = get_irn_mode(op);
3123 /* first convert to 32 bit signed if necessary */
3124 src_bits = get_mode_size_bits(src_mode);
3125 if (src_bits == 8) {
3126 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
3128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3130 } else if (src_bits < 32) {
3131 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
3133 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3137 assert(get_mode_size_bits(mode) == 32);
3140 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
3143 set_ia32_use_frame(store);
3144 set_ia32_op_type(store, ia32_AddrModeD);
3145 set_ia32_ls_mode(store, mode_Iu);
3147 /* exception for 32bit unsigned, do a 64bit spill+load */
3148 if(!mode_is_signed(mode)) {
3151 ir_node *zero_const = create_Immediate(NULL, 0, 0);
3153 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
3154 get_irg_frame(irg), noreg, nomem,
3157 set_ia32_use_frame(zero_store);
3158 set_ia32_op_type(zero_store, ia32_AddrModeD);
3159 add_ia32_am_offs_int(zero_store, 4);
3160 set_ia32_ls_mode(zero_store, mode_Iu);
3165 store = new_rd_Sync(dbgi, irg, block, 2, in);
3166 store_mode = mode_Ls;
3168 store_mode = mode_Is;
3172 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
3174 set_ia32_use_frame(fild);
3175 set_ia32_op_type(fild, ia32_AddrModeS);
3176 set_ia32_ls_mode(fild, store_mode);
3178 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
3184 * Create a conversion from one integer mode into another one
3186 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3187 dbg_info *dbgi, ir_node *block, ir_node *op,
3190 ir_graph *irg = current_ir_graph;
3191 int src_bits = get_mode_size_bits(src_mode);
3192 int tgt_bits = get_mode_size_bits(tgt_mode);
3193 ir_node *new_block = be_transform_node(block);
3195 ir_mode *smaller_mode;
3197 ia32_address_mode_t am;
3198 ia32_address_t *addr = &am.addr;
3201 if (src_bits < tgt_bits) {
3202 smaller_mode = src_mode;
3203 smaller_bits = src_bits;
3205 smaller_mode = tgt_mode;
3206 smaller_bits = tgt_bits;
3209 #ifdef DEBUG_libfirm
3211 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3216 match_arguments(&am, block, NULL, op, NULL,
3217 match_8bit | match_16bit |
3218 match_am | match_8bit_am | match_16bit_am);
3219 if (smaller_bits == 8) {
3220 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
3221 addr->index, addr->mem, am.new_op2,
3224 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
3225 addr->index, addr->mem, am.new_op2,
3228 set_am_attributes(new_node, &am);
3229 /* match_arguments assume that out-mode = in-mode, this isn't true here
3231 set_ia32_ls_mode(new_node, smaller_mode);
3232 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3233 new_node = fix_mem_proj(new_node, &am);
3238 * Transforms a Conv node.
3240 * @return The created ia32 Conv node
3242 static ir_node *gen_Conv(ir_node *node) {
3243 ir_node *block = get_nodes_block(node);
3244 ir_node *new_block = be_transform_node(block);
3245 ir_node *op = get_Conv_op(node);
3246 ir_node *new_op = NULL;
3247 ir_graph *irg = current_ir_graph;
3248 dbg_info *dbgi = get_irn_dbg_info(node);
3249 ir_mode *src_mode = get_irn_mode(op);
3250 ir_mode *tgt_mode = get_irn_mode(node);
3251 int src_bits = get_mode_size_bits(src_mode);
3252 int tgt_bits = get_mode_size_bits(tgt_mode);
3253 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3254 ir_node *nomem = new_rd_NoMem(irg);
3255 ir_node *res = NULL;
3257 if (src_mode == mode_b) {
3258 assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode));
3259 /* nothing to do, we already model bools as 0/1 ints */
3260 return be_transform_node(op);
3263 if (src_mode == tgt_mode) {
3264 if (get_Conv_strict(node)) {
3265 if (ia32_cg_config.use_sse2) {
3266 /* when we are in SSE mode, we can kill all strict no-op conversion */
3267 return be_transform_node(op);
3270 /* this should be optimized already, but who knows... */
3271 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
3272 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3273 return be_transform_node(op);
3277 if (mode_is_float(src_mode)) {
3278 new_op = be_transform_node(op);
3279 /* we convert from float ... */
3280 if (mode_is_float(tgt_mode)) {
3281 if(src_mode == mode_E && tgt_mode == mode_D
3282 && !get_Conv_strict(node)) {
3283 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3288 if (ia32_cg_config.use_sse2) {
3289 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3290 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3292 set_ia32_ls_mode(res, tgt_mode);
3294 if(get_Conv_strict(node)) {
3295 res = gen_x87_strict_conv(tgt_mode, new_op);
3296 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3299 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3304 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3305 if (ia32_cg_config.use_sse2) {
3306 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3308 set_ia32_ls_mode(res, src_mode);
3310 return gen_x87_fp_to_gp(node);
3314 /* we convert from int ... */
3315 if (mode_is_float(tgt_mode)) {
3317 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3318 if (ia32_cg_config.use_sse2) {
3319 new_op = be_transform_node(op);
3320 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3322 set_ia32_ls_mode(res, tgt_mode);
3324 res = gen_x87_gp_to_fp(node, src_mode);
3325 if(get_Conv_strict(node)) {
3326 res = gen_x87_strict_conv(tgt_mode, res);
3327 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3328 ia32_get_old_node_name(env_cg, node));
3332 } else if(tgt_mode == mode_b) {
3333 /* mode_b lowering already took care that we only have 0/1 values */
3334 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3335 src_mode, tgt_mode));
3336 return be_transform_node(op);
3339 if (src_bits == tgt_bits) {
3340 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3341 src_mode, tgt_mode));
3342 return be_transform_node(op);
3345 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3353 static int check_immediate_constraint(long val, char immediate_constraint_type)
3355 switch (immediate_constraint_type) {
3359 return val >= 0 && val <= 32;
3361 return val >= 0 && val <= 63;
3363 return val >= -128 && val <= 127;
3365 return val == 0xff || val == 0xffff;
3367 return val >= 0 && val <= 3;
3369 return val >= 0 && val <= 255;
3371 return val >= 0 && val <= 127;
3375 panic("Invalid immediate constraint found");
3379 static ir_node *try_create_Immediate(ir_node *node,
3380 char immediate_constraint_type)
3383 tarval *offset = NULL;
3384 int offset_sign = 0;
3386 ir_entity *symconst_ent = NULL;
3387 int symconst_sign = 0;
3389 ir_node *cnst = NULL;
3390 ir_node *symconst = NULL;
3393 mode = get_irn_mode(node);
3394 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3398 if(is_Minus(node)) {
3400 node = get_Minus_op(node);
3403 if(is_Const(node)) {
3406 offset_sign = minus;
3407 } else if(is_SymConst(node)) {
3410 symconst_sign = minus;
3411 } else if(is_Add(node)) {
3412 ir_node *left = get_Add_left(node);
3413 ir_node *right = get_Add_right(node);
3414 if(is_Const(left) && is_SymConst(right)) {
3417 symconst_sign = minus;
3418 offset_sign = minus;
3419 } else if(is_SymConst(left) && is_Const(right)) {
3422 symconst_sign = minus;
3423 offset_sign = minus;
3425 } else if(is_Sub(node)) {
3426 ir_node *left = get_Sub_left(node);
3427 ir_node *right = get_Sub_right(node);
3428 if(is_Const(left) && is_SymConst(right)) {
3431 symconst_sign = !minus;
3432 offset_sign = minus;
3433 } else if(is_SymConst(left) && is_Const(right)) {
3436 symconst_sign = minus;
3437 offset_sign = !minus;
3444 offset = get_Const_tarval(cnst);
3445 if(tarval_is_long(offset)) {
3446 val = get_tarval_long(offset);
3448 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3453 if(!check_immediate_constraint(val, immediate_constraint_type))
3456 if(symconst != NULL) {
3457 if(immediate_constraint_type != 0) {
3458 /* we need full 32bits for symconsts */
3462 /* unfortunately the assembler/linker doesn't support -symconst */
3466 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3468 symconst_ent = get_SymConst_entity(symconst);
3470 if(cnst == NULL && symconst == NULL)
3473 if(offset_sign && offset != NULL) {
3474 offset = tarval_neg(offset);
3477 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3482 static ir_node *create_immediate_or_transform(ir_node *node,
3483 char immediate_constraint_type)
3485 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3486 if (new_node == NULL) {
3487 new_node = be_transform_node(node);
3492 static const arch_register_req_t no_register_req = {
3493 arch_register_req_type_none,
3494 NULL, /* regclass */
3495 NULL, /* limit bitset */
3497 0 /* different pos */
3501 * An assembler constraint.
3503 typedef struct constraint_t constraint_t;
3504 struct constraint_t {
3507 const arch_register_req_t **out_reqs;
3509 const arch_register_req_t *req;
3510 unsigned immediate_possible;
3511 char immediate_type;
3514 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3516 int immediate_possible = 0;
3517 char immediate_type = 0;
3518 unsigned limited = 0;
3519 const arch_register_class_t *cls = NULL;
3520 ir_graph *irg = current_ir_graph;
3521 struct obstack *obst = get_irg_obstack(irg);
3522 arch_register_req_t *req;
3523 unsigned *limited_ptr = NULL;
3527 /* TODO: replace all the asserts with nice error messages */
3530 /* a memory constraint: no need to do anything in backend about it
3531 * (the dependencies are already respected by the memory edge of
3533 constraint->req = &no_register_req;
3545 assert(cls == NULL ||
3546 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3547 cls = &ia32_reg_classes[CLASS_ia32_gp];
3548 limited |= 1 << REG_EAX;
3551 assert(cls == NULL ||
3552 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3553 cls = &ia32_reg_classes[CLASS_ia32_gp];
3554 limited |= 1 << REG_EBX;
3557 assert(cls == NULL ||
3558 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3559 cls = &ia32_reg_classes[CLASS_ia32_gp];
3560 limited |= 1 << REG_ECX;
3563 assert(cls == NULL ||
3564 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3565 cls = &ia32_reg_classes[CLASS_ia32_gp];
3566 limited |= 1 << REG_EDX;
3569 assert(cls == NULL ||
3570 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3571 cls = &ia32_reg_classes[CLASS_ia32_gp];
3572 limited |= 1 << REG_EDI;
3575 assert(cls == NULL ||
3576 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3577 cls = &ia32_reg_classes[CLASS_ia32_gp];
3578 limited |= 1 << REG_ESI;
3581 case 'q': /* q means lower part of the regs only, this makes no
3582 * difference to Q for us (we only assigne whole registers) */
3583 assert(cls == NULL ||
3584 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3585 cls = &ia32_reg_classes[CLASS_ia32_gp];
3586 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3590 assert(cls == NULL ||
3591 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3592 cls = &ia32_reg_classes[CLASS_ia32_gp];
3593 limited |= 1 << REG_EAX | 1 << REG_EDX;
3596 assert(cls == NULL ||
3597 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3598 cls = &ia32_reg_classes[CLASS_ia32_gp];
3599 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3600 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3607 assert(cls == NULL);
3608 cls = &ia32_reg_classes[CLASS_ia32_gp];
3614 /* TODO: mark values so the x87 simulator knows about t and u */
3615 assert(cls == NULL);
3616 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3621 assert(cls == NULL);
3622 /* TODO: check that sse2 is supported */
3623 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3633 assert(!immediate_possible);
3634 immediate_possible = 1;
3635 immediate_type = *c;
3639 assert(!immediate_possible);
3640 immediate_possible = 1;
3644 assert(!immediate_possible && cls == NULL);
3645 immediate_possible = 1;
3646 cls = &ia32_reg_classes[CLASS_ia32_gp];
3659 assert(constraint->is_in && "can only specify same constraint "
3662 sscanf(c, "%d%n", &same_as, &p);
3670 /* memory constraint no need to do anything in backend about it
3671 * (the dependencies are already respected by the memory edge of
3673 constraint->req = &no_register_req;
3676 case 'E': /* no float consts yet */
3677 case 'F': /* no float consts yet */
3678 case 's': /* makes no sense on x86 */
3679 case 'X': /* we can't support that in firm */
3682 case '<': /* no autodecrement on x86 */
3683 case '>': /* no autoincrement on x86 */
3684 case 'C': /* sse constant not supported yet */
3685 case 'G': /* 80387 constant not supported yet */
3686 case 'y': /* we don't support mmx registers yet */
3687 case 'Z': /* not available in 32 bit mode */
3688 case 'e': /* not available in 32 bit mode */
3689 panic("unsupported asm constraint '%c' found in (%+F)",
3690 *c, current_ir_graph);
3693 panic("unknown asm constraint '%c' found in (%+F)", *c,
3701 const arch_register_req_t *other_constr;
3703 assert(cls == NULL && "same as and register constraint not supported");
3704 assert(!immediate_possible && "same as and immediate constraint not "
3706 assert(same_as < constraint->n_outs && "wrong constraint number in "
3707 "same_as constraint");
3709 other_constr = constraint->out_reqs[same_as];
3711 req = obstack_alloc(obst, sizeof(req[0]));
3712 req->cls = other_constr->cls;
3713 req->type = arch_register_req_type_should_be_same;
3714 req->limited = NULL;
3715 req->other_same = 1U << pos;
3716 req->other_different = 0;
3718 /* switch constraints. This is because in firm we have same_as
3719 * constraints on the output constraints while in the gcc asm syntax
3720 * they are specified on the input constraints */
3721 constraint->req = other_constr;
3722 constraint->out_reqs[same_as] = req;
3723 constraint->immediate_possible = 0;
3727 if(immediate_possible && cls == NULL) {
3728 cls = &ia32_reg_classes[CLASS_ia32_gp];
3730 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3731 assert(cls != NULL);
3733 if(immediate_possible) {
3734 assert(constraint->is_in
3735 && "immediate make no sense for output constraints");
3737 /* todo: check types (no float input on 'r' constrained in and such... */
3740 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3741 limited_ptr = (unsigned*) (req+1);
3743 req = obstack_alloc(obst, sizeof(req[0]));
3745 memset(req, 0, sizeof(req[0]));
3748 req->type = arch_register_req_type_limited;
3749 *limited_ptr = limited;
3750 req->limited = limited_ptr;
3752 req->type = arch_register_req_type_normal;
3756 constraint->req = req;
3757 constraint->immediate_possible = immediate_possible;
3758 constraint->immediate_type = immediate_type;
3761 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3762 const char *clobber)
3764 ir_graph *irg = get_irn_irg(node);
3765 struct obstack *obst = get_irg_obstack(irg);
3766 const arch_register_t *reg = NULL;
3769 arch_register_req_t *req;
3770 const arch_register_class_t *cls;
3775 /* TODO: construct a hashmap instead of doing linear search for clobber
3777 for(c = 0; c < N_CLASSES; ++c) {
3778 cls = & ia32_reg_classes[c];
3779 for(r = 0; r < cls->n_regs; ++r) {
3780 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
3781 if(strcmp(temp_reg->name, clobber) == 0
3782 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
3791 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
3795 assert(reg->index < 32);
3797 limited = obstack_alloc(obst, sizeof(limited[0]));
3798 *limited = 1 << reg->index;
3800 req = obstack_alloc(obst, sizeof(req[0]));
3801 memset(req, 0, sizeof(req[0]));
3802 req->type = arch_register_req_type_limited;
3804 req->limited = limited;
3806 constraint->req = req;
3807 constraint->immediate_possible = 0;
3808 constraint->immediate_type = 0;
3811 static int is_memory_op(const ir_asm_constraint *constraint)
3813 ident *id = constraint->constraint;
3814 const char *str = get_id_str(id);
3817 for(c = str; *c != '\0'; ++c) {
3826 * generates code for a ASM node
3828 static ir_node *gen_ASM(ir_node *node)
3831 ir_graph *irg = current_ir_graph;
3832 ir_node *block = get_nodes_block(node);
3833 ir_node *new_block = be_transform_node(block);
3834 dbg_info *dbgi = get_irn_dbg_info(node);
3838 int n_out_constraints;
3840 const arch_register_req_t **out_reg_reqs;
3841 const arch_register_req_t **in_reg_reqs;
3842 ia32_asm_reg_t *register_map;
3843 unsigned reg_map_size = 0;
3844 struct obstack *obst;
3845 const ir_asm_constraint *in_constraints;
3846 const ir_asm_constraint *out_constraints;
3848 constraint_t parsed_constraint;
3850 arity = get_irn_arity(node);
3851 in = alloca(arity * sizeof(in[0]));
3852 memset(in, 0, arity * sizeof(in[0]));
3854 n_out_constraints = get_ASM_n_output_constraints(node);
3855 n_clobbers = get_ASM_n_clobbers(node);
3856 out_arity = n_out_constraints + n_clobbers;
3857 /* hack to keep space for mem proj */
3861 in_constraints = get_ASM_input_constraints(node);
3862 out_constraints = get_ASM_output_constraints(node);
3863 clobbers = get_ASM_clobbers(node);
3865 /* construct output constraints */
3866 obst = get_irg_obstack(irg);
3867 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3868 parsed_constraint.out_reqs = out_reg_reqs;
3869 parsed_constraint.n_outs = n_out_constraints;
3870 parsed_constraint.is_in = 0;
3872 for(i = 0; i < out_arity; ++i) {
3875 if(i < n_out_constraints) {
3876 const ir_asm_constraint *constraint = &out_constraints[i];
3877 c = get_id_str(constraint->constraint);
3878 parse_asm_constraint(i, &parsed_constraint, c);
3880 if(constraint->pos > reg_map_size)
3881 reg_map_size = constraint->pos;
3883 out_reg_reqs[i] = parsed_constraint.req;
3884 } else if(i < out_arity - 1) {
3885 ident *glob_id = clobbers [i - n_out_constraints];
3886 assert(glob_id != NULL);
3887 c = get_id_str(glob_id);
3888 parse_clobber(node, i, &parsed_constraint, c);
3890 out_reg_reqs[i+1] = parsed_constraint.req;
3894 out_reg_reqs[n_out_constraints] = &no_register_req;
3896 /* construct input constraints */
3897 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3898 parsed_constraint.is_in = 1;
3899 for(i = 0; i < arity; ++i) {
3900 const ir_asm_constraint *constraint = &in_constraints[i];
3901 ident *constr_id = constraint->constraint;
3902 const char *c = get_id_str(constr_id);
3904 parse_asm_constraint(i, &parsed_constraint, c);
3905 in_reg_reqs[i] = parsed_constraint.req;
3907 if(constraint->pos > reg_map_size)
3908 reg_map_size = constraint->pos;
3910 if(parsed_constraint.immediate_possible) {
3911 ir_node *pred = get_irn_n(node, i);
3912 char imm_type = parsed_constraint.immediate_type;
3913 ir_node *immediate = try_create_Immediate(pred, imm_type);
3915 if(immediate != NULL) {
3922 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3923 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3925 for(i = 0; i < n_out_constraints; ++i) {
3926 const ir_asm_constraint *constraint = &out_constraints[i];
3927 unsigned pos = constraint->pos;
3929 assert(pos < reg_map_size);
3930 register_map[pos].use_input = 0;
3931 register_map[pos].valid = 1;
3932 register_map[pos].memory = is_memory_op(constraint);
3933 register_map[pos].inout_pos = i;
3934 register_map[pos].mode = constraint->mode;
3937 /* transform inputs */
3938 for(i = 0; i < arity; ++i) {
3939 const ir_asm_constraint *constraint = &in_constraints[i];
3940 unsigned pos = constraint->pos;
3941 ir_node *pred = get_irn_n(node, i);
3942 ir_node *transformed;
3944 assert(pos < reg_map_size);
3945 register_map[pos].use_input = 1;
3946 register_map[pos].valid = 1;
3947 register_map[pos].memory = is_memory_op(constraint);
3948 register_map[pos].inout_pos = i;
3949 register_map[pos].mode = constraint->mode;
3954 transformed = be_transform_node(pred);
3955 in[i] = transformed;
3958 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3959 get_ASM_text(node), register_map);
3961 set_ia32_out_req_all(new_node, out_reg_reqs);
3962 set_ia32_in_req_all(new_node, in_reg_reqs);
3964 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3970 * Transforms a FrameAddr into an ia32 Add.
3972 static ir_node *gen_be_FrameAddr(ir_node *node) {
3973 ir_node *block = be_transform_node(get_nodes_block(node));
3974 ir_node *op = be_get_FrameAddr_frame(node);
3975 ir_node *new_op = be_transform_node(op);
3976 ir_graph *irg = current_ir_graph;
3977 dbg_info *dbgi = get_irn_dbg_info(node);
3978 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3981 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3982 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3983 set_ia32_use_frame(new_node);
3985 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3991 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3993 static ir_node *gen_be_Return(ir_node *node) {
3994 ir_graph *irg = current_ir_graph;
3995 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3996 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3997 ir_entity *ent = get_irg_entity(irg);
3998 ir_type *tp = get_entity_type(ent);
4003 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
4004 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
4007 int pn_ret_val, pn_ret_mem, arity, i;
4009 assert(ret_val != NULL);
4010 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
4011 return be_duplicate_node(node);
4014 res_type = get_method_res_type(tp, 0);
4016 if (! is_Primitive_type(res_type)) {
4017 return be_duplicate_node(node);
4020 mode = get_type_mode(res_type);
4021 if (! mode_is_float(mode)) {
4022 return be_duplicate_node(node);
4025 assert(get_method_n_ress(tp) == 1);
4027 pn_ret_val = get_Proj_proj(ret_val);
4028 pn_ret_mem = get_Proj_proj(ret_mem);
4030 /* get the Barrier */
4031 barrier = get_Proj_pred(ret_val);
4033 /* get result input of the Barrier */
4034 ret_val = get_irn_n(barrier, pn_ret_val);
4035 new_ret_val = be_transform_node(ret_val);
4037 /* get memory input of the Barrier */
4038 ret_mem = get_irn_n(barrier, pn_ret_mem);
4039 new_ret_mem = be_transform_node(ret_mem);
4041 frame = get_irg_frame(irg);
4043 dbgi = get_irn_dbg_info(barrier);
4044 block = be_transform_node(get_nodes_block(barrier));
4046 noreg = ia32_new_NoReg_gp(env_cg);
4048 /* store xmm0 onto stack */
4049 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
4050 new_ret_mem, new_ret_val);
4051 set_ia32_ls_mode(sse_store, mode);
4052 set_ia32_op_type(sse_store, ia32_AddrModeD);
4053 set_ia32_use_frame(sse_store);
4055 /* load into x87 register */
4056 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
4057 set_ia32_op_type(fld, ia32_AddrModeS);
4058 set_ia32_use_frame(fld);
4060 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
4061 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
4063 /* create a new barrier */
4064 arity = get_irn_arity(barrier);
4065 in = alloca(arity * sizeof(in[0]));
4066 for (i = 0; i < arity; ++i) {
4069 if (i == pn_ret_val) {
4071 } else if (i == pn_ret_mem) {
4074 ir_node *in = get_irn_n(barrier, i);
4075 new_in = be_transform_node(in);
4080 new_barrier = new_ir_node(dbgi, irg, block,
4081 get_irn_op(barrier), get_irn_mode(barrier),
4083 copy_node_attr(barrier, new_barrier);
4084 be_duplicate_deps(barrier, new_barrier);
4085 be_set_transformed_node(barrier, new_barrier);
4086 mark_irn_visited(barrier);
4088 /* transform normally */
4089 return be_duplicate_node(node);
4093 * Transform a be_AddSP into an ia32_SubSP.
4095 static ir_node *gen_be_AddSP(ir_node *node)
4097 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
4098 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
4100 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
4104 * Transform a be_SubSP into an ia32_AddSP
4106 static ir_node *gen_be_SubSP(ir_node *node)
4108 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
4109 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
4111 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
4115 * This function just sets the register for the Unknown node
4116 * as this is not done during register allocation because Unknown
4117 * is an "ignore" node.
4119 static ir_node *gen_Unknown(ir_node *node) {
4120 ir_mode *mode = get_irn_mode(node);
4122 if (mode_is_float(mode)) {
4123 if (ia32_cg_config.use_sse2) {
4124 return ia32_new_Unknown_xmm(env_cg);
4126 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
4127 ir_graph *irg = current_ir_graph;
4128 dbg_info *dbgi = get_irn_dbg_info(node);
4129 ir_node *block = get_irg_start_block(irg);
4130 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
4132 /* Const Nodes before the initial IncSP are a bad idea, because
4133 * they could be spilled and we have no SP ready at that point yet.
4134 * So add a dependency to the initial frame pointer calculation to
4135 * avoid that situation.
4137 add_irn_dep(ret, get_irg_frame(irg));
4140 } else if (mode_needs_gp_reg(mode)) {
4141 return ia32_new_Unknown_gp(env_cg);
4143 panic("unsupported Unknown-Mode");
4149 * Change some phi modes
4151 static ir_node *gen_Phi(ir_node *node) {
4152 ir_node *block = be_transform_node(get_nodes_block(node));
4153 ir_graph *irg = current_ir_graph;
4154 dbg_info *dbgi = get_irn_dbg_info(node);
4155 ir_mode *mode = get_irn_mode(node);
4158 if(mode_needs_gp_reg(mode)) {
4159 /* we shouldn't have any 64bit stuff around anymore */
4160 assert(get_mode_size_bits(mode) <= 32);
4161 /* all integer operations are on 32bit registers now */
4163 } else if(mode_is_float(mode)) {
4164 if (ia32_cg_config.use_sse2) {
4171 /* phi nodes allow loops, so we use the old arguments for now
4172 * and fix this later */
4173 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
4174 get_irn_in(node) + 1);
4175 copy_node_attr(node, phi);
4176 be_duplicate_deps(node, phi);
4178 be_set_transformed_node(node, phi);
4179 be_enqueue_preds(node);
4187 static ir_node *gen_IJmp(ir_node *node)
4189 ir_node *block = get_nodes_block(node);
4190 ir_node *new_block = be_transform_node(block);
4191 ir_graph *irg = current_ir_graph;
4192 dbg_info *dbgi = get_irn_dbg_info(node);
4193 ir_node *op = get_IJmp_target(node);
4195 ia32_address_mode_t am;
4196 ia32_address_t *addr = &am.addr;
4198 assert(get_irn_mode(op) == mode_P);
4200 match_arguments(&am, block, NULL, op, NULL,
4201 match_am | match_8bit_am | match_16bit_am |
4202 match_immediate | match_8bit | match_16bit);
4204 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
4205 addr->mem, am.new_op2);
4206 set_am_attributes(new_node, &am);
4207 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4209 new_node = fix_mem_proj(new_node, &am);
4214 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
4217 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
4218 ir_node *val, ir_node *mem);
4221 * Transforms a lowered Load into a "real" one.
4223 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
4225 ir_node *block = be_transform_node(get_nodes_block(node));
4226 ir_node *ptr = get_irn_n(node, 0);
4227 ir_node *new_ptr = be_transform_node(ptr);
4228 ir_node *mem = get_irn_n(node, 1);
4229 ir_node *new_mem = be_transform_node(mem);
4230 ir_graph *irg = current_ir_graph;
4231 dbg_info *dbgi = get_irn_dbg_info(node);
4232 ir_mode *mode = get_ia32_ls_mode(node);
4233 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4236 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
4238 set_ia32_op_type(new_op, ia32_AddrModeS);
4239 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
4240 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
4241 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
4242 if (is_ia32_am_sc_sign(node))
4243 set_ia32_am_sc_sign(new_op);
4244 set_ia32_ls_mode(new_op, mode);
4245 if (is_ia32_use_frame(node)) {
4246 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4247 set_ia32_use_frame(new_op);
4250 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4256 * Transforms a lowered Store into a "real" one.
4258 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
4260 ir_node *block = be_transform_node(get_nodes_block(node));
4261 ir_node *ptr = get_irn_n(node, 0);
4262 ir_node *new_ptr = be_transform_node(ptr);
4263 ir_node *val = get_irn_n(node, 1);
4264 ir_node *new_val = be_transform_node(val);
4265 ir_node *mem = get_irn_n(node, 2);
4266 ir_node *new_mem = be_transform_node(mem);
4267 ir_graph *irg = current_ir_graph;
4268 dbg_info *dbgi = get_irn_dbg_info(node);
4269 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4270 ir_mode *mode = get_ia32_ls_mode(node);
4274 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
4276 am_offs = get_ia32_am_offs_int(node);
4277 add_ia32_am_offs_int(new_op, am_offs);
4279 set_ia32_op_type(new_op, ia32_AddrModeD);
4280 set_ia32_ls_mode(new_op, mode);
4281 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4282 set_ia32_use_frame(new_op);
4284 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4289 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
4291 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
4292 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
4294 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
4295 match_immediate | match_mode_neutral);
4298 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
4300 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
4301 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
4302 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
4306 static ir_node *gen_ia32_l_SarDep(ir_node *node)
4308 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
4309 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
4310 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
4314 static ir_node *gen_ia32_l_Add(ir_node *node) {
4315 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4316 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4317 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
4318 match_commutative | match_am | match_immediate |
4319 match_mode_neutral);
4321 if(is_Proj(lowered)) {
4322 lowered = get_Proj_pred(lowered);
4324 assert(is_ia32_Add(lowered));
4325 set_irn_mode(lowered, mode_T);
4331 static ir_node *gen_ia32_l_Adc(ir_node *node)
4333 return gen_binop_flags(node, new_rd_ia32_Adc,
4334 match_commutative | match_am | match_immediate |
4335 match_mode_neutral);
4339 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4341 * @param node The node to transform
4342 * @return the created ia32 vfild node
4344 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4345 return gen_lowered_Load(node, new_rd_ia32_vfild);
4349 * Transforms an ia32_l_Load into a "real" ia32_Load node
4351 * @param node The node to transform
4352 * @return the created ia32 Load node
4354 static ir_node *gen_ia32_l_Load(ir_node *node) {
4355 return gen_lowered_Load(node, new_rd_ia32_Load);
4359 * Transforms an ia32_l_Store into a "real" ia32_Store node
4361 * @param node The node to transform
4362 * @return the created ia32 Store node
4364 static ir_node *gen_ia32_l_Store(ir_node *node) {
4365 return gen_lowered_Store(node, new_rd_ia32_Store);
4369 * Transforms a l_vfist into a "real" vfist node.
4371 * @param node The node to transform
4372 * @return the created ia32 vfist node
4374 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4375 ir_node *block = be_transform_node(get_nodes_block(node));
4376 ir_node *ptr = get_irn_n(node, 0);
4377 ir_node *new_ptr = be_transform_node(ptr);
4378 ir_node *val = get_irn_n(node, 1);
4379 ir_node *new_val = be_transform_node(val);
4380 ir_node *mem = get_irn_n(node, 2);
4381 ir_node *new_mem = be_transform_node(mem);
4382 ir_graph *irg = current_ir_graph;
4383 dbg_info *dbgi = get_irn_dbg_info(node);
4384 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4385 ir_mode *mode = get_ia32_ls_mode(node);
4386 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4390 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4391 new_val, trunc_mode);
4393 am_offs = get_ia32_am_offs_int(node);
4394 add_ia32_am_offs_int(new_op, am_offs);
4396 set_ia32_op_type(new_op, ia32_AddrModeD);
4397 set_ia32_ls_mode(new_op, mode);
4398 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4399 set_ia32_use_frame(new_op);
4401 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4407 * Transforms a l_MulS into a "real" MulS node.
4409 * @return the created ia32 Mul node
4411 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4412 ir_node *left = get_binop_left(node);
4413 ir_node *right = get_binop_right(node);
4415 return gen_binop(node, left, right, new_rd_ia32_Mul,
4416 match_commutative | match_am | match_mode_neutral);
4420 * Transforms a l_IMulS into a "real" IMul1OPS node.
4422 * @return the created ia32 IMul1OP node
4424 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4425 ir_node *left = get_binop_left(node);
4426 ir_node *right = get_binop_right(node);
4428 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4429 match_commutative | match_am | match_mode_neutral);
4432 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4433 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4434 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4435 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4436 match_am | match_immediate | match_mode_neutral);
4438 if(is_Proj(lowered)) {
4439 lowered = get_Proj_pred(lowered);
4441 assert(is_ia32_Sub(lowered));
4442 set_irn_mode(lowered, mode_T);
4448 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4449 return gen_binop_flags(node, new_rd_ia32_Sbb,
4450 match_am | match_immediate | match_mode_neutral);
4454 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4455 * op1 - target to be shifted
4456 * op2 - contains bits to be shifted into target
4458 * Only op3 can be an immediate.
4460 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4461 ir_node *low, ir_node *count)
4463 ir_node *block = get_nodes_block(node);
4464 ir_node *new_block = be_transform_node(block);
4465 ir_graph *irg = current_ir_graph;
4466 dbg_info *dbgi = get_irn_dbg_info(node);
4467 ir_node *new_high = be_transform_node(high);
4468 ir_node *new_low = be_transform_node(low);
4472 /* the shift amount can be any mode that is bigger than 5 bits, since all
4473 * other bits are ignored anyway */
4474 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4475 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4476 count = get_Conv_op(count);
4478 new_count = create_immediate_or_transform(count, 0);
4480 if (is_ia32_l_ShlD(node)) {
4481 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4484 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4487 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4492 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4494 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4495 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4496 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4497 return gen_lowered_64bit_shifts(node, high, low, count);
4500 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4502 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4503 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4504 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4505 return gen_lowered_64bit_shifts(node, high, low, count);
4508 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) {
4509 ir_node *src_block = get_nodes_block(node);
4510 ir_node *block = be_transform_node(src_block);
4511 ir_graph *irg = current_ir_graph;
4512 dbg_info *dbgi = get_irn_dbg_info(node);
4513 ir_node *frame = get_irg_frame(irg);
4514 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4515 ir_node *nomem = new_NoMem();
4516 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4517 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4518 ir_node *new_val_low = be_transform_node(val_low);
4519 ir_node *new_val_high = be_transform_node(val_high);
4524 ir_node *store_high;
4526 if(!mode_is_signed(get_irn_mode(val_high))) {
4527 panic("unsigned long long -> float not supported yet (%+F)", node);
4531 store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
4533 store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
4535 SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node));
4536 SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node));
4538 set_ia32_use_frame(store_low);
4539 set_ia32_use_frame(store_high);
4540 set_ia32_op_type(store_low, ia32_AddrModeD);
4541 set_ia32_op_type(store_high, ia32_AddrModeD);
4542 set_ia32_ls_mode(store_low, mode_Iu);
4543 set_ia32_ls_mode(store_high, mode_Is);
4544 add_ia32_am_offs_int(store_high, 4);
4548 sync = new_rd_Sync(dbgi, irg, block, 2, in);
4551 fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync);
4553 set_ia32_use_frame(fild);
4554 set_ia32_op_type(fild, ia32_AddrModeS);
4555 set_ia32_ls_mode(fild, mode_Ls);
4557 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
4559 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
4562 static ir_node *gen_ia32_l_FloattoLL(ir_node *node) {
4563 ir_node *src_block = get_nodes_block(node);
4564 ir_node *block = be_transform_node(src_block);
4565 ir_graph *irg = current_ir_graph;
4566 dbg_info *dbgi = get_irn_dbg_info(node);
4567 ir_node *frame = get_irg_frame(irg);
4568 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4569 ir_node *nomem = new_NoMem();
4570 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4571 ir_node *new_val = be_transform_node(val);
4572 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4577 fist = new_rd_ia32_vfist(dbgi, irg, block, frame, noreg, nomem, new_val,
4579 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
4580 set_ia32_use_frame(fist);
4581 set_ia32_op_type(fist, ia32_AddrModeD);
4582 set_ia32_ls_mode(fist, mode_Ls);
4588 * the BAD transformer.
4590 static ir_node *bad_transform(ir_node *node) {
4591 panic("No transform function for %+F available.\n", node);
4595 static ir_node *gen_Proj_l_FloattoLL(ir_node *node) {
4596 ir_graph *irg = current_ir_graph;
4597 ir_node *block = be_transform_node(get_nodes_block(node));
4598 ir_node *pred = get_Proj_pred(node);
4599 ir_node *new_pred = be_transform_node(pred);
4600 ir_node *frame = get_irg_frame(irg);
4601 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4602 dbg_info *dbgi = get_irn_dbg_info(node);
4603 long pn = get_Proj_proj(node);
4608 load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred);
4609 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
4610 set_ia32_use_frame(load);
4611 set_ia32_op_type(load, ia32_AddrModeS);
4612 set_ia32_ls_mode(load, mode_Iu);
4613 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4614 * 32 bit from it with this particular load */
4615 attr = get_ia32_attr(load);
4616 attr->data.need_64bit_stackent = 1;
4618 if (pn == pn_ia32_l_FloattoLL_res_high) {
4619 add_ia32_am_offs_int(load, 4);
4621 assert(pn == pn_ia32_l_FloattoLL_res_low);
4624 proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
4630 * Transform the Projs of an AddSP.
4632 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4633 ir_node *block = be_transform_node(get_nodes_block(node));
4634 ir_node *pred = get_Proj_pred(node);
4635 ir_node *new_pred = be_transform_node(pred);
4636 ir_graph *irg = current_ir_graph;
4637 dbg_info *dbgi = get_irn_dbg_info(node);
4638 long proj = get_Proj_proj(node);
4640 if (proj == pn_be_AddSP_sp) {
4641 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4642 pn_ia32_SubSP_stack);
4643 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4645 } else if(proj == pn_be_AddSP_res) {
4646 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4647 pn_ia32_SubSP_addr);
4648 } else if (proj == pn_be_AddSP_M) {
4649 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4653 return new_rd_Unknown(irg, get_irn_mode(node));
4657 * Transform the Projs of a SubSP.
4659 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4660 ir_node *block = be_transform_node(get_nodes_block(node));
4661 ir_node *pred = get_Proj_pred(node);
4662 ir_node *new_pred = be_transform_node(pred);
4663 ir_graph *irg = current_ir_graph;
4664 dbg_info *dbgi = get_irn_dbg_info(node);
4665 long proj = get_Proj_proj(node);
4667 if (proj == pn_be_SubSP_sp) {
4668 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4669 pn_ia32_AddSP_stack);
4670 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4672 } else if (proj == pn_be_SubSP_M) {
4673 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4677 return new_rd_Unknown(irg, get_irn_mode(node));
4681 * Transform and renumber the Projs from a Load.
4683 static ir_node *gen_Proj_Load(ir_node *node) {
4685 ir_node *block = be_transform_node(get_nodes_block(node));
4686 ir_node *pred = get_Proj_pred(node);
4687 ir_graph *irg = current_ir_graph;
4688 dbg_info *dbgi = get_irn_dbg_info(node);
4689 long proj = get_Proj_proj(node);
4692 /* loads might be part of source address mode matches, so we don't
4693 transform the ProjMs yet (with the exception of loads whose result is
4696 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4699 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4701 /* this is needed, because sometimes we have loops that are only
4702 reachable through the ProjM */
4703 be_enqueue_preds(node);
4704 /* do it in 2 steps, to silence firm verifier */
4705 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4706 set_Proj_proj(res, pn_ia32_Load_M);
4710 /* renumber the proj */
4711 new_pred = be_transform_node(pred);
4712 if (is_ia32_Load(new_pred)) {
4715 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
4717 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
4718 case pn_Load_X_regular:
4719 return new_rd_Jmp(dbgi, irg, block);
4720 case pn_Load_X_except:
4721 /* This Load might raise an exception. Mark it. */
4722 set_ia32_exc_label(new_pred, 1);
4723 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc);
4727 } else if (is_ia32_Conv_I2I(new_pred) ||
4728 is_ia32_Conv_I2I8Bit(new_pred)) {
4729 set_irn_mode(new_pred, mode_T);
4730 if (proj == pn_Load_res) {
4731 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4732 } else if (proj == pn_Load_M) {
4733 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4735 } else if (is_ia32_xLoad(new_pred)) {
4738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
4740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
4741 case pn_Load_X_regular:
4742 return new_rd_Jmp(dbgi, irg, block);
4743 case pn_Load_X_except:
4744 /* This Load might raise an exception. Mark it. */
4745 set_ia32_exc_label(new_pred, 1);
4746 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4750 } else if (is_ia32_vfld(new_pred)) {
4753 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
4755 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
4756 case pn_Load_X_regular:
4757 return new_rd_Jmp(dbgi, irg, block);
4758 case pn_Load_X_except:
4759 /* This Load might raise an exception. Mark it. */
4760 set_ia32_exc_label(new_pred, 1);
4761 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4766 /* can happen for ProJMs when source address mode happened for the
4769 /* however it should not be the result proj, as that would mean the
4770 load had multiple users and should not have been used for
4772 if (proj != pn_Load_M) {
4773 panic("internal error: transformed node not a Load");
4775 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4779 return new_rd_Unknown(irg, get_irn_mode(node));
4783 * Transform and renumber the Projs from a DivMod like instruction.
4785 static ir_node *gen_Proj_DivMod(ir_node *node) {
4786 ir_node *block = be_transform_node(get_nodes_block(node));
4787 ir_node *pred = get_Proj_pred(node);
4788 ir_node *new_pred = be_transform_node(pred);
4789 ir_graph *irg = current_ir_graph;
4790 dbg_info *dbgi = get_irn_dbg_info(node);
4791 ir_mode *mode = get_irn_mode(node);
4792 long proj = get_Proj_proj(node);
4794 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4796 switch (get_irn_opcode(pred)) {
4800 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4802 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4803 case pn_Div_X_regular:
4804 return new_rd_Jmp(dbgi, irg, block);
4805 case pn_Div_X_except:
4806 set_ia32_exc_label(new_pred, 1);
4807 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4815 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4817 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4818 case pn_Mod_X_except:
4819 set_ia32_exc_label(new_pred, 1);
4820 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4828 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4829 case pn_DivMod_res_div:
4830 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4831 case pn_DivMod_res_mod:
4832 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4833 case pn_DivMod_X_regular:
4834 return new_rd_Jmp(dbgi, irg, block);
4835 case pn_DivMod_X_except:
4836 set_ia32_exc_label(new_pred, 1);
4837 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4847 return new_rd_Unknown(irg, mode);
4851 * Transform and renumber the Projs from a CopyB.
4853 static ir_node *gen_Proj_CopyB(ir_node *node) {
4854 ir_node *block = be_transform_node(get_nodes_block(node));
4855 ir_node *pred = get_Proj_pred(node);
4856 ir_node *new_pred = be_transform_node(pred);
4857 ir_graph *irg = current_ir_graph;
4858 dbg_info *dbgi = get_irn_dbg_info(node);
4859 ir_mode *mode = get_irn_mode(node);
4860 long proj = get_Proj_proj(node);
4863 case pn_CopyB_M_regular:
4864 if (is_ia32_CopyB_i(new_pred)) {
4865 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4866 } else if (is_ia32_CopyB(new_pred)) {
4867 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4875 return new_rd_Unknown(irg, mode);
4879 * Transform and renumber the Projs from a Quot.
4881 static ir_node *gen_Proj_Quot(ir_node *node) {
4882 ir_node *block = be_transform_node(get_nodes_block(node));
4883 ir_node *pred = get_Proj_pred(node);
4884 ir_node *new_pred = be_transform_node(pred);
4885 ir_graph *irg = current_ir_graph;
4886 dbg_info *dbgi = get_irn_dbg_info(node);
4887 ir_mode *mode = get_irn_mode(node);
4888 long proj = get_Proj_proj(node);
4892 if (is_ia32_xDiv(new_pred)) {
4893 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4894 } else if (is_ia32_vfdiv(new_pred)) {
4895 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4899 if (is_ia32_xDiv(new_pred)) {
4900 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4901 } else if (is_ia32_vfdiv(new_pred)) {
4902 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4905 case pn_Quot_X_regular:
4906 case pn_Quot_X_except:
4912 return new_rd_Unknown(irg, mode);
4916 * Transform the Thread Local Storage Proj.
4918 static ir_node *gen_Proj_tls(ir_node *node) {
4919 ir_node *block = be_transform_node(get_nodes_block(node));
4920 ir_graph *irg = current_ir_graph;
4921 dbg_info *dbgi = NULL;
4922 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4927 static ir_node *gen_be_Call(ir_node *node) {
4928 ir_node *res = be_duplicate_node(node);
4929 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4934 static ir_node *gen_be_IncSP(ir_node *node) {
4935 ir_node *res = be_duplicate_node(node);
4936 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4942 * Transform the Projs from a be_Call.
4944 static ir_node *gen_Proj_be_Call(ir_node *node) {
4945 ir_node *block = be_transform_node(get_nodes_block(node));
4946 ir_node *call = get_Proj_pred(node);
4947 ir_node *new_call = be_transform_node(call);
4948 ir_graph *irg = current_ir_graph;
4949 dbg_info *dbgi = get_irn_dbg_info(node);
4950 ir_type *method_type = be_Call_get_type(call);
4951 int n_res = get_method_n_ress(method_type);
4952 long proj = get_Proj_proj(node);
4953 ir_mode *mode = get_irn_mode(node);
4955 const arch_register_class_t *cls;
4957 /* The following is kinda tricky: If we're using SSE, then we have to
4958 * move the result value of the call in floating point registers to an
4959 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4960 * after the call, we have to make sure to correctly make the
4961 * MemProj and the result Proj use these 2 nodes
4963 if (proj == pn_be_Call_M_regular) {
4964 // get new node for result, are we doing the sse load/store hack?
4965 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4966 ir_node *call_res_new;
4967 ir_node *call_res_pred = NULL;
4969 if (call_res != NULL) {
4970 call_res_new = be_transform_node(call_res);
4971 call_res_pred = get_Proj_pred(call_res_new);
4974 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4975 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4976 pn_be_Call_M_regular);
4978 assert(is_ia32_xLoad(call_res_pred));
4979 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4983 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
4984 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
4986 ir_node *frame = get_irg_frame(irg);
4987 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4989 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4992 /* in case there is no memory output: create one to serialize the copy
4994 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4995 pn_be_Call_M_regular);
4996 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4997 pn_be_Call_first_res);
4999 /* store st(0) onto stack */
5000 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
5002 set_ia32_op_type(fstp, ia32_AddrModeD);
5003 set_ia32_use_frame(fstp);
5005 /* load into SSE register */
5006 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
5008 set_ia32_op_type(sse_load, ia32_AddrModeS);
5009 set_ia32_use_frame(sse_load);
5011 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
5017 /* transform call modes */
5018 if (mode_is_data(mode)) {
5019 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
5023 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
5027 * Transform the Projs from a Cmp.
5029 static ir_node *gen_Proj_Cmp(ir_node *node)
5031 /* this probably means not all mode_b nodes were lowered... */
5032 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
5037 * Transform and potentially renumber Proj nodes.
5039 static ir_node *gen_Proj(ir_node *node) {
5040 ir_node *pred = get_Proj_pred(node);
5041 if (is_Store(pred)) {
5042 long proj = get_Proj_proj(node);
5043 if (proj == pn_Store_M) {
5044 return be_transform_node(pred);
5047 return new_r_Bad(current_ir_graph);
5049 } else if (is_Load(pred)) {
5050 return gen_Proj_Load(node);
5051 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
5052 return gen_Proj_DivMod(node);
5053 } else if (is_CopyB(pred)) {
5054 return gen_Proj_CopyB(node);
5055 } else if (is_Quot(pred)) {
5056 return gen_Proj_Quot(node);
5057 } else if (be_is_SubSP(pred)) {
5058 return gen_Proj_be_SubSP(node);
5059 } else if (be_is_AddSP(pred)) {
5060 return gen_Proj_be_AddSP(node);
5061 } else if (be_is_Call(pred)) {
5062 return gen_Proj_be_Call(node);
5063 } else if (is_Cmp(pred)) {
5064 return gen_Proj_Cmp(node);
5065 } else if (get_irn_op(pred) == op_Start) {
5066 long proj = get_Proj_proj(node);
5067 if (proj == pn_Start_X_initial_exec) {
5068 ir_node *block = get_nodes_block(pred);
5069 dbg_info *dbgi = get_irn_dbg_info(node);
5072 /* we exchange the ProjX with a jump */
5073 block = be_transform_node(block);
5074 jump = new_rd_Jmp(dbgi, current_ir_graph, block);
5077 if (node == be_get_old_anchor(anchor_tls)) {
5078 return gen_Proj_tls(node);
5080 } else if (is_ia32_l_FloattoLL(pred)) {
5081 return gen_Proj_l_FloattoLL(node);
5083 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5087 ir_mode *mode = get_irn_mode(node);
5088 if (mode_needs_gp_reg(mode)) {
5089 ir_node *new_pred = be_transform_node(pred);
5090 ir_node *block = be_transform_node(get_nodes_block(node));
5091 ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred,
5092 mode_Iu, get_Proj_proj(node));
5093 #ifdef DEBUG_libfirm
5094 new_proj->node_nr = node->node_nr;
5100 return be_duplicate_node(node);
5104 * Enters all transform functions into the generic pointer
5106 static void register_transformers(void)
5110 /* first clear the generic function pointer for all ops */
5111 clear_irp_opcodes_generic_func();
5113 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
5114 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
5152 /* transform ops from intrinsic lowering */
5168 GEN(ia32_l_LLtoFloat);
5169 GEN(ia32_l_FloattoLL);
5175 /* we should never see these nodes */
5190 /* handle generic backend nodes */
5199 op_Mulh = get_op_Mulh();
5208 * Pre-transform all unknown and noreg nodes.
5210 static void ia32_pretransform_node(void *arch_cg) {
5211 ia32_code_gen_t *cg = arch_cg;
5213 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
5214 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
5215 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
5216 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
5217 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
5218 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
5223 * Walker, checks if all ia32 nodes producing more than one result have
5224 * its Projs, other wise creates new projs and keep them using a be_Keep node.
5226 static void add_missing_keep_walker(ir_node *node, void *data)
5229 unsigned found_projs = 0;
5230 const ir_edge_t *edge;
5231 ir_mode *mode = get_irn_mode(node);
5236 if(!is_ia32_irn(node))
5239 n_outs = get_ia32_n_res(node);
5242 if(is_ia32_SwitchJmp(node))
5245 assert(n_outs < (int) sizeof(unsigned) * 8);
5246 foreach_out_edge(node, edge) {
5247 ir_node *proj = get_edge_src_irn(edge);
5248 int pn = get_Proj_proj(proj);
5250 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
5251 found_projs |= 1 << pn;
5255 /* are keeps missing? */
5257 for(i = 0; i < n_outs; ++i) {
5260 const arch_register_req_t *req;
5261 const arch_register_class_t *class;
5263 if(found_projs & (1 << i)) {
5267 req = get_ia32_out_req(node, i);
5272 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
5276 block = get_nodes_block(node);
5277 in[0] = new_r_Proj(current_ir_graph, block, node,
5278 arch_register_class_mode(class), i);
5279 if(last_keep != NULL) {
5280 be_Keep_add_node(last_keep, class, in[0]);
5282 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
5283 if(sched_is_scheduled(node)) {
5284 sched_add_after(node, last_keep);
5291 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
5294 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
5296 ir_graph *irg = be_get_birg_irg(cg->birg);
5297 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
5300 /* do the transformation */
5301 void ia32_transform_graph(ia32_code_gen_t *cg) {
5303 ir_graph *irg = cg->irg;
5305 register_transformers();
5307 initial_fpcw = NULL;
5309 BE_TIMER_PUSH(t_heights);
5310 heights = heights_new(irg);
5311 BE_TIMER_POP(t_heights);
5312 ia32_calculate_non_address_mode_nodes(cg->birg);
5314 /* the transform phase is not safe for CSE (yet) because several nodes get
5315 * attributes set after their creation */
5316 cse_last = get_opt_cse();
5319 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
5321 set_opt_cse(cse_last);
5323 ia32_free_non_address_mode_nodes();
5324 heights_free(heights);
5328 void ia32_init_transform(void)
5330 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");