2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
32 #include "bearch_ia32_t.h"
34 #include "ia32_nodes_attr.h"
35 #include "../arch/archop.h" /* we need this for Min and Max nodes */
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
41 #include "gen_ia32_regalloc_if.h"
43 #define SFP_SIGN "0x80000000"
44 #define DFP_SIGN "0x8000000000000000"
45 #define SFP_ABS "0x7FFFFFFF"
46 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
48 #define TP_SFP_SIGN "ia32_sfp_sign"
49 #define TP_DFP_SIGN "ia32_dfp_sign"
50 #define TP_SFP_ABS "ia32_sfp_abs"
51 #define TP_DFP_ABS "ia32_dfp_abs"
53 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
54 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
55 #define ENT_SFP_ABS "IA32_SFP_ABS"
56 #define ENT_DFP_ABS "IA32_DFP_ABS"
58 extern ir_op *get_op_Mulh(void);
60 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
61 ir_node *op1, ir_node *op2, ir_node *mem);
63 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op, ir_node *mem);
67 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
70 /****************************************************************************************************
72 * | | | | / _| | | (_)
73 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
74 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
75 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
76 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
78 ****************************************************************************************************/
81 * Gets the Proj with number pn from irn.
83 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
84 const ir_edge_t *edge;
86 assert(get_irn_mode(irn) == mode_T && "need mode_T");
88 foreach_out_edge(irn, edge) {
89 proj = get_edge_src_irn(edge);
91 if (get_Proj_proj(proj) == pn)
98 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
99 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
100 static const struct {
102 const char *ent_name;
103 const char *cnst_str;
104 } names [ia32_known_const_max] = {
105 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
106 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
107 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
108 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
110 static struct entity *ent_cache[ia32_known_const_max];
112 const char *tp_name, *ent_name, *cnst_str;
119 ent_name = names[kct].ent_name;
120 if (! ent_cache[kct]) {
121 tp_name = names[kct].tp_name;
122 cnst_str = names[kct].cnst_str;
124 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
125 tp = new_type_primitive(new_id_from_str(tp_name), mode);
126 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
128 set_entity_ld_ident(ent, get_entity_ident(ent));
129 set_entity_visibility(ent, visibility_local);
130 set_entity_variability(ent, variability_constant);
131 set_entity_allocation(ent, allocation_static);
133 /* we create a new entity here: It's initialization must resist on the
135 rem = current_ir_graph;
136 current_ir_graph = get_const_code_irg();
137 cnst = new_Const(mode, tv);
138 current_ir_graph = rem;
140 set_atomic_ent_value(ent, cnst);
142 /* cache the entry */
143 ent_cache[kct] = ent;
146 return get_entity_ident(ent_cache[kct]);
151 * Prints the old node name on cg obst and returns a pointer to it.
153 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
154 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
156 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
157 obstack_1grow(isa->name_obst, 0);
158 isa->name_obst_size += obstack_object_size(isa->name_obst);
159 return obstack_finish(isa->name_obst);
163 /* determine if one operator is an Imm */
164 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
166 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
167 else return is_ia32_Cnst(op2) ? op2 : NULL;
170 /* determine if one operator is not an Imm */
171 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
172 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
177 * Construct a standard binary operation, set AM and immediate if required.
179 * @param env The transformation environment
180 * @param op1 The first operand
181 * @param op2 The second operand
182 * @param func The node constructor function
183 * @return The constructed ia32 node.
185 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
186 ir_node *new_op = NULL;
187 ir_mode *mode = env->mode;
188 dbg_info *dbg = env->dbg;
189 ir_graph *irg = env->irg;
190 ir_node *block = env->block;
191 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
192 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
193 ir_node *nomem = new_NoMem();
194 ir_node *expr_op, *imm_op;
195 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
197 /* Check if immediate optimization is on and */
198 /* if it's an operation with immediate. */
199 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
203 else if (is_op_commutative(get_irn_op(env->irn))) {
204 imm_op = get_immediate_op(op1, op2);
205 expr_op = get_expr_op(op1, op2);
208 imm_op = get_immediate_op(NULL, op2);
209 expr_op = get_expr_op(op1, op2);
212 assert((expr_op || imm_op) && "invalid operands");
215 /* We have two consts here: not yet supported */
219 if (mode_is_float(mode)) {
220 /* floating point operations */
222 DB((mod, LEVEL_1, "FP with immediate ..."));
223 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
224 set_ia32_Immop_attr(new_op, imm_op);
225 set_ia32_am_support(new_op, ia32_am_None);
228 DB((mod, LEVEL_1, "FP binop ..."));
229 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
230 set_ia32_am_support(new_op, ia32_am_Source);
232 set_ia32_ls_mode(new_op, mode);
235 /* integer operations */
237 /* This is expr + const */
238 DB((mod, LEVEL_1, "INT with immediate ..."));
239 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
240 set_ia32_Immop_attr(new_op, imm_op);
243 set_ia32_am_support(new_op, ia32_am_Dest);
246 DB((mod, LEVEL_1, "INT binop ..."));
247 /* This is a normal operation */
248 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
251 set_ia32_am_support(new_op, ia32_am_Full);
255 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
257 set_ia32_res_mode(new_op, mode);
259 if (is_op_commutative(get_irn_op(env->irn))) {
260 set_ia32_commutative(new_op);
263 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
269 * Construct a shift/rotate binary operation, sets AM and immediate if required.
271 * @param env The transformation environment
272 * @param op1 The first operand
273 * @param op2 The second operand
274 * @param func The node constructor function
275 * @return The constructed ia32 node.
277 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
278 ir_node *new_op = NULL;
279 ir_mode *mode = env->mode;
280 dbg_info *dbg = env->dbg;
281 ir_graph *irg = env->irg;
282 ir_node *block = env->block;
283 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
284 ir_node *nomem = new_NoMem();
285 ir_node *expr_op, *imm_op;
287 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
289 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
291 /* Check if immediate optimization is on and */
292 /* if it's an operation with immediate. */
293 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
294 expr_op = get_expr_op(op1, op2);
296 assert((expr_op || imm_op) && "invalid operands");
299 /* We have two consts here: not yet supported */
303 /* Limit imm_op within range imm8 */
305 tv = get_ia32_Immop_tarval(imm_op);
308 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
315 /* integer operations */
317 /* This is shift/rot with const */
318 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
320 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
321 set_ia32_Immop_attr(new_op, imm_op);
324 /* This is a normal shift/rot */
325 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
326 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
330 set_ia32_am_support(new_op, ia32_am_Dest);
332 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
334 set_ia32_res_mode(new_op, mode);
335 set_ia32_emit_cl(new_op);
337 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
342 * Construct a standard unary operation, set AM and immediate if required.
344 * @param env The transformation environment
345 * @param op The operand
346 * @param func The node constructor function
347 * @return The constructed ia32 node.
349 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
350 ir_node *new_op = NULL;
351 ir_mode *mode = env->mode;
352 dbg_info *dbg = env->dbg;
353 ir_graph *irg = env->irg;
354 ir_node *block = env->block;
355 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
356 ir_node *nomem = new_NoMem();
357 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
359 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
361 if (mode_is_float(mode)) {
362 DB((mod, LEVEL_1, "FP unop ..."));
363 /* floating point operations don't support implicit store */
364 set_ia32_am_support(new_op, ia32_am_None);
367 DB((mod, LEVEL_1, "INT unop ..."));
368 set_ia32_am_support(new_op, ia32_am_Dest);
371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
373 set_ia32_res_mode(new_op, mode);
375 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
381 * Creates an ia32 Add with immediate.
383 * @param env The transformation environment
384 * @param expr_op The expression operator
385 * @param const_op The constant
386 * @return the created ia32 Add node
388 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
389 ir_node *new_op = NULL;
390 tarval *tv = get_ia32_Immop_tarval(const_op);
391 dbg_info *dbg = env->dbg;
392 ir_graph *irg = env->irg;
393 ir_node *block = env->block;
394 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
395 ir_node *nomem = new_NoMem();
397 tarval_classification_t class_tv, class_negtv;
398 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
400 /* try to optimize to inc/dec */
401 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
402 /* optimize tarvals */
403 class_tv = classify_tarval(tv);
404 class_negtv = classify_tarval(tarval_neg(tv));
406 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
407 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
408 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
411 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
412 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
413 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
419 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
420 set_ia32_Immop_attr(new_op, const_op);
421 set_ia32_commutative(new_op);
428 * Creates an ia32 Add.
430 * @param env The transformation environment
431 * @return the created ia32 Add node
433 static ir_node *gen_Add(ia32_transform_env_t *env) {
434 ir_node *new_op = NULL;
435 dbg_info *dbg = env->dbg;
436 ir_mode *mode = env->mode;
437 ir_graph *irg = env->irg;
438 ir_node *block = env->block;
439 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
440 ir_node *nomem = new_NoMem();
441 ir_node *expr_op, *imm_op;
442 ir_node *op1 = get_Add_left(env->irn);
443 ir_node *op2 = get_Add_right(env->irn);
445 /* Check if immediate optimization is on and */
446 /* if it's an operation with immediate. */
447 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
448 expr_op = get_expr_op(op1, op2);
450 assert((expr_op || imm_op) && "invalid operands");
452 if (mode_is_float(mode)) {
454 if (USE_SSE2(env->cg))
455 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
457 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
462 /* No expr_op means, that we have two const - one symconst and */
463 /* one tarval or another symconst - because this case is not */
464 /* covered by constant folding */
465 /* We need to check for: */
466 /* 1) symconst + const -> becomes a LEA */
467 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
468 /* linker doesn't support two symconsts */
470 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
471 /* this is the 2nd case */
472 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
473 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
474 set_ia32_am_flavour(new_op, ia32_am_OB);
476 DBG_OPT_LEA1(op2, new_op);
479 /* this is the 1st case */
480 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
482 DBG_OPT_LEA2(op1, op2, new_op);
484 if (get_ia32_op_type(op1) == ia32_SymConst) {
485 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
486 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
489 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
490 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
492 set_ia32_am_flavour(new_op, ia32_am_O);
496 set_ia32_am_support(new_op, ia32_am_Source);
497 set_ia32_op_type(new_op, ia32_AddrModeS);
499 /* Lea doesn't need a Proj */
503 /* This is expr + const */
504 new_op = gen_imm_Add(env, expr_op, imm_op);
507 set_ia32_am_support(new_op, ia32_am_Dest);
510 /* This is a normal add */
511 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
514 set_ia32_am_support(new_op, ia32_am_Full);
515 set_ia32_commutative(new_op);
519 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
521 set_ia32_res_mode(new_op, mode);
523 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
529 * Creates an ia32 Mul.
531 * @param env The transformation environment
532 * @return the created ia32 Mul node
534 static ir_node *gen_Mul(ia32_transform_env_t *env) {
535 ir_node *op1 = get_Mul_left(env->irn);
536 ir_node *op2 = get_Mul_right(env->irn);
539 if (mode_is_float(env->mode)) {
541 if (USE_SSE2(env->cg))
542 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
544 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
547 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
556 * Creates an ia32 Mulh.
557 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
558 * this result while Mul returns the lower 32 bit.
560 * @param env The transformation environment
561 * @return the created ia32 Mulh node
563 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
564 ir_node *op1 = get_irn_n(env->irn, 0);
565 ir_node *op2 = get_irn_n(env->irn, 1);
566 ir_node *proj_EAX, *proj_EDX, *mulh;
569 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
570 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
571 mulh = get_Proj_pred(proj_EAX);
572 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
574 /* to be on the save side */
575 set_Proj_proj(proj_EAX, pn_EAX);
577 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
578 /* Mulh with const cannot have AM */
579 set_ia32_am_support(mulh, ia32_am_None);
582 /* Mulh cannot have AM for destination */
583 set_ia32_am_support(mulh, ia32_am_Source);
589 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
597 * Creates an ia32 And.
599 * @param env The transformation environment
600 * @return The created ia32 And node
602 static ir_node *gen_And(ia32_transform_env_t *env) {
603 ir_node *op1 = get_And_left(env->irn);
604 ir_node *op2 = get_And_right(env->irn);
606 assert (! mode_is_float(env->mode));
607 return gen_binop(env, op1, op2, new_rd_ia32_And);
613 * Creates an ia32 Or.
615 * @param env The transformation environment
616 * @return The created ia32 Or node
618 static ir_node *gen_Or(ia32_transform_env_t *env) {
619 ir_node *op1 = get_Or_left(env->irn);
620 ir_node *op2 = get_Or_right(env->irn);
622 assert (! mode_is_float(env->mode));
623 return gen_binop(env, op1, op2, new_rd_ia32_Or);
629 * Creates an ia32 Eor.
631 * @param env The transformation environment
632 * @return The created ia32 Eor node
634 static ir_node *gen_Eor(ia32_transform_env_t *env) {
635 ir_node *op1 = get_Eor_left(env->irn);
636 ir_node *op2 = get_Eor_right(env->irn);
638 assert(! mode_is_float(env->mode));
639 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
645 * Creates an ia32 Max.
647 * @param env The transformation environment
648 * @return the created ia32 Max node
650 static ir_node *gen_Max(ia32_transform_env_t *env) {
651 ir_node *op1 = get_irn_n(env->irn, 0);
652 ir_node *op2 = get_irn_n(env->irn, 1);
655 if (mode_is_float(env->mode)) {
657 if (USE_SSE2(env->cg))
658 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
664 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
665 set_ia32_am_support(new_op, ia32_am_None);
666 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
675 * Creates an ia32 Min.
677 * @param env The transformation environment
678 * @return the created ia32 Min node
680 static ir_node *gen_Min(ia32_transform_env_t *env) {
681 ir_node *op1 = get_irn_n(env->irn, 0);
682 ir_node *op2 = get_irn_n(env->irn, 1);
685 if (mode_is_float(env->mode)) {
687 if (USE_SSE2(env->cg))
688 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
694 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
695 set_ia32_am_support(new_op, ia32_am_None);
696 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
705 * Creates an ia32 Sub with immediate.
707 * @param env The transformation environment
708 * @param expr_op The first operator
709 * @param const_op The constant operator
710 * @return The created ia32 Sub node
712 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
713 ir_node *new_op = NULL;
714 tarval *tv = get_ia32_Immop_tarval(const_op);
715 dbg_info *dbg = env->dbg;
716 ir_graph *irg = env->irg;
717 ir_node *block = env->block;
718 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
719 ir_node *nomem = new_NoMem();
721 tarval_classification_t class_tv, class_negtv;
722 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
724 /* try to optimize to inc/dec */
725 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
726 /* optimize tarvals */
727 class_tv = classify_tarval(tv);
728 class_negtv = classify_tarval(tarval_neg(tv));
730 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
731 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
732 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
735 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
736 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
737 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
743 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
744 set_ia32_Immop_attr(new_op, const_op);
751 * Creates an ia32 Sub.
753 * @param env The transformation environment
754 * @return The created ia32 Sub node
756 static ir_node *gen_Sub(ia32_transform_env_t *env) {
757 ir_node *new_op = NULL;
758 dbg_info *dbg = env->dbg;
759 ir_mode *mode = env->mode;
760 ir_graph *irg = env->irg;
761 ir_node *block = env->block;
762 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
763 ir_node *nomem = new_NoMem();
764 ir_node *op1 = get_Sub_left(env->irn);
765 ir_node *op2 = get_Sub_right(env->irn);
766 ir_node *expr_op, *imm_op;
768 /* Check if immediate optimization is on and */
769 /* if it's an operation with immediate. */
770 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
771 expr_op = get_expr_op(op1, op2);
773 assert((expr_op || imm_op) && "invalid operands");
775 if (mode_is_float(mode)) {
777 if (USE_SSE2(env->cg))
778 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
780 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
785 /* No expr_op means, that we have two const - one symconst and */
786 /* one tarval or another symconst - because this case is not */
787 /* covered by constant folding */
788 /* We need to check for: */
789 /* 1) symconst + const -> becomes a LEA */
790 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
791 /* linker doesn't support two symconsts */
793 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
794 /* this is the 2nd case */
795 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
796 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
797 set_ia32_am_sc_sign(new_op);
798 set_ia32_am_flavour(new_op, ia32_am_OB);
800 DBG_OPT_LEA1(op2, new_op);
803 /* this is the 1st case */
804 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
806 DBG_OPT_LEA2(op1, op2, new_op);
808 if (get_ia32_op_type(op1) == ia32_SymConst) {
809 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
810 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
813 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
814 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
815 set_ia32_am_sc_sign(new_op);
817 set_ia32_am_flavour(new_op, ia32_am_O);
821 set_ia32_am_support(new_op, ia32_am_Source);
822 set_ia32_op_type(new_op, ia32_AddrModeS);
824 /* Lea doesn't need a Proj */
828 /* This is expr - const */
829 new_op = gen_imm_Sub(env, expr_op, imm_op);
832 set_ia32_am_support(new_op, ia32_am_Dest);
835 /* This is a normal sub */
836 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
839 set_ia32_am_support(new_op, ia32_am_Full);
843 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
845 set_ia32_res_mode(new_op, mode);
847 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
853 * Generates an ia32 DivMod with additional infrastructure for the
854 * register allocator if needed.
856 * @param env The transformation environment
857 * @param dividend -no comment- :)
858 * @param divisor -no comment- :)
859 * @param dm_flav flavour_Div/Mod/DivMod
860 * @return The created ia32 DivMod node
862 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
864 ir_node *edx_node, *cltd;
866 dbg_info *dbg = env->dbg;
867 ir_graph *irg = env->irg;
868 ir_node *block = env->block;
869 ir_mode *mode = env->mode;
870 ir_node *irn = env->irn;
875 mem = get_Div_mem(irn);
876 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
879 mem = get_Mod_mem(irn);
880 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
883 mem = get_DivMod_mem(irn);
884 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
890 if (mode_is_signed(mode)) {
891 /* in signed mode, we need to sign extend the dividend */
892 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
893 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
894 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
897 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
898 set_ia32_Const_type(edx_node, ia32_Const);
899 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
902 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
904 set_ia32_n_res(res, 2);
906 /* Only one proj is used -> We must add a second proj and */
907 /* connect this one to a Keep node to eat up the second */
908 /* destroyed register. */
909 if (get_irn_n_edges(irn) == 1) {
910 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
911 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
913 if (get_irn_op(irn) == op_Div) {
914 set_Proj_proj(proj, pn_DivMod_res_div);
915 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
918 set_Proj_proj(proj, pn_DivMod_res_mod);
919 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
922 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
925 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
927 set_ia32_res_mode(res, mode_Is);
934 * Wrapper for generate_DivMod. Sets flavour_Mod.
936 * @param env The transformation environment
938 static ir_node *gen_Mod(ia32_transform_env_t *env) {
939 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
943 * Wrapper for generate_DivMod. Sets flavour_Div.
945 * @param env The transformation environment
947 static ir_node *gen_Div(ia32_transform_env_t *env) {
948 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
952 * Wrapper for generate_DivMod. Sets flavour_DivMod.
954 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
955 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
961 * Creates an ia32 floating Div.
963 * @param env The transformation environment
964 * @return The created ia32 xDiv node
966 static ir_node *gen_Quot(ia32_transform_env_t *env) {
967 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
969 ir_node *nomem = new_rd_NoMem(env->irg);
970 ir_node *op1 = get_Quot_left(env->irn);
971 ir_node *op2 = get_Quot_right(env->irn);
974 if (USE_SSE2(env->cg)) {
975 if (is_ia32_xConst(op2)) {
976 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
977 set_ia32_am_support(new_op, ia32_am_None);
978 set_ia32_Immop_attr(new_op, op2);
981 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
982 set_ia32_am_support(new_op, ia32_am_Source);
986 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
987 set_ia32_am_support(new_op, ia32_am_Source);
989 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
990 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
998 * Creates an ia32 Shl.
1000 * @param env The transformation environment
1001 * @return The created ia32 Shl node
1003 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1004 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1010 * Creates an ia32 Shr.
1012 * @param env The transformation environment
1013 * @return The created ia32 Shr node
1015 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1016 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1022 * Creates an ia32 Shrs.
1024 * @param env The transformation environment
1025 * @return The created ia32 Shrs node
1027 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1028 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1034 * Creates an ia32 RotL.
1036 * @param env The transformation environment
1037 * @param op1 The first operator
1038 * @param op2 The second operator
1039 * @return The created ia32 RotL node
1041 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1042 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1048 * Creates an ia32 RotR.
1049 * NOTE: There is no RotR with immediate because this would always be a RotL
1050 * "imm-mode_size_bits" which can be pre-calculated.
1052 * @param env The transformation environment
1053 * @param op1 The first operator
1054 * @param op2 The second operator
1055 * @return The created ia32 RotR node
1057 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1058 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1064 * Creates an ia32 RotR or RotL (depending on the found pattern).
1066 * @param env The transformation environment
1067 * @return The created ia32 RotL or RotR node
1069 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1070 ir_node *rotate = NULL;
1071 ir_node *op1 = get_Rot_left(env->irn);
1072 ir_node *op2 = get_Rot_right(env->irn);
1074 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1075 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1076 that means we can create a RotR instead of an Add and a RotL */
1079 ir_node *pred = get_Proj_pred(op2);
1081 if (is_ia32_Add(pred)) {
1082 ir_node *pred_pred = get_irn_n(pred, 2);
1083 tarval *tv = get_ia32_Immop_tarval(pred);
1084 long bits = get_mode_size_bits(env->mode);
1086 if (is_Proj(pred_pred)) {
1087 pred_pred = get_Proj_pred(pred_pred);
1090 if (is_ia32_Minus(pred_pred) &&
1091 tarval_is_long(tv) &&
1092 get_tarval_long(tv) == bits)
1094 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1095 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1102 rotate = gen_RotL(env, op1, op2);
1111 * Transforms a Minus node.
1113 * @param env The transformation environment
1114 * @param op The Minus operand
1115 * @return The created ia32 Minus node
1117 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1122 if (mode_is_float(env->mode)) {
1124 if (USE_SSE2(env->cg)) {
1125 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1126 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1127 ir_node *nomem = new_rd_NoMem(env->irg);
1129 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1131 size = get_mode_size_bits(env->mode);
1132 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1134 set_ia32_sc(new_op, name);
1136 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1138 set_ia32_res_mode(new_op, env->mode);
1139 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1141 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1144 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1145 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1149 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1156 * Transforms a Minus node.
1158 * @param env The transformation environment
1159 * @return The created ia32 Minus node
1161 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1162 return gen_Minus_ex(env, get_Minus_op(env->irn));
1167 * Transforms a Not node.
1169 * @param env The transformation environment
1170 * @return The created ia32 Not node
1172 static ir_node *gen_Not(ia32_transform_env_t *env) {
1173 assert (! mode_is_float(env->mode));
1174 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1180 * Transforms an Abs node.
1182 * @param env The transformation environment
1183 * @return The created ia32 Abs node
1185 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1186 ir_node *res, *p_eax, *p_edx;
1187 dbg_info *dbg = env->dbg;
1188 ir_mode *mode = env->mode;
1189 ir_graph *irg = env->irg;
1190 ir_node *block = env->block;
1191 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1192 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1193 ir_node *nomem = new_NoMem();
1194 ir_node *op = get_Abs_op(env->irn);
1198 if (mode_is_float(mode)) {
1200 if (USE_SSE2(env->cg)) {
1201 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1203 size = get_mode_size_bits(mode);
1204 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1206 set_ia32_sc(res, name);
1208 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1210 set_ia32_res_mode(res, mode);
1211 set_ia32_immop_type(res, ia32_ImmSymConst);
1213 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1216 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1217 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1221 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1222 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1223 set_ia32_res_mode(res, mode);
1225 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1226 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1228 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1229 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1230 set_ia32_res_mode(res, mode);
1232 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1234 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1235 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1236 set_ia32_res_mode(res, mode);
1238 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1247 * Transforms a Load.
1249 * @param env The transformation environment
1250 * @return the created ia32 Load node
1252 static ir_node *gen_Load(ia32_transform_env_t *env) {
1253 ir_node *node = env->irn;
1254 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1255 ir_node *ptr = get_Load_ptr(node);
1256 ir_node *lptr = ptr;
1257 ir_mode *mode = get_Load_mode(node);
1260 ia32_am_flavour_t am_flav = ia32_B;
1262 /* address might be a constant (symconst or absolute address) */
1263 if (is_ia32_Const(ptr)) {
1268 if (mode_is_float(mode)) {
1270 if (USE_SSE2(env->cg))
1271 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1273 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1276 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1279 /* base is an constant address */
1281 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1282 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1285 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1291 set_ia32_am_support(new_op, ia32_am_Source);
1292 set_ia32_op_type(new_op, ia32_AddrModeS);
1293 set_ia32_am_flavour(new_op, am_flav);
1294 set_ia32_ls_mode(new_op, mode);
1296 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1304 * Transforms a Store.
1306 * @param env The transformation environment
1307 * @return the created ia32 Store node
1309 static ir_node *gen_Store(ia32_transform_env_t *env) {
1310 ir_node *node = env->irn;
1311 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1312 ir_node *val = get_Store_value(node);
1313 ir_node *ptr = get_Store_ptr(node);
1314 ir_node *sptr = ptr;
1315 ir_node *mem = get_Store_mem(node);
1316 ir_mode *mode = get_irn_mode(val);
1317 ir_node *sval = val;
1320 ia32_am_flavour_t am_flav = ia32_B;
1321 ia32_immop_type_t immop = ia32_ImmNone;
1323 if (! mode_is_float(mode)) {
1324 /* in case of storing a const (but not a symconst) -> make it an attribute */
1325 if (is_ia32_Cnst(val)) {
1326 switch (get_ia32_op_type(val)) {
1328 immop = ia32_ImmConst;
1331 immop = ia32_ImmSymConst;
1334 assert(0 && "unsupported Const type");
1340 /* address might be a constant (symconst or absolute address) */
1341 if (is_ia32_Const(ptr)) {
1346 if (mode_is_float(mode)) {
1348 if (USE_SSE2(env->cg))
1349 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1351 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1353 else if (get_mode_size_bits(mode) == 8) {
1354 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1357 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1360 /* stored const is an attribute (saves a register) */
1361 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1362 set_ia32_Immop_attr(new_op, val);
1365 /* base is an constant address */
1367 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1368 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1371 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1377 set_ia32_am_support(new_op, ia32_am_Dest);
1378 set_ia32_op_type(new_op, ia32_AddrModeD);
1379 set_ia32_am_flavour(new_op, am_flav);
1380 set_ia32_ls_mode(new_op, get_irn_mode(val));
1381 set_ia32_immop_type(new_op, immop);
1383 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1391 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1393 * @param env The transformation environment
1394 * @return The transformed node.
1396 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1397 dbg_info *dbg = env->dbg;
1398 ir_graph *irg = env->irg;
1399 ir_node *block = env->block;
1400 ir_node *node = env->irn;
1401 ir_node *sel = get_Cond_selector(node);
1402 ir_mode *sel_mode = get_irn_mode(sel);
1403 ir_node *res = NULL;
1404 ir_node *pred = NULL;
1405 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1406 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1408 if (is_Proj(sel) && sel_mode == mode_b) {
1409 ir_node *nomem = new_NoMem();
1411 pred = get_Proj_pred(sel);
1413 /* get both compare operators */
1414 cmp_a = get_Cmp_left(pred);
1415 cmp_b = get_Cmp_right(pred);
1417 /* check if we can use a CondJmp with immediate */
1418 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1419 expr = get_expr_op(cmp_a, cmp_b);
1422 pn_Cmp pnc = get_Proj_proj(sel);
1424 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1425 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1426 /* a Cmp A =/!= 0 */
1427 ir_node *op1 = expr;
1428 ir_node *op2 = expr;
1429 ir_node *and = skip_Proj(expr);
1430 const char *cnst = NULL;
1432 /* check, if expr is an only once used And operation */
1433 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1434 op1 = get_irn_n(and, 2);
1435 op2 = get_irn_n(and, 3);
1437 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1439 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1440 set_ia32_pncode(res, get_Proj_proj(sel));
1441 set_ia32_res_mode(res, get_irn_mode(op1));
1444 copy_ia32_Immop_attr(res, and);
1447 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1452 if (mode_is_float(get_irn_mode(expr))) {
1454 if (USE_SSE2(env->cg))
1455 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1461 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1463 set_ia32_Immop_attr(res, cnst);
1464 set_ia32_res_mode(res, get_irn_mode(expr));
1467 if (mode_is_float(get_irn_mode(cmp_a))) {
1469 if (USE_SSE2(env->cg))
1470 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1473 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1474 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1475 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1479 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1480 set_ia32_commutative(res);
1482 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1485 set_ia32_pncode(res, get_Proj_proj(sel));
1486 //set_ia32_am_support(res, ia32_am_Source);
1489 /* determine the smallest switch case value */
1490 int switch_min = INT_MAX;
1491 const ir_edge_t *edge;
1494 foreach_out_edge(node, edge) {
1495 int pn = get_Proj_proj(get_edge_src_irn(edge));
1496 switch_min = pn < switch_min ? pn : switch_min;
1500 /* if smallest switch case is not 0 we need an additional sub */
1501 snprintf(buf, sizeof(buf), "%d", switch_min);
1502 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1503 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1504 sub_ia32_am_offs(res, buf);
1505 set_ia32_am_flavour(res, ia32_am_OB);
1506 set_ia32_am_support(res, ia32_am_Source);
1507 set_ia32_op_type(res, ia32_AddrModeS);
1510 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1511 set_ia32_pncode(res, get_Cond_defaultProj(node));
1512 set_ia32_res_mode(res, get_irn_mode(sel));
1515 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1522 * Transforms a CopyB node.
1524 * @param env The transformation environment
1525 * @return The transformed node.
1527 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1528 ir_node *res = NULL;
1529 dbg_info *dbg = env->dbg;
1530 ir_graph *irg = env->irg;
1531 ir_mode *mode = env->mode;
1532 ir_node *block = env->block;
1533 ir_node *node = env->irn;
1534 ir_node *src = get_CopyB_src(node);
1535 ir_node *dst = get_CopyB_dst(node);
1536 ir_node *mem = get_CopyB_mem(node);
1537 int size = get_type_size_bytes(get_CopyB_type(node));
1540 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1541 /* then we need the size explicitly in ECX. */
1542 if (size >= 16 * 4) {
1543 rem = size & 0x3; /* size % 4 */
1546 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1547 set_ia32_op_type(res, ia32_Const);
1548 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1550 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1551 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1554 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1555 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1556 set_ia32_immop_type(res, ia32_ImmConst);
1559 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1567 * Transforms a Mux node into CMov.
1569 * @param env The transformation environment
1570 * @return The transformed node.
1572 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1574 ir_node *node = env->irn;
1575 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1576 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1578 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1587 * Transforms a Psi node into CMov.
1589 * @param env The transformation environment
1590 * @return The transformed node.
1592 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1593 ir_node *node = env->irn;
1594 ir_node *cmp_proj = get_Mux_sel(node);
1595 ir_node *cmp, *cmp_a, *cmp_b, *new_op;
1597 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1599 cmp = get_Proj_pred(cmp_proj);
1600 cmp_a = get_Cmp_left(cmp);
1601 cmp_b = get_Cmp_right(cmp);
1604 new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1605 cmp_a, cmp_b, get_Psi_val(node, 0), get_Psi_default(node), env->mode);
1607 set_ia32_pncode(new_op, get_Proj_proj(cmp_proj));
1609 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1616 * Following conversion rules apply:
1620 * 1) n bit -> m bit n > m (downscale)
1621 * a) target is signed: movsx
1622 * b) target is unsigned: and with lower bits sets
1623 * 2) n bit -> m bit n == m (sign change)
1625 * 3) n bit -> m bit n < m (upscale)
1626 * a) source is signed: movsx
1627 * b) source is unsigned: and with lower bits sets
1631 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1635 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1636 * if target mode < 32bit: additional INT -> INT conversion (see above)
1640 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1641 * x87 is mode_E internally, conversions happen only at load and store
1642 * in non-strict semantic
1646 * Create a conversion from x87 state register to general purpose.
1648 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1649 ia32_code_gen_t *cg = env->cg;
1650 entity *ent = cg->fp_to_gp;
1651 ir_graph *irg = env->irg;
1652 ir_node *block = env->block;
1653 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1654 ir_node *op = get_Conv_op(env->irn);
1655 ir_node *fist, *mem, *load;
1658 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1659 ent = cg->fp_to_gp =
1660 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1664 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1666 set_ia32_frame_ent(fist, ent);
1667 set_ia32_use_frame(fist);
1668 set_ia32_am_support(fist, ia32_am_Dest);
1669 set_ia32_op_type(fist, ia32_AddrModeD);
1670 set_ia32_am_flavour(fist, ia32_B);
1671 set_ia32_ls_mode(fist, mode_E);
1673 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1676 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1678 set_ia32_frame_ent(load, ent);
1679 set_ia32_use_frame(load);
1680 set_ia32_am_support(load, ia32_am_Source);
1681 set_ia32_op_type(load, ia32_AddrModeS);
1682 set_ia32_am_flavour(load, ia32_B);
1683 set_ia32_ls_mode(load, tgt_mode);
1685 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1689 * Create a conversion from x87 state register to general purpose.
1691 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1692 ia32_code_gen_t *cg = env->cg;
1693 entity *ent = cg->gp_to_fp;
1694 ir_graph *irg = env->irg;
1695 ir_node *block = env->block;
1696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1697 ir_node *nomem = get_irg_no_mem(irg);
1698 ir_node *op = get_Conv_op(env->irn);
1699 ir_node *fild, *store, *mem;
1703 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1704 ent = cg->gp_to_fp =
1705 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1708 /* first convert to 32 bit */
1709 src_bits = get_mode_size_bits(src_mode);
1710 if (src_bits == 8) {
1711 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1712 op = new_r_Proj(irg, block, op, mode_Is, 0);
1714 else if (src_bits < 32) {
1715 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1716 op = new_r_Proj(irg, block, op, mode_Is, 0);
1720 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1722 set_ia32_frame_ent(store, ent);
1723 set_ia32_use_frame(store);
1725 set_ia32_am_support(store, ia32_am_Dest);
1726 set_ia32_op_type(store, ia32_AddrModeD);
1727 set_ia32_am_flavour(store, ia32_B);
1728 set_ia32_ls_mode(store, mode_Is);
1730 mem = new_r_Proj(irg, block, store, mode_M, 0);
1733 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1735 set_ia32_frame_ent(fild, ent);
1736 set_ia32_use_frame(fild);
1737 set_ia32_am_support(fild, ia32_am_Source);
1738 set_ia32_op_type(fild, ia32_AddrModeS);
1739 set_ia32_am_flavour(fild, ia32_B);
1740 set_ia32_ls_mode(fild, mode_E);
1742 return new_r_Proj(irg, block, fild, mode_E, 0);
1746 * Transforms a Conv node.
1748 * @param env The transformation environment
1749 * @return The created ia32 Conv node
1751 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1752 dbg_info *dbg = env->dbg;
1753 ir_graph *irg = env->irg;
1754 ir_node *op = get_Conv_op(env->irn);
1755 ir_mode *src_mode = get_irn_mode(op);
1756 ir_mode *tgt_mode = env->mode;
1757 int src_bits = get_mode_size_bits(src_mode);
1758 int tgt_bits = get_mode_size_bits(tgt_mode);
1759 ir_node *block = env->block;
1760 ir_node *new_op = NULL;
1761 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1762 ir_node *nomem = new_rd_NoMem(irg);
1764 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1766 if (src_mode == tgt_mode) {
1767 /* this can happen when changing mode_P to mode_Is */
1768 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1769 edges_reroute(env->irn, op, irg);
1771 else if (mode_is_float(src_mode)) {
1772 /* we convert from float ... */
1773 if (mode_is_float(tgt_mode)) {
1775 if (USE_SSE2(env->cg)) {
1776 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1777 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1780 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1781 edges_reroute(env->irn, op, irg);
1786 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1787 if (USE_SSE2(env->cg))
1788 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1790 return gen_x87_fp_to_gp(env, tgt_mode);
1792 /* if target mode is not int: add an additional downscale convert */
1793 if (tgt_bits < 32) {
1794 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1795 set_ia32_am_support(new_op, ia32_am_Source);
1796 set_ia32_tgt_mode(new_op, tgt_mode);
1797 set_ia32_src_mode(new_op, src_mode);
1799 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1801 if (tgt_bits == 8 || src_bits == 8) {
1802 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1805 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1811 /* we convert from int ... */
1812 if (mode_is_float(tgt_mode)) {
1815 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1816 if (USE_SSE2(env->cg))
1817 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1819 return gen_x87_gp_to_fp(env, src_mode);
1823 if (get_mode_size_bits(src_mode) == tgt_bits) {
1824 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1825 edges_reroute(env->irn, op, irg);
1828 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1829 if (tgt_bits == 8 || src_bits == 8) {
1830 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1833 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1840 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1841 set_ia32_tgt_mode(new_op, tgt_mode);
1842 set_ia32_src_mode(new_op, src_mode);
1844 set_ia32_am_support(new_op, ia32_am_Source);
1846 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1854 /********************************************
1857 * | |__ ___ _ __ ___ __| | ___ ___
1858 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1859 * | |_) | __/ | | | (_) | (_| | __/\__ \
1860 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1862 ********************************************/
1864 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1865 ir_node *new_op = NULL;
1866 ir_node *node = env->irn;
1867 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1868 ir_node *mem = new_rd_NoMem(env->irg);
1869 ir_node *ptr = get_irn_n(node, 0);
1870 entity *ent = be_get_frame_entity(node);
1871 ir_mode *mode = env->mode;
1873 // /* If the StackParam has only one user -> */
1874 // /* put it in the Block where the user resides */
1875 // if (get_irn_n_edges(node) == 1) {
1876 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1879 if (mode_is_float(mode)) {
1881 if (USE_SSE2(env->cg))
1882 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1884 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1887 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1890 set_ia32_frame_ent(new_op, ent);
1891 set_ia32_use_frame(new_op);
1893 set_ia32_am_support(new_op, ia32_am_Source);
1894 set_ia32_op_type(new_op, ia32_AddrModeS);
1895 set_ia32_am_flavour(new_op, ia32_B);
1896 set_ia32_ls_mode(new_op, mode);
1898 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1900 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1904 * Transforms a FrameAddr into an ia32 Add.
1906 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1907 ir_node *new_op = NULL;
1908 ir_node *node = env->irn;
1909 ir_node *op = get_irn_n(node, 0);
1910 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1911 ir_node *nomem = new_rd_NoMem(env->irg);
1913 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
1914 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1915 set_ia32_am_support(new_op, ia32_am_Full);
1916 set_ia32_use_frame(new_op);
1917 set_ia32_immop_type(new_op, ia32_ImmConst);
1918 set_ia32_commutative(new_op);
1920 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1922 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
1926 * Transforms a FrameLoad into an ia32 Load.
1928 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1929 ir_node *new_op = NULL;
1930 ir_node *node = env->irn;
1931 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1932 ir_node *mem = get_irn_n(node, 0);
1933 ir_node *ptr = get_irn_n(node, 1);
1934 entity *ent = be_get_frame_entity(node);
1935 ir_mode *mode = get_type_mode(get_entity_type(ent));
1937 if (mode_is_float(mode)) {
1939 if (USE_SSE2(env->cg))
1940 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1942 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1945 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1947 set_ia32_frame_ent(new_op, ent);
1948 set_ia32_use_frame(new_op);
1950 set_ia32_am_support(new_op, ia32_am_Source);
1951 set_ia32_op_type(new_op, ia32_AddrModeS);
1952 set_ia32_am_flavour(new_op, ia32_B);
1953 set_ia32_ls_mode(new_op, mode);
1955 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1962 * Transforms a FrameStore into an ia32 Store.
1964 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
1965 ir_node *new_op = NULL;
1966 ir_node *node = env->irn;
1967 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1968 ir_node *mem = get_irn_n(node, 0);
1969 ir_node *ptr = get_irn_n(node, 1);
1970 ir_node *val = get_irn_n(node, 2);
1971 entity *ent = be_get_frame_entity(node);
1972 ir_mode *mode = get_irn_mode(val);
1974 if (mode_is_float(mode)) {
1976 if (USE_SSE2(env->cg))
1977 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1979 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1981 else if (get_mode_size_bits(mode) == 8) {
1982 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1985 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1988 set_ia32_frame_ent(new_op, ent);
1989 set_ia32_use_frame(new_op);
1991 set_ia32_am_support(new_op, ia32_am_Dest);
1992 set_ia32_op_type(new_op, ia32_AddrModeD);
1993 set_ia32_am_flavour(new_op, ia32_B);
1994 set_ia32_ls_mode(new_op, mode);
1996 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2002 * This function just sets the register for the Unknown node
2003 * as this is not done during register allocation because Unknown
2004 * is an "ignore" node.
2006 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2007 ir_mode *mode = env->mode;
2008 ir_node *irn = env->irn;
2010 if (mode_is_float(mode)) {
2011 if (USE_SSE2(env->cg))
2012 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2014 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2016 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2017 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2020 assert(0 && "unsupported Unknown-Mode");
2027 /*********************************************************
2030 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2031 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2032 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2033 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2035 *********************************************************/
2038 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2039 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2041 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2042 ia32_transform_env_t tenv;
2043 ir_node *in1, *in2, *noreg, *nomem, *res;
2044 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2046 /* Return if AM node or not a Sub or xSub */
2047 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2050 noreg = ia32_new_NoReg_gp(cg);
2051 nomem = new_rd_NoMem(cg->irg);
2052 in1 = get_irn_n(irn, 2);
2053 in2 = get_irn_n(irn, 3);
2054 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2055 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2056 out_reg = get_ia32_out_reg(irn, 0);
2058 tenv.block = get_nodes_block(irn);
2059 tenv.dbg = get_irn_dbg_info(irn);
2062 tenv.mode = get_ia32_res_mode(irn);
2064 DEBUG_ONLY(tenv.mod = cg->mod;)
2066 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2067 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2068 /* generate the neg src2 */
2069 res = gen_Minus_ex(&tenv, in2);
2070 arch_set_irn_register(cg->arch_env, res, in2_reg);
2072 /* add to schedule */
2073 sched_add_before(irn, res);
2075 /* generate the add */
2076 if (mode_is_float(tenv.mode)) {
2077 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2078 set_ia32_am_support(res, ia32_am_Source);
2081 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2082 set_ia32_am_support(res, ia32_am_Full);
2083 set_ia32_commutative(res);
2085 set_ia32_res_mode(res, tenv.mode);
2087 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2089 slots = get_ia32_slots(res);
2092 /* add to schedule */
2093 sched_add_before(irn, res);
2095 /* remove the old sub */
2098 DBG_OPT_SUB2NEGADD(irn, res);
2100 /* exchange the add and the sub */
2106 * Transforms a LEA into an Add if possible
2107 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2109 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2110 ia32_am_flavour_t am_flav;
2112 ir_node *res = NULL;
2113 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2115 ia32_transform_env_t tenv;
2116 const arch_register_t *out_reg, *base_reg, *index_reg;
2119 if (! is_ia32_Lea(irn))
2122 am_flav = get_ia32_am_flavour(irn);
2124 /* only some LEAs can be transformed to an Add */
2125 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2128 noreg = ia32_new_NoReg_gp(cg);
2129 nomem = new_rd_NoMem(cg->irg);
2132 base = get_irn_n(irn, 0);
2133 index = get_irn_n(irn,1);
2135 offs = get_ia32_am_offs(irn);
2137 /* offset has a explicit sign -> we need to skip + */
2138 if (offs && offs[0] == '+')
2141 out_reg = arch_get_irn_register(cg->arch_env, irn);
2142 base_reg = arch_get_irn_register(cg->arch_env, base);
2143 index_reg = arch_get_irn_register(cg->arch_env, index);
2145 tenv.block = get_nodes_block(irn);
2146 tenv.dbg = get_irn_dbg_info(irn);
2149 DEBUG_ONLY(tenv.mod = cg->mod;)
2150 tenv.mode = get_irn_mode(irn);
2153 switch(get_ia32_am_flavour(irn)) {
2155 /* out register must be same as base register */
2156 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2162 /* out register must be same as base register */
2163 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2170 /* out register must be same as index register */
2171 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2178 /* out register must be same as one in register */
2179 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2183 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2188 /* in registers a different from out -> no Add possible */
2195 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2196 arch_set_irn_register(cg->arch_env, res, out_reg);
2197 set_ia32_op_type(res, ia32_Normal);
2198 set_ia32_commutative(res);
2199 set_ia32_res_mode(res, tenv.mode);
2202 set_ia32_cnst(res, offs);
2203 set_ia32_immop_type(res, ia32_ImmConst);
2206 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2208 /* add Add to schedule */
2209 sched_add_before(irn, res);
2211 DBG_OPT_LEA2ADD(irn, res);
2213 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2215 /* add result Proj to schedule */
2216 sched_add_before(irn, res);
2218 /* remove the old LEA */
2221 /* exchange the Add and the LEA */
2226 * the BAD transformer.
2228 static ir_node *bad_transform(ia32_transform_env_t *env) {
2229 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2235 * Enters all transform functions into the generic pointer
2237 void ia32_register_transformers(void) {
2238 ir_op *op_Max, *op_Min, *op_Mulh;
2240 /* first clear the generic function pointer for all ops */
2241 clear_irp_opcodes_generic_func();
2243 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2244 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2291 /* constant transformation happens earlier */
2315 /* set the register for all Unknown nodes */
2318 op_Max = get_op_Max();
2321 op_Min = get_op_Min();
2324 op_Mulh = get_op_Mulh();
2333 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2336 * Transforms the given firm node (and maybe some other related nodes)
2337 * into one or more assembler nodes.
2339 * @param node the firm node
2340 * @param env the debug module
2342 void ia32_transform_node(ir_node *node, void *env) {
2343 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2344 ir_op *op = get_irn_op(node);
2345 ir_node *asm_node = NULL;
2350 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2351 if (op->ops.generic) {
2352 ia32_transform_env_t tenv;
2353 transform_func *transform = (transform_func *)op->ops.generic;
2355 tenv.block = get_nodes_block(node);
2356 tenv.dbg = get_irn_dbg_info(node);
2357 tenv.irg = current_ir_graph;
2359 tenv.mode = get_irn_mode(node);
2361 DEBUG_ONLY(tenv.mod = cg->mod;)
2363 asm_node = (*transform)(&tenv);
2366 /* exchange nodes if a new one was generated */
2368 exchange(node, asm_node);
2369 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2372 DB((cg->mod, LEVEL_1, "ignored\n"));